FPGA IMPLEMENTATION OF HIGH SPEED ARITHMETIC UNIT USING VEDIC MATHEMATICS Mrs. G. Shobana, Assistant Professor, S. RamaLakshmi,J. Lavanya [email protected][email protected][email protected]Department of Electronics and Communication Engineering Mepco Schlenk Engineering College (Autonomous), Sivakasi Abstract – Arithmetic Logic Unit (ALU) is an important building block of any computing systems. In this paper, high speed and energy efficient architecture for ALU is designed by using the concepts of Vedic mathematics. The arithmetic operations such as addition, subtraction, multiplication and division are performed using Vilokanum, Urdhav Triyagbhyam , Paravartya sutras . The proposed architecture is simulated using Verilog followed by synthesis using Xilinx ISE 14.1 and is implemented in Spartan – 6 FPGA .The performance of the proposed ALU architecture is analyzed and compared with the already available traditional arithmetic unit in terms of delay and resource complexity. It is shown that the proposed architecture is highly efficient in terms of delay compared to available methods. I.INTRODUCTION: Multipliers have been proven to be an important component while designing microprocessors and other applications where processing of a signal is in foreground.Since the processor depends upon on multiplier,multiplication is the key arithmetic technique for improving the performance of fast processor.Therefore,the technologies are looking for a new algorithm and hardware so as to implement the obtained operation in much optimized way in the terms of area and speed.The word “Vedic” is a consequential of “Vedic” comprising the accumulation of knowledge at a single platform.Jagadguru Swami Sri Bharati Krishna Tirthaji in between 1884-1960,implemented the concept of this ancient methodology that became very popular to achieve the processing of the data.Vedic mathematics deals with the various operation of mathematics like arithmetic algebra,geometry,equation etc.The use of Vedic mathematics concepts in the computation algorithm of a processor will reduce the complexity of execution time,speed,delay,area and power consumption etc. The paper starts with an introduction pertaining to the section I. Thereafter , Section II literature survey.Section III about the proposed model of vedic arithmetic unit.Section IV proposes Vedic methodology used for addition. Section V illustrates the steps approaching Vedic methodology for subtraction.SectionVI comprises the design of Vedic multiplication .Section VII discuss about the Vedic divider. Finally, obtained results are discussed in next section. II. LITERATURE SURVEY: Based on the Vedic mathematics concepts for digital signal processing applications,many researchers have proposed ALUs and other computational units.From these research, they have proved that conventional arithmetic computational algorithms are very robust when compared to proposed arithmetic computations. Garima Rawat have proposed an ALU design using vedic mathematics approach.He designed and analyzed about high speed 8*8 bit multiplier.This method is different from the conventional method of employing product of two numbers accomplished by the process of add and shift.And the proposed method involves the vertical and crossed multiplication and it was efficient and fast.[1]. Rahul Nimje have proposed an ALU design using Vedic mathematics concepts.He designed and analyzed vedic multiplier using Urdhav Triyagbhyam sutra.In this method of multiplication,he eliminate the unwanted multiplications steps with zeros,by enabling parallel generation of intermediate product.By this,he achieved high speed power efficient multiplier[2].
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FPGA IMPLEMENTATION OF HIGH
SPEED ARITHMETIC UNIT USING VEDIC
MATHEMATICS Mrs. G. Shobana, Assistant Professor, S. RamaLakshmi,J. Lavanya [email protected][email protected][email protected] Department of Electronics and Communication Engineering Mepco Schlenk Engineering College (Autonomous), Sivakasi
Abstract – Arithmetic Logic Unit (ALU) is an important
building block of any computing systems. In this paper,
high speed and energy efficient architecture for ALU is
designed by using the concepts of Vedic mathematics. The
arithmetic operations such as addition, subtraction,