FPGA CPLD Based Designing

1FPGA/CPLD Based Designs

Vinay [email protected] logic Pvt. Ltd., Pune

2AgendaWorld of ElectronicsIntroduction to Programmable LogicCPLD

Working principle, Architecture, I/O Block, Macrocell, programming, features, examples.FPGA

Working principle, Architecture, I/O Block, CLB, embedded memory, clock management, DSP capability, programming, features, examples.

Comparison of CPLD / FPGA Architecture.VHDL and its examplesPLD Design flowTiming Aspects & analysis of PLDsLatest trends in PLD MarketDesign Consideration for PLDsAdvantages of PLDsPrototyping SolutionsConclusionQ & A

3World of Electronics

MasterMicroprocessor/Microcontroller

Communication InterfaceSerial, parallel, high speed, USB, irDA, PCI

Digital LogicFPGAs/CPLDs

MemorySRAM, FLASH, DRAM

Analog CircuitrySensors, Buffers,

amplifiers, ADC, DAC

Power ElectronicsSCRs, optical isolators,

relays, IGBT

DisplaysLCDs,LEDs

An Electronic System

4World of Integrated Circuits

Integrated Circuits

Full-CustomASICs

Semi-CustomASICs

UserProgrammable

PLD

FPGAPAL PLACPLD

Controllers

5Programmable LogicSince the invent of PLD from 1980s with few gate count, they have grown into million gates, so as there usage in different applications.

Advantages like programmability and reconfiguration of PLDs has given ideas and shape to many applications.

Todays PLDs like FPGAs can compete with ASICs in terms of performance and gate counts.

From the time their use has increased in all sectors, like defense, consumer, multi media, communications, DSP, etc.

6What is Available?CPLD (Complex Programmable Logic Device) consists of multiple PLA blocks that are interconnected to realize larger digital systems.

FPGA (Field Programmable Gate Array) has narrower logic choices and more memory elements. LUT (Lookup Table) may replace actual logic gates.

7CPLD Working Principle (SOP)

A B C

CBACBAf +=1

CBABAf +=2

AND plane

Programmable AND array followed by fixed fan-in OR gates

Programmable switch or fuse

8What is an CPLD ?Integration of several PLD blocks with a programmable interconnect on a single chip

PLDBlockPLD

BlockPLD

BlockPLD

Block

Interconnection MatrixInterconnection Matrix

I/O B

lockI/O

Block

I/O B

lockI/O

Block

PLDBlockPLD

BlockPLD

BlockPLD

Block

I/O B

lockI/O

Block

I/O B

lockI/O

Block

Interconnection MatrixInterconnection Matrix

9FPGA - Working Principle (LUT)Look-up table with N-inputs can be used to implement any combinatorial function of N inputsLUT is programmed with the truth-table

A B C D Z 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0

LUTLUTABCD

Z

Truth-table

A

B

C

D

Z

Gate implementation

LUT implementation

10

What is an FPGA ?FPGA building blocks:

Programmable logic blocksImplement combinatorial and sequential logic

Programmable interconnectWires to connect inputs and outputs to logic blocks

Programmable I/O blocksSpecial logic blocks at the periphery of device for external connections

I/O

I/O

Logic block Interconnection switches

I/O

I/O

11

CPLDArchitecture and Examples

12

CPLD Working Principle(SOP)

A B C

CBACBAf +=1

CBABAf +=2

AND plane

Programmable AND array followed by fixed fan-in OR gates

Programmable switch or fuse

13

CPLD StructureIntegration of several PLD blocks with a programmable interconnect on a single chip

PLDBlockPLD

BlockPLD

BlockPLD

Block

Interconnection MatrixInterconnection Matrix

I/O B

lockI/O

Block

I/O B

lockI/O

Block

PLDBlockPLD

BlockPLD

BlockPLD

Block

I/O B

lockI/O

Block

I/O B

lockI/O

Block

Interconnection MatrixInterconnection Matrix

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CPLD Example- Xilinx XC 9500JTAGcontroller In system Programming ControllerJTAG

port

15

Architecture Description

Each XC9500 device is a subsystem consisting of multipleFunction Blocks (FBs) Provides programmable logic capability with 36 inputs and 18 outputs.

I/O Blocks(IOBs) The IOBs provide buffering for device inputs and outputs.

FastConnect switch matrix. Connects all FB outputs and inputs signals to the FB inputs.

16

Function Block

GlobalSet/Reset

GlobalClocks

17

PLD - Macrocell

A B C

Flip-flop

SelectEnable

D Q

Clock

AND plane

MUX

1f

18

Set control

Programmableinversion or XORproduct term

Up to 5 product terms

Global clock or product-term clock

Reset control

OE control

Macrocell

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I/O Block

20

I/O Block

Interfaces between internal Logic and I/O Pins.IOB consists of an

Input Buffer Compatible with standard 5V volt CMOS, 5VTTL and 3.3 V signal

levels.Output Driver Capable of supplying 24 mA output drive.

Output enable selection multiplexer Can be generated from, A product term signal, Any of the global OE

signals User programmable ground control To reduce system noise generated from large number of

simultaneous switching outputs.

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CPLD Example - Altera MAX7000

EPM7000 Series Device Macrocell

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Technology UsedCPLDs are non-volatile devices, I.e retain the program after Power-off.The EPROM, EEPROM, FastFlash are the non-volatile type of memory.The FastFlash technology is used because of its advantage over the EEPROM.

High Performance Logic Device.High Memory cell densityElectrical erasableHigh reliability and enduranceFast device programming times

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Xilinx CPLD Product Portfolio

1.8V core1.5V - 3.3V I/O SSTL, HSTL, LVCMOS, LVTTLLower power DataGATE

Clocking features Clock Divide CoolCLOCK DualEDGE

2.5V core1.8V - 3.3V I/OLVCMOS, LVTTLI/O Banking

3.3V core2.7V - 5V I/OLVCMOS, LVTTLLow power Fast Zero Power

3.3V core2.5V - 5.0V I/OLVCMOS, LVTTL

24

Altera CPLD Products

25

FPGA Architecture and Examples

26

Block R

AM

s

Block R

AM

s

ConfigurableLogicBlocks

I/OBlocks

BlockRAMs

What is an FPGA?

27

FPGA Block Diagram

28

Other FPGA Building BlocksClock distributionEmbedded memory blocksSpecial purpose blocks:

DSP blocks: Hardware multipliers, adders and registers

Embedded microprocessors/microcontrollersHigh-speed serial transceivers

29

FPGA Basic Logic ElementLUT to implement combinatorial logicRegister for sequential circuitsAdditional logic (not shown):

Carry logic for arithmetic functionsExpansion logic for functions requiring more than 4 inputs

LUTLUT

Out

Select

D Q

ABCD

Clock

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FPGA - Working Principle (LUT)Look-up table with N-inputs can be used to implement any combinatorial function of N inputsLUT is programmed with the truth-table

A B C D Z 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0

LUTLUTABCD

Z

Truth-table

A

B

C

D

Z

Gate implementation

LUT implementation

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LUT ImplementationExample: 3-input LUTBased on multiplexers (pass transistors)LUT entries stored in configuration memory cells 0/10/1

0/10/1

0/10/1

0/10/1

0/10/1

0/10/1

0/10/1

0/10/1

X1X2

X3

F

Configuration memorycells

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CLB Contains Four LUTs (Slices)Each CLB is connected to one switch matrix

Providing access to general routing resources

CIN

SwitchMatrix

TBUFTBUF

COUTCOUT

Slice S0X0Y0

Slice S1X0Y1

Fast Connects

Slice S2X1Y0

Slice S3X1Y1

CIN

SHIFT

High level of logic integrationWide-input functions 16:1 multiplexer in 1 CLB or

any function 32:1 multiplixer in 2 CLBs

Fast arithmetic functions2 look-ahead carry chains per CLB column

Addressable shift registers in LUT16-b shift register in 1 LUT128-b shift register in 1 CLB (dedicated shift chain)

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Block RAM

Spartan-IIITrue Dual-Port

Block RAM

Port A

Port B

Block RAMMost efficient memory implementation

Dedicated blocks of memoryIdeal for most memory requirements

4 to 104 memory blocks 18 kbits = 18,432 bits per block

Use multiple blocks for larger memories

Builds both single and true dual-port RAMs

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Digital Clock Manager (DCM)Up to 12 DCMs per device

Located on top and bottom edges of the dieDriven by clock input pads

DCMs provide:Delay-Locked LoopDigital Frequency Synthesizer Digital Phase ShifterDigital Spread Spectrum

Multiple outputs of each DCM can drive onto global clock buffersAll DCM outputs can drive general routing

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Xilinx - 18 x 18 Embedded MultiplierEmbedded 18-bit x 18-bit multiplier

2s complement signed operationMultipliers are organized in columns

18 x 18 signed multiplierFully combinatorialOptional registers with CE & RST (pipeline)Independent from adjacent block RAM

18 x 18Multiplier

Output (36 bits)

Data_A (18 bits)

Data_B (18 bits)

4x4 signed ~255 MHz

8x8 signed ~210 MHz

12x12 signed ~170 MHz

18x18 signed ~140 MHz

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Altera: Embedded DSP BlocksTwo DSP Block columns per deviceNumber varies by height of columnCan implement:

Eight 9x9 multipliersFour 18x18 multipliersOne 36x36 multiplier

Contains adder/subtractor/accumulatorRegistered inputs can become shift register

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Altera: Embedded DSP Block

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Input/Output Blocks (IOBs)IOB provides interface between the package pins and CLBsEach IOB can work as uni- or bi-directional I/OOutputs can be forced into High ImpedanceInputs and outputs can be registered

Advised for high-performance I/OInputs can be delayed

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Basic I/O Block Structure

DEC

Q

SR

DEC

Q

SR

DEC

Q

SR

Three-StateControl

Output Path

Input Path

Three-State

Output

Clock

Set/Reset

Direct Input

Registered Input

FF Enable

FF Enable

FF Enable

What more?

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Spartan-3 I/O PinStorage Element FunctionsDouble-Data-Rate TransmissionSlew Rate Control and Drive StrengthPull-Up and Pull-Down ResistorsDigitally Controlled Impedance (DCI)Keeper CircuitESD ProtectionSelectIO Signal Standards

41

Spartan-3 I/O Pin

Output Path

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Spartan-3 I/O Pin

Input Path

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Programmable InterconnectInterconnect hierarchy

Fast local interconnectHorizontal and vertical lines of various lengths

LE

LE

LE

LE

LE

LE

LE

LE

LE

LE

LE

LE

SwitchMatrix

Switch Matrix

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Switch Matrix Operation

6 pass transistors per switch matrix interconnect pointPass transistors act as programmable switchesPass transistor gates are driven by configuration memory cells

After ProgrammingBefore Programming

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Configuration Storage ElementsStatic Random Access Memory (SRAM)

each switch is a pass transistor controlled by the state of an SRAM bitFPGA needs to be configured at power-on

Flash Erasable Programmable ROM (Flash)each switch is a floating-gate transistor that can be turned off by injecting charge onto its gate. FPGA itself holds the programreprogrammable, even in-circuit

Fusible Links (Antifuse)Forms a forms a low resistance path when electrically programmedone-time programmable in special programming machine radiation tolerant

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FPGA Programming/ConfigurationConfiguration is process of loading design and device specific bit-stream into one or more FPGAs.

Volatile nature of FPGA makes the configuration considerations important because the configuration is required on each power-on.

FPGAs can be programmed from PC via programming cable or the programming file(BIT file) can be stored in a PROM.

Take care of other system modules during FPGA configuration.

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FPGA Programming/Configuration

48

Major FPGA VendorsSRAM-based FPGAs

Xilinx, Inc.Altera Corp.AtmelLattice Semiconductor

Flash & antifuse FPGAsActel Corp.Quick Logic Corp.

Share over 80% of the market

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FPGA Vendors & Device FamiliesXilinx

Virtex-II/Virtex-4: Feature-packed high-performance SRAM-based FPGASpartan 3: low-cost feature reduced versionCoolRunner: CPLDs

AlteraStratix/Stratix-II High-performance SRAM-based

FPGAsCyclone/Cyclone-II Low-cost feature reduced

version for cost-critical applications

MAX3000/7000 CPLDsMAX-II: Flash-based CPLDs

ActelAnti-fuse based FPGAs Radiation tolerant

Flash-based FPGAsLattice

Flash-based FPGAsCPLDs (EEPROM)

QuickLogicViaLink-based FPGAs

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Xilinx FPGA FamiliesOld families

XC3000, XC4000, XC5200Old 0.5m, 0.35m and 0.25m technology. Not recommended for modern designs.

High-performance familiesVirtex (0.22m)Virtex-E, Virtex-EM (0.18m)Virtex-II, Virtex-II PRO (0.13m)Virtex-4 (0.09m)

Low Cost FamilySpartan/XL derived from XC4000Spartan-II derived from VirtexSpartan-IIE derived from Virtex-ESpartan-3 derived from Virtex-II

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Altera FPGA FamiliesOld Families

FLEX 10K, FLEX 6000, FLEX 8000

High-performance FamiliesMercuryStratix, Stratix GX, Stratix IIAPEX 20K , APEX IIExcalibur

Low Cost FamilyCyclone, Cyclone II

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Comparison of CPLD / FPGA Architecture

53

CPLD Vs FPGA

Interconnect structure.

In-system performance.

Logic Utilization.

Applications.

54

Interconnect StructureCPLD uses a Continuous interconnect structure :

Consists of metal lines of uniform length traverse the entire length and width of the device.Since the resistances and capacitances of all interconnect paths is fixed, delays between any two logic cells can be predictable.This minimizes the logic skew.

FPGA uses a segmented interconnect structure. Consists of matrix of metal interconnects that run throughout the device. Switch matrices or Antifuses join the ends of these segments allowing signals to travel between logic cells.Number of segments required to interconnect signals is neither constant nor predictable, so delays are not fixed or specified until place and route is completed.

55

Logic UtilizationLogic cells in most FPGA architecture have fine granularity, therefore more logic cells are required to implement a function in FPGA than in a CPLD.

Logic cells in FPGA can contain only small portion of a design, so a heavy burden is placed on its segmented interconnect structure.

As design complexity increases, the probability of routing conflicts also increases leading to lower FPGA device utilization.

Logic density in FPGA is less due to only 9 variables, where as CPLD has 36 variables available.

56

Applications - FPGAsFPGAs

Basically register intensive applications.Data paths.Hardware Emulation.Image controller.Battery powered applications.Field-test equipments.Gate-array prototyping.

57

Applications - CPLDsCPLDs

Basically combinatorial functions.Bus interfacings.Comparators.High-speed wide decoders.Large fast state micro controllers.High speed GLUE Logic.System video controller.PAL integration.

58

VHDL and its examples.

59

VHDL LanguageHardware Description Language (HDL)

High-level language for to model, simulate, and synthesize digital circuits and systems.

History1980: US Department of Defense Very High Speed Integrated Circuit program (VHSIC)1987: Institute of Electrical and Electronics Engineers ratifies IEEE Standard 1076 (VHDL87)1993: VHDL language was revised and updated

Verilog is the other major HDLSyntax similar to C language

Many tools accept both Verilog and VHDL

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TerminologyBehavioral modeling

Describes the functionality of a component/systemFor the purpose of simulation and synthesis

Structural modelingA component is described by the interconnection of lower level components/primitivesFor the purpose of synthesis and simulation

Synthesis:Translating the HDL code into a circuit, which is then optimized

Register Transfer Level (RTL):Type of behavioral model used for instance for synthesis

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Digital Circuits and VHDL PrimitivesMost digital systems can be described based on a few basic circuit elements:

Combinational Logic Gates: NOT, OR, AND

Flip FlopLatchTri-state Buffer

Each circuit primitive can be described in VHDL and used as the basis for describing more complex circuits.

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Digital Circuit PrimitivesCombinational Logic Gates: NOT, OR, ANDFlip Flop/LatchTri-state BufferLogic gates can be modeled using concurrent signal assignments:

Z

63

4-to-1 Multiplexer

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity mux isport (

a, b, c, d: in std_logic;s: in std_logic_vector(1 downto 0);y: out std_logic);

end entity mux;

architecture mux1 of mux isbegin

process (a, b, c, d, s)begincase s is

when "00 => y y y y

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Sequential Logic: D-Flip Flop

architecture rtl of D_FF isbeginprocess (Clock, Reset) isbegin

if Reset = 1 thenQ

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Binary Counter

This example is not explicit on the primitives that are to be used to construct the circuit. The + operator is used to indicate the increment operation.

entity counter isgeneric (n : integer := 4); port (

clk : in std_logic;reset: in std_logic;count: out std_logic_vector(n-1 downto 0)

);end entity counter;

entity counter isgeneric (n : integer := 4); port (

clk : in std_logic;reset: in std_logic;count: out std_logic_vector(n-1 downto 0)

);end entity counter;

use ieee.numeric_std.all;

architecture binary of counter isSignal cnt : std_logic_vector(n-1 downto 0);begin

process (clk, reset)begin

if reset = '1' then -- async reset

cnt '0');elsif rising_edge(clk) then

cnt

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State Machine

If a trigger signal is received, will stretch it to 2 cycles and wait for accept signal

entity trigger isport (

clk, reset: in std_logic;trigger, accept : in std_logic; active: out std_logic);

end entity trigger;

architecture rtl of trigger istype state_type is (s0, s1, s2);signal cur_state,

next_state: state_type;begin

registers: process (clk, reset)begin

if (reset='1') then cur_state

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State Machine (cont.)process (cur_state, trigger,

accept) isbegin

case cur_state iswhen s0 =>

active

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PLD Design flow

69

FPGA Design Flow

Synthesis Translate Design into Device Specific Primitives Optimization to Meet Required Area & Performance Constraints

Design Specification

Place & Route Map Primitives to Specific Locations inside

Target Technology with Reference to Area & Performance Constraints Specify Routing Resources to Be Used

Design Entry/RTL CodingBehavioral or Structural Description of Design

LEMEM I/O

RTL Simulation Functional Simulation Verify Logic Model & Data Flow (No Timing Delays)

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FPGA Design Flow

Timing Analysis- Verify Performance Specifications Were Met- Static Timing Analysis

Gate Level Simulation- Timing Simulation- Verify Design Will Work in Target Technology

Program & Test- Program & Test Device on Board

tclk

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Specifications

Functional Simulation

Logic Synthesis

Design Entry

Static Timing Analysis

System partitioning and Floor-planning

Placement and RoutingPost-Layout Simulation

Programming

Production

Pre-Layout Simulation

Synth. Lib

Constraints

Timing Lib.

Design Flow

Static Timing Analysis

Test Bench

Sch, VHDL, Verilog

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EDA Tools : Altera Quartus IIFully integrated design tool

Multiple design entry methods Text-based: VHDL, Verilog,

AHDL Built-in schematics editor

Logic synthesisPlace & routeSimulation Timing & power analysisCreate netlist for timing simulationDevice programming

Xilinx ISE has similar kind of features

73

Timing Aspects & Analysis of PLDs

74

Timing IssuesBasic Questions

Does my design meet a given timing requirement, orHow fast I can run the design?Are there any chances of failures?

We know about nominal delay simulation; why not use it..?Requires too many patterns.Increases exponentially with the number of design inputs.Even worse if we consider sequences needed to initialize latches.

So what we do instead..??Separate function from time,Determine when transitions occur without worrying about how.

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Timing IssuesThe basic idea of Static Timing Analysis is,

To find that the data is transferred through the system safely.Instead of considering an infinitely long simulation sequence, fold all possible transitions back into a single clock cycle.If the design is working extremes, we can guarantee it always will.Static part just means we arent doing simulation (dynamic).

AB

C D

Clock rate?Data rate?

76

FPGAs - Fmax

All in MHz

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Synchronous or Asynchronous Synchronous designs have a clock that determines when signals should be sampled. The signals are either sampled at the rising edge or at the falling edge of the clock.

Unit of Time is Fixed

Asynchronous designs do not operate with a clock. Relies on handshaking between logic. Sensitive to glitches and ordering of signals.

Unit of Time is NOT Fixed

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Why Synchronous?Signals are sampled at well- defined time intervals.

Interfacing two synchronous blocks is simple. Interfacing asynchronous blocks is not simple.

Synthesis and other tools does not handle asynchronous logic very well.

FPGAs are NOT good for Asynchronous designs.

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What is the MAXIMUM frequency of operation for above system?

Maximum Frequency = 1/ (longest delay path I.e. Critical Path)

Timing Issues

CombinationalLogicCircuit

n m

K k

k-bitPresent State

Value

k-bitNext State

Value

clk

DFFDQ

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How To Improve Speed?The register-to-register delay is usually the delay path that sets the maximum clock rate.

From a design point of view,one can only affect the combinational logic between the registers

Need to shorten the maximum combinational delay pathSetup/Hold time of registers are fixed

Can shorten the delay by placing a register in the combinational logic to break longest delay path

This technique is called pipeliningAdds latency to the output (the number of clocks between an input value and its corresponding output result)

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Latest trends in PLD Market

82

Fight of Titans

83

State of the Art in FPGAs90 nm process on 300 mm wafers

Lower cost per function (LUT + register)Smaller and faster transistors: Higher speed

System speed up to 500 MHzMainly through smart interconnects, clock management, dedicated circuits, flexible I/O. Integrated transceivers running at 10 Gigabits/sec

More Logic and Better Features:>100,000 LUTs & flip-flops>200 embedded RAMs, and same number 18 x 18 multipliers

1156 pins (balls) with >800 GP I/O50 I/O standards, incl. LVDS with internal termination

16 low-skew global clock linesMultiple clock management circuits

On-chip microprocessor(s) and multi-Gbps transceivers

84

Latest Devices: Capacity & FeaturesXilinx Virtex-4

90nm processUp to 960 I/Os>2,00,000 logic cellsUp to 552 18kb block RAMs (~10Mb RAM)192 DSP slices (18x18 multiplier-accumulator)20 digital clock managers (DCM)24 high-speed serial transceivers (622Mb/s to 11.1Gb/s)Up to four PowerPC 405 cores

Altera Stratix-II90nm processUp to 1170 I/Os1,79,000 logic elements9.6Mb embedded RAM96 DSP blocks: 380 18x18 multipliers12 PLLsSerial I/O up to 1Gb/sNo hard processor cores

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Design Consideration for PLDs

86

Designing with FPGAA complete flat land (logic elements, memory, gates).No predefined architecture or controllers.Generation of timings and timing match.Control of bus.Handshaking of signals.Protocol development.Verification of logic.User to describe complete logic with HDLs.Logic dependant on ..HDL..HDL..HDL

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Designing with FPGA

FPGAMemories

Microcontroller

Analog Circuits

Communication

Peripherals

Handshaking

Timing

Voltage Levels

Protocols, Speed

Bus Control, triggering

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Advantages of PLDs

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Why to go for PLDs ?Flexibility.In system programmability.Less project development time.Best prototyping solution.Cost effective solutions.Involves less risk.Design security. Consumes less board area.Reconfigurable computing.Best suits hardware verification for design.

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Prototyping Solutions

91

Prototyping Solutions

A system model to test and develop the product before its final implementation.

Prototyping is like headache to designersEase of prototyping is necessityFlexibility is mustIndividual eval boards or kits available

Need for universal platform integrationModular approachUp gradation and addition of modules at regular interval.

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Prototyping Boards

Multi-vendor device support for Xilinx and AlteraPLDs.

All FPGA I/Os accessible through headers.

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Prototyping Boards

A universal platform for various technologiesAn excellent prototyping and system development platformModular approachModules can be integrated according to needsFlexible and easy up gradation

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Prog. Port

FPGA

FPGA

ModulesConfiguable I/Os

7 Seg Disp,LCD interface

Box Osc.

One Platform

Keypad Interface

SRAM89c51PIC uC

ADC/DAC..more

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Embedded System Development.High-Resolution Image Processing.High speed Digital Signal Processing.NIOS-II/ Microblaze Soft Processor Development.USB / LAN based application development.Process Control, automation and Industrial SystemsUniversal Prototyping Platform.

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ConclusionPLDs are

CheaperFasterBiggerMore versatileand easier to use

And obviously best choice for the system designer.

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Thank You..!

ni logic Pvt. Ltd.,Email: [email protected]

URL: www.ni2designs.com