Chapter 1 INTRODUCTION TO FPGA 1.1 INTRODUCTION An FPGA is a device that contains a matrix of reconfigurable gate array logic circuitry. When a FPGA is configured, the internal circuitry is connected in a way that creates a hardware implementation of the software application. Unlike processors, FPGAs use dedicated hardware for processing logic and do not have an operating system. FPGAs are truly parallel in nature so different processing operations do not have to compete for the same resources. As a result, the performance of one part of the application is not affected when additional processing is added. Also, multiple control loops can run on a single FPGA device at different rates. FPGA-based control systems can enforce critical interlock logic and can be designed to prevent I/O forcing by an operator. However, unlike hard-wired printed circuit board (PCB) designs which have fixed hardware resources, FPGA-based systems can literally rewire their internal circuitry to allow reconfiguration after the control system is deployed to the field. FPGA devices deliver the performance and reliability of dedicated hardware circuitry. A single FPGA can replace thousands of discrete components by incorporating millions of logic 1
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Chapter 1
INTRODUCTION TO FPGA
1.1 INTRODUCTION
An FPGA is a device that contains a matrix of reconfigurable gate array logic
circuitry. When a FPGA is configured, the internal circuitry is connected in a way that
creates a hardware implementation of the software application. Unlike processors,
FPGAs use dedicated hardware for processing logic and do not have an operating
system. FPGAs are truly parallel in nature so different processing operations do not
have to compete for the same resources. As a result, the performance of one part of
the application is not affected when additional processing is added. Also, multiple
control loops can run on a single FPGA device at different rates. FPGA-based control
systems can enforce critical interlock logic and can be designed to prevent I/O forcing
by an operator. However, unlike hard-wired printed circuit board (PCB) designs
which have fixed hardware resources, FPGA-based systems can literally rewire their
internal circuitry to allow reconfiguration after the control system is deployed to the
field. FPGA devices deliver the performance and reliability of dedicated hardware
circuitry. A single FPGA can replace thousands of discrete components by
incorporating millions of logic gates in a single integrated circuit (IC) chip. The
internal resources of an FPGA chip consist of a matrix of configurable logic blocks
(CLBs) surrounded by a periphery of I/O blocks. Signals are routed within the FPGA
matrix by programmable interconnect switches and wire routes. The design and
implementation of FPGA based Arithmetic Logic Unit is of core significance in
digital technologies as it is an integral part of central processing unit. ALU is capable
of calculating the results of a wide variety of basic arithmetical and logical
computations. The ALU takes, as input, the data to be operated on (called operands)
and a code, from the control unit, indicating which operation to perform. The output is
the result of the computation. Designed ALU will perform the following operations:
• Arithmetic operations
• Bitwise logic operations
1
All the modules described in the design are coded using VHDL which is a very
useful tool with its degree of concurrency to cope with the parallelism of digital
hardware. The top level module connects all the stages into a higher level at Register
Transfer Logic (RTL). RTL describes the requirements of data and control units in
terms of digital logic to execute the desired operations. Each instruction from the
architecture's instruction set is defined in detail in the RTL Once identifying the
individual approaches for input, output and other modules, the VHDL descriptions are
run through a VHDL simulator and then is downloaded the design on FPGA board for
verification.
FIGURE 1.1: Internal Structure of FPGA
In an FPGA logic blocks are implemented using multiple level low fan-in gates,
which gives it a more compact design compared to an implementation with two-level
AND-OR logic. FPGA provides its user a way to configure:
1. The intersection between the logic blocks and
2. The function of each logic block.
Logic block of an FPGA can be configured in such a way that it can provide
functionality as simple as that of transistor or as complex as that of a microprocessor.
It can used to implement different combinations of combinational and sequential logic
functions. Logic blocks of an FPGA can be implemented by any of the following:
2
Transistor pairs, combinational gates like basic NAND gates or XOR gates, N -input
Lookup tables, Multiplexers, Wide fan-in And -OR structure.
Routing in FPGAs consists of wire segments of varying lengths which can be
interconnected via electrically programmable switches. Density of logic block used in
an FPGA depends on length and number of wire segments used for routing. Number
of segments used for interconnection typically is a tradeoff between density of logic
blocks used and amount of area used up for routing. Simplified version of FPGA
internal architecture with routing.
FIGURE 1.2: Simplified Internal Structure of FPGA
1.2 Why do we need FPGAs? By the early 1980’s large scale integrated circuits (LSI) formed the back bone of most
of the logic circuits in major systems. Microprocessors, bus/IO controllers, system
timers were implemented using integrated circuit fabrication technology. Random
“glue logic” or interconnects were still required to help connect the large integrated
circuits in order to: 1. Generate global control signals (for resets etc.) 2. Data signals
from one subsystem to another sub system. Systems typically consisted of few large
scale integrated components and large number of SSI (small scale integrated circuit)
and MSI (medium scale integrated circuit) components. Initial attempt to solve this
problem led to development of Custom ICs which were to replace the large amount of
3
interconnect. This reduced system complexity and manufacturing cost, and improved
performance. However, custom ICs have their own disadvantages. They are relatively
very expensive to develop, and delay introduced for product to market (time to
market) because of increased design time. There are two kinds of costs involved in
development of custom ICs 1. Cost of development and design 2. Cost of manufacture
(A tradeoff usually exists between the two costs) Therefore the custom IC approach
was only viable for products with very high volume, and which were not time to
market sensitive. FPGAs were introduced as an alternative to custom ICs for
implementing entire system on one chip and to provide flexibility of re programibility
to the user. Introduction of FPGAs resulted in improvement of density relative to
discrete SSI/MSI components (within around 10x of custom ICs). Another advantage
of FPGAs over Custom ICs is that with the help of computer aided design (CAD)
tools circuits could be implemented in a short amount of time (no physical layout
process, no mask making, no IC manufacturing)
4
Chapter 2
IMPLEMENTATION TOOL
2.1 INTRODUCTION TO SPATRAN 3
FIGURE 2.1: SPARTAN 3 FPGA
The Spartan s3E family of Field-Programmable Gate Arrays (FPGAs) is specifically
designed to meet the needs of high volume, cost-sensitive consumer electronic
applications. The five-member family offers densities ranging from 100,000 to 1.6
million system gates, as shown in Table 1. The Spartan-3E family builds on the
success of the earlier Spartan-3 family by increasing the amount of logic per I/O,
significantly reducing the cost per logic cell. New features improve system
performance and reduce the cost of configuration. These Spartan-3E FPGA
enhancements, combined with advanced 90 nm process technology, deliver more
functionality and bandwidth per dollar than was previously possible, setting new
standards in the programmable logic industry. Because of their exceptionally low
cost, Spartan-3E FPGAs are ideally suited to a wide range of consumer electronics
applications, including broadband access, home networking, display/projection, and
5
digital television equipment. The Spartan-3E family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost, the lengthy development
cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA
programmability permits design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
2.2 POWER SUPPLYThe power supply to FPGA is given through the port shown below
FIGURE 2.2: Power Cable
2.3 JTAG CABLEJoint Text Action Loop Cable is used to transfer the data into the FPGA where it is to
be burnt and verified.
6
FIGURE 2.3: JTAG Cable
2.4 Spartan 3 Pin ConfigurationXC3S400_PQ208 is the main IC in the FPGA and has 208 pins ,52 on each side. The
figure below shows the pin configuration.
FIGURE 2.4 : XC3S400_PQ208 Pin Configuration
7
CHAPTER 3
IMPLEMENTATION OF 8 BIT ALU USING FPGA
3.1 VHDL CODE OF 8 BIT ALU
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_BIT.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity testpinbus is
Port ( move_up, move_down, clk : in STD_LOGIC;
A, B : in std_logic_vector (7 downto 0);
C : out std_logic_vector (7 downto 0);
lcd_rw : out std_logic; ---read&write control
lcd_e : out std_logic; ----enable control
lcd_rs : out std_logic; ----data or command control
data : out std_logic_vector(7 downto 0); ---data line
sel: inout STD_LOGIC_VECTOR (3 downto 0));
end testpinbus;
8
architecture Behavioral of testpinbus is
signal c1 : integer range 0 to 350000;
constant N: integer :=22;
type arr is array (1 to N) of std_logic_vector(7 downto 0);