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863
INDEX
Note: Page numbers for defining references are given in color.
- (ABEL subtraction) 253- (Verilog subtraction) 301- (VHDL subtraction) 488* (ABEL multiplication) 497* (optional sections) xvi* (Verilog multiplication) 301* (VHDL multiplication) 502∗ suffix 544, 546+ (ABEL addition) 253, 719+ (Verilog addition) 301+ (VHDL addition) 488⊕, Exclusive OR symbol 234, 447.AP suffix, ABEL 612.AR suffix, ABEL 612.C. symbol, ABEL 622.CLK suffix, ABEL 612.FB suffix, ABEL 616, 617.OE suffix, ABEL 424, 612.PIN suffix, ABEL 617.Q suffix, ABEL 617.SP suffix, ABEL 612.SR suffix, ABEL 612.X. symbol, ABEL 245/ (Verilog division) 301/= (VHDL inequality) 276, 466/ prefix, ABEL 244:, in bus name 359
:= (ABEL clocked assignment) 612
:= (VHDL variable assignment) 280
:> (ABEL clocked truth-table operator) 613
< (ABEL less than) 253< (Verilog less than) 304< (VHDL less than) 276<< (Verilog shift left) 301<= (ABEL less than or equal) 253<= (Verilog less than or equal) 304<= (Verilog nonblocking
assignment) 315<= (VHDL less than or equal) 276<= vs. =, Verilog 316= (ABEL unclocked assignment)
2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.
2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.
2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.
866 Index
ABEL (continued)<= (less than or equal) 253== (equality) 253= operator 248= unclocked assignment 246> (greater than) 253>= (greater than or equal) 253@ALTERNATE directive 245@CARRY directive 488^b binary prefix 253^h hexadecimal prefix 253{} (equation-block delimiters)
2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.
Index 867
addition 32ABEL 719Verilog 301
address hold time 826address input 800address setup time 826adjacency diagram 605adjacent states 606advanced courses xviAdvanced Micro Devices (AMD)
2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.
868 Index
automatic test-pattern-generation program 625, 644, 662
auto-refresh cycle, SDRAM 839axiom 185
Bbaby from hell 5back annotator 240back-end design process 242–243Bakeman, Ken xxiiibalanced code 71bank, DRAM 834barrel shifter 516base, number system 26base, transistor 158basis step 190Baylis, John 74^b binary prefix, ABEL 253BCD (binary-coded decimal) 48BCD addition 50BCD code 384, 408BCD decoder 386begin-end block, Verilog 317begin keyword, Verilog 317begin keyword, VHDL 258behavioral description, Verilog 312behavioral description, VHDL 278behavioral design, Verilog
84, 158–160bipolar logic family 85bipolar PAL devices 703bipolar PROM 810Bipolar Return-to-Zero (BPRZ) 72bipolar ROM 808biquinary code 50bird 571Birkner, John 508bistable 523–526, 590bit 26, 80bit_vector type, VHDL 260bit cell 69bit line 804bit rate 69bit select, Verilog 300bits per second 69bit time 69bit type, VHDL 260bit vector, Verilog 295, 299–302
bitwise boolean operators, Verilog 295
BJT (bipolar junction transistor) 84, 158–160
Blake, Gary 508block, Verilog 317block diagram 343, 344, 355, 357,
438, 11blocking assignment operator,
Verilog = 315blocking assignment statement,
Verilog 315, 331, 648blocking vs. non-blocking
assignments, Verilog 648, 755
Bly, Robert W. 508board-level design 22Bolton, Martin 789BOM (bill of materials) 343Boole, George 184, 229boolean, VHDL 261Boolean algebra 184, 229
See also switching algebraboolean operators, Verilog 295boolean reduction operators,
Verilog 302boolean type, VHDL 260boolean vs. logical, Verilog 304bootstrap ROM module 805borrow 32, 43, 476boundary inputs, iterative-circuit
459, 756boundary outputs, iterative-circuit
459, 756boxed comments xviiiBPRZ (Bipolar Return-to-Zero) 72bps 69branching method 221Brown, Charlie 526Brusaw, C. T. 508bubble 83, 90bubble-to-bubble logic design
351–353, 389, 390, 438, 448
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reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.
case statement, ABEL 614case statement, Verilog 310, 321,
404full 322parallel 321
case statement, VHDL 282casex keyword, Verilog 323casex statement, Verilog 323
casez keyword, Verilog 323casez statement, Verilog 323CAS latency 837cathode 156causality 362, 527CCD (charge-coupled device) 822CD (compact disc) 4, 81CD-R (writeable compact disc) 81ceiling function 53central office (CO) 4central processing unit (CPU) 799Chandrakasan, A. 174, 508Chaney, Thomas J. 775, 789character, VHDL 260, 261characteristic equation 540, 544,
550, 551, 564, 578characteristic impedance 182charge-coupled device (CCD) 822charge pump 812Charlie Brown 526check bits 60checksum 68checksum code 68chip 6chip-select (CS) input 813chip-select setup time 826chip viewer 240chip vs. IC 12Chua, H. T. 508Ciletti, Michael D. 336CINmax 146circle 548circuit description 184, 343circuit specification 342circular reasoning 559circular shift 748Cisco Systems iii, xxiiiCL 123clamp diode 153, 160Clare, Christopher R. 664Clark Kent 526
2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.
870 Index
CLB (configurable logic block) 850–854
clear input 527, 533, 680clock 7, 522, 523
distribution 172frequency 522gated 765–767in synchronous system 758jitter 684period 522recovery 740skew 683, 684, 759, 766tick 522, 542
CMOS vs. TTL 85CO (central office) 4Coburn, James 73code 48–56, 384coded state 560, 572, 605coded states 606code rate 78code word 48coding 241coding style
combinational multiplier 494combinational vs. combinatorial
376combination lock 568combination-lock state machine
620, 623, 637, 656combining theorem 189, 211com keyword, ABEL 244comma in Verilog sensitivity list
314command input 760comments
ABEL 244Verilog 293VHDL 258
committee, designed by 629common-emitter configuration 159common-mode signal 172communication 3, 344commutative law 188compact disc (CD) 4, 81, 816compact-disc player 799companded encoding 816comparators 319, 326, 458–473,
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reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.
Index 871
complement 186of a logic expression 192
complementary MOS See CMOScomplement number system 35complete set 233complete sum 218, 229, 236complex programmable logic
current spikes 124current-state-variables, ABEL 618custom LSI 16custom VLSI 381cut off (OFF) 159cut set 594CV2f power 123, 142
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reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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872 Index
cyclic-redundancy-check (CRC) code 65
Cypress Semiconductor 775, 789
Ddata bit 364dataflow description, Verilog
310–312dataflow description, VHDL
275–278dataflow design, Verilog 310–312dataflow design, VHDL 275–278data hold time 826Data I/O Corporation 243data output 800data setup time 826data sheet 98
CMOS 98–100TTL 166
data unit 759dating 208DC balance 71, 740DC fanout 111DC load 103, 116, 149, 763DC noise margin 97, 103, 112, 169
HIGH-state 148LOW-state 148TTL 164
DC noise margin, TTL 165DDPPonline xvi, xxi–xxii, 3dead time 419deassert 348debounce 688debugging 3, 113decade counter 716decade counting 725decimal codes 48–51decimal counter 725decimal decoder 386decimal point 26decimal-to-radix-r conversion 30decision window 772declarations, ABEL 244, 245
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reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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740error model 58errors in this book xxiiESD See electrostatic dischargeEspresso-II 224Espresso-MV 224essential hazard 609, 697, 762essential prime implicant 219Ethernet 740, 778, 779
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reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.
See also GAL devicegeneric constant, VHDL 274generic declaration, VHDL 274generic keyword, VHDL 274generic map, VHDL 274genvar keyword, Verilog 310Ghausi, M. 174giga- (G) 72gigabit Ethernet 171glitch 224, 373, 717, 735, 736, 766glue ICs 13Goldstine, Herman H. 229Golson, Steve 664Google xxiii, 12goto statement, ABEL 614
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reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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HDL text editor 9, 239Hellerman, Herbert 522helper output, PLD 395helper terms 375, 376Hennie, Frederick C. 664henries 124hertz 69hertz (Hz) 69hexadecimal addition 34hexadecimal digits A–F 27hexadecimal number system 27–29hexadecimal prefix ^h, ABEL 253hexadecimal-to-binary conversion
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reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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JJackson, Tom 859Jacobs, Joanne v, xxivJain, Prem xxiiiJ-K flip-flop 553J-K flip-flop 686job xviiJohnson, Howard 174, 790Johnson counter 735
self-correcting 736Joint Photographic Experts Group
(JPEG) 4joke 522
really bad 588joule 145JPEG (Joint Photographic Experts
Group) 4JTAG port 383juxtaposition 187
KK (kilo-) 72Karnaugh map 212
5-variable 235, 5646-variable 236
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reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.
878 Index
Karnaugh, M. 230Kaufman, Jennie xxiiiKent, Clark 526keywords, Verilog 293keywords, VHDL 258kilo- (K) 72Kleeman, Lindsay 789Klir, George J. 174kludge 766Knuth, Donald E. 73, 376Kohavi, Zvi 230, 664, 788
L_L suffix 387, 390laboratory courses xviLáng, Tomas 73larger-scale logic element 349,
TTL) 160, 689LOW-state DC noise margin 148LOW-state fanout 111, 148
TTL 165
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reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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metastability resolution time 771metastable state 525, 769metatheorem 193Michels, Diana 12Michelson, A. M. 74, 788microampere 88microampere (uA) 88Micron Technology 859
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reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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646, 702neg keyword, ABEL 248nerds 185, 230nested expansion formula 30nested if statement, Verilog 318nested when statement, ABEL 250nesting, if-then-else, ABEL
616net, Verilog 296net declaration, Verilog 296net list 242, 273, 306nets vs. variables, Verilog 297–298next-state function 545next-state logic 542
VHDL 628next-state logic, Verilog 649next statement, VHDL 283next-state-variables, ABEL 618
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Ooctal 421, 692octal number system 27–29octal-to-binary conversion 28odd-parity circuit 448odd-parity code 60off-set 199"off" transistor 87Ohm’s law 100Oliu, W. E. 508one-hot state assignment 562
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reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.
884 Index
programmable switch matrix (PSM) 857
programmer vs. logic designer 344programming 349
CPLD 382EEPLD 381EEPROM 811EPROM 810FPGA 382mask ROM 809PROM 809
programming and state machines 555
programming an EPROM 810–812programming voltage, EEPROM
QQDR SSRAM 832quad-data-rate (QDR) SSRAM 832quad gate 98quadruple gate 98quantizing distortion 817quiescent power dissipation 122Quine, W. V. 223, 229Quine-McCluskey algorithm 223Q vs. QN 592, 669Q vs. QN 528
RRaaum, Dave xxiii, 325, 339Rabaey, J. M. 174, 508race 596, 605, 758race-free state assignment 605–608radix 26radix-complement system 35radix point 26, 35radix-r-to-decimal conversion 29RAID (redundant array of
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reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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736self-correcting ring counter 733self-documenting code 682self-dual logic function 234self-timed systems 789semicolon, Verilog 317semiconductor diode 84, 156semicustom IC 16sense amplifier 834sensitivity list
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reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.
Index 887
stable total state 592, 603standard cell 16, 342standard-cell design 16standard logic package, IEEE 1164
343Strunk, William, Jr. 508subcube 58submachine 587subtraction 32subtraction, Verilog 301subtractor 474
full 476subtractors 476–478
See also adderssubtrahend 32, 32subtype, VHDL 262, 427subtype keyword, VHDL 261suggestive drawings 550sum bit 478sum-of-products expression 189,
193, 197, 201, 204, 207, 208, 209
sum term 197Sunnyvale, California 5Superman 526surface-mount technology (SMT)
17suspended statement, Verilog 312suspended VHDL process 279switch 687switch debouncing 687–689
2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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888 Index
switching, simultaneous 126, 127, 128
switching algebra 184, 185–199, 229
adding out 189ambiguous expression 188associative law 188binary operator 189combining theorem 189commutative law 188consensus theorem 190cover 189covering theorem 189DeMorgan’s theorem 190distributive law 189duality 193expression 186, 187juxtaposition 187multiplying out 189parenthesization 188precedence 187, 193theorem 188
365, 593, 597, 775template generator 240temporary failure 58tera- (T) 72termination 103, 182test_vectors, ABEL 245test_vectors keyword, ABEL
253test bench 10, 240, 241, 336
Verilog 294, 326, 506, 648, 659–662
VHDL 279, 285, 287–289, 628, 641–644
test enable (TE) 536testing 535, 536, 623test input, TI 536test-input generation 740test vectors 383, 625, 644, 662
ABEL 245, 253–255, 622Texas Instruments 508, 775, 788,
789, 859text 53
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Index 889
text editor, HDL 239tf 115T flip-flop 541, 711, 713, 727
with enable 541tH 708theorem, switching algebra 188The Phone Company (TPC) 4, 72,
73Thévenin equivalent 104Thévenin resistance 104Thévenin termination 182Thévenin voltage 104three-state buffer 132, 418–424three-state bus 132, 690
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890 Index
transition frequency 122, 145transition list 576–580, 680transition p-term 577transition-sensitive media 71transition statement 614transition s-term 579transition table 547, 552, 563, 591transition time 97, 115–120, 131
279variables vs. nets, Verilog 297–298variables vs. signals, VHDL 752
2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
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2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.
Index 893
Verilog (continued)test bench 326, 659–662three-state bus 431three-state output 430$time function 329time keyword 330time scale 330`timescale directive 330timing control 325–326,
330–331tri net type 296true 303unary minus 301unary plus 301variable 297variable declaration 297variables vs. nets 297–298vector 295, 299–302vector net 296vector padding 300vector variable 297vs. VHDL 295, 302, 310, 418while statement 325wire net type 296$write task 329z bit value 323
2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
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894 Index
VHDL (continued)generic map clause 274identifiers 258IEEE 1164, standard logic
VHDL-1987 256, 336VHDL-1993 256, 336VHDL-2002 256, 336VHSIC (Very High Speed
Integrated Circuit) 256VIHmin 102, 147
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Index 895
VIHmin , TTL 162VILmax 102, 146VILmax, TTL 164VLSI See very large-scale
Wwafer 11wait statement, VHDL 285Wakerly, John F. xxiv, 1, 73, 74Wakerly, Kate xxivWaser, Shlomo 73waveform editor 240waveform viewer 337WE-controlled write 826wedge ∧ 186weight 26, 37, 46
of MSB 37weighted code 50Weldon, E. J. Jr. 74when keyword, VHDL 258, 276when statement, ABEL 248while loop, VHDL 284while statement, Verilog 325White, E. B. 508widget, iterative 756widget, serial 756Widmer, Albert 74wimpy logic families 689
wired AND 138wired logic 138wire keyword, Verilog 296wire lengths 242with statement, ABEL 620word line 804word processor 9, 10working digital designers xviwork library, VHDL 269, 269worst-case delay 368wrapper 257wrist strap, conductive 113$write task, Verilog 329writeable compact disc (CD-R) 81write cycle 825
Zz bit value, Verilog 323ZBT SSRAM with flow-through
outputs 831ZBT SSRAM with pipelined
outputs 832zero-bus-turnaround (ZBT)
SSRAM 831zero-code suppression 73
2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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896 Index
2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,
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