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An electric motor is a machine which converts electrical energy to mechanical energy. Its action is based on the principle that when a current-carrying conductor is placed in a magnetic field, it experiences a magnetic force whose direction is given by Fleming’s left hand rule.
When a motor is in operation, it develops torque. This torque can produce
mechanical rotation. DC motors are also like generators classified into shunt wound or
series wound or compound wound motors.
FLEMING’S LEFT HAND RULE:
Keep the force finger, middle finger and thumb of the left hand mutually
perpendicular to one another. If the fore finger indicates the direction of magnetic field
and middle finger indicates direction of current in the conductor, then the thumb indicates
the direction of the motion of conductor.
PRINCIPLE OF OPERATION OF DC MOTOR:
Figure I show a uniform magnetic field in which a straight conductor carrying no
current is placed. The conductor is perpendicular to the direction of the magnetic field.
In figure II the conductor is shown as carrying a current away from the viewer, but
the field due to the N and S poles has been removed. There is no movement of the
conductor during the above two conditions. In figure III the current carrying conductor is
placed in the magnetic field. The field due to the current in the conductor supports the
main field above the conductor, but opposes the main field below the conductor.
Movement of
Conductor
Magnetic flux current carrying Conductor
N S
The result is to increase the flux density in to the region directly above the
conductor and to reduce the flux density in the region directly below the conductor. It is
found that a force acts on the conductor, trying to push the conductor downwards as
shown by the arrow. If the current in the conductor is reversed, the strengthening of flux
lines occurs below the conductor, and the conductor will be pushed upwards (figure-IV).
Now consider a single turn coil carrying a current as shown in the above figure. in view of the reasons given above, the coil side A will be forced to move downwards, whereas the coil side B will be forced to move upwards. The forces acting on the coil sides A and B will be of same magnitude. But their direction is opposite to one another. As the coil is wound on the armature core which is supported by the bearings, the armature will now rotate. The commutator periodically reverses the direction of current flow through the armature. Therefore the armature will have a continuous rotation.
A simplified model of such a motor is shown in figure VI. The conductors are
wound over a soft iron core. DC supply is given to the field poles for producing flux.
The conductors are connected to the DC supply through brushes
Let's start by looking at the overall plan of a simple 2-pole DC electric motor. A
simple motor has 6 parts, as shown in the diagram below.
An armature or rotor
A commutator
Brushes
An axle
A field magnet
A DC power supply of some sort
An electric motor is all about magnets and magnetism: a motor uses magnets to
create motion. If you have ever played with magnets you know about the fundamental
law of all magnets: Opposites attract and likes repel.
So if you have 2 bar magnets with their ends marked north and south, then the
North end of one magnet will attract the South end of the other. On the other hand, the
North end of one magnet will repel the North end of the other (and similarly south will
repel south). Inside an electric motor these attracting and repelling forces create rotational
motion.
In the diagram above and below you can see two magnets in the motor, the
armature (or rotor) is an electromagnet, while the field magnet is a permanent magnet
(the field magnet could be an electromagnet as well, but in most small motors it is not to
save power).
RACK AND PINIAN ARRANGEMENT:
The block is the impartent part of the unit as it houses the rack and pinion. This
block converts linear motion into rotary motion.
Rack and pinion gear system is used to transmit rotary motion into linear motion.
The rack is a portion of a gear having an infinite pitch diameter and the line of action is
tangent to the pinion.
Pinion:
This is a gear wheel which is provided to get mesh with rack to convert the linear
motion into rotary motion. They are made up of Cast iron.
Rack:
Rack teeth are cut horizontally about the required length. This is made up of Cast
iron.
BATTERIES
INTRODUCTION:
In isolated systems away from the grid, batteries are used for storage of excess
solar energy converted into electrical energy. The only exceptions are isolated sunshine
load such as irrigation pumps or drinking water supplies for storage. In fact for small
units with output less than one kilowatt. Batteries seem to be the only technically and
economically available storage means. Since both the photo-voltaic system and batteries
are high in capital costs. It is necessary that the overall system be optimized with respect
to available energy and local demand pattern. To be economically attractive the storage
of solar electricity requires a battery with a particular combination of properties:
(1) Low cost
(2) Long life
(3) High reliability
(4) High overall efficiency
(5) Low discharge
(6) Minimum maintenance
(A) Ampere hour efficiency
(B) Watt hour efficiency
We use lead acid battery for storing the electrical energy from the solar panel for
lighting the street and so about the lead acid cells are explained below.
2.1 LEAD-ACID WET CELL:
Where high values of load current are necessary, the lead-acid cell is the type most
commonly used. The electrolyte is a dilute solution of sulfuric acid (H₂SO₄). In the
application of battery power to start the engine in an auto mobile, for example, the load
current to the starter motor is typically 200 to 400A. One cell has a nominal output of
2.1V, but lead-acid cells are often used in a series combination of three for a 6-V battery
and six for a 12-V battery.
The lead acid cell type is a secondary cell or storage cell, which can be recharged.
The charge and discharge cycle can be repeated many times to restore the output voltage,
as long as the cell is in good physical condition. However, heat with excessive charge
and discharge currents shortends the useful life to about 3 to 5 years for an automobile
battery. Of the different types of secondary cells, the lead-acid type has the highest
output voltage, which allows fewer cells for a specified battery voltage.
2.2 CONSTRUCTION:
Inside a lead-acid battery, the positive and negative electrodes consist of a group
of plates welded to a connecting strap. The plates are immersed in the electrolyte,
consisting of 8 parts of water to 3 parts of concentrated sulfuric acid. Each plate is a grid
or framework, made of a lead-antimony alloy. This construction enables the active
material, which is lead oxide, to be pasted into the grid. In manufacture of the cell, a
forming charge produces the positive and negative electrodes. In the forming process,
the active material in the positive plate is changed to lead peroxide (pbo₂). The negative
electrode is spongy lead (pb).
Automobile batteries are usually shipped dry from the manufacturer. The
electrolyte is put in at the time of installation, and then the battery is charged to from the
plates. With maintenance-free batteries, little or no water need be added in normal
service. Some types are sealed, except for a pressure vent, without provision for adding
water.
The construction parts of battery are shown in figure.
CONTROL UNIT -89C52
In our project 89C52 Microcontroller is used as a control unit.
INTRODUCTION ABOUT MICRO CONTROLLER:
A microcontroller consists of a powerful CPU tightly coupled with memory
(RAM, ROM or EPROM), various I/O features such as serial port(s), parallel port(s),
Timer/Counter(s), Interrupt controller, Data Acquisition interfaces-Analog to Digital
Converter (ADC), Digital to Analog Converter (DAC), everything integrated onto a
single silicon chip.
It does not mean that any micro controller should have above said features on-
chip. Depending on the need and area of application for which it is designed, the on-chip
features present in it may or may not include all the individual sections said above. Any
micro computer system requires memory to store a sequence of instructions making up a
program, parallel port or serial port for communicating with an external system,
timer/counter for control purposes like generating time delays, baud rate for the serial
port, apart from the controlling unit called the Central Processing Unit.
MEMORY ASSOCIATED WITH AT-89C52:
PROGRAM MEMORY:
A program memory is a block of memory, which can be used to store a sequence
of program codes (by using special EPROM / PROM programmers). It can only be read
from and not written into, under normal operating conditions.
There can be up to 64 k bytes of program memory in AT-89C52. in ROM and
EPROM versions of the MCS-351 family of devices, the lower 4K are provided on-chip
whereas in ROM fewer versions, all program memory is external.
In ROM and EPROM versions of this device, if the special control signals EA
(External Access enable) is strapped off Vcc, and then program fetches to addresses 0000
to 0FFF are directed to the internal ROM. The program fetch will be from external
memory, where EA* is grounded.
After reset, the CPU begins execution from address location 0000 of the program
memory.
Figure shows a map of the AT-89C52-program memory
FFFF FFFF 1000 OR 0FFF 0000 0000
DATA MEMORY:
Data memory is the Read/Write memory. Hence, it can be both read from and
written into. AT-89C52 has got 128 bytes of internal data memory and 64K of external
data memory.
FF 80 FFFF 7F AND 0000 00
60K Bytes Internal
4 K Bytes Internal
64 K Bytes External
SFRS DIRECT
ADDRESSSING ONLY
DIRECT AND
INDIRECT ADDRESS
ING
64 K Bytes External
INTERNAL DATA MEMORY:
Internal data memory addresses are one byte wide, which includes 128 bytes of
on-chip RAM plus a number of special Function Registers. The 128 bytes of RAM can
be accessed either by direct addressing (MOV data address) or by indirect addressing
(MOV @ R i ).
The lowest 32bytes (00-1F) of on-chip RAM are grouped into 4 banks of 8
registers each. Program instructions call out these registers as R0 through R7 > Bits 3
and 4 (PSW.3 and PSW.4) in register program status word (PSW) select which register
bank is n use. This allows more efficient use of code space, since register instructions are
shorter than instructions that use direct addressing.
Reset initializes the stack pointer register to 7 and its incremented once to start
from locating 08, which is register R0 of second register bank. Hence, in order to use
more than one register bank, the stack pointer should be initialized to a different location
of RAM if it is not used for data storage.
The next 16 bytes (20-2F) from a block of bit addressable memory space, which
can also byte addressed.
Bytes 30 through 7F are available to the user as data RAM. However, is the stack
pointer has been initialized to this area, enough number of bytes should be left a side to
prevent stack overflow.
I/O STRUCTURE OF AT-89C52:
AT-89C52 has four 8-bit parallel ports (hence 8*4=32 I/O lines are available). All
four parallel ports are bi-directional. Each line consists of a latch, an output driver and an
input buffer.
The four ports are named as port 0 (po), port 1 (p1), port 2 (p2) and port 3(p3).
They are bit addressable and has to be represented in the form PX.Y is i.e. bit Y of port X
while using bit addressing mode. PX.0 is the LSB (least significant Bit) of port x and
px.7 is the MSB (Most Significant Bit) of that port.
Out of the four ports, port 0 and port 2 are used in accesses to external memory.
All the port 3 pins are multifunctional. Port 3 is an 8-bit bidirectional with internal pull-
ups
Port pin Alternate Functions
P3.0 RXD (Serial input port)
P3.1 TXD (Serial output port)
P3.2 INTO (External Interrupt 0)
P3.3 INT1 (External Interrupt 1)
P3.4 T0 (Timer 0 External input)
P3.5 T1 (Timer 1 External Input)
P3.6 WR (External Data memory write strobe)
P3.7 RD (External Data memory Read Strobe)
PORT 0:
Port 0 is an 8-bit open drain bi-directional I/O port. It is also the multiplexed low
order address and data bus during access to external memory.
It also receives the instruction bytes during EPROM programming and outputs
instruction bytes during program verification. (External pull-ups are required during
verification). Port 0 can sink (and operation and source) eight LS TTL input.
PORT 1:
Port 1 is an 8-bit bi-directional with internal pull-ups. It receives the low order
address byte during EPROM program verification. The port-1 output buffers can
sink/source four LS TTL inputs.
PORT 2:
Port 2 is an 8-bit bi-directional with external pull-ups. It emits the high order
address byte during accesses to external memory.
It also receives, these high-order address bits during EPROM programming
Verification. Port 2 can sink/source four LS TTL inputs.
RST:
While the oscillator is running a high on this pin for two machine cycles resets the
device. A small external pull down resistor (8.2k) from RST to Vss permits power on
reset when a capacitor (10 micro frequencies) also connected from this pin to Vcc.
ALE/PROG:
Address latch enable is the output for latching low byte of the address, during
access 10 external memory. ALE is activated at a constant rate of 1/6 the oscillator
frequency except during an external data memory access at which time one ALE pulse is
skipped. ALE can sink/source eight LS TTL inputs. This pin is also the program pulse
input (PROG) during EPROM programming.
PSEN:
Program Store Enable is the read strobe to external program memory. PSEN is
activated twice each machine cycle, during fetches form external program memory.
PSEN is not activated during fetches from internal program memory. PSEN can
sink/source 8 LS TTL inputs.
EA/Vpp:
When external access enable (EA) is held high, the AT-89C52 execute out of
internal program memory (Unless the program counter exceeds OFF (H)). When EA is
held low, the AT-89C52 H executes only out of external program memory. This pin also
receives the 21 Volts programming. Supply Voltage (Vpp) during EPROM
programming. This pin should not be floated during normal.
XTAL1:
It is inputs to the inverting amplifier that forms the oscillator. XTAL1 should be
grounded when an external oscillator is used.
XTAL 2:
It is Outputs to the inverting amplifier that forms the oscillator, and input to the
internal clock generator, receives the external oscillator signal when an external oscillator
is used.
Vss - Circuit ground potential
Vcc - Supply Voltage during Programming Verification and normal
Operation.
TIMERS/COUNTERS:
AT-89C52 has two 16-bit timer/counter 0, and timer/counter 1. They can be
configured in any of the four operating modes, which are selected by bit-pars (m1, 0) in
register TMOD (Timer/counter Mode control). Modes 0, 1 and 2 are the same for the
timer/counters. Mode 3 is different.
FEATURES OF AT-89C52:
Now a days an 8-bit AT-89C52/8031/8751 and 16 bit 8097 micro controllers
available in the form of kits. Its special features are summarized as:-
4k Bytes of Flash
128 Bytes of RAM
32 I/O lines
A five vector two level interrupt architecture.
A full duplex serial port
On chip Oscillator and clock circuitry.
ADDRESSING MODES:
The AT-89C52 instructions operate on data stored in internal CPU registers,
external memory or on the I/O ports. There are a number of methods (modes) in which
these registers, memory (internal or external) and I/O Ports (Internal / External) can be
addressed, called addressing modes. This section gives a brief summary of the various
types of addressing modes available in AT-89C52.
These Modes are:
Immediate
Direct
Indirect
Register
Register Specific
Indexed
IMMEDIATE ADDRESSING:
In this mode, the data to be operated upon is in the location immediately following
the opcodes. For example, the instruction,
MOV A, # 41
-Loads the accumulator with the hex value 41.
‘//’ Signifies IMMEDIATE ADDRESSING.
DIRECT ADDRESSING:
In direct addressing, the operand is specified by an 8-bit address field in the
instruction. For example, the instruction,
INC 20
Increments the contents of the On-Chip data address 20 by one.
INDIRECT ADDRESSING:
In indirect addressing, the instruction specifies a register, which contains the
address of the operand. Both internal and external RAM can be indirectly addressed.
The address register for 8-bit address can be R0 or R1 of the selected register bank
or the stack pointer. The address register for 16-bit address can only be the 16-bit “data
pointer” register, DPTR. For example, the instruction,
MOVX @DPTR, A
-Writes the contents of the accumulator to the address held by the DPTR register.
RESISTOR ADDRESSING:
The register banks, containing resistors R0 through R7, can be accessed by certain
instructions, which carry a 3-bit register specification within the opcode of the
instruction. Instructions that access the registers this way are code efficient, since this
mode eliminates an address byte.
When the instruction is executed, one of the eight resistors in the selected bank at
the execution time by two bank select bits is selected at the execution time by the two
bank select bits in the PSW. For example, the instruction,
MOV A, R0
-Copies the contents of the resistor R0 (of the selected bank) to the accumulator.
INDEXED ADDRESSING:
Only program memory can be accessed with indexed intended for reading look-up
tables in program memory. A 16-bit base resistor (Either DPTR or the Program counter)
points to the base of the table and accumulator is set up with the table entry number. The
address of the table entry in program memory is formed by adding the accumulator data
to the base pointer. The instruction,
MOVC A,@A+DPTR
This function reads the contents of program memory, whose address is obtained
by adding the content of DPTR and accumulator copies it to the accumulator.
1 40
2 39
3 38
4 37
5 36
6 35
7 34
8 33
9 32
10 31
11 30
12 29
13 28
14 27
15 26
16 25
17 24
18 23
19 22
20 21
PIN DIAGRAM OF AT89C52: PDIP
P1.0 Vcc
P1.1 P 0.0(AD 0)
P1.2 P 0.1 (AD 1)
P1.3 P 0.2 (AD 2)
P1.4 P 0.3 (AD 3)
P1.5 P 0.4 (AD 4)
P1.6 P 0.5 (AD 5)
P1.7 P 0.6 (AD 6)
RST P 0.7 (AD 7)
(R X D) P3.0 EA / VPP
(T X D) P3.1 ALE/PROG
(INT 0) P3.2 PSEN
(INT 1) P3.3 P2.7 (A 15)
(T 0) P3.4 P2.6 (A 14)
(T1) P3.5 P2.5 (A 13)
(WR) P3.6 P2.4 (A 12)
(RD) P3.7 P2.3 (A 11)
XTAL 2 P2.2 (A 10)
XTAL 1 P2.1 (A 9)
RAM ADDRRESISTOR
RAM PORT 0LATCH
PORT 2LATCH
FLASH
PORT 0 DRIVERS PORT 2 DRIVERS
B REGISTER ACC
STACK POINTER
PROGRAM ADDRESS REGISTER
TMP 2 TMP 1 BUFFER
PC INCREME
N-TER
INTERRUPT SERIAL PORT AND TIMER BLOCKS
PSW PROGRAM COUNTER
DPTRTIMING AND
CONTROL
INSTRUCT-ION
REGISTER
PORT 1 LATCH
PORT 3 LATCH
PORT 1 DRIVERS PORT 3 DRIVERSOSC
GND P2.0 (A 8)
PLCC
P 0. 0 – P 0 . 7 P2.0 – P2.7
Vcc
GND
ALU
PSENALE/PROGEA/Vpp
RST
P1.0 – P1.7 P3.0 – P3.7
ACCUMULATOR:
Accumulator is the Accumulator register mnemonics for Accumulator. Specific
instruction however, refer to the Accumulator simply A.
B REGISTER:
The B register is used during multiply and divide operations. For other
instructions can be treated as another scratch pad register.
PROGRAM STATUS WORD:
The PSW resistor contains program status information. The program status word
(PSW) contains several status bits that reflect the current state of the CPU. The PSW
resides in SFR space. It contains the carry bit, the auxiliary carry 9for BCD operations),
the two register bank select bits, the overflow flag a parity bit and two user definable
status flags. The carry bit other than serving the functions of a carry bit in arithmetic
operations, also serves as the ‘Accumulator’ for a number of Boolean operations. The bits
and RSI are used to select one of the register bans. A number instruction refers of their
RAM location R0 through R7. The selection of which the four banks is being referred to
is made on the bass of the bits RS0 and RS1 execution time.
The lower 32B are grouped into 4 banks of 8 resistors. Program instructions call
out there resistors as R0 through R7 bits in the PSW select which register is n use. The
parity bit reflects the number is in the accumulator. P=1 if the accumulator contains an
old number of 1 s and p=0 if the accumulator contains an even number of 1 s. Thus the
number of 1 s in the accumulator plus P is always even. Two bits in the PSW are
uncommitted and may be used as general-purpose status flags.
PROGRAM STATUS WORD OF AT89C52 DEVICES:
7F (H)
2F (H)20 (H)
Bank-3 1F (H)18 (H)
Bank-2 17 (H)10 (H)
Bank-1 0F (H)08 (H)
Bank-0 07 (H)00 (H)
THE LOWER 128 BYTES OF INTERNAL RAM
Bit addressable Space
Bit address 0-7F (H)
Bank Select Bit 11
In PSW
C AC FO RS1 RS0 OV P
Parity of accumulator by hard ware to 1 bit if it contains an old number of 1 s otherwise set to 0
User Definable Flag
Overflow Flag set by Arithmetic Operation
Resistor Bank Select bit- 0
Carry flag receives carry out from bit-1 of ALU
operation
Auxiliary carry flag receives carry out from bit-
1 of addition operands
General Purpose Status Flag
Register Bank Select bit-1
10 4 Banks of 8
resistors
R0 - R7
01
00
STACK POINTER:
The stack pointer resistor is 8-bit wide. It is incremented before data is stored
during PUSH and CALL execution while the stack may where in on-chip RAM. The
stack pointer is initialized to 07(H) after a reset. This causes the stack to begin at location
08(H).
DATA POINTER:
The data pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL).
Its intended function is to hold a 16-bit address. It may be manipulated as a 16-bit resistor
or 08 two independent bit registers. Ports 0 to 3 – p0, p1, p2 and p3 are the SFR latches
for ports 0, 1, 2, and 3 respectively.
SERIAL DATA BUFFER:
The serial data buffer is actually two separate resistors transmit buffer and a
receive buffer resistor. When data is moved to SBUF, it goes to the transmit buffer where
it is held for serial transmission. (Moving a byte to SBUF is what initiates the
transmission) When data is moved from SBUF, it comes from the receive buffer.
TIME RESISTORS:
Resistors pairs (TH0, TL), (TH1, TL1) and (TH2, TL2) are the 16-bits counting
resistors for the interrupt system, the timer counters and the serial port.