Foundations of Computing and Communication Lecture 7 The von Neumann Architecture Based on The Foundations of Computing and the Information Technology Age, Chapter 6 Lecture overheads c John Thornton 2007
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Foundations of Computing and
Communication
Lecture 7
The von Neumann Architecture
Based on The Foundations of Computing and the Information Technology Age, Chapter 6
Lecture overheads c© John Thornton 2007
Lecture Objective
To gain a practical understanding of how a program executes
within the von Neumann architecture.
Overview of Topics
• The von Neumann Architecture
• The Fetch-Execute Cycle
• Instruction Set Architectures
• Basic Program Instructions
• Executing a Simple Program
• The Evolution of the von Neumann Architecture
1
The von Neumann Architecture
The architecture that underpins
the operation of a modern com-
puter still adheres to a structure
put forward by John von Neumann
(and John Mauchly and Presper
Eckert) in 1946. This structure
separates the internal operation of
a computer into two basic logical
components: the central process-
ing unit (CPU) and memory.
Control Arithmetic
Logic UnitandUnit
CPU
OutputInput
Memory
2
General Purpose Memory
• It’s all data! The revolutionary idea behind the architec-ture was that data and program instructions were both to bestored in the same format within the same internal memorydevices (like universal Turing machine tape). This only be-came practical with the development of high speed electronicmemory after WWII.
• The stored program concept: In this way programs wereto be stored within the computer rather than being accessedfrom a separate location during runtime.
• The programmer has control: Because there is no physicaldistinction between data and program instructions it is therole of the programmer to ensure that memory locations arecorrectly read, interpreted and written to.
3
Digital Synchronism
• The von Neumann bottleneck: Given input devices from
which data can be loaded into memory and output devices
to store and display results, the focus of the von Neumann
architecture is the passage of data back and forth between
memory and the CPU.
• The importance of the clock: To work correctly this pas-
sage of data has to be rigidly synchronised via the control of
a system clock.
• Digital states: The system clock enforces a sufficient gap
for the machine to move from one state to another. Hence
components must wait until all other relevant processes have
moved to a new state before starting the next computation.
4
The Fetch-Execute Cycle
The process of moving from one state to another according tothe ticking of a system clock is known as the fetch-execute cycle.In the fetch step, the CPU control unit fetches an instructionfrom memory and stores it in an instruction register. In theexecute step, the instruction triggers processes that change thevalues in the CPU data registers. The next instruction is thenfetched and the cycle repeats.
• Addressable memory: The emphasis on always movingdata back and forth from memory means the CPU mustbe able to access memory as fast as possible via direct ad-dressing, i.e. by having a key value that can directly unlocka memory location without having to perform a search.
5
The Fetch-Execute Cycle
Central Processing Unit
Control Unit ALU
RegistersFetch Execute
Instruction
Data 3
Data 1
Data 2
PointerMemory
Data 0
00100000 00000000
00000000 00000000
... ...0110100000000111
00000001 011001000000000000000000
01000010 0001100100110000 0001010000010000 00010000
001000000110000001100000 00110000
000110010101000001010001 00011000
000101110101001001010011 00010110 00000000
00000000
00000000
00000000
00000000
6
Inside the CPU
• The Pointer Register is used by the control unit to fetchthe next instruction - it holds the memory address of aninstruction and is automatically updated after each fetch topoint to the address of the next instruction.
• Control Unit Instructions take care of loading and stor-ing data back and forth from memory, updating the pointerregister and halting the program execution.
• Arithmetic and Logic Unit Instructions perform the arith-metic and logical transformations on the data stored in thedata registers.
7
The Turing Machine Analogy
Just as a Turing machine reads a symbol from a tape and, ac-cording to that symbol and its internal state, writes anothersymbol, changes state and moves the tape, a von Neumann ma-chine reads a symbol string from memory and according to thevalue of that string and the current state of its registers, writesanother string to memory, changes the state of its registers andmoves to read another memory location.
Turing machine tape → Memory;Turing machine rules → CPU circuits;Direction of tape movement → Pointer register;Current and next states → Instruction register;Current symbol → Data copied from memory to data registers;Next symbol → Data copied from data registers to memory.
8
It Could Have Been Different...
• Serial processing: Both the Turing and von Neumann ma-chines enforce that one thing must be done after anotherin strict sequence. The power of the modern computer hascome from performing the von Neumann fetch-execute cyclewith enormous speed.
• The self-timing systems of nature: Nature manages toperform far more sophisticated calculations by using mas-sively parallel, asynchronous systems. Instead of doing onething over and over with great speed, a brain does millionsof things at once relatively slowly.
• Mathematical roots: von Neumann chose a sequential dig-ital architecture because it is simpler to build and works wellfor the kinds of mathematical problems that faced the USmilitary in 1946.
9
Instruction Set Architectures
• The connection between instructions and processors:
Unlike the five elements of a Turing machine instruction, the
form of a von Neumann machine’s instruction set is not fixed
and thereby helps define the processor architecture.
• Op-codes and operands: typically an instruction is divided
into an op-code that represents an operation and zero to
many operands on which the operation is to be performed:
op-code operand 1 operand 2 operand 3
1 1 0 0 1 0 1 1 1 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 0 0 1
10
An Instruction Language
• Formal Languages: the choice of an instruction set and the
form in which the set is encoded defines a formal language.
• A two-state alphabet: the standard alphabet of a modern
machine language takes the form of two states: {0,1}. This
choice is based on the practical need to efficiently represent
and manipulate states as electrical charges.
• Boolean algebra represents a formal language suitable for
manipulating a two state alphabet using a remarkably small
set of primary logical operations: AND, OR and NOT
11
The Three Primary Logical Instructions
AND OR NOT0 AND 0 = 0 0 OR 0 = 0 NOT 0 =10 AND 1 = 0 0 OR 1 = 1 NOT 1 =01 AND 0 = 0 1 OR 0 = 11 AND 1 = 1 1 OR 1 = 1
10110110 10110110AND 01101000 OR 01101000 NOT 01101000
00100000 11111110 10010111
12
Combining Operators
All other logical operations can be expressed using a combination
of the AND, OR and NOT operators, for example:
A XOR B = (A AND NOT(B)) OR (NOT(A) AND B)
XOR0 XOR 0 = 00 XOR 1 = 11 XOR 0 = 11 XOR 1 = 0
10110110XOR 01101000
11011110
13
The Logic of Addition
ADD0 + 0 = 000 + 1 = 011 + 0 = 011 + 1 = 10
Dividing each result above into a leading and trailing bit showsthat the trailing bit (T) is only “on” when the original bits aredifferent (i.e. when 1 + 0 = 01 or 0 + 1 = 01). Hence we candecide the value of the trailing bit using an XOR operation.
Similarly, the leading bit (L) in the answer is only “on” whenboth the original bits are also “on” (i.e. when 1 + 1 = 10).Hence we can decide the value of the leading bit using an AND
operation.
14
The Logic of Addition
• Representing the two bits to be
added as A and B, the leading re-
sult bit as L and the trailing result
bit as T, gives:
A + B = LTwhereL = A AND BT = A XOR B
• To handle multiple bit numbers
we also need to add the carry bit
arriving from the previous column
to the right. We can achieve this
by adding this carry in bit (Cin)
to the trailing bit of our first ad-
dition, as follows:
T + Cin = CSwhereC = T AND CinS = T XOR Cin
15
The Logic of Addition
We now need to combine the carry out information into a singlebit that can be passed to the next column. This bit should be“on” if either of the additions produced a carry, i.e:
Cout = C OR L
Given input bits: A, B and Cin, and output bits: S and Cout,where A and B are the bits that line up in column n of ouroriginal pair of binary numbers, Cin is the value of the carry inbit arriving from column n – 1, S is the resulting bit sum forcolumn n and Cout is the carry out bit to be sent to column n +1, we can perform a complete column addition as follows:
S = (A XOR B) XOR CinCout = ((A XOR B) AND Cin) OR (A AND B)
16
More Complex Instructions
• General addition: By combining binary column “adders” wecan add together binary numbers of arbitrary size.
• The instruction set: Our instruction set now consists of 5operations: AND, OR, NOT, XOR and ADD
• Subtraction: To subtract two binary numbers we can usethe same complement method Pascal used for his calculator.For a binary number, two’s complement is found by subtract-ing each digit from one (using NOT) and adding one:
ADD(NOT(A), 0001)
17
Subtraction
Subtraction is achieved by adding the two’s complement of the
number you wish to subtract and discarding the final carry bit.
For example, to subtract 7 – 3:
= 0111− 0011= ADD(0111, ADD(NOT(0011),0001))= ADD(0111, ADD(1100,0001))= ADD(0111,1101)= 0100
Here the answer 0100 is given after removing the carry bit (i.e.
the full answer is 10100). If the leading bit of this truncated
string is one then the string represents a two’s complement neg-
ative number, otherwise it represents a normal positive number.
18
Shifting
If we take a bit string to be a bi-
nary number then the SHIFT oper-
ator has the same effect as mov-
ing the decimal point in a base ten
number. So moving a binary point
left in a base two number is equiv-
alent to dividing by two. Similarly,
a left shift will move the binary
point to the right and is equiva-
lent to multiplying by two.
trailing bitshifted out
..
10 1 1 0100
zero bitshifted in
shifted inzero bits
shifted outleading bits
108
54
2
10 1 1 0100
01 01010 1
4
54
216
x
01 1 0 0011
Left Shift −2 bits
Right Shift +1 bit
19
Control Unit Instructions
• The LOAD and STORE instructions control the the move-ment of data between memory and the CPU data registers.
• The conditional BRANCH instruction tests a condition (suchas whether or not a register holds a non-zero value) and, ifthe condition is met, it overrides the fixed update of theprogram counter and places a new address in the pointerregister. This allows the flow of program control to “jump”anywhere in memory.
• The HALT instruction terminates a program and switchesthe computer off.
20
Sequence, Selection and Iteration
• Selection and iteration: A conditional BRANCH allows se-
lection (if) and iteration (do while).
• Sequence: Everything else sequentially follows fetch and ex-
ecute instructions that copy data and perform simple logical
transformations until the program halts.
• Input and Output: I/O devices can be accessed and con-
trolled by reading and writing data to reserved memory lo-
cations.
• Another universal language: That’s it! All programming,
hence all effective procedures can be captured by the simple
set of instructions we have described.
21
A von Neumann Machine Programming LanguageAND register address register address register address
1 0 0 1 * * * * * * * * * * * *
OR register address register address register address1 0 0 0 * * * * * * * * * * * *
XOR register address register address register address0 1 1 1 * * * * * * * * * * * *
ADD register address register address register address0 1 1 0 * * * * * * * * * * * *
LOAD register address memory address0 1 0 1 * * * * * * * * * * * *
STORE register address memory address0 1 0 0 * * * * * * * * * * * *
BRANCH register address memory address0 0 1 1 * * * * * * * * * * * *
NOT register address register address unused0 0 1 0 * * * * * * * *
SHIFT register address register address unused0 0 0 1 * * * * * * * *
HALT unused0 0 0 0
22
A Simple Programming Problem
A university subject convenor has decided to give out bonusmarks to students who have unusual and original ideas. Thesemarks accrue in addition to the marks given for the regular as-signments and make it possible for a student to score more than100% for the overall subject. Unfortunately, the university’s finalgrading system is not very flexible and if it finds a student withmore than 100% it assumes an error has occurred and the sub-ject convenor must explain what has happened. To avoid thissituation we need to write a program that checks a student’sfinal mark and makes sure anyone getting more than 100% hastheir final mark reduced back to 100%. In programming terms,we can express the problem as follows:
If an overall mark is greater than 100then set the overall mark to 100
23
The Solution
1 LOAD register-3-address value-one-address load value 1 in0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 0 register 32 LOAD register-2-address value-one-hundred-address load value 100 in0 1 0 1 0 0 1 0 0 0 0 1 0 1 1 1 register 23 LOAD register-1-address value-seven-address load value 7 in0 1 0 1 0 0 0 1 0 0 0 1 1 0 0 0 register 14 LOAD register-0-address mark-address load mark M in0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 register 05 NOT register-0-address register-0-address unused negate M and store0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 as ¬M in register 06 ADD register-0-address register-3-address register-0-address store ¬M + 1 as0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 -M in register 07 ADD register-0-address register-2-address register-0-address store -M + 100 as0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ∆ in register 08 SHIFT register-0-address register-1-address unused right shift ∆ by 7 to0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 isolate sign bit B9 BRANCH register-0-address halt-address branch to HALT if0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 B is zero10 STORE register-2-address mark-address store mark = 1000 1 0 0 0 0 1 0 0 0 0 1 1 0 0 1 back to memory11 HALT unused terminate program0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24
Control Unit ALU
InstructionFetch
Pointer00000010
Data 200000000
Data 000000000
000101100101001101010010 00010111
000110000101000101010000 00011001
000000000010000001100000 00110000
001000000110000000010000 00010000
Memory
... ...
00110000 000101000001100101000010
00000000 0000000001100100
0000011100000001
01101000
Instruction
Increment
LOAD
Pointer
01010011
LOADInstruction 1:
Data 300000001
Data 100000000
into register−3value−one
00010110
Central Processing Unit
2
4
1
3
6
5
25
Central Processing Unit
Control Unit ALU
InstructionFetch
Data 000000000
Instruction
Increment
LOAD
Pointer
LOADInstruction 2:
Data 3
Data 100000000
00000001
Data 201100100
01010010
Pointer00000100
into register−2
000110000101000101010000 00011001
000000000010000001100000 00110000
001000000110000000010000 00010000
Memory
... ...
00110000 000101000001100101000010
00000000 00000000
00000111 01101000
01010011 00010110
00000001
01010010 00010111
01100100
00010111
value−one−hundred
4
1
3
5
6
2
26
Central Processing Unit
Control Unit ALU
InstructionFetch
Data 000000000
Instruction
Increment
LOAD
Pointer
LOADInstruction 3:
Data 3
Data 1
00000001
Data 2
Pointer00000110
into register−1
01010000 000110010000000000100000
01100000 001100000010000001100000
00010000 00010000
Memory
... ...
00110000 000101000001100101000010
00000000 00000000
01101000
01010011 00010110
00000001
value−seven
01010001 00011000
0000011101100100
0001011101010010
01100100
01010001 00011000
00000111
4
1
3
5
2
6
27
Central Processing Unit
Control Unit ALU
InstructionFetch
Instruction
Increment
LOAD
Pointer
LOADInstruction 4:
Data 3
Data 1
00000001
Data 2
Pointer00001000
into register−0
000000000010000001100000 00110000
001000000110000000010000 00010000
Memory
... ...
00110000 000101000001100101000010
00000000 00000000
01010011 00010110
00000001 01100100
0001011101010010
01100100
mark
01010001 00011000
00000111
00000111
01010000 00011001
01101000Data 0
01010000 00011001
01101000
4
1
3
2
5 6
28
Central Processing Unit
Control Unit ALU
InstructionFetch
Instruction 5:NOT
register−0 =not(register−0)
InstructionDecode
Instruction
IncrementPointer
Data 3
Data 1
00000001
Data 2
Pointer00001010
01100000 001100000010000001100000
00010000 00010000
Memory
... ...
00110000 000101000001100101000010
00000000 00000000
01010011 00010110
00000001 01100100
0001011101010010
01100100
01010001 00011000
00000111
00000111
Data 010010111
00100000 00000000
01101000
0001100101010000
00100000 00000000
SaveResult
NOT
4
1
3
2
5
6
7
29
Central Processing Unit
Control Unit ALU
InstructionFetch
InstructionDecode
Instruction 6:ADD
register−0 =register−0 + register−3 Instruction
IncrementPointer
Data 3
Data 1
Data 2
Pointer
001000000110000000010000 00010000
Memory
... ...
00110000 000101000001100101000010
00000000 00000000
01010011 00010110
00000001 01100100
0001011101010010
01100100
01010001 00011000
00000111
00000111
Data 01001100001101000
0001100101010000
SaveResult
00001100
00100000 0000000001100000 00110000
01100000 00110000
00000001
ADD
4
1
3 5
8
7
62
30
Central Processing Unit
Control Unit ALU
InstructionFetch
InstructionDecode
Instruction
IncrementPointer
Data 3
Data 1
Data 2
Pointer
00010000 00010000
Memory
... ...
00110000 000101000001100101000010
00000000 00000000
01010011 00010110
00000001 01100100
000101110101001001010001 00011000
00000111
00000111
Data 01111110001101000
0001100101010000
SaveResult
00001110
00100000 00000000
Instruction 7:ADD
register−0 =register−0 + register−2
01100000 00100000 01100100
0011000001100000
00000001
01100000 00100000
ADD
4
1
3 5
8
7
6
2
31
Central Processing Unit
Control Unit ALU
InstructionFetch
InstructionDecode
Instruction
IncrementPointer
Data 3
Data 1
Data 2
PointerMemory
... ...
00110000 000101000001100101000010
00000000 00000000
01010011 00010110
00000001 01100100
000101110101001001010001 00011000
00000111Data 0
0000000101101000
0001100101010000
SaveResult
00100000 000000000011000001100000
00000001
Instruction 8:SHIFT
register−1 bitsregister−0 by
00010000
01100000 00100000 0110010000010000
00000111
00010000
00010000
00010000
SHIFT
4
1
3 5
8
7
2
6
32
Central Processing Unit
Control Unit ALU
InstructionFetch
BRANCH
Instruction
IncrementPointer
Data 3
Data 1
Data 2
PointerMemory
... ...
000110010100001000000000 00000000
01010011 00010110
00000001 01100100
000101110101001001010001 00011000
00000111Data 0
0000000101101000
000110010101000000100000 00000000
0011000001100000
00000001
00010010
01100000 00100000 01100100
00110000 000101000001000000010000
00000111
00110000 00010100
BRANCHto halt−address
if register−0 is zero
Instruction 9:
4
1
3
5
2
33
Central Processing Unit
Control Unit ALU
InstructionFetch
STORE
Instruction
IncrementPointer
Data 3
Data 1
Data 2
PointerMemory
... ...
00000000 00000000
01010011 00010110
00000001 01100100
000101110101001001010001 00011000
00000111Data 0
000110010101000000100000 00000000
0011000001100000
00000001
00010100
01100000 001000000001000000010000
00000111
00110000 00010100
00000001
01000010 00011001
01100100
01000010 00011001
01100100
Instruction 10:
mark = register−2STORE
4
1
3
5
6
2
34
Central Processing Unit
Control Unit ALU
InstructionFetch
HALT
Instruction
Data 3
Data 1
Data 2
PointerMemory
... ...
01010011 00010110
00000001 01100100
000101110101001001010001 00011000
00000111Data 0
000110010101000000100000 00000000
0011000001100000
00000001
01100000 001000000001000000010000
00000111
00110000 00010100
00000001
00000000 000000000001100101000010
01100100
00000000 00000000
00010100
01100100
HALTInstruction 11:
1
3
2
35
The Evolution of the von Neumann Architecture
Most modern PCs use a bus archi-
tecture to connect different sys-
tem components to the CPU. Still
adheres to von Neumann’s basic
functional design and still suffers
from von Neumann’s bottleneck.
Parallel processing architectures
alleviate the bottleneck by mul-
tiplying processors - but each
processor is still uses the fetch-
execute paradigm.
CPU
Registers
ALU
UnitControl
System Bus
Memory Hard−Disk
Keyboard
Monitor
36
Lecture Exercise
Using the Instruction Set Architecture (ISA) described in the
lecture, devise a program to solve the following problem: the
Global Regulated Economic Efficiency Development Bank offers
loan accounts to farmers in underdeveloped areas. Every month
the bank checks its accounts to decide if an account keeping
fee should be charged. It uses the following rule: if an account
balance is less than or equal US$25 then charge the account a
US$5 fee, otherwise leave the account balance unchanged.
You should write each instruction as a 16 bit binary number
that specifies the necessary register and memory addresses and
diagrammatically show how the program and data would be rep-
resented in memory.
37
Related Documents
