Outline Floorplanning and Topology Generation for Application-Specific Network-on-Chip Bei Yu 1 Sheqin Dong 1 Song Chen 2 Satoshi GOTO 2 1 Department of Computer Science & Technology Tsinghua University, Beijing, China 2 Graduate School of IPS Waseda University, Kitakyushu, Japan 2010.01.20 Bei Yu Floorplanning & Topology Generation for NoCs
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Floorplanning and Topology Generation for Application ...Switch Communication Graph(SCG) Path Allocation on SCG Minimize power consumption Minimize hop-count Satisfy width constraints
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Outline
Floorplanning and Topology Generation forApplication-Specific Network-on-Chip
Bei Yu1 Sheqin Dong1 Song Chen2 Satoshi GOTO2
1Department of Computer Science & TechnologyTsinghua University, Beijing, China
2Graduate School of IPSWaseda University, Kitakyushu, Japan
2010.01.20
Bei Yu Floorplanning & Topology Generation for NoCs
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Previous WorksProblem Formulation
Network-on-Chip
Solution to global communication challengesAlternative to Bus communication architectures
Better modularityLower power consumptionScalability
Regular NoCs and Application-Specific NoCsNetwork components:
SwitchNetwork Interface (NI)
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
S=Switch
DSP
NI
RISCCPU
NISRAM
NI
calcNI
samp
NI
MediaCPU
NI
SDRAMNI
VU SRAM
S
S
NINI
S
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Previous WorksProblem Formulation
Regular or Application-Specific Topology
Regular TopologyTask Scheduling and Mapping problem
Application-Specific Topology?1 Irregular core sizes2 Different communication flow requirements3 Reducing energy by reducing hop count and switch count4 Possibly higher performance
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
S=Switch
DSP
NI
RISCCPU
NISRAM
NI
calcNI
samp
NI
MediaCPU
NI
SDRAMNI
VU SRAM
S
S
NINI
S
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Previous WorksProblem Formulation
Regular or Application-Specific Topology
Regular TopologyTask Scheduling and Mapping problem
Application-Specific Topology?1 Irregular core sizes2 Different communication flow requirements3 Reducing energy by reducing hop count and switch count4 Possibly higher performance
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
Node
SNI
S=Switch
DSP
NI
RISCCPU
NISRAM
NI
calcNI
samp
NI
MediaCPU
NI
SDRAMNI
VU SRAM
S
S
NINI
S
Focus on Application-Specific Topology Generation!
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Previous WorksProblem Formulation
Previous Works
–K.Srinivasan et al. TVLSI 06:
Used fixed floorplan as optimization starting point
Switch at corners of cores
–Murali et al. ICCAD06:
Two steps topology generation procedure using min-cut partitioner
Greedy based path allocation assignment
–Chan & Parameswaran, ASPDAC08:
Iterative refinement strategy
supports both packet-switched networks and point to point connections
–Murali et al. ASPDAC09:
Synthesis approach for 3D NoC
LP based switch position computation
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Previous WorksProblem Formulation
Motivations
In previous works:Partition w/o physical informationFail to consider area consumption of NI and Switch
In our works:Integrate partition into floorplanning phaseConsider Switches and NI area consumptionMin-Cost-Flow algorithm to insert NIEffective paths allocation to minimize power consumption
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Previous WorksProblem Formulation
Problem Formulation
Input:a set of n cores C = {c1, c2, . . . , cn}.switches number m.
core communication graph(CCG).
network components power model.
Output: an NoC topology satisfying
minimize area consumption.
minimize the communication energy.
v1
v2
v3
v4
v5
v6
CCG: Core Communication Graph.
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Previous WorksProblem Formulation
Synthesis Algorithm
Obtain min-cut partitions of CCGCommunication RequirementDistances between cores
Cores in a cluster share a switch
Switch Communication Graph(SCG)
Path Allocation on SCGMinimize power consumptionMinimize hop-countSatisfy width constraints
v1
v2
v3
v4
v5
v6
s1 s2
s3
s1
s2
s3
SCG
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Partition Driven FloorplanningSwitches and Network Interfaces InsertionEnergy Aware Path Allocation
Overview of Algorithm
Path Allocation
Floorplanning
Post-Floorplanning
CoreSize
CCGGenerate new floorplan
Partition
Stop?No
Switches Insertion
Network Interfaces Insertion
Optimized Floorplan
Yes
Generate floorplan with partitions.
c1 c2
c3
c4
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Partition Driven FloorplanningSwitches and Network Interfaces InsertionEnergy Aware Path Allocation
Overview of Algorithm
Path Allocation
Floorplanning
Post-Floorplanning
CoreSize
CCGGenerate new floorplan
Partition
Stop?No
Switches Insertion
Network Interfaces Insertion
Optimized Floorplan
Yes
Insert Switches.
c1 c2
c3
c4s1
s2
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Partition Driven FloorplanningSwitches and Network Interfaces InsertionEnergy Aware Path Allocation
Overview of Algorithm
Path Allocation
Floorplanning
Post-Floorplanning
CoreSize
CCGGenerate new floorplan
Partition
Stop?No
Switches Insertion
Network Interfaces Insertion
Optimized Floorplan
Yes
Insert NI with Min-Cost Flow Algorithm.
c1 c2
c3
c4s1
s2NI NI
NINI
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Partition Driven FloorplanningSwitches and Network Interfaces InsertionEnergy Aware Path Allocation
Overview of Algorithm
Path Allocation
Floorplanning
Post-Floorplanning
CoreSize
CCGGenerate new floorplan
Partition
Stop?No
Switches Insertion
Network Interfaces Insertion
Optimized Floorplan
Yes
Dynamic Programming basedPath Allocation.
c1 c2
c3
c4s1
s2NI NI
NINI
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Partition Driven FloorplanningSwitches and Network Interfaces InsertionEnergy Aware Path Allocation
Partition Driven Floorplanning
Traditionally, partition before floorplanning(-)Lose physical information
In our workIntegrate partition into floorplanningCores with larger communication incline to one clusterMinimize interconnect power consumption
Define new edge weight w ′ij in CCG:
w ′ij = αw ×
wij
max w+ αd ×
mean disdisij
Using CBL1 as topological representationRecord white space information
1X. Hong et al, IEEE Transaction on CAS 2004.Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Partition Driven FloorplanningSwitches and Network Interfaces InsertionEnergy Aware Path Allocation
Switches Insertion
After floorplanning stageEach cluster has a minimal bounding box.
Heuristical method to insert switches:
1 Switch initially in the center ofbounding box.
2 Partition the white space into grids.3 Sort switches.4 Insert switches in grids one by one.
In cluster pk , cost of insert switch k to grid g:
Costgk =∑
i,j
wij × (disgi + disgj),∀eij ∈ E
Choose free grid with smallest Cost .
c1 c2
c3
c4
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Partition Driven FloorplanningSwitches and Network Interfaces InsertionEnergy Aware Path Allocation
Switches Insertion
After floorplanning stageEach cluster has a minimal bounding box.
Heuristical method to insert switches:
1 Switch initially in the center ofbounding box.
2 Partition the white space into grids.3 Sort switches.4 Insert switches in grids one by one.
In cluster pk , cost of insert switch k to grid g:
Costgk =∑
i,j
wij × (disgi + disgj),∀eij ∈ E
Choose free grid with smallest Cost .
c1 c2
c3
c4s2s1
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Partition Driven FloorplanningSwitches and Network Interfaces InsertionEnergy Aware Path Allocation
Switches Insertion
After floorplanning stageEach cluster has a minimal bounding box.
Heuristical method to insert switches:
1 Switch initially in the center ofbounding box.
2 Partition the white space into grids.3 Sort switches.4 Insert switches in grids one by one.
In cluster pk , cost of insert switch k to grid g:
Costgk =∑
i,j
wij × (disgi + disgj),∀eij ∈ E
Choose free grid with smallest Cost .
c1 c2
c3
c41 2 3 4
896107
5
s2s1
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Partition Driven FloorplanningSwitches and Network Interfaces InsertionEnergy Aware Path Allocation
Switches Insertion
After floorplanning stageEach cluster has a minimal bounding box.
Heuristical method to insert switches:
1 Switch initially in the center ofbounding box.
2 Partition the white space into grids.3 Sort switches.4 Insert switches in grids one by one.
In cluster pk , cost of insert switch k to grid g:
Costgk =∑
i,j
wij × (disgi + disgj),∀eij ∈ E
Choose free grid with smallest Cost .
c1 c2
c3
c41 2 3 4
896107
5
s2s1
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Partition Driven FloorplanningSwitches and Network Interfaces InsertionEnergy Aware Path Allocation
Switches Insertion
After floorplanning stageEach cluster has a minimal bounding box.
Heuristical method to insert switches:
1 Switch initially in the center ofbounding box.
2 Partition the white space into grids.3 Sort switches.4 Insert switches in grids one by one.
In cluster pk , cost of insert switch k to grid g:
Costgk =∑
i,j
wij × (disgi + disgj),∀eij ∈ E
Choose free grid with smallest Cost .
c1 c2
c3
c41 2 3 4
896107
5
s1s2
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Partition Driven FloorplanningSwitches and Network Interfaces InsertionEnergy Aware Path Allocation
After flow (s1→ s3):shortest path from s2 to s3 iss1→ s4→ s3.
s2
s3
s4s1
t24=1t34=2
tij:power from i to j ?
t12=2->4
t23=2->4
s2
s3
s4s1
1->32->4t12=2->4
t23=2->4
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Partition Driven FloorplanningSwitches and Network Interfaces InsertionEnergy Aware Path Allocation
Energy Aware Path Allocation
disn(i , d): distance from node i to d
dise(i , j , d): distance i to d using eij
DP based method to find paths:
dise(i , j , d) =
{tid , j = dtij + disn(j , d), otherwise
disn(i , d) =
{0, i = dmink dise(i , k , d), otherwise
run time is bounded by O(|V | · |E |)if dise(i , j , d) = disn(i , d), then path(i , d) = j .
1
2
3
4
5
6
7
2
3
7
4
2
5
25
3
22
6
4
1
2
3
4
5
6
7
8
10
9
6
9
7
67
7
22
8
4
dise(i,j,7)
Find initial paths.
Label dise(i , j , 7).
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Partition Driven FloorplanningSwitches and Network Interfaces InsertionEnergy Aware Path Allocation
Update Paths
1: //Update when tij change to (tij + ∆t);2: tij ← (tij + ∆t);3: queue q.push(eij );4: while q is not empty do5: eab ← q.pop();6: dise(a, b, d)← tab + disn(b, d);7: if PATH[a][d ] = b then8: Find k ∈ Post(a)a to minimize
disn(k , d) + tak ;9: disn(a, d)← disn(k , d) + tak ;
10: path(a, d)← k ;11: q.push(epa), ∀p ∈ Pre(a)b;12: end if13: end while
aPost(a) = {vk |∀vk ∈ V & eak ∈ E}bPre(a) = {vk |∀vk ∈ V & eka ∈ E}
1
2
3
4
5
6
72
2
4
2->10
7
15
1615
910
9
86
1
2
3
4
5
6
7
8
10
9
6
9
7
67
7
22->10
8
4
dise(i,j,7)
Remove path 3→ 5.Add path 3→ 6.
Bei Yu Floorplanning & Topology Generation for NoCs
DSP: re-solves all distances by Dijkstra’s Shortest Path Algorithm.Ours: effective path update algorithm.
Larger graph, more effective.
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Conclusion
In our works:Intgrate partition into floorplanning phaseConsider Switches and NI area consumptionMin-Cost-Flow algorithm to insert NIEffective paths allocation to minimize power consumption
Bei Yu Floorplanning & Topology Generation for NoCs
IntroductionAlgorithm
Experimental Results
Thank You !
Bei Yu Floorplanning & Topology Generation for NoCs