Quantitative Analysis of Floating Point Arithmetic on FPGA Based Custom Computing Machines Nabeel Shirazi, A1 Walters, and Peter Athanas Virginia Polytechnic Institute and State University Department of Electrical Engineering Blacksburg, Virginia 2406 1-0 1 1 1 [email protected]Abstract Many algorithms rely on jloating point arithmetic for the dynamic range o f representations and require mil- lions of calculations per second. Such computationally intensive algorithms ar e candidates or acceleration using custom computing machines (CC Ms) being tailored or the application. Unfortunately, jloating point operat ors require excessive area (or time} fo r conventional i mple- mentations. Instead, custom or mat s, derived fo r individ- ual applications, are feasible on CCM s, and can be implemented on a fraction o f a single FPGA. Using higher-level languages, like VHDL, acilitates the devel- opment of custom o perators without signif rcantl y impact- ing operator performance or area. Properties, including area consump tion and speed o f working arithmetic opera- tor units us ed in real-time applications, are discussed. 1.0 Introduction Until recently, any meaningful floating po int arlth- metic has been virtually i mpossible to implement o n FPGA based systems due to the limited density and speed o f older FPGAs. In addition, mapping difficulties occurred due to the inherent complexity of floating point arithmetic. Wi th the introduction of hig h level languages such as VHDL, rapid prototyping of floating point units h a s become possible. Elaborate simulation and synthesis tools at a higher design level aid the designer for a more controllable and maintainable product. Although low level design specifications were alternately possible, the strategy used in the work presented here w a s to specify every aspect of the design in VH DL and rely on automated synthesis to generate the FPGA mapping. Image and digital signal processing applications typically require high calculation throughput [2,6]. The arithmetic operators presented here were implemented for real-time signal processing on the Splash-2 CCM, which include a 2-D fast Fourier transform (FFT) and a systolic array implementation of a FIR filter. Such signal process- ing techniques necessitate a large dynamic range of num- bers. The use of floating point helps to alleviate the underflow and overflo w problems often seen in fixed point formats. An advantage of using a CC M for floating point implemen tation is the ability to customize the format and algorithm data flo w to suit the applicat ion’s needs. This paper examines the implementations of vari- ous arithmetic operators using two floating point formats similar to the IEEE 754 standard [5]. Eighteen and sixteen bit floating point adders/subtracters, multipliers, and dividers have been synthesized for Xilinx 4010 FPGAs [8]. The floating formats us ed are discussed in Section 2. Sections 3, 4, and 5 present the algorithms, implementa- tions, and optimizations used for the different operatois. Finally a summary, in terms of size and speed, .ci f the d k - ferent floating point units is given Section 6. 2. 0 Floating Point Format Representation The format which was used is similar to the BE E 754 standard used to store floating point numbers. For comparison purposes, singl e precision floating point uses the 32 bit IEEE 754 format shown in Figure 1 . I s I e f I Bit#: 31 30 23 22 0 Figure 1 : 32 Bit Floating Point Format. 155 0-8186-7086-X/95 04.00 0 1995 EE E
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for the dynamic range of representations and require mil-
lions of calculations per second. Such computationallyintensive algorithms are candidates or acceleration using
custom computing machines (CC Ms )being tailored o r the
application. Unfortunately, jloating point operators
require excessive area (o r time} fo r conventional imple-
mentations. Instead, custom or mat s, derived fo r individ-
ual applications, are feasible on CCM s, and can be
implemented on a fraction of a single FPGA. Using
higher-level languages, like V HD L, acilitates the devel-opment of custom o perators without signifrcantly impact-
ing operator performance or area. Properties, includingarea consump tion and speed of working arithmetic opera-tor units used in real-time applications, are discussed.
1.0 Introduction
Until recently, any meaningful floating point arlth-
metic has been virtually impossible to implement on
FPGA based systems due to the limited density and speed
of older FPGAs. In addition, mapping difficulties
occurred due to the inherent complexity of floating point
arithmetic. With the introduction of high level languages
such as VHDL, rapid prototyping of floating point units
has become possible. Elaborate simulation and synthesis
tools at a higher design level aid the designer for a morecontrollable and maintainable product. Although low
level design specifications were alternately possible, the
strategy used in the work presented here was to specify
every aspect of the design in VHDL and rely on automated
synthesis to generate the FPGA mapping.
Image and digital signal processing applicationstypically require high calculation throughput [2,6]. The
arithmetic operators presented here were implemented for
real-time signal processing on the Splash-2 CCM, which
include a 2-D fast Fourier transform (FFT) and a systolic
array implementation of a FIR filter. Such signal process-
ing techniques necessitate a large dynamic range of num-
bers. The use of floating point helps to alleviate the
underflow and overflow problems often seen in fixed point
formats. An advantage of using a CC M for floating point
implementation is the ability to customize the format and
algorithm data flow to suit the application’s needs.
This paper examines the implementations of vari-
ous arithmetic operators using two floating point formats
similar to the IEEE 754 standard [5] . Eighteen and sixteenbit floating point adders/subtracters, multipliers, and
dividers have been synthesized for Xilinx 4010 FPGAs
[8]. The floating formats used are discussed in Section 2.
Sections 3, 4, and 5 present the algorithms, implementa-
tions, and optimizations used for the different operatois.
Finally a summary, in terms of size and speed, .cif thedk-
ferent floating point units is given Section6.
2.0 Floating Point Format R epresentation
The format which was used is similar to the BE E
754 standard used to store floating point numbers. For
comparison purposes, single precision floating point uses
although a special case for 1.0 has to be made. The nor-
malization process is done automatically with k,. Once
the addition is done, the result becomes the new exponent
passed onto Stage 2. The mantissa in Stage 1 directly goes
to the memory address buffer to obtain the new mantissa,
but the old mantissa continues into Stage 2 and is replaced
in Stage 3. Stage 2 of the pipeline waits for the data to
become available from the memory. This occurs at Stage
3. The new mantissa is inserted into the final operand to
be passed to the multiplier. Although threepipeline stages
are shown here, additional stages occur due to the pipe-
lined multiplier to make a total of five stages.
FG Function
Generators
6.0 Summ ary and Conclusions
Adder/Subtracter Multiplier Divider
28% 44% 46%
The aim in designing the floating point units was topipeline each unit a sufficient number of times in order to
maximize speed and to minimize area It is important to
note that once the pipeline is full, a result is output every
clock cycle. A summary of the resulting size and speed ofthe 16 bit and 18 bit floating point units is given in Tables
4 and 5 respectively.
The Synopsys Version 3.0a VHDL compiler was
used along with the Xilinx 5.0 tools to compile the VHDL
description of the floating point arithmetic units. The Xil-
inx timing tool, xdeluy, was used to estimate the speed of
the designs.
Speed
Tested Speed
8.6 MHz 4.9 MHz 4.7MHz
10 MHz 10MHz 10MHz
I I I
Speed I 9.3MHz I 6.0MHz I 5.9MHz
FG Function
Generators
ni p Flops
Stages
TABLE 4. Summary of 16 bit Floating Point Units.
Adder/Subtracter Multiplier Divider
26 % 36% 38%
13% 13% 32%
3 3 5
To implement single precision floating point arith-
metic units on the Splash-2 architecture, the size of the
floating point arithmetic units would increase between 2
to 4 imes over the 18 bit format. A multiply unit would
requiretwo Xilinx 4010 chips and an adder/subtracter unit
I FliDFlo~s I 14% I 14% I 34% I
I Stages 1 3 1 3 1 5 1
I I I I I
TABLE 5. Summary of 18 bit Floating Point Units.
broken up into four 12-bit multipliers, allocating two per
chip[4]. We found that a 16x16 bit multiplier was the larg-
est parallel integer multiplier that could fit into a Xilinx
4010 chip. When synthesized, this multiplier used 75%of
the chip area
InputData Coefficient Data
PartialConvolution Sum
$6
Figure 7; The diagram shows a single Splash-2PE design for an FIR tap to ac complish complexmultiplication. The architecture can achiev e twofloating-point calculations per clock cyc le.
Figure 8: A block diagram of a four PE Sp~Sh-2esign for a complexfloating point multiplier used in a FFT butterfly operation. Six floatingoperations are calculated every clock cycle at 10 MHz .
Each of the floating point arithmetic units has been
incorporated into two applications: a 2-D FFT [6] and aFIR filter [7]. The FFT application operates at 10MI-Iz
and the results of the transform are stored in memory onthe Splash-2array board. These results were checked by
doing the same transform on a SPARC workstation An
FIR tap design using a floating point adder and multiplierunit is shown in Figure 7. The complex floating point
multiplier used in the 2-D FFT butterfly calculation is
shown in Figure 8.
Acknowledgments
We wish to express our gratitude to Dr. J. T,
McHenry and Dr. D. Buell. We would also like to thank
Professor J. A. DeGroat of The Ohio State University for
technicaladvice,This research has beep supported in part by the
National Science Foundation (NSF) under gmnt M I P -
9308390.
References
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