Flip Flops, Registers. Today: First Hour : Types of Latches, Flip Flips Section 6.1.4-6.1.6 of Katz’s Textbook In-class Activity #1 Second Hour : Storage and Shift Registers Section 7.1 of Katz’s Textbook In-class Activity #2. State Diagrams for Latches. Truth Table Summary - PowerPoint PPT Presentation
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1
Flip Flops, RegistersFlip Flops, Registers
Today:
• First Hour: Types of Latches, Flip FlipsLatches, Flip Flips– Section 6.1.4-6.1.6 of Katz’s Textbook
– In-class Activity #1
• Second Hour: Storage and Shift Registers• Section 7.1 of Katz’s Textbook
– In-class Activity #2
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State Diagrams for LatchesState Diagrams for Latches
State Behavior of R-S Latch
Truth Table Summary of R-S Latch Behavior
Q Q Q Q
Q Q
0 1 1 0
0 0
Q Q1 1
Q
hold 0 1
unstable
S
0 0 1 1
R
0 1 0 1
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State Diagram: R-S LatchState Diagram: R-S Latch
Theoretical R-S Latch State Diagram
Q Q Q Q
Q Q
0 1 1 0
0 0
SR = 1 0
SR = 0 1
SR = 0 1
SR = 1 1
SR = 1 0
SR = 1 1
SR = 00, 01 SR = 00, 10
Q Q1 1
SR = 0 0
SR = 0 0, 11
SR = 11
SR = 1 0SR = 0 1
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Observed R-S BehaviorObserved R-S Behavior
Q Q Q Q
Q Q
0 1 1 0
0 0
SR = 1 0
SR = 0 1
SR = 0 1
SR = 1 1
SR = 1 0
SR = 1 1
SR = 00, 01 SR = 00, 10
SR = 0 0
SR = 11
SR = 0 0
Very difficult to observe R-S Latch in the 1-1 state
R-S Clocked Latch: used as storage element in narrow width clocked systems its use is not recommended! however, fundamental building block of other flipflop types
J-K Flipflop: versatile building block can be used to implement D and T FFs usually requires least amount of logic to implement ƒ(In,Q,Q+) but has two inputs with increased wiring complexity
because of 1's catching, never use master/slave J-K FFs edge-triggered varieties exist
D Flipflop: minimizes wires, much preferred in VLSI technologies simplest design technique best choice for storage registers
T Flipflops: don't really exist, constructed from J-K FFs usually best choice for implementing counters
Preset and Clear inputs highly desirable!!
Comparison of FFsComparison of FFs
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Timing issues revisitedTiming issues revisited
J
K
Q
\ Q
100 Set Reset Toggle
Problem: Keeps toggling!
R
S Q
Q
LatchQ
QJ
K
10
Master section - clock high
J-K inputs generate P outputs
Master section - clock high
J-K inputs generate P outputs
Slave section - clock low
Ps are unchanging and generate Qs
Slave section - clock low
Ps are unchanging and generate Qs
J-K Master/Slave F-FJ-K Master/Slave F-F
R
S
Q
Q
Latch
R
S
Q
Q
Latch
Clock
J
K
Q
Q
P
P
Clock
Two-stage memory element Two-stage memory element Two-stage memory element Two-stage memory element
Two-phase clock operation - Feedback has no effect until next time clock is highTwo-phase clock operation - Feedback has no effect until next time clock is high
- a 0-1-0 glitch on the J or K inputs leads to a state change!- I.e. If input 1 any time during the clock period, it will be interpreted as a 1 for computing output
=> forces designer to use hazard-free logic
Solution: edge-triggered logic called “Flip-flops”
Negative Edge-TriggeredD flipflop
Schematic when clock is high: R=S=0 I.e. Hold state
– LW uses A,B,C,D for inputs and QA,QB,QC,QD for outputs.
– Motorola uses P0,P1,P2,P3 for inputs, Q0,Q1,Q2,Q3 for outputs and DSR & DSL for serial inputs.
• NoteNote that the normal LW convention is that A is the lo-order bit. This is the way you normally connect the hex keyboard and the hex display. For the 194, A and QA are the hi-order bits. It's confusing.
• Right shift in more detail. All together on the rising clock:
SR QA, QA QB, QB QC, QC QD, QD is lost.
Connecting QD to SR makes a circular shift register.
• Left shift in more detail.
SL QD, QD QC, QC QB, QB QA, QA is lost.
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Do Activity #2 NowDo Activity #2 NowDue: End of Class Today
RETAIN THE LAST PAGE (#3)!!
For Next Class:• Bring Randy Katz Textbook, & TTL Data Book
• Required Reading:– Sec 7.2, 7.3 of Katz
• This reading is necessary for getting points in the Studio Activity!