Flex Logix eFPGA as Silicon Debugger v1.1 · significantly improving the visibility and control at various points inside the device. 2. About Flex Logix eFPGA 2.1. ... Flex Logix

FlexLogixeFPGAasSiliconDebuggerApplicationNotev1.1

Contents1. Introduction.................................................................................................................................................2

2. AboutFlexLogixeFPGA................................................................................................................................2

2.1. IntroductiontoEmbeddedFPGAs.......................................................................................................2

2.2 EFLXEmbeddedFPGAs........................................................................................................................2

3. PriorArt........................................................................................................................................................3

4. Debug,ConfigurationandManagementmoduleineFPGA.........................................................................4

5. SimpleExample............................................................................................................................................6

5.1 TraditionalSoCmodule.......................................................................................................................6

5.2 LimitedVisibilityandControllability....................................................................................................7

5.3 ProtectingyourdesignwitheFLEXembeddedFPGA..........................................................................7

5.3.1. ImproveObservability.................................................................................................................8

5.3.2. AddEventTriggers......................................................................................................................9

5.3.3. SeeHiddenDatawithEmbeddedLogicAnalyzer......................................................................10

5.3.4. Future-proofYourDesign..........................................................................................................12

6. Conclusions................................................................................................................................................14

FlexLogixeFPGAasSiliconDebugger

2

1. IntroductionSilicondebuggingisverychallengingasvisibilityinsidethedeviceislimitedtoalimitedsetofviewpointsthatareavailableinhardware.Thoseviewpointsmayinclude:

• DeviceIOs• Deviceregisters• Predefinedsignalsroutedtoadebugport

Thefirsttworesourcesareconsideredfreeastheyarepartoftheproductdefinitionanddon’trequireadditionaleffortorresourcestobeimplemented.

ThedebugportispurposelyaddedtohelpdebugthedeviceandisusuallycomposedofabigMUXthatcanselectavarietyofsignalsatdifferentpredefinedpointsinsidethedevice.Atanygiventime,onlyapredefinedsetofthosesignalscanbeavailableatthedebugportforobservation.

Thisapplicationnotedescribesanewandimprovedwaytoadddebugcapabilitiestoasilicondevice,significantlyimprovingthevisibilityandcontrolatvariouspointsinsidethedevice.

2. AboutFlexLogixeFPGA

2.1. IntroductiontoEmbeddedFPGAsAnFPGAcombinesanarrayofprogrammable/reconfigurablelogicblocksinaprogrammableinterconnectfabric.InanFPGAchip,theouterrimofthechipconsistsofacombinationofGPIO,SERDESandspecializedPHYssuchasDDR3/4.InadvancedFPGAs,theI/Oringisroughly1/4ofthechipandthe“fabric”isroughly3/4ofthechip.The“fabric”itselfismostlyinterconnectintoday’sFPGAchipswhere20-25%ofthefabricareaisprogrammablelogicand75-80%isprogrammableinterconnect(notincludingconfigurationbits).Programmablelogicincludingconfigurationbitsandinterconnectincludingconfigurationbitsarecloserto50-50.AnembeddedFPGAisanFPGAfabricwithoutthesurroundingringofGPIO,SERDES,andPHYs.Instead,anembeddedFPGAconnectstotherestofthechipusingstandarddigitalsignaling,enablingverywide,faston-chipinterconnects.

2.2 EFLXEmbeddedFPGAsFlexLogixprovideshigh-density,high-performance,energy-efficientembeddedFPGAhardIP.EFLXisascalablearchitectureofsilicon-provenIPthatenablesembeddedFPGA’sfrom120LUTsto>100KLUTs.Thesmallestcore(EFLX-100)has120LUTswith152inputsand152outputs.Thelargercore(EFLX-2.5K)has2,520LUTswith632inputsand632outputs.Thecorescanbe“tiled”toformarrays.TheEFLX-100corescanbetiledtobuildarraysupto5x5or3,000LUTsofreconfigurablelogicwith760inputsand760outputs.TheEFLX-2.5Kcorescanbetiledtobuildarraysupto7x7or123KLUTsofreconfigurablelogicwith4,424inputsand4,424outputs.TheEFLXcoreshavetwoversionsthatcanbemixedtogetherinarrays.Oneversionisalllogicandtheotherhas22-bitMACsforDSPfunctions.Thesmallcorecanhave2MACsandthelargecorescanhave40MACs.Thecoresalsosupportmemorystructuresthatcanbepartofthearrayforsmallsizesoroutsideofthearrayforlargersizes.

FlexLogixeFPGAasSiliconDebugger

3

TheembeddedFPGAisprogrammedusingVerilogorVHDLwhichareinputtoasynthesistoolsuchasSynopsys’Synplify.TheEFLXCompilertakesthesynthesizedoutputandpacks/places/routesthearrayandgeneratesabitstreamwhichprogramstheEFLXarraytoemulatetheRTL.ThebitstreamforasingleEFLX-100is~50Kbitsandcanbestoredinthesameflashmemorythatstorestheembeddedprocessorcode.TheEFLXarraycanbereprogrammedatanytime,justlikewithanembeddedprocessor.EFLXarrayscanbeintegratedintoanSoCorMCUinthreecommonwaysasdepictedinFigure1.

Figure1EFLEXuseexamples

3. PriorArtTherearemanySoCs,custombuiltforvariousapplicationlikeCPU,networking,storage,GPU,acceleratorsandmanymore.Theirarchitectureiscustomizedfortheirpurposebutallofthemincludesomebasicmodulesthatallowthemto:

• Receivedata• Storethedata• Processthedata• Outputresults• Managethedevice• Testanddebugthedevice

TheblockdiagraminFigure2showsonesuchdesign.NotehowtheConfiguration&ManagementmodulehassimilarsystemconnectionsastheDebugmodule.However,theDebugmoduleusuallyconnectstoalargervarietyofsignals,includingwidedatabusses,andtypicallyhasalargemultiplexerthatallowsreal-timevisibilityofthosesignalsthroughtheDebugPort.

FlexLogixeFPGAasSiliconDebugger

4

Figure2TypicalSoC

ThisarchitecturecreatesroutingcongestionaroundtheDebugmoduleandislimitedinvisibilitybythedesignofthemultiplexerinsidetheDebugmodule.Furthermore,thesignalscanonlybeobservedbyphysicallyconnectingintotheDebugPortmakingitextremelydifficulttodebugdevicesthatareoperationalinthefield.

4. Debug,ConfigurationandManagementmoduleineFPGATheFlexLogixeFPGAaddsahighdegreeofflexibilitytotheSoC.TheConfigurationandManagementmoduletogetherwiththeDebugmoduleareexcellentcandidatesforimplementationineFPGAasshowninFigure3.

MediaAccessController

MediaAccessController

MediaAccessController

MemoryController

CPU PeripheralBus

Queueing

Configurationand

Management

DDR

PCIe

DebugRAMTrafficManager

Debug

FlexLogixeFPGAasSiliconDebugger

5

Figure3eFPGAaddsflexibilityandsimplifiesthearchitectureandrouting

Thefactorsthatledtothissuggestionare:

• Visibilityandcontrollabilityarehighlydesirableforbothmanagementanddebugfunctionality.OneEFLX2.5KeFPGAcorehas632inputsand632outputs,andoneEFLX100corehas152inputsand152outputs,providingexpandedaccesstochipmanagementanddebug.

• ConnectivityofbothConfigurationandManagementmoduleandtheDebugmoduleareverysimilarandlargelyredundant.IntegrationofConfigurationManagementandDebugintoasinglemoduleandpruningofredundantconnectivityreducesroutingcongestion.

• DebuggingtheSoCusuallyrequiresacombinationofsignalmonitoringthroughthemanagementandconfigurationaswellasthedebugport.Addingreal-timevisibilitytoallsignals,aswellascontrol,inasinglepoint(eFPGA)highlysimplifiesthedebugprocess.

• ThelogicimplementedintheeFPGAcoreallowsforreal-timeinterventionatpre-definedpointsinthedeviceallowingtoaddaftermarketfunctionalityorbugworkaroundstothedevice,reducingtheriskofadevicere-spin.

• TheflexiblelogicinsidetheeFPGAallowsforverycomplexeventtriggersthatcanhelpcaptureandfilterrelevanteventswithouttheuseofexternallogicanalyzers.

• DatacanbecapturedandstoredintheeFPGAorRAMforremoteaccess.• Additionalstatisticscanbeeasilygatheredbasedontheconnectedsignals.Unneededstatisticscan

beeliminatedtoreducesiliconarea.• StaticConfigurationregisterscanbereducedtoconstantsimplementedintheeFPGAconfiguration

file.TheirvaluescanbechangedbymodifyingtheeFPGAimageanddon’toccupyflip-flops.• HavingthosecapabilitiesinallSoCs,withouttheneedofexpensiveandcomplexlabequipment,

allowforlow-costhighlyparallelizeddiagnosticeffortinthelabandinthefieldoverlongperiodsoftime.

MediaAccessController

MemoryController

CPU PeripheralBus

Queueing

eFPGAConfigurationManagementandDebug

DDR

PCIe

RAMTrafficManager

MediaAccessController

MediaAccessController

FlexLogixeFPGAasSiliconDebugger

6

5. SimpleExample5.1 TraditionalSoCmoduleForthisexample,we’lluseasortengineastheDUT(DesignUnderTest).Thesortenginereceivespacketsofdataononesideandoutputsthesamepacketswiththeirdatasortedinascendingorderontheotherside.

ThediagraminFigure4showsthearchitectureofthissortengine.

Theoperationmodeofthesortengineisasfollowing:

• Receivethedatapackets(in_stage)• StorethedatapacketsintheSRAM• ThesortmodulesortsthedataintheSRAM• Transmitthesorteddatapackets(out_stage)• CPUinterfacestoconfig_and_managementtoprogramvariousconfigurationparametersand

monitortheactivity• Thedesigncanbedebuggedbyobservingvarioussignalsinthedebug_monitormodule

Theinputprotocolisasimpledata_inanddata_v_inprotocol,wherethedatapacketstartswiththeassertionofthedata_v_insignalandendswithitsde-assertion.Nopausesarepermittedinamiddleofadatapacket,onlybetweenthepackets.Themodulein_stagealsohasahold_inoutputsignalthat,whenTRUE,isaskingthedatasendertoholdafterthecurrentpacket,untilhold_inisFALSEagain.

Inasimilarway,theout_stagemodulehasdata_out,data_v_outoutputsandhold_outinput.Thedata_outanddata_v_outareoutputtingsortedpacketsandthehold_outinputsignalcanstoptheout_stagemodulefromoutputtingpackets,alsoonpacketboundaries.

Figure4SortengineintraditionalSoC

WRITE_ARBIN_STAGE OUT_STAGE

SORT

SRAM

READ_ARB

CONFIG&MANAGEMENTREGISTERS

data_in data_out

CPUI/F

DEBUGMONITOR

debug

FlexLogixeFPGAasSiliconDebugger

7

ThesortmodulewillreaddatafromtheSRAMandsortthedata,maintainingthepacketstructure.ThesortalgorithmusedQuick-Sort.

5.2 LimitedVisibilityandControllabilityTheDebugMonitorandConfig&Managementblocks(orangeinFigure4),requirealotofflexibilityandoccupyalotofareainsilicon.

MostoftheregistersintheConfig&Managementarerarelychangedbytheuserandonlycontainstaticconfiguration.

TheDebugmoduleshouldallowvisibilityinalldesignsignalsbutitispracticallylimitedbytheroutingcomplexityofmultiplexingmanysignalsintoalimited-sizedebugbuswhileallowinganypossibleconfigurationofsignals.Inpractice,thismodulewilllimitvisibilitytoasmallsetofpredefinedsignalconfigurations.

5.3 ProtectingyourdesignwitheFLEXembeddedFPGATheFlexLogixeFPGAallowsanewdegreeofflexibilitytobeaddedtoyourdesign.HerearevariousfeaturesoftheeFPGAcoresthatcanhelpimprovevisibilityandcontrollabilityofyourdesign:

Feature Benefit

Hundredsofinputsandoutputs

• Greatestpossibleobservability,tapintohundredsofplaces

Configurablerouting • Routeanycombinationofsignalstothedebugport,triggersorstorageforgreatestvisibility

Storageelements • Sampledataatthetappoints,allowsforbacktrackingandformonitoringhigh-speedsignals

• Savesthecostoflogicanalyzersandallowsdebuginthefield

Configurablelogiccells • Buildcustomcomplexeventtriggerstodetecteventsofinterest

eLogicAnalyzer • Storemeaningfuldataaroundtriggereventsandaccessitremotely• Savethecostoflogicanalyzersandallowdebuginthefield

Alloftheabove • AugmentorreplaceentiredesignstosavetheASICfromcostlyre-spins

ThesamedesignofFigure4canbeimprovedbyaddinganeFPGAcoreasshowninFigure5.

TheeFPGAcoreconnectstoallmajorbussesandsignalsintheoriginaldesign.Inaddition,twointerfacemultiplexersallowtheeFPGAtoselectthenormaloperationofthedesignorcompletelyreplacethedesign.

FlexLogixeFPGAasSiliconDebugger

8

Figure5SortenginedesignwitheFPGA

5.3.1. ImproveObservabilityTheoriginaldesignhadalimitednumberofsignalsconnectedtothedebugport.Sincethedebugportislimitedinsize,onlyasmallsetofthesignalscanbeobservedatanytimeandthedesignermustpredefinewhatsignalcombinationwillbemadeavailable.Belowisadesignexample.Note:somesignalsarereplicatedinseveralconfigurationsofthemultiplexerandonly32signalscanbeviewedatanygiventime.

// example of how a debug port is usually implemented in ASIC. // debug port outputs output [31:0] debug; // to debug port wire [2:0] debug_mux; // CPU Write Register reg [31:0] debug; wire [31:0] debug1, debug2, debug3, debug4, debug5, debug6, debug7, debug8; assign debug1 = {data_v_in, data_v_out, hold_in, hold_out, req1, req2, WE1, WE2, write_ptr, write_ptr_to_out_stage, read_ptr}; // mix of major signals assign debug2 = {hold_in, read_ptr[6:0], data_v_in, write_ptr[6:0], data_in}; // cutting MSB of pointers to save wires assign debug3 = {ack_w2, WE2, WE1, WE, 3'h0, data_w, adrs_w}; // write_arb assign debug4 = {ack_r2, req2, req1, 4'h0, data_r, adrs_r}; // read_arb assign debug5 = {WE2, ack_w2, adrs_w2[1:0], req2, ack_r2, data_r2, adrs_r2}; // sort read assign debug6 = {WE2, ack_w2, adrs_r2[1:0], req2, ack_r2, data_w2, adrs_w2}; // sort write assign debug7 = {adrs_w1[1:0], adrs_w2[1:0], WE1, WE2, WE, data_w, adrs_w}; // SRAM read assign debug8 = {req1, req2, ack_r2, adrs_r1[1:0], adrs_r2[1:0], data_r, adrs_r}; // SRAM read always @(debug1 or debug2 or debug3 or debug4 or debug5 or debug6 or debug7 or debug8 or debug_mux) begin case (debug_mux) 0: debug = debug1; 1: debug = debug2; 2: debug = debug3; 3: debug = debug4;

WRITE_ARBIN_STAGE OUT_STAGE

SORT

SRAM

READ_ARBdata_in data_out

CPUI/F

debug

eFPGA

FlexLogixeFPGAasSiliconDebugger

9

4: debug = debug5; 5: debug = debug6; 6: debug = debug7; 7: debug = debug8; endcase // case (debug_mux) end // always @ (...

UsingtheeFPGAyoucanachievebetterobservabilityasfollows:

• ChooseoneormultipleEFLEXeFPGAcoresbasedondesignneedsandimplementthemonyourSoCo EFLEX-2.5Kcoreshave632inputsand632outputspercoreo EFLEX-100coreshave152inputsand152outputspercore

• MaptheeFPGAinputstothesignalsyouwanttomonitorattheSoCdesignstage;thosewilltypicallybethesignalsontherightsideoftheassignstatementsabove

• AfterASICproduction,assignanysignalstothedebugport(32-bitinthisexample)• CompileandloadthedesignintheeFPGA

// Example of how to route signals in the eFPGA // No need to implement a MUX as the design can be changed and reloaded on demand output [31:0] debug; // to debug port assign debug = {data_v_in, data_v_out, hold_in, hold_out, req1, req2, WE1, WE2, write_ptr, write_ptr_to_out_stage, read_ptr}; // mix of major signals

Figure6ExampleofdebugsignalmultiplexingusingaFLEX-100core

5.3.2. AddEventTriggersLookingforaspecificeventislikelookingforaneedleinahaystackunlessyouhaveatriggerthatcanidentifytheevent.Forexample,inthesortdesign,wemightencounterasituationwherethedataiscorruptedandobservingthefillleveloftheSRAM(whenitfillsup)willhelpfindthebug.However,thedebugmultiplexerinthisdesignonlyallowstoseethereadandwritepointerswithoutactuallyseeingwhataddressiswrittentoorreadandbywhomatthesametime.Asimpletriggerwillhelpdetecttheeventwhileobservingtherelevantdata,addressandcontrolbussesasexplainedintheprevioussection.

UsingtheeFPGAyoucanbuildandtrigger:

• ChooseoneormultipleEFLEXeFPGAcoresbasedondesignneedsandimplementthemonyourSoCo EFLEX-2.5Kcoreshave2,520LUTspercore(or1,860LUTsand40DSPs)o EFLEX100coreshave96LUTspercore

SoCcore

SOC_in

SOC_out

64

64

DEBUG_out64

EFLX_CFG EFLX_CONFIG

GPIO_in

GPIO_out16

16

GPIO_dir16

GPIO[15:0]I

OOE

I/O

I/OEFLX-100

Core

I/O

I/O

SoCChip

FlexLogixeFPGAasSiliconDebugger

10

• MaptheeFPGAinputstothesignalsyouwanttomonitorattheSoCdesignstage• AftertheASICproduction,buildthetriggerlogicintheeFPGAcore• Assignthetriggersandanyothersignalstothedebugport(32-bitinthisexample)• CompileandloadthedesignintheeFPGA

// Example of trigger logic to detect buffer overfill wire buffer_overfill; // makes sure there is always room for one more packet assign buffer_overfill = (write_ptr - read_ptr) > ((1<<AddressSize) - max_pkt_size)); assign debug = {buffer_overfill, WE1, WE2, WE, 1’b0, adrs_w1, adrs_w2, adrs_w};

5.3.3. SeeHiddenDatawithEmbeddedLogicAnalyzerADebugportthat’shardwiredtoabunchofsignalsisnotalwayssufficienttoseeallthedesiredsignals(32GPIOonlyinthisexample).Inaddition,thespeedofthedebugportisnotalwayssufficienttoseehigh-speedsignals.

ThislimitationcanbeovercomebyinstancingtheeLA(embeddedLogicAnalyzer)insideaEFLEXcore.TheeLAisfullyimplementedintheeFPGAcoreandcanconnectdirectlytotheSoCdebugportoranembeddedCPU.TheeLAcanusetheRAMelementsoftheEFLEX2.5KoruseexternalSRAMforlargerstorage.

Figure7EmbeddedLogicAnalyzer(eLA)andtriggeroneFPGA

TheFlexLogixeLA(EmbeddedLogicAnalyzer)hasthefunctionalityofahigh-endlogicanalyzerthatisavailableinanydesignwithaFlexLogixeFPGA.TheeLAallowsloggingofinternalsignalsatveryhighspeedsbasedoncomplextriggersorcontinuoussampling.Thetriggereventlocationcanbeanywherewithintherangeoftheloggingbuffer.

SoC

CUSTOMERDESIGN

eFPGA

input_signalsSW_clk

data_outconfig

clk

EmbeddedLogic

Analyzer

trigger

CPU(embeddedor

external)

SRAM(optional)

FlexLogixeFPGAasSiliconDebugger

11

ThetriggersimplementedasdescribedintheprevioussectionareusedtotriggereLA.TheeLAwillstoredataaroundthetriggerevent,dependingonitsconfiguration.TheeLAcanbeconfiguredtoworkwithanexternalSRAM(higherstoragecapacity)oruseinternalstorageelements.

Afterthetriggerisdetectedanddataisreadyfordownload,theCPUcanaccessthedata,throughaverysimpleserialinterface,processanddisplayit.AGUIsnapshotisshowninFigure8,showinghowtheinputsandoutputsonapre-sortesstagedescribedfurtheron.

WhentheCPUisembedded,thisoperationcanbeperformedcompletelyremotely,evenonchipsdeployedatacustomerlocation,allowingforaveryflexibledebugcapabilityfortheSoCitselfandevenfortheentiresystemwheretheSoCisdeployed.

module eLogiAnalyser( // stub instance of Embedded Logic Analyzer // Outputs eLA_data_out, // Inputs clk, eLA_input_signals, eLA_trigger, eLA_SW_clk, eLA_config); parameter eLA_SIGNAL_COUNT = 128; // EFLEX-2.5K has 632 inputs, EFLEX-100 has 224 max inputs // Global inputs input clk; // high speed clock that samples eLA_input_signals // design inputs input [eLA_SIGNAL_COUNT:0] eLA_input_signals; input eLA_trigger; // trigger condition // debug interface input eLA_SW_clk; // software clock for eLA_data_out & eLA_config output eLA_data_out; // serial data out input eLA_config; // configuration input for trigger location endmodule // eLogiAnalyzer

FlexLogixeFPGAasSiliconDebugger

12

Figure8EmbeddedLogicAnalyzeroutputdisplay

5.3.4. Future-proofYourDesignNewcustomerrequirementsandbugfixesareahigh-riskfactortoanySoCdesign.TheuseofsiliconproventhateFPGAcoresfromFlexLogixcanreducethisriskbyallowingnewfunctionalitytobeaddedtoyourexistingdesign,byleveragingeFPGAtoaugmentyourexistingSoCdesign.

Forexample,Figure5showshoweFPGAcanbeaddedtotheSortdesigninawaythatitcaninjectorinterceptdataonthedata-path.

Thedesignermaydeterminethatinsomescenario,thesortmachineisnotfastenoughanditmustbesomehowaccelerated.

Asimplepre-sortoftheinputdatacanspeed-uptheQuick-Sortalgorithm,reducingafullsetofreadsandwritesofeachpacket.Hereisanexampleofsuchadesign.

FlexLogixeFPGAasSiliconDebugger

13

Figure9Pre-Sort

TheinputtothePre-Sortisconnectedtothewire-tapofthedata_insignalinFigure5andtheoutputsareconnectedtothebypassMUX(left-sideMux,lowerinput).TheMUXisconfiguredtoselectthePre-Sortinputandthedesignincreasesitsperformancebyreducingtheoverallsortprocessingtime.

// This module does one stage of ascending sort on a stream of data // new reset signal as the eFPGA has its own reset `timescale 100ps/100ps module one_sort ( // Outputs data_out, data_v_out, // Inputs clk, data_in, data_v_in ); parameter WordSize = 16; input clk; input [WordSize-1:0] data_in; input data_v_in; output [WordSize-1:0] data_out; output data_v_out; reg [WordSize-1:0] data_out, data_s1, data_s2; reg data_v_out, data_v_s1, data_v_s2; wire switch; assign switch = data_v_s1 & data_v_s2 & // don't switch on first and last data (data_s2 > data_s1); // ascending order // replacing the reset condition with initial for simulation purposes only initial begin

FF

FFdata_v_in data_v_out

data_in[15:0]

FF

FF

?(s1>s2)

MUX

switch

1

0

MUX

1

0

s1 FFFF

data_out[15:0]

eFPGAs2

FlexLogixeFPGAasSiliconDebugger

14

data_out = {WordSize{1'b0}}; data_s1 = {WordSize{1'b0}}; data_s2 = {WordSize{1'b0}}; data_v_out = 1'b0; data_v_s1 = 1'b0; data_v_s2 = 1'b0; end always @(posedge clk) begin data_s1 <= #1 data_in; data_s2 <= #1 switch ? data_s2 : data_s1; data_out <= #1 switch ? data_s1 : data_s2; data_v_out <= #1 data_v_s2; data_v_s1 <= #1 data_v_in; data_v_s2 <= #1 data_v_s1; end endmodule // one_sort_stage

ThedesignsuggestedherefitswithinoneeFLEX-100core.OnTSMC16FF+process,thisdesignrunsat454MHz.

Manyotherfunctionsandmodificationscanbeperformedinsimilarways.

6. ConclusionsDebuggingcapabilitiesarealwayswelcomed,forinitialproductbring-uporforobservinganddebuggingfunctionalitylateron.

AvarietyofdebuggingfeaturesareavailablebyimplementingtheFlexLogixembeddedFPGAcores.Thisincludes:

• Highobservability–themanyeFPGAIOsallowforthousandsofsignalstobemonitored• Eventdetection–theeFPGAlogiccanbeconfiguredtodetectverycomplexsignalpatternstohelp

identifymeaningfulevents• Highvisibility–datacanbeloggedbytheeLAinsidetheeFPGAmemoryorinexternalSRAMsand

thenstudiedoffline• Highcontrollability–theDUTcanbeaugmentedbylogicmodulesimplementedintheeFPGA,saving

costlySoCre-spinsandreducingtime-to-marketofnewandimprovedfunctionality