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FLASH MEMORY RELIABILITYCorso di Laurea in Ingegneria ElettronicaPolitecnico di Milano, 10 Dicembre 2009
Angelo ViscontiNumonyx
R2-Technology CenterNon Volatile Memory Technology Development
• Focusing on reliability, the most important difference between NAND and NOR is the tunnel oxide thickness:– to achieve fast program/erase times NAND has thinner
tunnel oxide (typically 8nm versus 10nm for NOR)• A less important role is played by the differences in
programming mechanisms and VT distributions• From here follows, NOR Flash are considered, unless
Intrinsic vs Single-Bit Failure Modes• We call intrinsic those failure mechanisms affecting all the cell in a uniform way:
– They can be studied on single cells in test structures.– Related to materials properties
• Single-bit failure mechanisms affect few cells of a large sample set (e.g. several 100Mb):– They require a real device or a test chip for investigations– Can be related either to extrinsic defects (e.g. particles) or to specific configurations of intrinsic
During F-N erase (and F-N program in NAND):• Generation of oxide traps by high-field conduction• Generation of interface states at Si/SiO2 interface• The generation rate is field dependent• Electrons captured by traps into the oxide
• Degradation is due to interface states generated in the channel• Transconductance degradation causes a VT increase• Sub-threshold slope degradation causes bit-line leakage after erase (the leakage of
• Interface states generation and charge trapping in the oxide occurs along the whole channel during Program/Erase
• The window closure is the result of three contributions :– Variation of the transistor VT, measured at the floating gate– Oxide conduction variation– Transconductance degradation, leading to higher VG for the same ID
• Optimized cell design & operation are necessary to prevent Program/Erase window closure
• Intrinsic data retention for fresh devices can be well beyond 10 years• Most of the failure mechanisms are thermally activated• Process qualification includes 250oC retention bake for few weeks
• Thermal emission or tunneling (for traps close to the interface)
• High thermal activation (Ea = 1.1-1.3 eV)• Logarithmic in time• Slightly electric field dependent• Accumulated charge dependent• QOUT = f(T, log t, VT, Number of cycles)
• After P/E cycling, a finite amount of negative charge is accumulated (QACC)in tunnel oxide depending on– Number of P/E cycles– Average time between P/E cycles– Operating Temperature
• During bake treatment performed after cycling, QACC is released based on 1.1-1.3 eV activation energy mechanism
• Released charge originates a finite negative ΔVT
• ΔVT is not related to electronic charge loss from floating gate
High Temperature Retention after Cycling
QACC = QT(number of cycles) - QOUT(T, log t, VT, number of cycles)
• the impact of extrinsic defects have been dramatically reduced through the improvements ofprocess technology and screening effectiveness (electrical stresses, retention bakes)
After more than 15 years of high volume manufacturing and continuous learning:
Extrinsic, process-related defects may affect reliability, but ...
Note: single bit due to P1-P1 soft short. ECC able to correct. Screening possible by dedicated pattern able to activate single bit between wafer level test and assy
• Intrinsic reliability of Flash memory:– Endurance limit 105 - 106 cycles– No major issues for retention (> 10 years)– Important role is played by relaxation phenomena
• Over-erasing problem solved by design:– Over-erase verify and reprogramming
• Major issue is single-bit charge loss after cycling:– Tunnel oxide thickness > 9 nm for NOR– ECC for NAND, because of thinner tunnel oxide– Process solutions to decrease the oxide defect density– Design solutions to reduce the electric field in storage
References (1)General and intrinsic reliability•P. Cappelletti and A. Modelli, “Flash Memory Reliability,” in Flash Memories edited by P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Kluwer 1999, pp 399-441.•R. Shiner, J. Caywood, and B. Euzent, “Data retention in EPROMs,” IRPS 1980, p. 238.•N. Mielke, “New EPROM data-loss mechanisms,” IRPS 1983, pp. 106-113.•S. Yamada et al, “Degradation mechanism of Flash EEPROM programming after program/erase cycles,”IEDM 1993, pp. 23-26.•R. Yamada, Y. Mori, Y. Okuyama, J. Yugami, T. Nishimoto, and H. Kume, “Analysis of detrap currentdue to oxide traps to improve flash memory retention,” IRPS 2000, pp. 200-204.•G. Ghidini , G.A. Sebastiani, and D. Brazzelli, “Stress induced leakage current and bulk oxide trapping: Temperature evolution,” IRPS 2002, pp. 415-416.•N. Mielke, H. Belgal, I. Kalastirsky, P. Kalavade, A. Kurtz, Q. Meng, N. Righos, and J. Wu, “FlashEEPROM Threshold Instabilities due to Charge Trapping During Program/Erase Cycling,” IEEE Trans. Dev. and Mat. Reliability Vol 4 No 3, Sep 2004 pp. 335-344.•P. Cappelletti, R. Bez, A. Modelli, and A. Visconti, “What we have learned on Flash Memory Reliability in the Last Ten Years,” IEDM 2004, pp. 489-492.
References (2)Fast erase, erratic bits•J.M.Z. Tseng, “Observation of Fast Erase Due to Enhanced Generation of Holes Caused by Electron Impact Ionization,” IEEE-EDL vol. 23, Aug 2002, pp 491-493.•A. Chimenton and P. Olivo, “Flash Memory Reliability: an improvement against the Erratic Erasephenomena using the Constant Charge Erasing Scheme,” SSDM 2002, pp 156-157.•A. Chimenton and P. Olivo, “Erratic erase in flash memories—Part II: Dependence on operating conditions,” IEEE Trans. Electron Devices, vol. 91, Apr. 2003, pp. 1015-1021.
Experimental characterization and modelling of the anomalous leakage after cycling:•S. Yamada et al. “Non-uniform Current Flow through Thin Oxide after Fowler-Nordheim CurrentStress,” IRPS 1996, pp.108-112.•F. Arai et al. “Extended data retention process technology for highly reliable flash EEPROMs of 106 to107 W/E cycles,” IRPS 1998, pp. 378-382.•Y. Manabe et al. ”Detailed observation of small leak currents in flash memories with thin tunnel oxide,”ICMTS 1998, pp. 95-99.•H. Kameyama et al., “A new data retention mechanism after endurance stress on Flash memory,” IRPS2000, pp. 194-199.•F. Schuler et al. “Long time estimate of failures rates due to low temperature charge loss,” NVSMW2000, pp. 102-105.
References (3)•G. Tempel et al. “Abnormal charge loss of Flash cells at medium temperatures,” NVSMW 2000, p. 105.•G. Tao et al. “Data retention prediction for modern floating gate non-volatile memories,”Microelectronics Reliability, vol. 40, 2000, pp. 1561-1566.•A. Modelli, et al. “A new conduction mechanism for the anomalous cells in thin oxides Flash EEPROMs”, IRPS 2001, pp. 61-66.•P.J. Kuhn et al. “A reliability methodology for low temperature data retention in floating gate non-volatile memories,” IRPS 2001, pp. 266-270.•G. Tempel et al. “Observation of a general Log2 dependency of the faiulure rate of anomalous low temperature leaky bits,” in NVSMW 2001, pp. 117-119.•H. Belgal, N. Righos, I. Kalastirsky, J. Peterson, R.Shiner, N. Mielke, “A New Reliability Model for Post-Cycling Charge Retention of Flash Memories,” IRPS 2002, pp. 7-20.•F. Schuler, R. Degraeve, P. Hendrickikx, D. Wellekins, "Physical description of anomalous charge loss in floating gate based NVM's and identification of its dominant parameter," IRPS 2002, pp 26-33.•M. Suhail, T. Harp, J. Bridwell, P.J. Kuhn, "Effects of Fowler Nordheim Tunneling Stress vs. Channel Hot Electron Stress on Data Retention Characteristics of Floating Gate Non-Volatile Memories," IRPS2002, pp. 439-440.•A. Hoefler, J.M. Higman, T. Harp, and P.J. Kuhn, "Statistical Modeling of the Program/Erase Cycling Acceleration of Low Temperature Data Retention in Floating Gate Nonvolatile Memories," IRPS 2002,pp 21-25.
•G. Tao, A. Scarpa, H. Valk, L. van Marwijk, K. van Dijk, F. Kuper, "Fast wafer level monitoring of stress induced leakage current in deep sub-micron embedded nonvolatile memory processes," Proc.Integrated Reliability Workshop, pPRR-3.1.•T. Wang, Nian-Kai Zous, Chih-Chieh Yeh, "Role of Positive Trapped Charge in Stress-InducedLeakage Current for Flash EEPROM Devices," IEEE Trans. El. Dev., Vol. 49, No. 11, Nov 2002, pp. 1910-1916.•D. Ielmini, A.S. Spinelli, A.L. Lacaita and A. Modelli, "A Statistical Model for SILC in Flash Memories," IEEE Trans. El. Dev., Vol 49, No 11, Nov 2002, pp 1955-1961.•A. Chimenton, A.S. Spinelli, D. Ielmini, A.L. Lacaita, A. Visconti, P. Olivo, "Drain accelerated degradation of tunnel oxides in Flash memories," IEDM 2002, pp. 167-170.
Radiation Damage•C. Claeys, H. Ohyama, E. Simoen, M. Nakabayashi, K. Kobayashi, "Radiation damage in flash memory cells," Nuclear Instr. And Methods in Physics Research B 186 (2002), pp. 392-400.•G. Cellere, A. Paccagnella, L. Larcher, A. Chimenton, J. Wyss, A. Candelori, A. Modelli, "Anomalous Charge Loss From Floating-Gate Memory Cells Due to Heavy Ions Irradiation", IEEE Trans. on Nuclear Science, December 2002, pp. 3051-3058.•G. Cellere, A. Paccagnella, A. Visconti, M. Bonanomi, P. Caprara, S. Lora, “A model for TID effects on Floating Gate memory cells” IEEE Trans. on Nuclear Science, December 2004, pp. 3753-3758