1 of 14 06.06.2014 Marius Wensing, M. Sc. Firmware development and testing of the ATLAS IBL BOC card TIPP2014, Amsterdam Firmware development and testing of the ATLAS IBL Back-Of-Crate card Marius Wensing on behalf of the ATLAS IBL DAQ group TIPP2014, Amsterdam, 2nd-6th of June 2014
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Firmware development and testing of the ATLAS IBL Back-Of-Crate card
Marius Wensing on behalf of the ATLAS IBL DAQ group TIPP2014, Amsterdam, 2nd-6th of June 2014. Firmware development and testing of the ATLAS IBL Back-Of-Crate card. ATLAS Pixel Detector. ATLAS is one of the four big experiments at the LHC at CERN. - PowerPoint PPT Presentation
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1 of 1406.06.2014
Marius Wensing, M. Sc.Firmware development and testing of the ATLAS IBL BOC cardTIPP2014, Amsterdam
Firmware development and testing of the ATLAS IBL Back-Of-Crate card
Marius Wensing on behalf of the ATLAS IBL DAQ group
TIPP2014, Amsterdam, 2nd-6th of June 2014
2 of 1406.06.2014
Marius Wensing, M. Sc.Firmware development and testing of the ATLAS IBL BOC cardTIPP2014, Amsterdam
ATLAS Pixel Detector
ATLAS is one of the four big experiments at the LHC at CERN.
Pixel Detector is the innermost detector with 80 mio. pixels in 3 barrel-layers and 3 disks per side.
Currently it is being updated with a new innermost layer (Insertable B-Layer) with additional 12 mio. pixels.
Pictures: CERN
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Marius Wensing, M. Sc.Firmware development and testing of the ATLAS IBL BOC cardTIPP2014, Amsterdam
Insertable B-Layer
Bandwidth permodule increasesby a factor of 2
IBL stave:
–12 planar double-chip modules
–8 3D single-chip modules
→ 32 front-end chips per stave New readout hardware
to cope with higher bandwidth
Pixel B-Layer IBL
Pixel size [µm x µm] 50 x 400 50 x 250
Number of pixels per module
46080 53760
Distance to interaction point in z [mm]
50.5 33
Readout bandwidth per module [Mbit/s]
160 320
→ Details in Cécile Lapoire’s IBL overview talk
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Marius Wensing, M. Sc.Firmware development and testing of the ATLAS IBL BOC cardTIPP2014, Amsterdam
IBL readout system
IBL readout isbased on thecurrent Pixeldetector readout.
Parts of the Off-Detector-system:–ROD: Read-Out-Driver (→ details in next talk by Shaw-Pin Chen)
–BOC: Back-Of-Crate card
–TIM: Timing, Trigger, Control Interface Module
–SBC: VME Single-Board-Computer
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Marius Wensing, M. Sc.Firmware development and testing of the ATLAS IBL BOC cardTIPP2014, Amsterdam
ATLAS IBL BOC card
BOC card is responsible for signal processing of data to and from the detector as well as monitoring the signalquality and providing the link to thehigher level readout.
Components:
–1 BOC Control FPGA (BCF, Spartan-6)
–2 BOC Main FPGAs (BMF, Spartan-6)
for signal processing
–Gigabit Ethernet, VME
–Optics: SNAP12, QSFP Optical interfaces:
–Downlink: 16 channels (BPM, 40 Mbit/s)
–Uplink: 32 channels (8b10b, 160 Mbit/s)
–Higher level readout: 8x 2 Gbit/s SLINK
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Marius Wensing, M. Sc.Firmware development and testing of the ATLAS IBL BOC cardTIPP2014, Amsterdam
Signal processing
Downlink (to the detector):
Uplink (from the detector):
Requirements:• Sending clock phase is unknown• 160 Mbit/s data stream• 8b10b encoded data
Requirements:• BPM encoding of clock and data
into single data stream• Adjustment of the detector timing in
steps of ~100 ps
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Marius Wensing, M. Sc.Firmware development and testing of the ATLAS IBL BOC cardTIPP2014, Amsterdam
Implementation of the Fine Delay block
Adjustment of the detector timing is needed to compensate the effect of fibre lengths and distances to the interaction point.
Requirements:
–Delay in steps of around 100 ps
–Duty cycle should not exceed (50±2)%
to ensure proper optoboard operation. Different approaches were
taken into account:
–External delay chips
–Propagation delays in-
side the FPGA
– IODELAY2 primitive
Picture: Xilinx
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Marius Wensing, M. Sc.Firmware development and testing of the ATLAS IBL BOC cardTIPP2014, Amsterdam
Implementation of Fine Delay with IODELAY2
Spartan-6 has different configuration options for the IODELAY primitive: