Young Won Lim 6/9/18 Finite State Machine (1A)
Young Won Lim6/9/18
Finite State Machine (1A)
Young Won Lim6/9/18
Copyright (c) 2013 - 2018 Young W. Lim.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".
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FSM Overview (1A) 3 Young Won Lim6/9/18
FSM and Digital Logic Circuits
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
Latch D FlipFlop Registers Timing Mealy machine Moore machine Traffic Lights Examples
FSM Overview (1A) 4 Young Won Lim6/9/18
NOR-based SR Latch – SET / RESET
https://en.wikipedia.org/wiki/Flip-flop_(electronics)
S=0
R=1
RESET Q=0
Q=1
S=1
R=0
SET Q=1
Q=0
1
0
0
1 1
0
0
1
FSM Overview (1A) 5 Young Won Lim6/9/18
NOR-based SR Latch – HOLD
S=0
R=0
HOLD Q=old Q
Q=old Q
https://en.wikipedia.org/wiki/Flip-flop_(electronics)
S=0
R=0
HOLD Q=old Q
Q=old Q
0
0
0
1 0
0
0
1→0
→1 →0
→1
FSM Overview (1A) 6 Young Won Lim6/9/18
NOR-based SR Latch
R
S
Q
SETbegins
RSTbegins
SETbegins
RSTbegins
S=1R=0
S=0R=1
S=1R=0
S=0R=1
S=0R=0
S=0R=0
S=0R=0
S=0R=0
Holdbegins
Holdbegins
Holdbegins
Holdbegins
S=1
R=0
SET Q=1
Q=0
S=0
R=1
RESET Q=0
Q=1
S=0
R=0
HOLD Q=old Q
Q=old Q
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
FSM Overview (1A) 7 Young Won Lim6/9/18
NOR-based SR Latch States
S=1
R=0
SET
Q=1
Q=0
S=0
R=1
RESETQ=0
Q=1
S=0
R=0
HOLD Q=old Q
Q=old Q
S=1
R=0
S=0
R=1
S=0
R=0
S=0
R=1
S=0
R=0
S=1
R=0
Q=1
Q=0
Q=0
Q=1
S
R Q
Q
SETRESETHOLD NOR based SR Latch
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
FSM Overview (1A) 8 Young Won Lim6/9/18
0 1
SR Latch States
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
SET SETHOLD, HOLD,
RESET
RESET S=1
R=0
SET
S=0
R=1
RESET
S=0
R=0
HOLD Q=old Q
Q=old Q
Q=1
Q=0
Q=0
Q=1
FSM Overview (1A) 9 Young Won Lim6/9/18
NOR-based D Latch – SET / RESET
https://en.wikipedia.org/wiki/Flip-flop_(electronics)
C
C
1
1
1
1
0
0
1
1
0
S=1
R=0
SET Q=1
Q=0
S=0
R=1
RESET Q=0
Q=1
1
0
0
1
S
R
S
R
D=1
C=1
D=0
C=1
0
FSM Overview (1A) 10 Young Won Lim6/9/18
NOR-based D Latch – HOLD
C
https://en.wikipedia.org/wiki/Flip-flop_(electronics)
C
0
0
0
0
0
0
0
1
S
R
S
RS=0
R=0
HOLD Q=old Q
Q=old Q
S=0
R=0
HOLD Q=old Q
Q=old Q
D=X
C=0
D=X
C=0
FSM Overview (1A) 11 Young Won Lim6/9/18
NOR-based D Latch – Set / Reset / Hold
C
D
Q
transparent opaque transparent opaque
SETbegins
RSTbegins
SETbegins
RSTbegins
Holdbegins
Holdbegins
C
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
FSM Overview (1A) 12 Young Won Lim6/9/18
NOR-based D Latch – transparent / opaque
C
D
Q
transparent opaque transparent
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
D→Qinput→output input→output
D→Q
C QQ
D QQ
transparent
C QQ
D QQ
opaque
1
0
C=1 C=0 C=1
FSM Overview (1A) 13 Young Won Lim6/9/18
NOR-based D Latch States
Q=1
Q=0
Q=0
Q=1
C=1
D=1
C=1
D=0
C=0
D=X
C=1
D=0
C=0
D=X
C=1
D=1
C
D
C Q
Q
SETRESETHOLD NOR based D Latch
Q
Q
SETRESETHOLD
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
FSM Overview (1A) 14 Young Won Lim6/9/18
D Latch States
0 1
C
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
C=1
D=1
Trans 1
C=1
D=0
Trans0
C=0
D=X
Opaque Q=old Q
Q=old Q
Q=1
Q=0
Q=0
Q=1
Opaque, Opaque,
Transparent 0 Transparent 1
Transparent 0
Transparent 1
FSM Overview (1A) 15 Young Won Lim6/9/18
Master-Slave FlipFlops
C
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
C
Y
YD
C
Q
Q
FSM Overview (1A) 16 Young Won Lim6/9/18
Master-Slave D FlipFlop
D
Y
Y
Q
D
Q
Master D Latch
Slave D Latch
Master-Slave D F/F
Y
the hold output of the master is transparently reaches the output of the slave
this value is held for another half period
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
FSM Overview (1A) 17 Young Won Lim6/9/18
Master Slave D FlipFlop – transparent / opaque
C
D
Q
transparent
opaque
transparent
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
D→Qinput→output input→output
D→Q
D QQ
transparent
D QQ
opaque
else
fallingedge
fallingedge
opaque opaque
FSM Overview (1A) 18 Young Won Lim6/9/18
Master-Slave D FlipFlop – Falling Edge
Master D Latch
Slave D Latch
D
C Q
Q D
C Q
Q
D
Q
Q
D
CK
Q
Q
D
CK
Q
D
CK
Q
Y
Y
CK
CK
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
FSM Overview (1A) 19 Young Won Lim6/9/18
D Latch & D FlipFlop
Level Sensitive D Latch
Edge Sensitive D FlipFlop
D
Q
Q
CK
D
CK
Q
D
Q
Q
C
D
Q
CK=1 transparentCK=0 opaque
CK=1→0 transparentelse opaque
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
FSM Overview (1A) 20 Young Won Lim6/9/18
D FlipFlop with Enable (1)
D
Q
QD
EN
Q
QCK
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
EN=1 Regular D Flip FlopSampling D input @ posedge of CK
EN=0 Holding D Flip FlopSampling Q output @ posedge of CK
D
Q
Q Q
Q
1
D
EN
CK0
0
1
0
1
FSM Overview (1A) 21 Young Won Lim6/9/18
D FlipFlop with Enable (2)
D
Q
Q
EN
D
EN
Q
CK
D
EN
Q
CK
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
D
Q
Q Q
Q
D
EN
CK
0
1
FSM Overview (1A) 22 Young Won Lim6/9/18
Registers
https://en.wikiversity.org/wiki/The_necessities_in_Computer_Design
D Q
D Q
D Q
D Q
D3
D2
D1
D0
Q3
Q2
Q1
Q0
Q3
Q2
Q1
Q0
D3
D2
D1
D0
CLK
Register
Inpu
ts to
FF
s
Out
puts
of F
Fs
FSM Overview (1A) 23 Young Won Lim6/9/18
FF Timing (Ideal)
D3:0
Q3:0
Inputs to FFs
Outputs of FFs
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
Q3
Q2
Q1
Q0
D3
D2
D1
D0
Register
FSM Overview (1A) 24 Young Won Lim6/9/18
States
Q(t+1) Q(t+2) Q(t+3) Q(t+4) Q(t+5)Q(t)
D3:0
Q3:0
(t+1)th edge
(t+2)th edge
(t+3)th edge
(t+4)th edge
(t+5)th edge
(t)th edge
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
Q3
Q2
Q1
Q0
D3
D2
D1
D0
Register
Inputs Outputs
State
FSM Overview (1A) 25 Young Won Lim6/9/18
Sequence of States
? ? ? ? ? ?
Q(t+1) Q(t+2) Q(t+3) Q(t+4) Q(t+5)Q(t)
D3:0
Q3:0
Find inputs to FFs
which will make outputs in this sequence
(t+1)th edge
(t+2)th edge
(t+3)th edge
(t+4)th edge
(t+5)th edge
(t)th edge
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
Q3
Q2
Q1
Q0
D3
D2
D1
D0
Register
Inputs Outputs
State
FSM Overview (1A) 26 Young Won Lim6/9/18
How to change current state
NextSt
CurrSt
Compute NextSt from CurrSt, Ta, Tb
This NextSt becomes a new CurrSt
Compute NextSt
CurrSt <= NextSt
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
Q3
Q2
Q1
Q0
D3
D2
D1
D0
Register
Current State
Next State
comb
CurrentState
NextState
input
gatedelay
FSM Overview (1A) 27 Young Won Lim6/9/18
Finding FF Inputs
D Q
D Q
D Q
D Q
CombNextStateLogic
D3
D2
D1
D0
Q3
Q2
Q1
Q0
FSMinputs
During the tth clock edge period,
Compute the next state Q(t+1) using the current state Q(t) and other external inputs
Place it to FF inputs
After the next clock edge, (t+1)th, the computed next state Q(t+1) becomes the current state
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
Current State
Next State
FSM Overview (1A) 28 Young Won Lim6/9/18
Method of Finding FF Inputs
Q(t+1) Q(t+2) Q(t+3) Q(t+4) Q(t+5) Q(t+6)
Q(t+1) Q(t+2) Q(t+3) Q(t+4) Q(t+5)Q(t)
D3:0
Q3:0
FSM Inputs
Find the boolean functions D3, D2, D1, D0in terms of Q3, Q2, Q1, Q0, and external FSM inputsfor all possible cases.
Q(t)
Inputs +
Q(t+1)
CurrentState
NextState
input
Q(t) Q(t+1)
FSM Overview (1A) 29 Young Won Lim6/9/18
State Transition
Q(t+1)
Q(t+1)Q(t)
D3:0
Q3:0
FSMInputs
Q(t+1)
Q(t)
Inputs
Compute the next stateusing the current state and external inputsin the current clock cycle
After the next clock edge, the computed next state (FF Inputs) becomes the current state (FF Outputs)https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
Q3
Q2
Q1
Q0
D3
D2
D1
D0
Register
Current State
Next State
comb
FSM Overview (1A) 30 Young Won Lim6/9/18
Traffic Lights Example
https://en.wikiversity.org/wiki/The_necessities_in_Computer_Design
FSM Overview (1A) 31 Young Won Lim6/9/18
FSM Inputs and Outputs
LA
LA
LB
LB
TB
TB
TA
TA
Traffic Lights - Outputs
LA
LB
Sensor - Inputs
TB
TA
https://en.wikiversity.org/wiki/The_necessities_in_Computer_Design
FSM Overview (1A) 32 Young Won Lim6/9/18
Four States
LA
LA
LB
LB
LA
LA
LB
LB
LA
LA
LB
LB
LA
LA
LB
LB
TB
TA
=0
=0
TA =1
TB =1
https://en.wikiversity.org/wiki/The_necessities_in_Computer_Design
GR YR
RGRY
FSM Overview (1A) 33 Young Won Lim6/9/18
00GR
01YR
11RY
10RG
TA=1
TA=0
TB=1
TB=0
1
1
0
0
0
1
0 X 0
1 X X
0 1 X
0 0 X
1 X X
0 X 1
S0
TA
TB
S'1
1
0
0
0
1
1
S1
1
0
0
1
0
0
S'0
State Transition Diagrams and Tables
0
0
1
1
1 1 0
0 1 0
1 0 1
0 0 0
S2L
A1L
A0L
B1
1
1
0
0
S1
1
0
0
0
LB0
Y
G
R
R
R
R
Y
G
G:00Y:01R:10
FSM Overview (1A) 34 Young Won Lim6/9/18
Next State Functions S1’ and S2’
1
1
0
0
0
1
0 X 0
1 X X
0 1 X
0 0 X
1 X X
0 X 1
S0
TA
TB
S'1
1
0
0
0
1
1
S1
1
0
0
1
0
0
S'0
1
1
0
0
0
1
0 X 0
1 X X
0 1 X
0 0 X
1 X X
0 X 1
S0
TA
TB
S'1
1
0
0
0
1
1
S1
S1 S0
S1 S0T B
S1 S0T B
S'1 = S1 S0 + S1S0
= S1 + S0
0 X 0
1 X X
0 1 X
0 0 X
1 X X
0 X 1
S0
TA
TB
1
0
0
0
1
1
S1
1
0
0
1
0
0
S'0
S1 S0T A
S1 S0T B
S '0 = S1S0T A + S1 S0T B
https://en.wikiversity.org/wiki/The_necessities_in_Computer_Design
S '1 = S1 + S0
S '0 = S1S0T A + S1 S0T B
FSM Overview (1A) 35 Young Won Lim6/9/18
Output Functions : LA1, LA0, LB0, LB1
000110
0
0
1
1
1 1 0
0 1 0
1 0 1
0 0 0
S2L
A1L
A0L
B1
1
1
0
0
S1
1
0
0
0
LB0
1 1
0 1
1 0
0 0
S2L
A1
1
1
0
0
S1
LA1=S1
1 0
0 0
1 1
0 0
S2
LA0
1
1
0
0
S1
LA 0=S1 S0
0
0
1
1
1
0
1
0
S2
LB1
1
1
0
0
S1
1
0
1
0
S2
1
1
0
0
S1
1
0
0
0
LB0
LB1=S1 LB0=S1 S0
https://en.wikiversity.org/wiki/The_necessities_in_Computer_Design
LA1=S1
LA 0=S1 S0
LB1=S1
LB0=S1 S0
FSM Overview (1A) 36 Young Won Lim6/9/18
Moore FSM
D Q
D Q
S'1
S'0
S1
S0
TA
TB
LA1
LA0
LB1
LB0
S1
S0
clk
Current State
Next State
inputs
outputs
states00: S001: S110: S211: S3
outputs (LA/LB)00: Green01: Yellow10: Red11: X
NextSt
CurrSt
This NextSt becomes a new CurrSt
Compute NextSt
CurrSt <= NextSt
https://en.wikiversity.org/wiki/The_necessities_in_Computer_Design
Compute NextSt from CurrSt, Ta, Tb
gatedelay
FSM Overview (1A) 37 Young Won Lim6/9/18
Moore FSM Implementation
D Q
D Q
S'1
S'0
S1
S0
TA
TB
S '1 = S1 + S0
S '0 = S1S0T A + S1 S0T B
LA1
LA0
LB1
LB0
LA1=S1
LA0=S1S0
LB1=S1
LB0=S1S0
Next States
Outputs
S'0 = S1S0T A
+ S1S0TB
S '1 = S1 + S0
Inputs TA
TB
Current State S1
S0
S1
S0
Current State S1
S0
LA1=S1
LA 0=S1 S0
LB1=S1
LB0=S1 S0
clk
Current State
Next State
inputs
outputs
states00: S001: S110: S211: S3
outputs (LA/LB)00: Green01: Yellow10: Red11: X https://en.wikiversity.org/wiki/The_necessities_in_Computer_Design
FSM Overview (1A) 38 Young Won Lim6/9/18
Next State Functions S1’ and S2’
1
1
0
0
0
1
0 X 0
1 X X
0 1 X
0 0 X
1 X X
0 X 1
S0
TA
TB
S'1
1
0
0
0
1
1
S1
1
0
0
1
0
0
S'0
https://en.wikiversity.org/wiki/The_necessities_in_Computer_Design
S '1 = S1 + S0
S '0 = S1S0T A + S1 S0T B
Current State
Next State
FSMInputs
{00,01,10,11}
(T AT B )
× {00,01,10,11}→{00,01,10,11}
(S1 S0) (S1 S0)
FSM Overview (1A) 39 Young Won Lim6/9/18
Cartesian Product
1
1
0
0
0
1
0 X 0
1 X X
0 1 X
0 0 X
1 X X
0 X 1
S0
TA
TB
S'1
1
0
0
0
1
1
S1
1
0
0
1
0
0
S'0
0
0
0
0
1
1
0 1 1
0 1 0
0 0 1
0 0 0
1 0 1
1 0 0
S0
TA
TB
S'1
0
0
0
0
0
0
S1
0
0
1
1
0
0
S'0
1
1
1
1
1
1
0 0 1
0 0 0
1 1 1
1 1 0
0 1 1
0 1 0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
1 0 1
1 0 0
1
1
0
0
0
0
1 1 1
1 1 0
1
1
0
0
Current State
Next State
FSMInputs
{00,01,10,11}
(T AT B )
× {00,01,10,11}→{00,01,10,11}
(S1 S0) (S1 S0)
FSM Overview (1A) 40 Young Won Lim6/9/18
Output Functions : LA1, LA0, LB1, LB0
G : 00Y : 01R : 10
0
0
1
1
1 1 0
0 1 0
1 0 1
0 0 0
S2L
A1L
A0L
B1
1
1
0
0
S1
1
0
0
0
LB0
https://en.wikiversity.org/wiki/The_necessities_in_Computer_Design
LA1=S1
LA 0=S1 S0
LB1=S1
LB0=S1 S0
Current State
FSMOutput
{00,01,10,11} {0010,0110, 1000,1001}→
(LA 1, LA 0, LB1, LB 0)(S1 S0)
FSM Overview (1A) 41 Young Won Lim6/9/18
Moore FSM
1
clock
StateRegister
Next StateCombinational
Logic
Output Combinational
LogicD Q D Q D Q
D Q D Q D Q
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
Current State
Next State
FSMOutputs
FSMInputs
FSM Overview (1A) 42 Young Won Lim6/9/18
Mealy FSM
1
clock
StateRegister
Next StateCombinational
Logic
Output Combinational
LogicD Q D Q D Q
D Q D Q D Q
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
Current State
Next State
FSMOutputs
FSMInputs
FSM Overview (1A) 43 Young Won Lim6/9/18
State Diagram
https://en.wikipedia.org/wiki/Finite-state_machine
ST2 ST0 ST1
E: Entry Action
X: Exit Action
I: Input Action
state
output
active output
active output
active output mealy
moore
moore
time
FSM Overview (1A) 44 Young Won Lim6/9/18
Acceptors
https://en.wikipedia.org/wiki/Finite-state_machine
Acceptor FSM: parsing the string "nice"
FSM Overview (1A) 45 Young Won Lim6/9/18
Recognizers
https://en.wikipedia.org/wiki/Finite-state_machine
Representation of a finite-state machine;
determines whether a binary number has
an even number of 0s,
where S1 is an accepting state.
FSM Overview (1A) 46 Young Won Lim6/9/18
Classifiers
https://en.wikipedia.org/wiki/Finite-state_machine
A classifier is a generalization of a finite state machine that, similar to an acceptor, produces a single output on termination but has more than two terminal states
FSM Overview (1A) 47 Young Won Lim6/9/18
Transducers
https://en.wikipedia.org/wiki/Finite-state_machine
Transducers generate output based on a given input and/or a state using actions. They are used for control applications and in the field of computational linguistics.
FSM Overview (1A) 48 Young Won Lim6/9/18
Acceptors, Recognizers, Transducers
https://cs.stanford.edu/people/eroberts/courses/soco/projects/2004-05/automata-theory/basics.html
acceptors: either accept the input or not
recognizers: either recognize the input
transducers: generate output from given input
FSM Overview (1A) 49 Young Won Lim6/9/18
General Transducers
https://en.wikipedia.org/wiki/Transducer
Transducers are used in electronic communications systems to convert signals of various physical forms to electronic signals, and vice versa. In this example, the first transducer could be a microphone, and the second transducer could be a speaker.
FSM Overview (1A) 50 Young Won Lim6/9/18
Transducers : Moore and Mealy Machines
https://en.wikipedia.org/wiki/Finite-state_machine
Fig. 6 Transducer FSM: Moore model example
Fig. 7 Transducer FSM: Mealy model example
There are two input actions (I:):
"start motor to close the door if command_close arrives"
"start motor in the other direction to open the door if command_open arrives".
FSM Overview (1A) 51 Young Won Lim6/9/18
Moore machine example
https://en.wikipedia.org/wiki/Moore_machine
output does not depend on inputs
FSM Overview (1A) 52 Young Won Lim6/9/18
Mealy machine
https://en.wikipedia.org/wiki/Mealy_machine
input / output
output does depend on inputs
FSM Overview (1A) 53 Young Won Lim6/9/18
Mathematical Model – transducers (1)
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
A finite-state transducer is a sextuple (Σ, Γ, S, s0, δ, ω), where:
● Σ is the input alphabet (a finite non-empty set of symbols).● Γ is the output alphabet (a finite, non-empty set of symbols).● S is a finite, non-empty set of states.● s
0 is the initial state, an element of S.
● δ is the state-transition function: δ : S × Σ → S● ω is the output function.
Moore machine : ω : S → ΓMealy machine : ω : S × Σ → Γ
(Σ, Γ, S, s0, δ, ω)
(I, O, S, f, g, σ)
FSM Overview (1A) 54 Young Won Lim6/9/18
Mathematical Model – transducers (2)
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
If the output function is a function of a state and input alphabet (ω : S × Σ → Γ) that definition corresponds to the Mealy model, and can be modelled as a Mealy machine.
If the output function depends only on a state (ω : S → Γ) that definition corresponds to the Moore model, and can be modelled as a Moore machine.
A finite-state machine with no output function at all is known as a semiautomaton or transition system.
FSM Overview (1A) 55 Young Won Lim6/9/18
Mathematical Models – acceptors
https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design
A deterministic finite state machine or acceptor deterministic finite state machine is a quintuple (Σ, S, s
0, δ, F), where:
● Σ is the input alphabet (a finite, non-empty set of symbols).● S is a finite, non-empty set of states.● s
0 is an initial state, an element of S.
● δ is the state-transition function: δ : S × Σ → S ● F is the set of final states, a (possibly empty) subset of S. output function ω
A set of accepted states
output set {0, 1}
FSM Overview (1A) 56 Young Won Lim6/9/18
Finite State Tranducers and Acceptors
finite-state transducer (Σ, Γ, S, s0, δ, ω)
finite state acceptor (Σ, S, s0, δ, F)
limited finite state machine (Σ, S, δ)
Finite State Automaton (FSA)
Finite State Machine (FSM)
Σ is the input alphabet (a finite non-empty set of symbols).S is a finite, non-empty set of states.δ is the state-transition function: δ : S × Σ → Ss
0 is the initial state, an element of S.
F is the set of final states, a (possibly empty) subset of S.Γ is the output alphabet (a finite, non-empty set of symbols).ω is the output function.
Young Won Lim6/9/18
References
[1] http://en.wikipedia.org/[2]