Final presentation – part B Dor Obstbaum and Kami Elbaz Advisor: Moshe Porian November 2012 FPGA SETTING USING FLASH Bi – semester project
Final presentation – part B
Feb 23, 2016
FPGA Setting Using Flash. Final presentation – part B. Bi – semester project. Dor Obstbaum and Kami Elbaz. Advisor: Moshe Porian . November 2012. FPGA Setting Using Flash. Project movie. Content. Introduction. Introduction Display FLASH Performance Configuration Testability - PowerPoint PPT Presentation
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Final presentation – part B
Dor Obstbaum and Kami Elbaz
Advisor: Moshe Porian
November 2012
FPGA SETTING USING FLASH
Bi – semester project
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Content• Introduction• Display• FLASH
• Performance
• Configuration
• Testability
• GUI• Conclusions
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Motivation• Hardware operates by configuration written
in the registers
registers
Hardware System
FPGA setting using FLASH system
Software HostFLASH memory
• Software writes up to date configuration in the FLASH memory
• FPGA setting using FLASH system does the connection
Software
Independent!
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
TOP Architecture
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
What have we achieved in part B of the project?
•CFI interface with FLASH memory•Automatic configuration of clients using data base stored in FLASH•Wishbone Bus upgrade for enhancing system performance•Watchdog and Power features added•GUI with abundant capabilities
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Display client
Technical Demands:•VESA protocol •Operates on a 65 MHz clock•Produces 3 kinds of pictures: lines, columns, damka squares• control frame ROI and shape width and color•Supports any kind of Resolution and timing by Generics•Inputs: Wishbone interface to configure registers•Outputs: RGB, hsync, vsync, blank
1024
768
Our Configuration
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Display client
65 MHz100 MHz
Integrated from
RunLen project
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Display client
Integrated from
RunLen project
Enable Lines
Line ROILine width
RGB start val
Enable Lines
Line ROI
RGB start val
RGB
Line color diff
Line color diff
Line width
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Display client
We Want Our Frames like These:
And NOT like these:
How do we keep Synchronization when registersAre updated?
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Synthetic Data Provider
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Waveform
Wishbone transactions configures registers
Register Valid is ‘0’ while registers are updated
VESA generator requests data for a new frame
Valid Data is supplied after 1 cycle
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI
Conclusions
FLASH Memory
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
FLASH Client
Technical Demands:•Common FLASH Interface protocol (CFI)•Wishbone Interface•Performs Read, Write, Reset and Erase transactions•Initiative read on power-on•Contains a timeout algorithm•Generic: adaptable to different FLASH sizes and clock frequencies.
BUS
Wishbone
CFI
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
FLASH Client block diagramInitiative read for configuration
Read address 0x000000
System power on
FLASH
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Write transaction
FLASH
Write command
BUS transaction ends. Client enters stall
mode while writing data to FLASH.
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Performance – Wishbone upgrade
Wishbone Master
Wishbone Slave
Standard bus
RegistersControl unit
RAM
Address advancer
FSMFSM FSM
Pipeline bus
Registers
RAM
Wishbone Bus – Old version
Wishbone Bus – New version
Wishbone Slave
•Simple interface•Enhanced performance•Less logic elements•Contains Watchdog
Wishbone Master
FSMstart
done
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Performance enhancement
•Throughput: 1/12 [bytes/cycle]
•Throughput: 1 [bytes/cycle]
Old version
New version
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Simple Interface – RX path exampleOld version
New version
MDWM mediates between mp-decoder, wishbone master and RAM
No need for MDWM
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Configuration
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Config Control Block•Reads data from FLASH into internal RAM•Configures clients using Wishbone bus transactions•Option for re-configuration•Option for unit disable
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Testability – Test plan• All FLASH transactions• Correct configuration of clients• Generic system• System boundaries• Hardware tests
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Test environment
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
GUI - CapabilitiesOperational features:•Read, Write and erase transactions to FLASH•Data abstraction – very little knowledge needed for operation•Data base creation – for storing in FLASH•Direct transaction to clients•Easy work with text files•Generates only correct packets with legal valuesDebug features:•TX and RX messages display•Option for changing or removing CRC/EOF/SOF•Generates text files available for simulation
GUI user guide
included
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
GUI appearance
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
Synthesis results
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
max frequency
Improvement of 4.6% from part A of the project
•Required frequency: 100 MHz•Part A max frequency: 128.34 MHz•Part B max frequency: 134.25 MHz
Possible ApplicationAny hardware client can be connected to the system if it possesses a Wishbone Slave connection. Such a client could be a Pulse Width Modulator (PWM) . A PWM can define a unique frequency for many servo controllers.In order to prevent the case that on system power on there would be some default insufficient value on the frequency input of servo devices, the PWM will function as a client of the FPGA setting using FLASH system.Data would be loaded from the Flash memory for correct configuration.
Introduction
Display
FLASH
Performance
Configuration
Testability
GUI and p&r
Conclusions
What have we learned?• Planning and Specifying a Project• Writing reusable generic code• Protocols: UART, Wishbone, VESA, CFI• Read and understand Verilog code• Integration of many components• Verify logic correctness using waveforms, text files, BMP
files and scripts• Testing our hardware using GUI and debug with signaltap• Documentation of the work done• SVN, Code Review and running a project diary are useful
tools• Expect code to be used by others in the future
DEMO
Related Documents
