8/8/2019 Final CA Project
1/37
8/8/2019 Final CA Project
2/37
ACKNOWLEDGEMENT:
The satisfaction that accompanies that the successful completion ofany task would be incomplete without the mention of people whoseceaseless cooperation made it possible, whose constant guidanceand encouragement crown all efforts with success. We are grateful toour lecturer Sir Aqeel for the guidance, inspiration and constructivesuggestions that helpful us in the preparation of this project. We arealso thanking our colleagues who have helped in successful
completion of the project.
8/8/2019 Final CA Project
3/37
CERTIFICATEThis is to certify that this report of Intel 3002(Bit Slice)
Processor embodies the original work done by WALEEDABRAR, Hafiz Nabeel Ijaz and M.ASAD KAYANIduring this project submission as a partial fulfillment of the
requirement for the Semester project for BCSE-4 Bachelors
of Computer in Software Engineering.
FOUNDATION UNIVERSITY ISLAMABAD
8/8/2019 Final CA Project
4/37
Bit Slice Processors
TABLE OF CONTENT:
Abstract:.................................................................................................................................................... 4
GOALS:........................................................................................................................................................ 4
INTRODUCTION:.......................................................................................................................................... 4
What is Processor.....................................................................................................................................5
World First Processor............................................................................................................................6HISTORY:.....................................................................................................................................................7
Basic
Concept. 10
Main Components11
Arithmetic and Logic Unit(ALU):.................................................................................................... 12Barrel Shifter..12
Floating Point Unit:.............................................................................................................................. 13
Back-Side Bus:....................................................................................................................................... 13Multiplexer:............................................................................................................................................. 13
Processor Register:.............................................................................................................................. 14
Memory Management Unit:............................................................................................................... 15
Translation Look aside Buffer................................................................................................................ 16
CPU Cache..............................................................................................................................................16
Register File................................................................................................................ 18Micro code............................................................................................................................................. 18
Control Unit........................................................................................................................................... 19
Clock Rate:...........................................................................................................................................19
Cpu Design:............................................................................................................................................. 20
CPU Goals:............................................................................................................................................... 21
Embedded Design:............................................................................................................................... 22
Embedded Process Economics :........................................................................................................ 22
Bit Slicing:............................................................................................................................................. 23
Processor Family:................................................................................................................................... 24
Intel 3002:............................................................................................................................................... 25
3002 Information:................................................................................................................................ 26Data Sheet of 3002:.............................................................................................................................. 28
Pin Description:.................................................................................................................................... 29
Logical Description:................................................................................................................................ 30
Block Diagram of 3002:........................................................................................................................... 30
Characteristics:...................................................................................................................................... 31
8/8/2019 Final CA Project
5/37
Waveforms:............................................................................................................................................. 35
References:........................................................................................................................................... 36
3
8/8/2019 Final CA Project
6/37
Abstract:
In this project we have explained the Architecture of Processor, how processor
gets started and what are the key features and benefits of processors in field of
computers. This project explains the processor right from the scratch and describes
each and every component.
GOALS: The main objective of the CPU is to perform mathematical calculations on binary
numbers; still there are other goals of using CPU as well. It can provide high throughput
for multiple programs. It is aimed to consume less power with better performance. It
provides viable connectivity to develop more advance and parallel systems. The cost is
less and the performance is more. It can be redesigned and converted to small size, in
order to increase the performance of the system, lower the cost and increase the speed
of the system. It can provide very good compatibility with very large scale integrated
circuits. Which helps in compressing the transistors on one chip and hence the speed ofsystem is enhanced. This is because tiny transistors switch in a fast and swift manner.
The early designs of CPU were based on clock rate however today micro electrical
designs are more popular.
INTRODUCTION:
The Central Processing Unit (CPU) or the processoris the portion of a
computer system that carries out the instructions of a computer program, and is the
primary element carrying out the computer's functions. This term has been in use in the
computer industry at least since the early 1960s. The form, design and implementation
of CPUs have changed dramatically since the earliest examples, but their fundamental
operation remains much the same.
Early CPUs were custom-designed as a part of a larger, sometimes one-of-a-kind, and
computer. However, this costly method ofdesigning custom CPUs for a particular
application has largely given way to the development of mass-produced processors that
are made for one or many purposes. This standardization trend generally began in the
era of discrete transistor mainframes and minicomputers and has rapidly accelerated
with the popularization of the integrated (IC). The IC has allowed increasingly complex
CPUs to be designed and manufactured to tolerances on the order ofnanometers. Both
the miniaturization and standardization of CPUs have increased the presence of these
digital devices in modern life far beyond the limited application of dedicated computing
machines. Modern microprocessors appear in everything from automobiles to cell
phones and children's toys.
6
http://en.wikipedia.org/wiki/Computer_programhttp://en.wikipedia.org/wiki/Designinghttp://en.wikipedia.org/wiki/Minicomputerhttp://en.wikipedia.org/wiki/Nanometerhttp://en.wikipedia.org/wiki/Automobilehttp://en.wikipedia.org/wiki/Cell_phonehttp://en.wikipedia.org/wiki/Cell_phonehttp://en.wikipedia.org/wiki/Computer_programhttp://en.wikipedia.org/wiki/Designinghttp://en.wikipedia.org/wiki/Minicomputerhttp://en.wikipedia.org/wiki/Nanometerhttp://en.wikipedia.org/wiki/Automobilehttp://en.wikipedia.org/wiki/Cell_phonehttp://en.wikipedia.org/wiki/Cell_phone8/8/2019 Final CA Project
7/37
What is Processor:-
In the simplest of terms, its your computers brain. The processor tells your
computer what to do and when to do it, it decides which tasks are more important and
prioritizes them to your computers needs.
There is and have been many processors on the market, running at many different
speeds. The speed is measured in Megahertz or MHz. A single MHz is a calculation of 1
million cycles per second (or computer instructions), so if you have a processor running
at 2000 MHz, then your computer is running at 2000,000,000 cycles per second, which
in more basic terms is the amount of instructions your computer can carry out. Another
important abbreviation is Gigahertz or GHz. A single GHz or 1 GHz is the same as 1000
MHz. Sounds a bit confusing, so here is a simple conversion:1000 MHz (Megahertz) = 1GHz (Gigahertz) = 1000,000,000 Cycles per second (or
computer instructions).
Now you can see why they abbreviate it, could you imagine going to a PC store and
asking for a one thousand million cycle PC please. A bit of a mouth full isnt it?
So when buying a new computer always looks for fastest you can afford. The fastest on
the market at the time of writing this article is 3.8 GHz (3800 MHz). Remember though
that it is not necessary to purchase such a fast processor, balance your needs, do you
really need top of the range? Especially when the difference says between a 3.5 GHz
(3500 MHz) and a 3.8 GHz (3800 MHz) processor will be barely noticed (if noticed at
all) by you, while the price difference is around 100. With the money you save you
could get a nice printer and scanner package.
Now that we have covered the speeds, there is one more important subject to cover.
Which processor? There are 3 competitors at present, the AMD Athlon, Intel Pentium
and the Intel Celeron. They come in many guises, but basically the more cores they
have and the higher the speed means better and faster.
Processors now come as dual core, triple core and quad core. These processors are
the equivalent of running two cpu's (Dual core), three CPU's (Triple core) or four (Quad
core).
In the past Intel Pentium the best and most expensive of them all, and remains today
one of the most popular on the market. In laymans terms it is/was the designer
7
8/8/2019 Final CA Project
8/37
processor, although AMD have some superb if not better releases and equally highly
priced and advanced products. It would be hard to say which is best as they are direct
competitors.
Lastly there is the Intel Celeron; this processor is a budget version of the Intel Pentium 4, the
processor you find in most budget computers. If the purse is tight, and you need a computer, then
this is your port of call. You will find many sub 400 computers fitted with this processor.
World First Processor:-The Intel 4004 was a 4-bitcentral processing unit (CPU) released
by Intel Corporation in 1971. It was the first complete CPU on one chip, and also
the first commercially available microprocessor. Such a feat of integration was
made possible by the use of then new silicon gate technology allowing a higher
number of transistors and a faster speed than was possible before. The 4004
employed a 10 m silicon-gate enhancement load pMOS technology and could
execute approximately 92,000 instructions per second (that is, a single
instruction cycle was 10.8 microseconds).
8
http://en.wikipedia.org/wiki/4-bithttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Intel_Corporationhttp://en.wikipedia.org/wiki/Micrometrehttp://en.wikipedia.org/wiki/PMOS_logichttp://en.wikipedia.org/wiki/Instructions_per_secondhttp://en.wikipedia.org/wiki/Microsecondhttp://en.wikipedia.org/wiki/4-bithttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Intel_Corporationhttp://en.wikipedia.org/wiki/Micrometrehttp://en.wikipedia.org/wiki/PMOS_logichttp://en.wikipedia.org/wiki/Instructions_per_secondhttp://en.wikipedia.org/wiki/Microsecond8/8/2019 Final CA Project
9/37
Micro architecture and pin out
Intel 4004 architectural block diagram.Intel 4004 DIP chip pinout.
History Of Processors [1]1971: 4004 Microprocessor
The 4004 was Intel's first microprocessor. This breakthroughinvention powered the Busicom calculator and paved the way for
embedding intelligence in inanimate objects as well as the personalcomputer.
1972: 8008 MicroprocessorThe 8008 was twice as powerful as the 4004. A 1974 article in Radio
Electronics referred to a device called the Mark-8 which used the8008. The Mark-8 is known as one of the first computers for the home
--one that by today's standards was difficult to build, maintain andoperate.
1974: 8080 MicroprocessorThe 8080 became the brains of the first personal computer--the Altair,
allegedly named for a destination of the Starship Enterprise fromthe Star Trektelevision show. Computer hobbyists could purchase akit for the Altair for $395. Within months, it sold tens of thousands,
creating the first PC back orders in history.
9
http://en.wikipedia.org/wiki/Pinouthttp://www.tayloredge.com/museum/processor/1974_8080.JPGhttp://www.tayloredge.com/museum/processor/1972_8008.JPGhttp://www.tayloredge.com/museum/processor/1971_4004.JPGhttp://en.wikipedia.org/wiki/File:4004_dil.svghttp://en.wikipedia.org/wiki/File:4004_dil.svghttp://en.wikipedia.org/wiki/File:4004_arch.svghttp://en.wikipedia.org/wiki/File:4004_arch.svghttp://en.wikipedia.org/wiki/Pinout8/8/2019 Final CA Project
10/37
1978: 8086-8088 MicroprocessorA pivotal sale to IBM's new personal computer division made the8088 the brains of IBM's new hit product--the IBM PC. The 8088's
success propelled Intel into the ranks of the Fortune 500,and Fortune magazine named the company one of the "Business
Triumphs of the Seventies."
1982: 286 MicroprocessorThe Intel 286, originally known as the 80286, was the first Intelprocessor that could run all the software written for its predecessor.
This software compatibility remains a hallmark of Intel's family ofmicroprocessors. Within 6 years of its release, an estimated 15million 286-based personal computers were installed around the
world.
1985: Intel386 MicroprocessorThe Intel386microprocessor featured 275,000 transistors--more
than 100times as many as the original 4004. It was a 32-bit chip andwas "multi tasking," meaning it could run multiple programs at the
same time.
1989: Intel486 DX CPU MicroprocessorThe Intel486processor generation really meant you go from acommand-level computer into point-and-click computing. "I could
have a color computer for the first time and do desktop publishing ata significant speed," recalls technology historian David K. Allison of
the Smithsonian's National Museum of American History. TheIntel486 processor was the first to offer a built-in math coprocessor,
which speeds up computing because it offloads complex mathfunctions from the central processor.
1993: Intel Pentiu m ProcessorThe Intel Pentium processor allowed computers to more easily
incorporate "real world" data such as speech, sound, handwriting andphotographic images. The Intel Pentium brand, mentioned in the
comics and on television talk shows, became a household word soonafter introduction.
1995: Intel Pentium Pro ProcessorReleased in the fall of 1995 the Intel Pentium Pro processor is
designed to fuel 32-bit server and workstation applications, enabling
fast computer-aided design, mechanical engineering and scientificcomputation. Each Intel Pentium Pro processor is packaged
together with a second speed-enhancing cache memory chip. Thepowerful Pentium Pro processor boasts 5.5 million transistors.
1997: Intel Pentium II ProcessorThe 7.5 million-transistor Intel Pentium II processor incorporates
Intel MMX technology, which is designed specifically to processvideo, audio and graphics data efficiently. It was introduced in
innovative Single Edge Contact (S.E.C) Cartridge that alsoincorporated a high-speed cache memory chip. With this chip, PC
users can capture, edit and share digital photos with friends andfamily via the Internet; edit and add text, music or between-scene
10
http://www.tayloredge.com/museum/processor/1997_PentiumII.JPGhttp://www.tayloredge.com/museum/processor/1995_PentiumPro.JPGhttp://www.tayloredge.com/museum/processor/1993_Pentium.JPGhttp://www.tayloredge.com/museum/processor/1989_80486.JPGhttp://www.tayloredge.com/museum/processor/1985_80386.JPGhttp://www.tayloredge.com/museum/processor/1982_80286.JPGhttp://www.tayloredge.com/museum/processor/1978_8088.JPG8/8/2019 Final CA Project
11/37
transitions to home movies; and, with a video phone, send video overstandard phone lines and the Internet.
1998: Intel Pentium II Xeon ProcessorThe Intel Pentium II Xeon processors are designed to meet the
performance requirements of mid-range and higher servers and
workstations. Consistent with Intel's strategy to deliver unique
processor products targeted for specific markets segments, the IntelPentium II Xeon processors feature technical innovations specifically
designed for workstations and servers that utilize demanding
business applications such as Internet services, corporate data
warehousing, digital content creation, and electronic and mechanical
design automation. Systems based on the processor can be
configured to scale to four or eight processors and beyond.
1999: Intel Celeron ProcessorContinuing Intel's strategy of developing processors for specific
market segments, the Intel Celeron processor is designed for the
value PC market segment. It provides consumers great performanceat an exceptional price, and it delivers excellent performance for uses
such as gaming and educational software.
1999: Intel Pentiu m III ProcessorThe Intel Pentium III processor features 70 new instructions--
Internet Streaming SIMD extensions-- that dramatically enhance theperformance of advanced imaging, 3-D, streaming audio, video and
speech recognition applications. It was designed to significantlyenhance Internet experiences, allowing users to do such things asbrowse through realistic online museums and stores and download
high-quality video. The processor incorporates 9.5 million transistors,and was introduced using 0.25-micron technology.
1999: Intel Pentium III Xeon ProcessorThe Intel Pentium III Xeonprocessor extends Intel's offerings to the workstation andserver market segments, providing additional performance for e-Commerce applications
and advanced business computing. The processors incorporate the Intel Pentium IIIprocessor's 70 SIMD instructions, which enhance multimedia and streaming video
applications. The Intel Pentium III Xeon processor's advance cache technology speedsinformation from the system bus to the processor, significantly boosting performance. It is
designed for systems with multiprocessor configurations.
2000: Intel Pentium 4 ProcessorUsers of Intel Pentium 4 processor-based PCs can create
professional-quality movies; deliver TV-like video via the Internet;communicate with real-time video and voice; render 3D graphics in
real time; quickly encode music for MP3 players; and simultaneouslyrun several multimedia applications while connected to the Internet.The processor debuted with 42 million transistors and circuit lines of
0.18 microns. Intel's first microprocessor, the 4004, ran at 108kilohertz (108,000 hertz), compared to the Intel Pentium 4processor's initial speed of 1.5 gigahertz (1.5 billion hertz). If
automobile speed had increased similarly over the same period, youcould now drive from San Francisco to New York in about 13
11
http://www.tayloredge.com/museum/processor/2000_Pentium4.jpghttp://www.tayloredge.com/museum/processor/1999_PentiumIII.jpghttp://www.tayloredge.com/museum/processor/1999_Celeron.jpghttp://www.tayloredge.com/museum/processor/1998_PentiumIIXeon.JPG8/8/2019 Final CA Project
12/37
seconds.
2001: Intel Xeon ProcessorThe Intel Xeon processor is targeted for high-performance and mid-range, dual-
processor workstations, dual and multi-processor server configurations coming in thefuture. The platform offers customers a choice of operating systems and applications,
along with high performance at affordable prices. Intel Xeon processor-based workstationsare expected to achieve performance increases between 30 and 90 percent over systems
featuring Intel Pentium III Xeon processors depending on applications andconfigurations. The processor is based on the Intel NetBurst architecture, which isdesigned to deliver the processing power needed for video and audio applications,
advanced Internet technologies, and complex 3-D graphics.
2001: Intel Itanium ProcessorThe Itanium processor is the first in a family of 64-bit products from Intel. Designed for
high-end, enterprise-class servers and workstations, the processor was built from theground up with an entirely new architecture based on Intel's Explicitly Parallel Instruction
Computing (EPIC) design technology. The processor delivers world-class performance forthe most demanding enterprise and high-performance computing applications, including e-
Commerce security transactions, large databases, mechanical computer-aidedengineering, and sophisticated scientific and engineering computing.
2002: Intel Itanium 2 ProcessorThe Itanium 2 processor is the second member of the Itanium processor family, a line ofenterprise-class processors. The family brings outstanding performance and the volume
economics of the Intel Architecture to the most data-intensive, business-critical andtechnical computing applications. It provides leading performance for databases, computer-
aided engineering, secure online transactions, and more.
2003: Intel Pentium M Processor
The Intel Pentium M processor, the Intel 855 chipset family, and the IntelPRO/Wireless 2100 network connection are the three components of Intel Centrinomobile technology. Intel Centrino mobile technology is designed specifically for portablecomputing, with built-in wireless LAN capability and breakthrough mobile performance. It
enables extended battery life and thinner, lighter mobile computers.
B a s i c c o n c e p tIn-order processors In earlier processors, the processing of instructions is normally done inthese steps:
1. Instructionfetch.
2. If input operands are available (in registers for instance), the instruction is
dispatched to the appropriate functional unit. If one or more operand is unavailable during
the current clock cycle (generally because they are being fetched from memory), the
processor stalls until they are available.
3. The instruction is executed by the appropriate functional unit.
4. The functional unit writes the results back to the register file.
12
http://en.wikipedia.org/wiki/Instruction_(computer_science)http://en.wikipedia.org/wiki/Fetchhttp://en.wikipedia.org/wiki/Operandhttp://en.wikipedia.org/wiki/Functional_unithttp://en.wikipedia.org/wiki/Computer_memoryhttp://en.wikipedia.org/wiki/Register_filehttp://en.wikipedia.org/wiki/Instruction_(computer_science)http://en.wikipedia.org/wiki/Fetchhttp://en.wikipedia.org/wiki/Operandhttp://en.wikipedia.org/wiki/Functional_unithttp://en.wikipedia.org/wiki/Computer_memoryhttp://en.wikipedia.org/wiki/Register_file8/8/2019 Final CA Project
13/37
Ou t-of-order processorsThis new paradigm breaks up the processing of instructions into these steps:
1. Instructions fetch.
2. Instruction dispatch to an instruction queue (also called instruction buffer
orreservation stations).
3. The instruction waits in the queue until its input operands are available. The
instruction is then allowed to leave the queue before earlier, older instructions.
4. The instruction is issued to the appropriate functional unit and executed by
that unit.
5. The results are queued.6. Only after all older instructions have their results written back to the register
file, and then this result is written back to the register file. This is called the graduation or
retires stage.
The key concept of OoO processing is to allow the processor to avoid a class of stalls
that occur when the data needed to perform an operation are unavailable. In the outline
above, the OoO processor avoids the stall that occurs in step (2) of the in-orderprocessor when the instruction is not completely ready to be processed due to missing
data.
OoO processors fill these "slots" in time with other instructions that are ready, and then
re-order the results at the end to make it appear that the instructions were processed as
normal. The way the instructions are ordered in the original computer code is known
as program order; in the processor they are handled in data order, the order in which the
data, operands, become available in the processor's registers. Fairly complex circuitry is
needed to convert from one ordering to the other and maintain a logical ordering of the
output; the processor itself runs the instructions in seemingly random order.
The benefit of OoO processing grows as the instruction pipeline deepens and the speed
difference between main memory (orcache memory) and the processor widens. On
modern machines, the processor runs many times faster than the memory, so during the
time an in-order processor spends waiting for data to arrive, it could have processed a
large number of instructions.
Main Components
Arithmetic logic unit (ALU) Barrel shifter Floating-point unit (FPU) Back-side bus Multiplexer Register Memory management unit (MMU) Translation look aside buffer (TLB) Cache register file microcode control unit
13
http://en.wikipedia.org/wiki/Reservation_stationshttp://en.wikipedia.org/wiki/Instruction_pipelinehttp://en.wikipedia.org/wiki/Main_memoryhttp://en.wikipedia.org/wiki/Cache_memoryhttp://en.wikipedia.org/wiki/Arithmetic_logic_unithttp://en.wikipedia.org/wiki/Barrel_shifterhttp://en.wikipedia.org/wiki/Floating-point_unithttp://en.wikipedia.org/wiki/Back-side_bushttp://en.wikipedia.org/wiki/Multiplexerhttp://en.wikipedia.org/wiki/Processor_registerhttp://en.wikipedia.org/wiki/Memory_management_unithttp://en.wikipedia.org/wiki/Translation_lookaside_bufferhttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Register_filehttp://en.wikipedia.org/wiki/Microcodehttp://en.wikipedia.org/wiki/Control_unithttp://en.wikipedia.org/wiki/Reservation_stationshttp://en.wikipedia.org/wiki/Instruction_pipelinehttp://en.wikipedia.org/wiki/Main_memoryhttp://en.wikipedia.org/wiki/Cache_memoryhttp://en.wikipedia.org/wiki/Arithmetic_logic_unithttp://en.wikipedia.org/wiki/Barrel_shifterhttp://en.wikipedia.org/wiki/Floating-point_unithttp://en.wikipedia.org/wiki/Back-side_bushttp://en.wikipedia.org/wiki/Multiplexerhttp://en.wikipedia.org/wiki/Processor_registerhttp://en.wikipedia.org/wiki/Memory_management_unithttp://en.wikipedia.org/wiki/Translation_lookaside_bufferhttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Register_filehttp://en.wikipedia.org/wiki/Microcodehttp://en.wikipedia.org/wiki/Control_unit8/8/2019 Final CA Project
14/37
CPU clock
Arithmetic logic unit:-
In computing, an arithmetic logic unit (ALU) is a digital circuit that
performs arithmetic and logical operations. The ALU is a fundamental building block of
the central processing unit (CPU) of a computer, and even thesimplest microprocessors contain one for purposes such as maintaining timers. The
processors found inside modern CPUs and graphics processing units (GPUs)
accommodate very powerful and very complex ALUs; a single component may contain a
number of ALUs.
Mathematician John von Neumann proposed the ALU concept in 1945, when he wrote a
report on the foundations for a new computer called the EDVAC. Research into ALUs
remains an important part of computer, falling under Arithmetic and logic structures in
the ACM Computing Classification System.
Barrel shifter
A barrel shifter is a digital circuit that can shift a data word by a specified number
ofbits in one clock cycle. It can be implemented as a sequence ofmultiplexers (mux.),
and in such an implementation the output of one mux. is connected to the input of the
next mux. in a way that depends on the shift distance.
For example, take a 4-bit barrel shifter, with inputs A, B, C and D. The shifter can cyclethe order of the bits ABCD as DABC, or BCDA; in this case, no bits are lost. That is, it
can shift all of the outputs up to three positions to the right (and thus make any cyclic
combination of A, B, C and D). The barrel shifter has a variety of applications, including
being a vital component in microprocessors (alongside the ALU).
The number of multiplexers required for an n-bit word is . Four common word
sizes and the number of multiplexers needed are listed below:
64-bit
32-bit 16-bit
14
http://en.wikipedia.org/wiki/CPU_clockhttp://en.wikipedia.org/wiki/Computinghttp://en.wikipedia.org/wiki/Digital_circuithttp://en.wikipedia.org/wiki/Arithmetichttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Graphics_processing_unithttp://en.wikipedia.org/wiki/John_von_Neumannhttp://en.wikipedia.org/wiki/EDVAChttp://en.wikipedia.org/wiki/ACM_Computing_Classification_Systemhttp://en.wikipedia.org/wiki/Digital_circuithttp://en.wikipedia.org/wiki/Bit_shifthttp://en.wikipedia.org/wiki/Word_(computer_science)http://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Clock_cyclehttp://en.wikipedia.org/wiki/Multiplexerhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Arithmetic_logic_unithttp://en.wikipedia.org/wiki/Word_sizehttp://en.wikipedia.org/wiki/Word_sizehttp://en.wikipedia.org/wiki/CPU_clockhttp://en.wikipedia.org/wiki/Computinghttp://en.wikipedia.org/wiki/Digital_circuithttp://en.wikipedia.org/wiki/Arithmetichttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Graphics_processing_unithttp://en.wikipedia.org/wiki/John_von_Neumannhttp://en.wikipedia.org/wiki/EDVAChttp://en.wikipedia.org/wiki/ACM_Computing_Classification_Systemhttp://en.wikipedia.org/wiki/Digital_circuithttp://en.wikipedia.org/wiki/Bit_shifthttp://en.wikipedia.org/wiki/Word_(computer_science)http://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Clock_cyclehttp://en.wikipedia.org/wiki/Multiplexerhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Arithmetic_logic_unithttp://en.wikipedia.org/wiki/Word_sizehttp://en.wikipedia.org/wiki/Word_size8/8/2019 Final CA Project
15/37
8-bit
Floating-point unit
A floating-point unit (FPU) is a part of a computersystem specially designed to carry
out operations on floating numbers. Typical operations
are addition, subtraction, multiplication, division, and square root. Some systems(particularly older, microcode-based architectures) can also perform various
transcendental such as exponential ortrigonometric calculations, though in most modern
processors these are done with software library routines.
In most modern general purpose computer architectures, one or more FPUs are
integrated with the CPU; however many embedded processors, especially older designs,
do not have hardware support for floating-point operations.
When a CPU is executing a program that calls for a floating-point operation, there are
three ways to carry it out:
A floating-point unit emulator (a floating-point library)
Add-on FPU
Integrated FPU
Back-side bus
In personal computermicroprocessorarchitecture, a back side bus (BSB),
or backside bus, is a computer bus used to connect the CPU to CPU cache memory,
usually L2. If a design utilizes it along with a front-side bus (FSB), it is said to use a dual-bus architecture, or in Intels terminology Dual Independent Bus (DIB) architecture. The
dual-bus architecture has been used in a number of designs, including the IBM and Free
scale (formerly the semiconductor division of Motorola) PowerPC processors (certain
PowerPC 604 models, the PowerPC 7xx family, and the Free scale7xxx line), as well as
the Intel Pentium processor, which used it to access their L2 cache (earlier Intel
processors accessed the L2 cache over the FSB, while later processors moved it on-
chip).
Multiplexer
In electronics, a multiplexer or mux (occasionally the terms muldex or muldemare
also found for a combination multiplexer-demultiplexer) is a device that
performs multiplexing; it selects one of many analog or digital input signals and forwards
the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are
used to select which input line to send to the output.
An electronic multiplexer makes it possible for several signals to share one device or
resource, for example one A/D converteror one communication line, instead of having
one device per input signal.
15
http://en.wikipedia.org/wiki/Computerhttp://en.wikipedia.org/wiki/Additionhttp://en.wikipedia.org/wiki/Subtractionhttp://en.wikipedia.org/wiki/Multiplicationhttp://en.wikipedia.org/wiki/Division_(mathematics)http://en.wikipedia.org/wiki/Square_roothttp://en.wikipedia.org/wiki/Microcodehttp://en.wikipedia.org/wiki/Exponentialhttp://en.wikipedia.org/wiki/Trigonometrichttp://en.wikipedia.org/wiki/Computer_architecturehttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Embedded_processorhttp://en.wikipedia.org/wiki/Personal_computerhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Bus_(computing)http://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Front-side_bushttp://en.wikipedia.org/wiki/Dual_independent_bushttp://en.wikipedia.org/wiki/IBMhttp://en.wikipedia.org/wiki/Freescale_Semiconductorhttp://en.wikipedia.org/wiki/Freescale_Semiconductorhttp://en.wikipedia.org/wiki/PowerPChttp://en.wikipedia.org/wiki/604e#PowerPC_604http://en.wikipedia.org/wiki/PowerPC_7xxhttp://en.wikipedia.org/wiki/Freescale_Semiconductorhttp://en.wikipedia.org/wiki/PowerPC_G4http://en.wikipedia.org/wiki/Electronicshttp://en.wikipedia.org/wiki/Multiplexinghttp://en.wikipedia.org/wiki/A/D_converterhttp://en.wikipedia.org/wiki/Computerhttp://en.wikipedia.org/wiki/Additionhttp://en.wikipedia.org/wiki/Subtractionhttp://en.wikipedia.org/wiki/Multiplicationhttp://en.wikipedia.org/wiki/Division_(mathematics)http://en.wikipedia.org/wiki/Square_roothttp://en.wikipedia.org/wiki/Microcodehttp://en.wikipedia.org/wiki/Exponentialhttp://en.wikipedia.org/wiki/Trigonometrichttp://en.wikipedia.org/wiki/Computer_architecturehttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Embedded_processorhttp://en.wikipedia.org/wiki/Personal_computerhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Bus_(computing)http://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Front-side_bushttp://en.wikipedia.org/wiki/Dual_independent_bushttp://en.wikipedia.org/wiki/IBMhttp://en.wikipedia.org/wiki/Freescale_Semiconductorhttp://en.wikipedia.org/wiki/Freescale_Semiconductorhttp://en.wikipedia.org/wiki/PowerPChttp://en.wikipedia.org/wiki/604e#PowerPC_604http://en.wikipedia.org/wiki/PowerPC_7xxhttp://en.wikipedia.org/wiki/Freescale_Semiconductorhttp://en.wikipedia.org/wiki/PowerPC_G4http://en.wikipedia.org/wiki/Electronicshttp://en.wikipedia.org/wiki/Multiplexinghttp://en.wikipedia.org/wiki/A/D_converter8/8/2019 Final CA Project
16/37
On the other end, a demultiplexer (or demux) is a device taking a single input signal and
selecting one of many data-output-lines, which is connected to the single input. Amultiplexer is often used with a complementary demultiplexer on the receiving end.
An electronic multiplexer can be considered as a multiple-input, single-output switch, and
a demultiplexer as a single-input, multiple-output switch. The schematic symbol for a
multiplexer is an isosceles trapezoid with the longer parallel side containing the input pins
and the short parallel side containing the output pin. The schematic on the right shows a
2-to-1 multiplexer on the left and an equivalent switch on the right. The sel wire connects
the desired input to the output.
Processor register
In computer architecture, a processor register (or general purpose register) is a
small amount ofstorage available on the CPU whose contents can be accessed more
quickly than storage available elsewhere. Typically, this specialized storage is not
considered part of the normal memory range for the machine. Most, but not all, modern
computers adopt the so-called load-store architecture. Under this paradigm data is
'shuffled' from subordinated memory be it L# cache orRAM into registers,
'crunched' therein by running instructions from the instruction, then transferred out. A
common property ofcomputer programs is locality of reference: the same values areoften accessed repeatedly; and holding these frequently used values in registers
improves program execution performance.
Processor registers are at the top of the memory hierarchy, and provide the fastest way
for a CPU to access data. The term is often used to refer only to the group of registers
that are directly encoded as part of an instruction, as defined by the instruction set. More
properly, these are called the "architectural registers". For instance, the x86 instruction
set defines a set ofeight 32-bit registers, but a CPU that implements the x86 instruction
set will often contain many more registers than just these eight.
Architecture
Integerregisters
Double FPregisters
x86 8 8
x86-64 16 16
IBM/360 16 4
Z/Architecture
16 16
Itanium 128 128
UltraSPARC
32 32
POWER 32 32
Alpha 32 32
6502 3 0
PIC 1 0
16
http://en.wikipedia.org/wiki/MISO#Characterization_of_systemshttp://en.wikipedia.org/wiki/MISO#Characterization_of_systemshttp://en.wikipedia.org/wiki/Isosceles_trapezoidhttp://en.wikipedia.org/wiki/Computer_architecturehttp://en.wikipedia.org/wiki/Computer_storagehttp://en.wikipedia.org/wiki/CPUhttp://en.wikipedia.org/wiki/Load-store_architecturehttp://en.wikipedia.org/wiki/CPU_cache#Multi-level_cacheshttp://en.wikipedia.org/wiki/RAMhttp://en.wikipedia.org/wiki/Computer_programhttp://en.wikipedia.org/wiki/Locality_of_referencehttp://en.wikipedia.org/wiki/Memory_hierarchyhttp://en.wikipedia.org/wiki/CPUhttp://en.wikipedia.org/wiki/Instruction_sethttp://en.wikipedia.org/wiki/X86http://en.wikipedia.org/wiki/Processor_register#Some_examples%23Some_exampleshttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/X86http://en.wikipedia.org/wiki/X86-64http://en.wikipedia.org/wiki/IBM/360http://en.wikipedia.org/wiki/Z/Architecturehttp://en.wikipedia.org/wiki/Z/Architecturehttp://en.wikipedia.org/wiki/Itaniumhttp://en.wikipedia.org/wiki/UltraSPARChttp://en.wikipedia.org/wiki/UltraSPARChttp://en.wikipedia.org/wiki/POWERhttp://en.wikipedia.org/wiki/DEC_Alphahttp://en.wikipedia.org/wiki/MOS_Technology_6502http://en.wikipedia.org/wiki/PIC_microcontrollerhttp://en.wikipedia.org/wiki/MISO#Characterization_of_systemshttp://en.wikipedia.org/wiki/MISO#Characterization_of_systemshttp://en.wikipedia.org/wiki/Isosceles_trapezoidhttp://en.wikipedia.org/wiki/Computer_architecturehttp://en.wikipedia.org/wiki/Computer_storagehttp://en.wikipedia.org/wiki/CPUhttp://en.wikipedia.org/wiki/Load-store_architecturehttp://en.wikipedia.org/wiki/CPU_cache#Multi-level_cacheshttp://en.wikipedia.org/wiki/RAMhttp://en.wikipedia.org/wiki/Computer_programhttp://en.wikipedia.org/wiki/Locality_of_referencehttp://en.wikipedia.org/wiki/Memory_hierarchyhttp://en.wikipedia.org/wiki/CPUhttp://en.wikipedia.org/wiki/Instruction_sethttp://en.wikipedia.org/wiki/X86http://en.wikipedia.org/wiki/Processor_register#Some_examples%23Some_exampleshttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/X86http://en.wikipedia.org/wiki/X86-64http://en.wikipedia.org/wiki/IBM/360http://en.wikipedia.org/wiki/Z/Architecturehttp://en.wikipedia.org/wiki/Z/Architecturehttp://en.wikipedia.org/wiki/Itaniumhttp://en.wikipedia.org/wiki/UltraSPARChttp://en.wikipedia.org/wiki/UltraSPARChttp://en.wikipedia.org/wiki/POWERhttp://en.wikipedia.org/wiki/DEC_Alphahttp://en.wikipedia.org/wiki/MOS_Technology_6502http://en.wikipedia.org/wiki/PIC_microcontroller8/8/2019 Final CA Project
17/37
microcontroller
AVRmicrocontroller
32 0
ARM 16 16
Memory Management Unit
A memory management unit (MMU), sometimes called paged memory
management unit (PMMU), is a computer hardware component responsible for handlingaccesses to memory requested by the CPU. Its functions include translation ofvirtual
addresses to physical addresses(i.e., virtual memory management), memory
protection, cache control, busarbitration, and, in simpler computer architectures
(especially 8-bit systems), bank switching.
Modern MMUs typically divide the virtual address space (the range of addresses used by
the processor) into pages, each having a size which is a power of 2, usually a
few kilobytes, but they may be much larger. The bottom n bits of the address (the offset
within a page) are left unchanged. The upper address bits are the (virtual) page number.
The MMU normally translates virtual page numbers to physical page numbers via an
associative cache called a Translation Look aside Buffer(TLB). When the TLB lacks a
translation, a slower mechanism involving hardware-specific data structures or software
assistance is used. The data found in such data structures are typically called page table
entries (PTEs), and the data structure itself is typically called a page table. The physical
page number is combined with the page offset to give the complete physical address.
A PTE or TLB entry may also include information about whether the page has been written
to (the dirty bit), when it was last used (the accessed bit, for aleast recently used page
replacement algorithm), what kind of processes (user mode, supervisor mode) may read
and write it, and whether it should be cached.
Translation Look Aside Buffer
A translation look aside buffer (TLB) is a CPU cache that memory management
hardware uses to improve virtual address translation speed. It was the first cache
introduced in processors. All current desktop and server processors (such as x86) use a
TLB.
17
http://en.wikipedia.org/wiki/PIC_microcontrollerhttp://en.wikipedia.org/wiki/Atmel_AVRhttp://en.wikipedia.org/wiki/Atmel_AVRhttp://en.wikipedia.org/wiki/ARM_architecturehttp://en.wikipedia.org/wiki/Computer_hardwarehttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Virtual_addresshttp://en.wikipedia.org/wiki/Virtual_addresshttp://en.wikipedia.org/wiki/Physical_addresshttp://en.wikipedia.org/wiki/Virtual_memoryhttp://en.wikipedia.org/wiki/Memory_protectionhttp://en.wikipedia.org/wiki/Memory_protectionhttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Computer_bushttp://en.wikipedia.org/wiki/Arbiter_(electronics)http://en.wikipedia.org/wiki/8-bithttp://en.wikipedia.org/wiki/Bank_switchinghttp://en.wikipedia.org/wiki/Address_spacehttp://en.wikipedia.org/wiki/Page_(computer_science)http://en.wikipedia.org/wiki/Kilobytehttp://en.wikipedia.org/wiki/Translation_Lookaside_Bufferhttp://en.wikipedia.org/wiki/Page_tablehttp://en.wikipedia.org/wiki/Least_recently_usedhttp://en.wikipedia.org/wiki/Page_replacement_algorithmhttp://en.wikipedia.org/wiki/Page_replacement_algorithmhttp://en.wikipedia.org/wiki/User_modehttp://en.wikipedia.org/wiki/Supervisor_modehttp://en.wikipedia.org/wiki/Cachehttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Memory_management_unithttp://en.wikipedia.org/wiki/Memory_management_unithttp://en.wikipedia.org/wiki/Virtual_addresshttp://en.wikipedia.org/wiki/X86http://en.wikipedia.org/wiki/PIC_microcontrollerhttp://en.wikipedia.org/wiki/Atmel_AVRhttp://en.wikipedia.org/wiki/Atmel_AVRhttp://en.wikipedia.org/wiki/ARM_architecturehttp://en.wikipedia.org/wiki/Computer_hardwarehttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Virtual_addresshttp://en.wikipedia.org/wiki/Virtual_addresshttp://en.wikipedia.org/wiki/Physical_addresshttp://en.wikipedia.org/wiki/Virtual_memoryhttp://en.wikipedia.org/wiki/Memory_protectionhttp://en.wikipedia.org/wiki/Memory_protectionhttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Computer_bushttp://en.wikipedia.org/wiki/Arbiter_(electronics)http://en.wikipedia.org/wiki/8-bithttp://en.wikipedia.org/wiki/Bank_switchinghttp://en.wikipedia.org/wiki/Address_spacehttp://en.wikipedia.org/wiki/Page_(computer_science)http://en.wikipedia.org/wiki/Kilobytehttp://en.wikipedia.org/wiki/Translation_Lookaside_Bufferhttp://en.wikipedia.org/wiki/Page_tablehttp://en.wikipedia.org/wiki/Least_recently_usedhttp://en.wikipedia.org/wiki/Page_replacement_algorithmhttp://en.wikipedia.org/wiki/Page_replacement_algorithmhttp://en.wikipedia.org/wiki/User_modehttp://en.wikipedia.org/wiki/Supervisor_modehttp://en.wikipedia.org/wiki/Cachehttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Memory_management_unithttp://en.wikipedia.org/wiki/Memory_management_unithttp://en.wikipedia.org/wiki/Virtual_addresshttp://en.wikipedia.org/wiki/X868/8/2019 Final CA Project
18/37
The TLB is typically implemented as content-addressable memory (CAM). The CAM
search key is the virtual address and the search result is a physical address. If the
requested address is present in the TLB, the CAM search yields a match quickly and the
retrieved physical address can be used to access memory. This is called a TLB hit. If the
requested address is not in the TLB, it is a miss and the translation proceeds by looking up
the page table in a process called a page walk. The page walk is an expensive process, as
it involves reading the contents of multiple memory locations and using them to compute
the physical address. After the physical address is determined by the page walk, the virtual
address to physical address mapping is entered into the TLB.
CPU Cache
A CPU cache is a cache used by the central processing unit of a computerto reduce the
average time to access memory. The cache is a smaller, faster memory which stores
copies of the data from the most frequently used main memory locations. As long as mostmemory accesses are cached memory locations, the average latency of memory accesses
will be closer to the cache latency than to the latency of main memory.
When the processor needs to read from or write to a location in main memory, it first
checks whether a copy of that data is in the cache. If so, the processor immediately reads
from or writes to the cache, which is much faster than reading from or writing to main
memory.
Most modern desktop and server CPUs have at least three independent caches:
an instruction cache to speed up executable instruction fetch, a data cache to speed up
data fetch and store, and a translation look aside bufferused to speed up virtual-to-physical address translation for both executable instructions and data.
18
http://en.wikipedia.org/wiki/Content-addressable_memoryhttp://en.wikipedia.org/wiki/Page_tablehttp://en.wikipedia.org/wiki/Cachehttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Computerhttp://en.wikipedia.org/wiki/Computer_storagehttp://en.wikipedia.org/wiki/Main_memoryhttp://en.wikipedia.org/wiki/RAM_latencyhttp://en.wikipedia.org/wiki/Translation_lookaside_bufferhttp://en.wikipedia.org/wiki/Content-addressable_memoryhttp://en.wikipedia.org/wiki/Page_tablehttp://en.wikipedia.org/wiki/Cachehttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Computerhttp://en.wikipedia.org/wiki/Computer_storagehttp://en.wikipedia.org/wiki/Main_memoryhttp://en.wikipedia.org/wiki/RAM_latencyhttp://en.wikipedia.org/wiki/Translation_lookaside_buffer8/8/2019 Final CA Project
19/37
In order of increasing (worse) hit times and decreasing (better) miss rates
direct mapped cachethe best (fastest) hit times, and so the best tradeoff for
"large" caches
2-way set associative cache
2-way skewed associative cache "the best tradeoff for .... caches whosesizes are in the range 4K-8K bytes" Andr Seznec
4-way set associative cache
fully associative cache the best (lowest) miss rates, and so the best tradeoff
when the miss penalty is very high
If each location in main memory can be cached in either of two locations in the cache, one
logical question is: which two? The simplest and most commonly used scheme, shown in
the right-hand diagram above, is to use the least significant bits of the memory location's
index as the index for the cache memory, and to have two entries for each index. One
benefit of this scheme is that the tags stored in the cache do not have to include that part of
the main memory address which is implied by the cache memory's index. Since the cache
tags are fewer bits, they take less area [on the microprocessor chip] and can be read and
compared faster.
Register file
A register file is an array ofprocessor registers in a central processing unit (CPU).Modern integrated circuit-based register files are usually implemented by way of fast static
RAMs with multiple ports. Such RAMs are distinguished by having dedicated read and
write ports, whereas ordinary multiported SRAMs will usually read and write through the
same ports.
The instruction set architecture of a CPU will almost always define a set of registers which
are used to stage data between memory and the functional units on the chip. In simpler
CPUs, these architectural registers correspond one-for-one to the entries in a physical
register file within the CPU. More complicated CPUs use register renaming, so that the
mapping of which physical entry stores a particular architectural register changes
dynamically during execution. The register file is part of the architecture and visible to the
programmer, as opposed to the concept of transparent caches.
Most register files make no special provision to prevent multiple write ports from writing the
same entry simultaneously. Instead, the instruction scheduling hardware ensures that only
one instruction in any particular cycle writes a particular entry. If multiple instructions
targeting the same register are issued, all but one have their write enables turned off.
The crossed inverters take some finite time to settle after a write operation, during which a
read operation will either take longer or return garbage. It is common to have bypass
multiplexers that bypass written data to the read ports when a simultaneous read and writeto the same entry is commanded. These bypass multiplexers are often just part of a larger
19
http://en.wikipedia.org/wiki/Processor_registerhttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Static_RAMhttp://en.wikipedia.org/wiki/Static_RAMhttp://en.wikipedia.org/wiki/Instruction_set_architecturehttp://en.wikipedia.org/wiki/Register_renaminghttp://en.wikipedia.org/wiki/Instruction_set_architecturehttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Processor_registerhttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Static_RAMhttp://en.wikipedia.org/wiki/Static_RAMhttp://en.wikipedia.org/wiki/Instruction_set_architecturehttp://en.wikipedia.org/wiki/Register_renaminghttp://en.wikipedia.org/wiki/Instruction_set_architecturehttp://en.wikipedia.org/wiki/CPU_cache8/8/2019 Final CA Project
20/37
bypass network that forwards results that have not yet been committed between functional
units.
Microcode:
Microcode is a layer of hardware-level instructions and/or data structures involved in
the implementation of higher level code instructions in many computers and other
processors; it resides in a special high-speed memory and translates machine instructions
into sequences of detailed circuit-level operations. It helps separate the machine
instructions from the underlying electronics so that instructions can be designed and
altered more freely. It also makes it feasible to build complex multi-step instructions while
still reducing the complexity of the electronic circuitry compared to other methods. Writing
microcode is often called microprogramming and the microcode in a particular processor
implementation is sometimes called a micro program. The elements composing a micro
program exist on a lower conceptual level than a normal application program. Each
element is differentiated by the "micro" prefix to avoid confusion: microinstruction, microassembler, micro programmer, micro architecture, etc.
Control Unit
A control unit in general is a central (or sometimes distributed but clearly distinguishable)
part of whatsoever machinery that controls its operation, provided that a piece of
machinery is complex and organized enough to contain any such unit. One domain in
which the term is specifically used is the area of computer design. In the automotive
industry, the control unit helps maintain various functions of the motor vehicle. In modern
computer designs, the control unit is typically an internal part of the CPU with its overall
role and operation unchanged. The functions performed by the control unit vary greatly by
the internal architecture of the CPU, since the control unit really implements this
architecture.
Clock Rate
The clock rate is the rate in cycles per second (measured in hertz) or the frequency of the
clock in any synchronous circuit, such as acentral processing unit (CPU). For example,
a crystal oscillatorfrequency reference typically is synonymous with a fixed sinusoidalwaveform; a clock rate is that frequency reference translated by electronic circuitry (AD
20
http://en.wikipedia.org/wiki/Electronicshttp://en.wikipedia.org/wiki/Automotive_industryhttp://en.wikipedia.org/wiki/Automotive_industryhttp://en.wikipedia.org/wiki/Motor_vehiclehttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Hertzhttp://en.wikipedia.org/wiki/Synchronous_circuithttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Crystal_oscillatorhttp://en.wikipedia.org/wiki/Analog-to-digital_converterhttp://en.wikipedia.org/wiki/Electronicshttp://en.wikipedia.org/wiki/Automotive_industryhttp://en.wikipedia.org/wiki/Automotive_industryhttp://en.wikipedia.org/wiki/Motor_vehiclehttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Hertzhttp://en.wikipedia.org/wiki/Synchronous_circuithttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Crystal_oscillatorhttp://en.wikipedia.org/wiki/Analog-to-digital_converter8/8/2019 Final CA Project
21/37
Converter) into a corresponding square wave pulse [typically] for digital electronics
applications. In this context the use of the word, speed (physical movement), should not be
confused with frequency or its corresponding clock rate. Thus, the term "clock speed" is
a misnomer.
A single clock cycle (typically shorter than a nanosecond in modern non-
embeddedmicroprocessors) toggles between a logical zero and a logical one state.
Historically, the logical zero state of a clock cycle persists longer than a logical one statedue to thermal and electrical specification constraints.
CPU manufacturers typically charge premium prices for CPUs that operate at higher clock
rates. For a given CPU, the clock rates are determined at the end of the manufacturing
process through actual testing of each CPU. CPUs that are tested as complying with a
given set of standards may be labeled with a higher clock rate, e.g., 1.50 GHz, while those
that fail the standards of the higher clock rate yet pass the standards of a lesser clock rate
may be labeled with the lesser clock rate, e.g., 1.33 GHz, and sold at a lower price.
The clock rate of a CPU is only useful for providing comparisons between CPUs in the
same family. An IBM PC with an Intel 80486CPU running at 50 MHz will be about twice asfast as one with the same CPU and memory running at 25 MHz, while the same will not be
true for MIPS R4000 running at the same clock rate as the two are different processors that
implement different architectures and micro architectures. Furthermore, there are many
other factors to consider when comparing the performance of CPUs, like the clock rate and
width of the CPU's data bus, the latency of the memory, and the cache architecture.
CPU design
CPU design is the design engineering task of creating a central processingunit (CPU), a component ofcomputer hardware.
CPU design focuses on these areas:
1. data paths (such as ALUs and pipelines)
2. control unit: logic which controls the data paths
3. Memory components such as register files, caches
4. Clock circuitry such as clock drivers, PLLs, clock distribution networks
5. Pad transceiver circuitry
6. Logic gate cell library which is used to implement the logic
CPUs designed for high-performance markets might require custom designs for each of
these items to achieve frequency, power-dissipation, and chip-area goals.
CPUs designed for lower performance markets might lessen the implementation burden
by:
Acquiring some of these items by purchasing them as intellectual property
Use control logic implementation techniques (logic synthesis using CAD
tools) to implement the other components - datapaths, register files, clocks
21
http://en.wikipedia.org/wiki/Analog-to-digital_converterhttp://en.wikipedia.org/wiki/Speedhttp://en.wikipedia.org/wiki/Misnomerhttp://en.wikipedia.org/wiki/Cycles_Per_Instructionhttp://en.wikipedia.org/wiki/1_E-9_shttp://en.wikipedia.org/wiki/Embedded_systemhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Intel_80486http://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Data_bushttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Design_engineerhttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Computer_hardwarehttp://en.wikipedia.org/wiki/Datapathhttp://en.wikipedia.org/wiki/Arithmetic_logic_unithttp://en.wikipedia.org/wiki/Pipeline_(computing)http://en.wikipedia.org/wiki/Control_unithttp://en.wikipedia.org/wiki/Control_unithttp://en.wikipedia.org/wiki/Phase-locked_loophttp://en.wikipedia.org/wiki/Library_(electronics)http://en.wikipedia.org/wiki/Power_consumptionhttp://en.wikipedia.org/wiki/Power_consumptionhttp://en.wikipedia.org/wiki/Intellectual_propertyhttp://en.wikipedia.org/wiki/Logic_synthesishttp://en.wikipedia.org/wiki/Analog-to-digital_converterhttp://en.wikipedia.org/wiki/Speedhttp://en.wikipedia.org/wiki/Misnomerhttp://en.wikipedia.org/wiki/Cycles_Per_Instructionhttp://en.wikipedia.org/wiki/1_E-9_shttp://en.wikipedia.org/wiki/Embedded_systemhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Intel_80486http://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Data_bushttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Design_engineerhttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Computer_hardwarehttp://en.wikipedia.org/wiki/Datapathhttp://en.wikipedia.org/wiki/Arithmetic_logic_unithttp://en.wikipedia.org/wiki/Pipeline_(computing)http://en.wikipedia.org/wiki/Control_unithttp://en.wikipedia.org/wiki/Phase-locked_loophttp://en.wikipedia.org/wiki/Library_(electronics)http://en.wikipedia.org/wiki/Power_consumptionhttp://en.wikipedia.org/wiki/Intellectual_propertyhttp://en.wikipedia.org/wiki/Logic_synthesis8/8/2019 Final CA Project
22/37
Common logic styles used in CPU design include:
Unstructured random logic
Finite-state machines
Microprogramming (common from 1965 to 1985)
Programmable logic array (common in the 1980s, no longer common)
Device types used to implement the logic include:
Transistor-transistor logic Small Scale Integration logic chips - no longer used
for CPUs
Programmable Array Logic and Programmable logic devices - no longer used
for CPUs
Emitter-coupled logic (ECL) gate arrays - no longer common
CMOS gate arrays - no longer used for CPUs
CMOS ASICs - what's commonly used today, they're so common that the
term ASIC is not used for CPUs Field-programmable gate arrays (FPGA) - common forsoft microprocessors,
and more or less required forreconfigurable computing
A CPU design project generally has these major tasks:
Programmer-visible instruction set architecture, which can be implemented by
a variety ofmicro architectures
Architectural study and performance modeling in ANSI C/C++ orSystem C
High-level synthesis (HLS) orRTL (eg. logic) implementation RTL Verification
Circuit design of speed critical components (caches, registers, ALUs)
Logic synthesis or logic-gate-level design
Timing analysis to confirm that all logic and circuits will run at the specified
operating frequency
Physical design including floor planning, place and route of logic gates
Checking that RTL, gate-level, transistor-level and physical-level
representations are equivalent
Checks forsignal integrity, chip manufacturability
As with most complex electronic designs, the logic verification effort (proving that the
design does not have bugs) now dominates the project schedule of a CPU.
Key CPU architectural innovations include index register, cache, virtual memory, instruction
pipelining, superscalar, CISC, RISC, virtual machine, emulators, micro program, and stack.
22
http://en.wikipedia.org/wiki/Finite-state_machinehttp://en.wikipedia.org/wiki/Microprogramminghttp://en.wikipedia.org/wiki/Programmable_logic_arrayhttp://en.wikipedia.org/wiki/Transistor-transistor_logichttp://en.wikipedia.org/wiki/Small_Scale_Integrationhttp://en.wikipedia.org/wiki/Programmable_Array_Logichttp://en.wikipedia.org/wiki/Programmable_logic_devicehttp://en.wikipedia.org/wiki/Emitter-coupled_logichttp://en.wikipedia.org/wiki/Gate_arrayhttp://en.wikipedia.org/wiki/CMOShttp://en.wikipedia.org/wiki/Gate_arrayhttp://en.wikipedia.org/wiki/CMOShttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/Field-programmable_gate_arrayhttp://en.wikipedia.org/wiki/Soft_microprocessorhttp://en.wikipedia.org/wiki/Reconfigurable_computinghttp://en.wikipedia.org/wiki/Instruction_set_architecturehttp://en.wikipedia.org/wiki/Microarchitecturehttp://en.wikipedia.org/wiki/Microarchitecturehttp://en.wikipedia.org/wiki/ANSI_Chttp://en.wikipedia.org/wiki/C%2B%2Bhttp://en.wikipedia.org/wiki/SystemChttp://en.wikipedia.org/wiki/High-level_synthesishttp://en.wikipedia.org/wiki/Register_transfer_levelhttp://en.wikipedia.org/wiki/Circuit_designhttp://en.wikipedia.org/wiki/Logic_synthesishttp://en.wikipedia.org/wiki/Static_timing_analysishttp://en.wikipedia.org/wiki/Floorplanninghttp://en.wikipedia.org/wiki/Place_and_routehttp://en.wikipedia.org/wiki/Signal_integrityhttp://en.wikipedia.org/wiki/Design_rule_checkinghttp://en.wikipedia.org/wiki/Functional_verificationhttp://en.wikipedia.org/wiki/Index_registerhttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Virtual_memoryhttp://en.wikipedia.org/wiki/Instruction_pipelininghttp://en.wikipedia.org/wiki/Instruction_pipelininghttp://en.wikipedia.org/wiki/Superscalarhttp://en.wikipedia.org/wiki/Complex_instruction_set_computerhttp://en.wikipedia.org/wiki/Reduced_instruction_set_computerhttp://en.wikipedia.org/wiki/Virtual_machinehttp://en.wikipedia.org/wiki/Emulatorhttp://en.wikipedia.org/wiki/Microprogramhttp://en.wikipedia.org/wiki/Stack_(data_structure)http://en.wikipedia.org/wiki/Finite-state_machinehttp://en.wikipedia.org/wiki/Microprogramminghttp://en.wikipedia.org/wiki/Programmable_logic_arrayhttp://en.wikipedia.org/wiki/Transistor-transistor_logichttp://en.wikipedia.org/wiki/Small_Scale_Integrationhttp://en.wikipedia.org/wiki/Programmable_Array_Logichttp://en.wikipedia.org/wiki/Programmable_logic_devicehttp://en.wikipedia.org/wiki/Emitter-coupled_logichttp://en.wikipedia.org/wiki/Gate_arrayhttp://en.wikipedia.org/wiki/CMOShttp://en.wikipedia.org/wiki/Gate_arrayhttp://en.wikipedia.org/wiki/CMOShttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/Field-programmable_gate_arrayhttp://en.wikipedia.org/wiki/Soft_microprocessorhttp://en.wikipedia.org/wiki/Reconfigurable_computinghttp://en.wikipedia.org/wiki/Instruction_set_architecturehttp://en.wikipedia.org/wiki/Microarchitecturehttp://en.wikipedia.org/wiki/ANSI_Chttp://en.wikipedia.org/wiki/C%2B%2Bhttp://en.wikipedia.org/wiki/SystemChttp://en.wikipedia.org/wiki/High-level_synthesishttp://en.wikipedia.org/wiki/Register_transfer_levelhttp://en.wikipedia.org/wiki/Circuit_designhttp://en.wikipedia.org/wiki/Logic_synthesishttp://en.wikipedia.org/wiki/Static_timing_analysishttp://en.wikipedia.org/wiki/Floorplanninghttp://en.wikipedia.org/wiki/Place_and_routehttp://en.wikipedia.org/wiki/Signal_integrityhttp://en.wikipedia.org/wiki/Design_rule_checkinghttp://en.wikipedia.org/wiki/Functional_verificationhttp://en.wikipedia.org/wiki/Index_registerhttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Virtual_memoryhttp://en.wikipedia.org/wiki/Instruction_pipelininghttp://en.wikipedia.org/wiki/Instruction_pipelininghttp://en.wikipedia.org/wiki/Superscalarhttp://en.wikipedia.org/wiki/Complex_instruction_set_computerhttp://en.wikipedia.org/wiki/Reduced_instruction_set_computerhttp://en.wikipedia.org/wiki/Virtual_machinehttp://en.wikipedia.org/wiki/Emulatorhttp://en.wikipedia.org/wiki/Microprogramhttp://en.wikipedia.org/wiki/Stack_(data_structure)8/8/2019 Final CA Project
23/37
G o a l sThe first CPUs were designed to do mathematical calculations faster and more reliably
thanhuman computers.
Each successive generation of CPU might be designed to achieve some of these goals:
higher performance levels of a single program or thread
higher throughput levels of multiple programs/threads
less power consumption for the same performance level
lower cost for the same performance level
greater connectivity to build larger, more parallel systems
more specialization to aid in specific targeted markets
Re-designing a CPU core to a smaller die-area helps achieve several of these goals.
Shrinking everything (a "photo mask shrink"), resulting in the same number oftransistors on a smaller die, improves performance (smaller transistors switch faster),
reduces power (smaller wires have less parasitic capacitance) and reduces cost (more
CPUs fit on the same wafer of silicon).
Releasing a CPU on the same size die, but with a smaller CPU core, keeps
the cost about the same but allows higher levels of integration within one VLSI chip
(additional cache, multiple CPUs, or other components), improving performance and
reducing overall system cost.
Embedded designAs measured by units shipped, most CPUs are embedded in other machinery,
such as telephones, clocks, appliances, vehicles, and infrastructure. Embedded processors
sell in the volume of many billions of units per year, however, mostly at much lower price
points than that of the general purpose processors.
These single-function devices differ from the more familiar general-purpose CPUs in
several ways:
Low cost is of utmost importance.
It is important to maintain a low power dissipation as embedded devices often
have a limited battery life and it is often impractical to include cooling fans.
To give lower system cost, peripherals are integrated with the processor on
the same silicon chip.
Keeping peripherals on-chip also reduces power consumption as external
GPIO ports typically require buffering so that they can source or sink the relatively high
current loads that are required to maintain a strong signal outside of the chip.
Many embedded applications have a limited amount of physical space
for circuitry; keeping peripherals on-chip will reduce the space required for the circuit
board.
23
http://en.wikipedia.org/wiki/Human_computershttp://en.wikipedia.org/wiki/Low-powerhttp://en.wikipedia.org/wiki/Photomaskhttp://en.wikipedia.org/wiki/VLSIhttp://en.wikipedia.org/wiki/Human_computershttp://en.wikipedia.org/wiki/Low-powerhttp://en.wikipedia.org/wiki/Photomaskhttp://en.wikipedia.org/wiki/VLSI8/8/2019 Final CA Project
24/37
The program and data memories are often integrated on the same
chip. When the only allowed program memory is ROM, the device is known as
a microcontroller.
For many embedded applications, interrupt latency will be more critical than
in some general-purpose processors.
Embedded Processor EconomicsAs of 2009, more CPUs are produced using the ARM architecture instruction set than any
other 32-bit instruction set. The ARM architecture and the first ARM chip were designed in
about one and a half years and 5 man years of work time.
The 32-bit Parallax Propellermicrocontroller architecture and the first chip were designed
by two people in about 10 man years of work time.
It is believedthat the 8-bit AVR architecture and first AVR microcontroller was conceived
and designed by two students at the Norwegian Institute of Technology.
The 8-bit 6502 architecture and the first 6502 chip were designed in 13 months by a group
of about 9 people.
Bit slicing
Bit slicing is a technique for constructing a processorfrom modules of smaller bit width.
Each of these components processes one fielder "slice" of an operand. The grouped
processing components would then have the capability to process the chosen full word-
length of a particular software design. Bit slice processors usually consist of an arithmetic
logic unit (ALU) of 1, 2, 4 or 8 bits and control lines (including carry oroverflow signals that
are internal to the processor in non-bit sliced designs). For example, two 4-bit ALUs could
be arranged side by side, with control lines between them, to form 8-bit, 16-bit, 32-bit
words (so the designer can add as many slices he wants to make it to manipulate longer
words lengths). A micro sequencerorControl ROM would be used to execute logic to
provide data and control signals to regulate function of the component ALUs. Examples of
bit-slice microprocessor modules can be seen in the Intel 3000 family, the AMD's Am2900family the National SemiconductorIMP-16 and IMP-8 family, and the 74181.
During the era this technique was most common (mid-1970's through 1980's), there was
some debate over how much bus width was necessary in a given computer system, and
silicon chip technology and parts were generally much more expensive than today. Using
multiple simpler (and cheaper) ALUs was seen as a way to increase computing power in a
cost effective manner. 32-bit architectures were being discussed but few were in
production. 16-bit processors were common but expensive, and the 8-bit processors, such
as the Z80 were widely used in the nascent home computer market. Combining
components to produce bit slice products allowed engineers and students to create morepowerful and complex computers at a more reasonable cost, using off-the-shelf
24
http://en.wikipedia.org/wiki/Read-only_memoryhttp://en.wikipedia.org/wiki/Microcontrollerhttp://en.wikipedia.org/wiki/ARM_architecturehttp://en.wikipedia.org/wiki/Parallax_Propellerhttp://en.wikipedia.org/wiki/Atmel_AVRhttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Operandhttp://en.wikipedia.org/wiki/Arithmetic_logic_unithttp://en.wikipedia.org/wiki/Arithmetic_logic_unithttp://en.wikipedia.org/wiki/Arithmetic_overflowhttp://en.wikipedia.org/wiki/Microsequencerhttp://en.wikipedia.org/w/index.php?title=Control_ROM&action=edit&redlink=1http://en.wikipedia.org/wiki/Intel_3000http://en.wikipedia.org/wiki/AMD_Am2900http://en.wikipedia.org/wiki/AMD_Am2900http://en.wikipedia.org/wiki/National_Semiconductorhttp://en.wikipedia.org/wiki/IMP-16http://en.wikipedia.org/w/index.php?title=IMP-8&action=edit&redlink=1http://en.wikipedia.org/wiki/74181http://en.wikipedia.org/wiki/Z80http://en.wikipedia.org/wiki/Read-only_memoryhttp://en.wikipedia.org/wiki/Microcontrollerhttp://en.wikipedia.org/wiki/ARM_architecturehttp://en.wikipedia.org/wiki/Parallax_Propellerhttp://en.wikipedia.org/wiki/Atmel_AVRhttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Operandhttp://en.wikipedia.org/wiki/Arithmetic_logic_unithttp://en.wikipedia.org/wiki/Arithmetic_logic_unithttp://en.wikipedia.org/wiki/Arithmetic_overflowhttp://en.wikipedia.org/wiki/Microsequencerhttp://en.wikipedia.org/w/index.php?title=Control_ROM&action=edit&redlink=1http://en.wikipedia.org/wiki/Intel_3000http://en.wikipedia.org/wiki/AMD_Am2900http://en.wikipedia.org/wiki/AMD_Am2900http://en.wikipedia.org/wiki/National_Semiconductorhttp://en.wikipedia.org/wiki/IMP-16http://en.wikipedia.org/w/index.php?title=IMP-8&action=edit&redlink=1http://en.wikipedia.org/wiki/74181http://en.wikipedia.org/wiki/Z808/8/2019 Final CA Project
25/37
components that could be custom-configured. The complexities of creating new computer
architecture were greatly reduced when the details of the ALU were already specified (and
debugged). The main advantage in the late 60's to mid 80's being though, that bit slicing
made it economically possible in smaller processors to use bipolar transistors, which switch
much faster than NMOS or CMOS transistors. This allowed for much higher clock rates, for
applications were speed was needed. For example DSP functions or matrix transformation,
or as in the Xerox Alto the combination of flexibility and speed, before discrete CPUs was
able to deliver that.
Bit slicing (although it was not called that) was also used in computers before integrated
circuits. The first bit-sliced machine was EDSAC 2, built at the University of Cambridge
Mathematical Laboratory in 1956-8. Another example was the Storage Address Registers
(StARs) of the IBM, which were built on IBM Standard Modular System cards containing a
one-bit slice of the four registers in the basic machine.
In more recent times, the term bit slicing was re-coined by Matthew Kwan to refer to the
technique of using a general purpose CPU to implement multiple parallel simple virtual
machines using general logic instructions to perform Single Instruction Multiple
Data operations. This technique is also known as SWAR, SIMD within a Register.
T h e b i t - s l i c e p r o c e s s o r3000 Family
25
http://en.wikipedia.org/wiki/EDSAC_2http://en.wikipedia.org/wiki/University_of_Cambridge_Mathematical_Laboratoryhttp://en.wikipedia.org/wiki/University_of_Cambridge_Mathematical_Laboratoryhttp://en.wikipedia.org/wiki/IBM_Standard_Modular_Systemhttp://en.wikipedia.org/wiki/SIMDhttp://en.wikipedia.org/wiki/SIMDhttp://en.wikipedia.org/wiki/SWARhttp://en.wikipedia.org/wiki/Bit_slicinghttp://en.wikipedia.org/wiki/Intel_3000http://en.wikipedia.org/wiki/File:KL_intel_D3002.jpghttp://en.wikipedia.org/wiki/File:KL_intel_D3002.jpghttp://en.wikipedia.org/wiki/EDSAC_2http://en.wikipedia.org/wiki/University_of_Cambridge_Mathematical_Laboratoryhttp://en.wikipedia.org/wiki/University_of_Cambridge_Mathematical_Laboratoryhttp://en.wikipedia.org/wiki/IBM_Standard_Modular_Systemhttp://en.wikipedia.org/wiki/SIMDhttp://en.wikipedia.org/wiki/SIMDhttp://en.wikipedia.org/wiki/SWARhttp://en.wikipedia.org/wiki/Bit_slicinghttp://en.wikipedia.org/wiki/Intel_30008/8/2019 Final CA Project
26/37
Intel D3002.
Introduced 3rd Qtr, 1974 Members of the family
3001-Microcontrol Unit
3002-2-bit Arithmetic Logic Unit slice
3003-Look-ahead Carry Generator
3205-High-performance 1 Of 8 Binary Decoder 3207-Quad Bipolar-to-MOS Level Shifter and Driver
3208-Hex Sense Amp and Latch for MOS Memories
3210-TTL-to-MOS Level Shifter and High Voltage Clock Driver
3211-ECL-to-MOS Level Shifter and High Voltage Clock Driver
3212-Multimode Latch Buffer
3214-Interrupt Control Unit
3216-Parallel,Inverting Bi-Directional Bus Driver
3222-Refresh Controller for 4K NMOS DRAMs
3226-Parallel,Inverting Bi-Directional Bus Driver 3232-Address Multiplexer and Refresh Counter for 4K DRAMs
3235-Quad Bipolar-to-MOS Driver
3242-Address Multiplexer and Refresh Counter for 16K DRAMs
3245-Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K
3246-Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K
3404-High-performance 6-bit Latch
3408-Hex Sense Amp and Latch for MOS Memories
Intel 3002(Bit Slice)
Intel 3000 bit-slice processor family was introduced in 1973. The family includes
components that can be used to build microprocessors with data width in increments of
two, i.e. 2-bit, 4-bit, 6-bit microprocessors, and so on. One of the main components of the
3000 family is Intel 3002 Central Processing Element (CPE). The 3002 CPE is a 2-bit ALU
and register file that can perform logical and arithmetic operations, left/right shifting and
bit/zero value testing. The 3002 also includes 11 registers and an accumulator. Multiple
3002 CPE elements can be chained together to process 4-bit or wider data. The 3002 CPEelements do not fetch instructions from memory - it's a task of Intel 3001 Micro program
Controller Unit (MCU). The 3001 MCU can address up to 512 words of program memory,
and it provides a way to conditionally or unconditionally jump to some memory locations.
The 512-word memory is viewed by the 3001 element as 32 rows by 16 columns matrix.
The MCU can jump to row 0, to any column within current row, any row within current
column, or to any location within a subset of columns/rows, but not to any arbitrary location.
Other function of the 3001 chip is to control carry input/output logic of the array of CPE
elements.
The only second-source manufacturer of 3000 components was Sign tics. Czechoslovakiaand USSR cloned Intel 3002, 3001 and other chips from 3000 family.
26
http://docs.google.com/fileview?id=0ByX0R-KjYec7YmE1Y2MyZWYtYTE1Zi00ZWFmLTk0OWQtYmRmMTA5ZmRlMWEx&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7YjU0N2Y5YTYtOGY2Yi00NWM0LThmYjAtZmQzNzJhMDY3ZjU5&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7YzE1MzhlN2YtYTk0OS00ZTJkLWIwY2QtN2U5YjU2ZTcxZWY3&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MmE4NmExYzEtYmM5Mi00NGI4LWE0NDctN2NlNGM4ZmUyNTdh&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7NDZmMmRkNWQtYWQ4Ni00YWZmLWEwNmYtNGZiN2E1Zjg2MjFh&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7NGE5Y2M1ZjItMzY0MC00NzRlLTkwMTUtZDgzNzA1Y2RmMTgz&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MmRmOTEzMTQtZmM0Zi00ODZjLTkyZGMtYmM4OWRmOTU0OWVl&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7OGJhM2I1ZDgtYzYwNC00YTAwLTkxZjktOTBhOWUzOWJiN2Zl&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7NWE2NjI5ZjUtOGM3Yi00ZDhmLTgzNzYtN2JjMGZiMDIxMWNm&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7YmI2MTMzYTEtOWEyYi00MTg1LTkzYmUtN2I0NGIyZmU2ZGY2&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MWZjYmYzZjAtZGRhOS00NzY5LThjMDUtYTgwOGFkNWUyYzA2&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MDg0Yzk2MTQtZGU2OC00NzIwLTlkNzktZjc2NTIxNDI3OTk5&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MWZjYmYzZjAtZGRhOS00NzY5LThjMDUtYTgwOGFkNWUyYzA2&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7NjA1MjhjOWItNDdjMS00MTg0LWE5M2UtZjhiMjNkYTgzOTIy&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7YjcwMTQyNjctZWU5MS00MWZkLWE4MzItNmJhZTk2ZDg4ZDA0&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MWU5NjBhNDYtZmMxNy00NTZjLWI0YTMtYmJlZjUyYzQzZWU4&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MjE0NGQ2ZDItODE2MC00NTZiLTg5ODktNGY4OWFiYzg1OTBl&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MjJkYWYyNWUtNmQ2MS00ZWNkLWJiZDctODFhYjVkZjM2MDBm&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MGZmNTI2NWYtMTcyMi00MGEwLTgwMGYtMTMzYzY2Zjc5ZTg1&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7NGE5Y2M1ZjItMzY0MC00NzRlLTkwMTUtZDgzNzA1Y2RmMTgz&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7YmE1Y2MyZWYtYTE1Zi00ZWFmLTk0OWQtYmRmMTA5ZmRlMWEx&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7YjU0N2Y5YTYtOGY2Yi00NWM0LThmYjAtZmQzNzJhMDY3ZjU5&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7YzE1MzhlN2YtYTk0OS00ZTJkLWIwY2QtN2U5YjU2ZTcxZWY3&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MmE4NmExYzEtYmM5Mi00NGI4LWE0NDctN2NlNGM4ZmUyNTdh&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7NDZmMmRkNWQtYWQ4Ni00YWZmLWEwNmYtNGZiN2E1Zjg2MjFh&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7NGE5Y2M1ZjItMzY0MC00NzRlLTkwMTUtZDgzNzA1Y2RmMTgz&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MmRmOTEzMTQtZmM0Zi00ODZjLTkyZGMtYmM4OWRmOTU0OWVl&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7OGJhM2I1ZDgtYzYwNC00YTAwLTkxZjktOTBhOWUzOWJiN2Zl&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7NWE2NjI5ZjUtOGM3Yi00ZDhmLTgzNzYtN2JjMGZiMDIxMWNm&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7YmI2MTMzYTEtOWEyYi00MTg1LTkzYmUtN2I0NGIyZmU2ZGY2&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MWZjYmYzZjAtZGRhOS00NzY5LThjMDUtYTgwOGFkNWUyYzA2&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MDg0Yzk2MTQtZGU2OC00NzIwLTlkNzktZjc2NTIxNDI3OTk5&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MWZjYmYzZjAtZGRhOS00NzY5LThjMDUtYTgwOGFkNWUyYzA2&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7NjA1MjhjOWItNDdjMS00MTg0LWE5M2UtZjhiMjNkYTgzOTIy&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7YjcwMTQyNjctZWU5MS00MWZkLWE4MzItNmJhZTk2ZDg4ZDA0&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MWU5NjBhNDYtZmMxNy00NTZjLWI0YTMtYmJlZjUyYzQzZWU4&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MjE0NGQ2ZDItODE2MC00NTZiLTg5ODktNGY4OWFiYzg1OTBl&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MjJkYWYyNWUtNmQ2MS00ZWNkLWJiZDctODFhYjVkZjM2MDBm&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7MGZmNTI2NWYtMTcyMi00MGEwLTgwMGYtMTMzYzY2Zjc5ZTg1&hl=en_GBhttp://docs.google.com/fileview?id=0ByX0R-KjYec7NGE5Y2M1ZjItMzY0MC00NzRlLTkwMTUtZDgzNzA1Y2RmMTgz&hl=en_GB8/8/2019 Final CA Project
27/37
Intel 3002 microprocessor regarded as the prototype. Not be strictly Intel 3002 CPU chip
(CPU), because it is not built-in command, he is only a 2-bit slicer processor, real time to
computing, from the external storage hardware will be needed The instructions read in
3002, that the real core is used to perform some basic logic operations. Also, the market is
more popular 4-bit slicer, two arrived in the last 3002 to a 4-bit slicer, and the same as the
chip would require a number of times, so Intel 3002 is not a hot commodity. Of course,
bringing together more than 3002 satellites can handle more bits, for example, eight times
3002 can be combined to handle 16-bit [5].
The right side of this Intel 3002 is the rarest white ceramic C3002, but also ES
(Engineering Sample) version, which is published within the flow. March 2006, eBay had a
private collector above a box of his father's pressure Po total of 16 Intel C3002 ES
Nachulaimai together, and finally the total transaction price as high as US $ 4400.00
(approximately 130 000 combined NT), but are was bought with a buyer, but he refused to
sell to any one.
Bus Width 2-n bits data/address (depending on number of slices used)
3002-2-bit Arithmetic Logic Unit slice
General information
Type Bit Slice Processor
Frequency (MHz) ? 100 ns cycle time
Package 28-pin ceramic DIP
Introduction date 1973
Architecture / Micro architecture
Manufacturing process Schottky bipolar
Data width 2 bit
Electrical/Thermal parameters
V core (V) ? 5 5%Minimum/Maximum operating temperature
(C) ?
0 70
Typical/Maximum power dissipation (W) 0.73 / 1
Intel 3002 Engineering Sample (C3002 ES) is against
Intel 3002 (D3002) is counter-
27
http://docs.google.com/fileview?id=0ByX0R-KjYec7YjU0N2Y5YTYtOGY2Yi00NWM0LThmYjAtZmQzNzJhMDY3ZjU5&hl=en_GBhttp://www.cpu-world.com/CPUs/BSP.htmlhttp://www.cpu-world.com/Glossary/C/CPU_Frequency.htmlhttp://www.cpu-world.com/Glossary/C/CPU_Frequency.ht