Fifo Buffers

8/11/2019 Fifo Buffers

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Working of a FIFO ??

> FIFO is used for high throughput asynchronous data transfer.

> When youre sending data from one domain to another domain and if high performance is required,you can not just get away with simpe synchroni!er" #etafop $.

> %s you cant afford to oose cock cyces"In synchroni!er you merey wait for additiona cock cycesunti you guarantee metasta&iity free operation$, you come up with storageeement and reasona&y compe' handshaking scheme for contro signas to faciitate the transfer.

> %n %synchronous FIFO has two interfaces, one for writing the data into the FIFO and the other forreading the data out of FIFO. It has two cocks, one for writing and the other for reading.

> (ock % writes the data in the FIFO and (ock ( reads out the data from it. )o faciitate error freeoperations, we ha*e FIFO fu and FIFO empty signas. )hese signas are generated with respect to thecorresponding cock.

> +eep in mind that, &ecause contro signas are generated in their corresponding domains and suchdomains are asynchronous to each other, these contro signas ha*e to &e synchroni!ed through thesynchroni!er

> FIFO fu signa is used &y &ock % "when FIFO is fu, we don-t want &ock % to write data intoFIFO, this data wi &e ost$, so it wi &e dri*en &y the write cock.

> imiary, FIFO empty wi &e dri*en &y the read cock. /ere read cock means &ock ( cock andwrite cock means &ock % cock

> %synchronous FIFO is used at paces when the performance matters more, when one does not wantto waste cock cyces in handshake and more resources are a*aia&e.


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FIFO memory &uffers 000000000000000

/ow it works?00 )here are two cocks in*o*ed, a aunch cock during which the data is stored in the FIFO just ikewrite cock, and a capture cock where the data is read from the FIFO ike read cock.

00 In a circuar FIFO concept, the memory address of the incoming data is in the write pointer. )headdress of the first data word in the FIFO that is to &e read out is in the read pointer. %fter reset, &othpointers indicate the same memory ocation. %fter each write operation, the write pointer is set to thene't memory ocation. )he reading of a data word sets the read pointer to the ne't data word that is to&e read out. )he read pointer constanty foows the write pointer. When the read pointer reaches thewrite pointer, the FIFO is 1#2)3. If the write pointer catches up with the read pointer, the FIFO isF455

FIFO memory &uffers 0000000000000000000FIFO 5imitations600 FIFO is not of much use if aunch cock is faster than capture cock, and if a*erage data rate isgreater than capture rate, &ecause after a whie, the FIFO woud &ecome F455.

/ow to decide of FIFO &uffer i!e?

00 FIFO depth is decided as 6"data &ytes "&urst$ written in write cock$ 0 "data &ytes read in read cock in the time taken to write the&urst$.


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1'ampe6 uppose 788 &ytes &urst is to &e written at 988 #/:, 9 &yte per write cock. and ;ead cockis


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%s per standard the e*ent queue is ogicay segmented into four different regions.> For sake of simpicity were showing the three main e*ent queues.> )he DInacti*eE e*ent queue has &een omitted as 8 deay e*ents that it deas with is not arecommended guideine.

0> G%cti*e e*ent queue 6

> %ccording to the I111 Heriog spec, e*ents can &e schedued to any of the e*ent queues, &ut e*entscan &e remo*ed ony from the Dacti*eE e*ent queue. %s shown in the image, the Gacti*e e*ent queuehods &ocking assignments, continuous assignments. primiti*e IO updates and write commands.

> Within Dacti*eE queue a e*ents ha*e same priority, which is why they can get e'ecuted in any orderand is the source of nondeterminism in Heriog.

0> C(% ;egion "Con0&ocking assignment$ 6

> )here is a separate queue for the 5/ update for the non&ocking assignments. %s you can see that5/ updates queue is taken up after Dacti*eE e*ents ha*e &een e'hausted, &ut 5/ updates for thenon&ocking assignments coud re0trigger acti*e e*ents.

0> 2ostpone region 6


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>5asty once the ooping through the Dacti*eE and non &ocking 5/ update queue has setted downand finished, the DpostponedE queue is taken up where stro&e and monitor commands are e'ecuted,again without any particuar preference of order.

%t the end simuation time is incremented and whoe cyce repeats.


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Jated cocks 6Kock signas that are passed through some gate other than &uffer and in*erters are caed gated cocks.)hese cock signas wi &e under the contro of gated ogic. Kock gating is used to turn off cock tosome sections of design to sa*e power. Kick here to read more a&out cock gating.

Jenerated cocks 6

Jenerated cocks are the cocks that are generated from other cocks &y a circuit within the design suchas di*idermutipier circuit.

generated cock 6GKock is the master cock and new cock is generated from F9L output. #aster cock is defined withthe constraint GcreateMcok. 4ness and unti new generated cock is defined as Ggenerated cocktiming anaysis toos wont consider it as generated cock. /ence to accompish this requirement useDcreateMgeneratedMcockE command. GK5+ pin of F9 is now treated as cock definition point for thenew generated cock. /ence cock path deay ti F9K5+ contri&utes source atency whereas deayfrom F9K5+ contri&utes network atency.

kew 6kew is the difference in arri*a of cock at two consecuti*e pins of a sequentia eement is caed skew.

Kock skew is the *ariation at arri*a time of cock at destination points in the cock network. )hedifference in the arri*a of cock signa at the cock pin of different fops.

)wo types of skews are defined6 5oca skew and Jo&a skew.

5oca skew 65oca skew is the difference in the arri*a of cock signa at the cock pin of reated fops.

Jo&a skew 6


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Jo&a skew is the difference in the arri*a of cock signa at the cock pin of non reated fops. )hisaso defined as the difference &etween shortest cock path deay and ongest cock path deay reachingtwo sequentia eements

)iming 2ath 6)iming path is defined as the path &etween start point and end point where start point and end point is

defined as foows6

tart 2oint6% input ports or cock pins of a sequentia eement are considered as *aid start point.

1nd 2oint6% output port or @ pin of sequentia eement is considered as 1nd point.

>For tatic )iming %naysis ")%$ design is spit into different timing path and each timing path deayis cacuated &ased on gate deays and net deays.

>In timing path data gets aunched and tra*erses through com&inationa eements and stops when itencounter a sequentia eement. In any timing path, in genera "there are e'ceptions$B deayrequirements shoud &e satisfied within a cock cyce.

>In a timing path wherein start point is sequentia eement and end point is sequentia eement, if thesetwo sequentia eements are triggered &y two different cocks"i.e. asynchronous$ then a common eastcommon mutipe "5K#$ of these two different cock periods shoud &e considered to find the aunchedge and capture edge for setup and hod timing anaysis.

@ifferent )iming 2aths%ny synchronous design is spit into *arious timing paths and each timing path is *erified for its timingrequirements. In genera four types of timing paths can &e identified in a synchronous design.

)hey are6N Input to ;egisterN Input to OutputN ;egister to ;egisterN ;egister to Output

tatic power Hs @ynamic 2ower 6

tatic power is power dissipation for dc suppy ony. to cacuate is just using the equation 2=IH "I=I@@L ,H=H@@ $

using dc operating point anaysis you coud o&tain those *aue.

@ynamic power dissipation has many cases, such as charging and discharging capacitors, o*erturn ofin*erter and atch.

tatic power 6 when the transistors in OFF state@ynamic 6 when the transistors in OC state


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%synchronous ;eset 60

0Co fitering of reset ine is a*aia&e for inputs coming directy from. e'terna reset pins. % soution ispossi&e howe*er. ee &eow.

0;eset synchroni!ation circuit is required on %IKs with asynchronous reset0Kircuit shown wi pro*ide asynchronous reset and synchronous deassertion.

0)hese fip0fops must &e kept out of the @F) scan chain.

#1)%)%(I5I)3 60


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Whene*er a signa changes too cose to the cock edge it is &eing samped on, the captured *aue isnon0deterministic due to setuphod *ioations. )his phenomenon is caed #etasta&iity and withoutproper pre*ention and *erification, metasta&iity propagation coud cause serious design errors. Forsynchronous designs, this is not a major issue as tatic )iming %naysis ")%$ toos can fag theseissues with setuphod checks.

/owe*er, metasta&iity is an una*oida&e issue for signas crossing asynchronous cock domains ascock domain crossings are not timed &y )% toos. @ue to the asynchronous nature of the transmit andrecei*e cocks, it is possi&e that the transmit data might change within the setup and hod window ofthe recei*e cock, hence resuting in an unpredicta&e *aue and deay at the output of the fop.

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Fifo Buffers

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