Field Effect Transistor (FET)

1

Field Effect Transistor (FET)

2

Introduction

Field Effect Transistor (FET)

Junction Field Effect Transistor (JFET)

Metal Oxide Semiconductor FET

(MOSFET)

Depletion TypeMOSFET

Enhancement TypeMOSFET

3

Junction Field Effect Transistor (JFET) n-channel JFET p-channel JFET

4

JFET Introduction

• JFET is always operated with the gate source p-n junction reversed biased.

5

JFET IntroductionChannel width and thus the channel resistance can be

controlled by varying the gate voltage.

JFET biased for construction Greater VGG narrows the channel

Less VGG widens the channel Water analogy for the JFET control

6

JFET Characteristics and Parameters

• For VGS = 0 v, the value of VDS at which ID becomes essentially constant is the pinch-off voltage (Vp) and is denoted as IDSS.

• Breakdown occurs at point C when ID begins to increase very rapidly with any further increase in VDS .

7

VGS controls ID.

The value of VGS that makes ID approximately zero is the cutoff voltage VGS(off). The JFET must operate between VGS = 0 and VGS(off) .

8

Transfer Characteristics • William Bradford Shockley derived a relationship

between ID and VGS which is known as Shockley’s equation and is given by

• The above equation suggests that when VGS = 0, ID = IDSS. When VGS = Vp, ID = 0

2

p

GSDSSD V

V1II

9

Transfer curve from the drain characteristics

10

ExampleThe following parameters are obtained from a certain

JFET datasheet: VP = -8 v and IDSS = 5 mA. Determine the values of ID for each value of VGS ranging from 0 v to -8 v in 1 v steps. Plot the transfer characteristic curve from these data.

Solution:2

p

GSDSSD V

V1II

mA5801mA5I

2

D

mA83.3811mA5I

2

D

11

mA81.2821mA5I

2

D

mA95.1831mA5I

2

D

mA25.1841mA5I

2

D

mA703.0851mA5I

2

D

mA313.0861mA5I

2

D

mA078.0871mA5I

2

D

mA0881mA5I

2

D

12

-8 -7 -6 -5 -4 -3 -2 -1 00

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5 x 10-3

VGS

ID

13

FET Biasing• The following relations can be applied to the dc

analysis of most of the FET amplifiers:A0IG

SD II 2

p

GSDSSD V

V1II

14

JFET Biasing: Fixed Bias Circuit

15

JFET Biasing: Fixed Bias Circuit0IG

0RIV GGRG

Circuit for dc analysis

16

Fixed Bias CircuitGS Loop:• Apply KVL

GGGS VV

• Apply the Shockley’s Equation:2

p

GSDSSD V

V1II

• Plot Shockley’s equation:

17

Fixed Bias Circuit• Q-Point:

18

Fixed Bias Circuit• DS Loop

DSDDDD VRIV

DDDDDS RIVV

Also note that0VS

0VVVV DSDDS

DSD VV

In addition0VVVV GSGGS

GSG VV

19

Example: Determine the following for the given Fig.(a) VGSQ (b) IDQ (c) VDS (d) VD (e) VG (f) VS.Solution:(a) VGSQ = -VGG = -2 V

mA625.5821mA10

VV1II

22

P

GSDSSDQ

(b)

(c) V75.4RIVV DDDDDS

(d) VD = VDS = 4.75 V

(e) VG = VGS = -2 V(f) VS = 0 V

20

JFET Biasing: Self Bias Configuration

21

Self Bias Circuit: DC Analysis

Self-bias Circuit for dc analysis

22

JFET Self Bias CircuitIG = 0IS = ID From GS Loop: -VGS = VRS

or VGS = -ISRS

Substituting IS = ID

VGS = -IDRS.

23

JFET Self Bias CircuitShockley Equation:

2

p

SDDSS

2

p

GSDSSD V

RI1IVV1II

2

p

SDDSSD V

RI1II

24

JFET Self Bias Circuit: Q-Point

Self-Bias Line:Since VGS = -IDRS .If ID = 0 then VGS = 0and ID = IDDS/2 (say), then VGS = -IDDS RS /2Superimposing this straight

line on the transfer curve, we get Q-point as shown in the Fig.

Self Bias line

Transfer Curve(Shockley equation)

25

JFET Self Bias CircuitDS Loop: Using KVL

Substituting IS = ID,

or

In addition

SSDSDDDD RIVRIV

SDDSDDDD RIVRIV

DSDDDDS RRIVV

SDS RIV

0VG

DRDDSDSD VVVVV

26

JFET Self Bias Circuit: Example 1Determine the following: VGSQ , IDQ, VDS, VS, VG, and VD.Solution:Step 1: Draw the self bias line: VGS = - IDRS , When ID = 0, VGS = 0.Choosing ID = 4 mA, VGS = -4mA×1 k = -4 vThe line is drawn below:

27VGS (volts)

JFET Self Bias Circuit: Example 1Step 2: Plot the Shockley equation: (IDSS = 8mA, VP = -6v)

2

p

GSDSSD V

V1II

VGS0 -1 -3 -4 -5 -6

ID (mA) 8 5.55 2 0.88 0.22 0

I D (m

A)

-6 -5 -4 -3 -2 -1 00

1

2

3

4

5

6

7

8

28

JFET Self Bias Circuit: Example 1Step 3: Show the Shockley curve and the self bias line on the same

graph paper

From the graph, VGSQ = -2.6 v, IDQ = 2.6 mA

-6 -5 -4 -3 -2 -1 00

1

2

3

4

5

6

7

8

I D (m

A)

VGS (volts)

Self bias line

Shockley Curve

Q-Point

29

JFET Self Bias Circuit: Example 1Step 4: Find the remaining quantities: VDS = VDD – ID(RS + RD ) = 20 – 2.6mA( 1 k + 3.3 k) = 8.82 v

VS = IDRS = (2.6mA)(1k) = 2.6 vVG = 0 vVD = VDS + VS = 8.82 + 2.6 = 11.42 v

(or VD = VDD – IDRD = 11.42 v)

30

JFET Biasing: Voltage Divider Circuit

31

JFET Biasing: Voltage Divider Circuit dc analysis

VG

21

DD2G RR

VRV

Applying KVL, 0VVV RSGSG

orRSGSG VVV

But VRS = ISRS = IDRS

Therefore

SDGSG RIVV

S

GSGD R

VVI

32

Voltage Divider Circuit: Q-Point

Bias Line:(i) When ID = 0VGS = VG – IDRS = VG – (0)(RS)VGS = VG

(ii) When VGS = 0

S

G

S

GSGD R

0VRVVI

S

GD R

VI

Plot this line along with the Shockley Curve, as shown in the Figure.

33

JFET Biasing: Voltage Divider Circuit dc analysis

VG

0RIVRIV sSDSDDDD

sSDDDDDS RIRIVV

)RR(IVV SDDDDDS

DDDDD RIVV

SDS RIV

21

DD2R1R RR

VII

From DS Loop:

34

Voltage Divider Circuit: Example

Determine the following:(a) IDQ and VGSQ.(b) VD

(c) VS

(d) VDS

(e) VDG.

35

Voltage Divider Circuit: Example 1

Solution: IDSS = 8 mA, Vp = -4 v. Shockley Equation:

Bias Line:

2GS3

2

p

GSDSSD 4

V1108VV1II

VGS -4 -2 -1 0ID mA 0 2 4.5 8

v82.110270101.2

1610270RR

VRV 36

3

21

DD2G

)105.1(I82.1

RIVV3

D

SDGGS

When ID = 0, VGS = 1.82 v For VGS = 0, ID = 1.82/1.5k = 1.21 mA

36

From the Figure, IDQ = 2.4 mA, VGSQ = -1.8 v

(b) VD = VDD - IDRD = 16 – (2.4mA)(2.4k) = 10.24 v(c) VS = IDRS = 16 – (2.4mA)(2.4k) = 10.24 v

(d) VDS = V DD – ID(RD + RS ) = 16 – (2.4mA)(2.4k + 1.5k) = 6.64 v

(e) VDG = VD - VG = 10.24 – 1.82 = 8.42 v

37

Voltage Divider Circuit: Example 2For the given network, Detrmine(a) VG.(b) IDQ and VGSQ.(c) VD and VS.(d) VDSQ .Solution:(a)

(b) IDSS = 10mA, Vp = -3.5 v

v16.2k110k910

20k910RR

VRV21

DD1G

2GS3

2

p

GSDSSD 4

V11010VV1II

38

VGS (volts) -3.5 -2 -1 0ID (mA) 0 1.8 5.1 10

Bias Line: VGS = VG – IDRS = 2.16 – ID(1.1k)When ID = 0, VGS = 2.6 vWhen VGS = 0, I = 2.16/1.1k = 2mAFrom the graph, we see thatIDQ = 3.3 mA, VGSQ = -1.5 v(c) VD = VDD – IDQRD = 20 - (3.3mA)(2.2k) = 12.74 v VS = IDRS = 3.63 v(d) VDSQ = VDD – IDQ(RD +RS ) = 9.11 v

39

Metal-Oxide -Semiconductor Field Effect Transistor (MOSFET)

MOSFET

Depletion –Type MOSFET

Enhancement-Type MOSFET

40

N- Channel Depletion-Type MOSFET

Construction of D-MOSFET(n-Channel)

• The foundation of this type of FET is the substrate (p-type material).

• The source and drain terminals are connected through metallic contacts to n doped regions linked by an n channel.

• The gate is also connected to a metal contact surface but remains insulated from the n-channel by a SiO2 layer.

41

Basic Operation and Charactersitics of N – Channel D-MOSFET

I D= I S= IDSS

VGS = 0

• When VGS = 0 and VDS is applied, the drain current ID = IDSS flows through the circuit due to the free electrons of the n-channel.

42

Basic Operation and Characterstics of N-Channel D-MOSFET

• When VGS < 0, recombination between electrons and holes occurs. The more negative the bias, the higher the rate of combination. The resulting level of ID is reduced and becomes zero at pinch-off voltage. Electrons repelled by

negative Potential at gate.

43

Basic Operation and Charactersitics of D-MOSFET

When VGS > 0, the gate will draw additional electrons from the p-substrate due to the reverse leakage current and the drain current increases at a rapid rate.

44

Example: Sketch the transfer characteristics for an n-channel depletion type MOSFET with IDSS = 10 mA and Vp = -4 v.

Solution: 2

GS3

2

p

GSDSSD 4

V11010VV1II

VGS -4 -2 -1 0 +1ID (mA) 0 2.5 5.6 10 15.6

The curve is plotted on the next slide.

45

Gate Source Voltage

Drai

n Cu

rren

t (A)

-4 -3 -2 -1 0 10

0.005

0.01

0.015

0.02

46

P-Channel depletion type MOSFET

47

Symbols

N-Channel P-Channel

48

Example1: For the n-channel depletion type MOSFET of the Fig., determine

(a) IDQ and VGSQ.(b) VDS.Solution: Shockley Equation:

18 v

2GS3

2

p

GSDSSD

3V1106

VV1II

VGS -3 -2 -1 0 1

ID (mA) 0 0.7 2.7 6 10.7

49

Bias Line:

v5.1M100M1018M10

RRVRV

21

DD2G

)750(I5.1RIVV DSDGGS

When ID = 0, VGS = 1.5,

When VGS = 0, ID = VG/RS = 1.5/750 = 2 mA

From the graph, IDQ = 3.1 mA, VGSQ = -0.8 v

VDS = VDD – ID(RD + RS) = 10.1 v

50

Example2: Determine the following for the given network. (a) IDQ and VGSQ (b) VD.

Solution:(a) Shockley Equation:

2GS3

2

p

GSDSSD

8V1108

VV1II

VGS -8 -6 -5 -4 -2 0 1 2ID(mA) 0 0.5 1.125 2.00 4.5 8.00 10.125 12.5

51

Bias Line:VGS = -IDRS. When VGS = 0, ID = 0.When ID = 2.5 mA (say)VGS = -2.510-3 2.4 1000 = -6V

-8 -6 -2 0 2-4.30

4

6

8

10

12

14

1.7

I D (m

A)

VGS (volts)

From the graph paperVGSQ = 4.3 V, ID = 1.7mA(b) VD = VDD – ID RD = 20 – (1.7mA)(6.2k) = 9.46 V

ShockleyEquation

Bias LineQ-Point

52

Example 3: For the following network, determine (a) IDQ and VGSQ (b) VDS and VS.

Solution: Shockley Equation:

2GS3

2

p

GSDSSD

8V1108

VV1II

VGS -8 -6 -5 -4 -2 0 1 2ID(mA) 0 0.5 1.125 2.00 4.5 8.00 10.125 12.5

53

Bias Line:VGS = -VSS – IDRS.When ID = 0VGS = -(-4) = 4 VWhen VGS = 0ID = -VSS/RS = 4/0.39k = 10.26 mA(a) From the graphVGSQ 0.5 V, IDQ 9mA(b) VDS = VDD – IDQ(RD + RS) = 7.69 V VS = -VGSQ = -0.5V

-8 -6 -4 -2 2 4 60.50

2

4

6

8

12

14

109

10

I D (m

A)

VGS (volts)Sh

ockley

Equati

on

Bias

Line

Q-Point

54

N-Channel Enhancement Type MOSFETThe construction of an

enhancement type MOSFET is quite similar to that of the depletion type MOSFET except for the absence of a channel between the drain and source terminals.

When VGS = 0, ID = 0 because the n-channel is absent.

55

Basic Operation and Characteristics of an n-Channel E-MOSFET

When VGS > 0 & VDS > 0,A depletion region is creatednear the SiO2 layer void ofholes.As VGS increases, theconcentration of electronsnear the SiO2 increases and there is some flow between drain and source.The level of VGS that results in thesignificant increase in ID iscalled the Threshold Voltage (VT).

56

Basic Operation and Characteristics of an n-Channel E-MOSFET

If VGS > VT is constant and VDS is increased, ID will Increase and will reach saturation.

57

Drain Characteristics of an n-channel enhancement-type MOSFET

58

Transfer characteristics for n-channel enhancement type MOSFET from the drain characteristics.

2TGSD VVkI where 2)Th(GS)on(GS

)on(D

VVI

k

59

p-Channel enhancement-type MOSFET

60

Symbols

61

Feedback Biasing of n-Channel e-MOSFET

Equations:GSDS VV DDDDGS RIVV

From the above equations, we get 0IDDGS D

VV 0VD

DDD GSR

VI

62

Feedback Biasing of n-Channel e-MOSFET

63

Example: Determine IDQ and VDSQ for the enhancement-type MOSFET of the following.

Solution: For the transfer curve

3

2

2)TH(GS)on(GS

)on(D

1024.0)38(

mA6

VVI

k

2TGSD VVkI

VGS 3 6 8 10ID 0 2.16mA 6 11.76mA

64

For the network bias line:

For ID = 0, VGS = VDD = 12 v, and for VGS = 0ID = VDD /ID = 12 v / 2k = 6 mAFrom the graphVGSQ = 6.4 vIDQ = 2.75 mA

DDDDGS RIVV

65

Voltage Divider Bias

21

DD2G RR

VRV

Applying KVL around the indicated loop:0VVV RSGSG

orRSGGS VVV

sDGGS RIVV

For the output section:

SDDDSSDDSDD

RDSRDD

RRIVRIVRI

VVVVSD

)RR(IVV SDDDDDS

66

Example: Determine IDQ and VDSQ for the given enhancement type MOSFET.

Solution: Network:

v18M)1822(40M18

RRVRV

21

DD2G

DSDGGS Ik82.018RIVV

When VGS = 0, mA95.21k82.0

18ID

When ID = 0, VGS = 18 v

67

Device:

23

22)TH(GS)on(GS

)on(D v/A1012.0510

mA3VV

Ik

2GS32

)TH(GSGSD 5V1012.0VVkI

VGS 5 10 15 20ID

(mA)0 0.48 12 27

From the graphVGSQ = 12.5 vIDQ = 6.7 mA

v4.14RRIVV DSDDDDS

68

Combination NetworksExample1: Determine the levels of VD and VC for the

given network:Solution:

v62.3k24k8216k24

RRVRV

21

CC2B

v92.27.062.3VVV BEBE

mA825.1k6.192.2

RV

RV

IE

E

E

RE

E

mA825.1II EC

CSD III

v07.11)k7.2)(mA825.1(16)k7.2(I16V DD

69

2

p

GSQDSSDQ V

V1II

Plot the following equation

From the plot, VGSQ = -3.7 v

NowVC = VB – VGSQ = 3.62 – (-3.7) = 7.32 v

70

Example 2: Determine VD for the given network.Solution:From the JFET:VGS = -IDRS = -ID(2.4k)From this equation, the selfBias line is plotted as shown Below.

71

The resulting Q_point is at:VGSQ = -2.6 V, IDQ = 1mA

For the BJT:IE IC = ID = 1mAIB = IC/ = 1mA/80 = 12.5AVB = VCC – IBRB = 16 – 12.5A470k = 10.125 VVE = VD = VB – VBE = 10.125 – 0.7 = 9.425 V

72

Example 3: For the network of Fig. (a), determine:VG , VGSQ, IDQ, IE, IB, VD and VC.Solution:VG = 3.3 VVGSQ = -1.25 VIDQ = 3.75 mAIE = 3.75 mAIB = 23.44AVD = 11.56 VVC = 15.88 V

Fig. (a)