Ferroelektrische Schichten und Heterostrukturen: Deposition, Anwendung und „Interface Engineering“* H. Kohlstedt Forschungszentrum Jülich, Institut für Festkörperforschung, IFF Forschungszentrum Forschungszentrum Jülich *pdf file of this talk: [email protected]
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Ferroelektrische Schichten und Heterostrukturen: Depp, g ......Millipede –Scanning Probe Memory Organic FeFETOrganic FeFET Millipede with Ferroelectrics I Photo detector x,y,z Deformation
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Ferroelektrische Schichten und Heterostrukturen: Deposition, Anwendung und „Interface Engineering“*p , g „ g g
H. Kohlstedt
Forschungszentrum Jülich, Institut für Festkörperforschung, IFF
Forschungszentrum Forschungszentrum Jülich *pdf file of this talk: [email protected]
Ferroelectric Materials
(PVDF)PbZrxTi1-xO3 (PVDF)BaTiO3
Polyvinylidene fluoride: [C2H2F2] nBa or Pb
FC+PTi
H
H+P -P
O
CH
-Pc
F
Effects related to Ferroelectric Materials
Piezo electric effect Polarization switch
+/-PF P
P VE
Pyro electric effectC i l t i ff t Pyro electric effect
ΔT
ΔIConverse piezo electric effect
S
P AΔTPL = L ± ΔL
S
E
Technological applicationsFerroelectric RAM’sFerroelectric RAM s Smart cards Portable electronic devices
Ferroelectric
PiezoelectricPiezoelectric
PyroelectricPyroelectric
SAW devices for mobileThermal IR pyroelectric detectors
SAW devices for mobile technology and gas sensing
Ferroelectric Random Access MemoryFerroelectric Random Access MemoryFeRAM
BasicsNanoscale Characterization of Ferroelectric Materials, M. Alexe and A. GruvermanNanoscience and Technology, Spinger-Verlag 2004
Ferroelectric Memories, J. F. Scott, Springer Series in Advanced Microelectronics, (Springer-Verlag Berlin Heidelberg New York 2000)
gy, p g g
Ferroelectric Random Access Memories: H. Ishiwara, M. Okuyama, eds., Topics in Applied Physics, Vol. 93 (Springer-Verlag, Berlin Heidelberg 2004).
(Springer-Verlag, Berlin Heidelberg, New York 2000).
Nanoscale Phenomena in Ferroelectric Thin Films, S. Hong, Kluwer Academic Pub. 2004
Matrix Architecture: Random Access Memory
1T1C ll
DRAM: Dynamic Random Access Memory
Bit line decoder
1T1C cell
TBit line decoder
Sense amplifier
tro
lc
Data
C
ne
de
co
de
r
co
nt
log
ic
Address
C
Wo
rdli
n
DRAM Cell
Word line
Bit line1T1C cell
Word line
TransistorTransistor
DRAM it
Sense Amplifier
DRAM capacitor“1” charged Cap.“0” non charged Cap.CBL
Cmin ≅ 30 fF
Linear dielectric:SiO2, Si3N4, HfO2, etc.
Ferroelectric Capacitor
Electrode
Ferroelectric V∼
ElectrodeElectrode
FeRAM Cell
Word line
Bit line1T1C cell
Word line
TransistorTransistorSense Amplifier
CBLFerroelectric Capacitor
Hysteretic dielectric:PZT, SBT etc.
Ferroelectric Hysteresis
“1”Pr
PbZr Ti O
Metal
P
1
zatio
n Curr
PbZrxTi1-xO3
Metal
P
E“0”
Pola
ri
rent
Electric Field or Voltage
Ec0
Electric Field or VoltagePr = 10 – 80 µC/cm2
Ec = 50 – 300 kV/cm
Thin Film Capacitor: t = 100 nm
VC = 0.5 V - 2 V
Ferroeletric Random Access Memory (FeRAM) Principle
cm2 )P “1”
0 5
1.0 switching
nsity
(kA
/c1
0.0
0.5non-switching
urre
nt d
en
Vc
V
“0”0 10 20 30
C
Time (ns)Vbias
0
Different remanent polarization states
diff t t i t t b h i t li d lt⇒ different transient current behavior to an applied voltage pulse
Integrating the current ⇒ switched charge QS and non-switched charge QNS (distinction between the two logic states)
Uniformity of an ALD grown amorphous PZT film in a 3D trench structure T. Watanabe, S. Hoffmann-Eifert, et al., J. Electrochem. Society 154, G262 (2007)
200
250
5
6Pb
Ti (-
)
Diameter: 180 nmLS1LS1
LS3
100
150
2
3
4
nsity
(Cou
nt)
TiZr
ity ra
tio, P
b/T
0 50 100 150 200 250 3000
50
0
1
2
Inte
n
Inte
ns
LS2 0 50 100 150 200 250 300Distance (nm)
200
250
5
6
Pb -) 200
250
5
6Pb
-)LS2 LS3
40 nmLS2
100
150
200
3
4
5
ity (C
ount
)
TiZr ra
tio, P
b/Ti
(-
100
150
200
3
4
5
ity (C
ount
)Ti
Zr ratio
, Pb/
Ti (-LS2 LS3
0
50
100
0
1
2
Inte
ns
Zr
Inte
nsity
0
50
100
0
1
2
Inte
nsi
Inte
nsity
0 50 1000 0
Distance (nm)0 50 100 150 200
0 0
Distance (nm)
3D technology indeed possible with homogenous PZT composition!
Vertical Capacitor Concept
2D planar Toshiba/Infineon
Hysteresis
Electrodes separated
F l t iFerroelectric material
New concept has potential for high density applications/small cell sizes:
H. Ishiwara “Current Satus of Ferroelectric Random –Access MemoryMRS Bulletin, 29, No.1, 823 (2004).and Int. Techn. Roadmap for Semic. Ed. ITRS, San Jose 2003p ,
For standard FeRAMs
2007: 512 Mb2010: 1Gb2015: 10 Gb
Summary for FeRAMs II
Example: Texas Instrument for 64 Mbit mobile Applications:
Future: 3D 1T-1C Cells in Productions with 20 nm thin PZT!
If this obstacle will be overcome ULSI FeRAM chips are visiblepVery competitive with other Non-volatile RAMs
Ferroelectric Field Effect Transistor
FeFET
Ferroelectric Field Effect Transistor
GateP
D iCh lSource DrainChannel
Si
FeFET: Readout
FeFETFloating gate Transistor
FlashLogic Device
n-MOSFETNon-volatile Memory Device
DSG
Pn+ n+
Ferroelectric gate oxideG t id
p SiB
Channel
Ferroelectric gate oxideFloating gate
e- in the floating gateshift the threshold
Gate oxide
polarizationshifts the threshold
Ids
IIon
Read Voltage
VTH“0” “1”
Ioff
Memory Window
Write Voltage“1”
“0”
VGB
Stacked FeRAM Cell vs. FeFET
Stacked cell FeFETFe
Bit LineDrive Line
P
PZT
Si
PZT
W
WordLine • Ferroelectric in direct contact with Si
Fe-Si interface
• Capacitor and transistor
Fe Si interfaceA single device
• Capacitor and transistor separated by appr. 100 nm
• Diffusion barriers
!
Two individual devices
The History of FeFETs
F FET P t t (1957 1973)
• 1st FeFET Publication (1963) TGS on CdS (J. L. Moll)
• FeFET Patents (1957, 1973)
• 1st FeFET Publication on Si (1974) BixTiyO3 (S. Wu)
• MFMIS with a retention time >106 s reported BLT (2003)
• FeFET still elusive (2002) (T. P. Ma)
• MFMIS with a retention time >10 s reported BLT (2003)
No products with FeFETs up to now!
Where are the show stoppers?
p p
Where are the show stoppers?
Short Rentention Times
Reason(s) not yet clear!
30-day-long Retention in an FeFET
Si-HfO2-SBT Gate Stack
K. Takahashi et al.,Abs. Int. Conf. Solid State Devices and Materials,,Tokyo. Paper D1-2 (2004).
Si- Fe Interface
PLD: Pulse Laser Deposition
Interdiffusion:
aus: T. Yamaguchi et al.: Jpn. J. Appl. Phys. Vol. 39, 2058 (2000).
Summary for FeFET
• FeFET are still in the research State• Performance improvement from Year to Year (small Steps)• Performance improvement from Year to Year (small Steps)• FeFETs in production not visible for the next five years
Uncon entional approaches are ell come!Unconventional approaches are well come!Separate ferroelectricity from source-drain channel
GateStray Field
For example:
Strain Effect of Fe Transfer to Channel,Change of Carrier Mobility
H. Shin in:Nanoscale Phenomena in Ferroelectric Thin Films, S. Hong, Kluwer Academic Pub. 2004
Entire Organic-FeFET
R S h d L M j ki d MR. Schroeder, L. Majewski, and M. Grell, Adv. Mat. 16 (2004) 633.
Ronal C G Naber et alRonal C.G. Naber et al., Nature Materials, February 2005
University of Groningen and Philips Research
Flexible substrates, cheap but slow
Need for New Non-volatile Memory Technology
Needs:– Low power (low voltage)– Fast write/read times– Near infinite number of write/read cycles– Compatible with Si logic processp g p– Minimum added process cost– Small cell size (for high density applications)
Limitations of Flash / EEPROM Technologies:– Slow write, large added process cost, large voltages
Possible Technologies:– Ferroelectric RAM – Ferroelectric FET
Nice overview:MRS Bulletin 29, November 2004Emerging Solid-State Memory TechnologiesFerroelectric FET