FEI4 CLKGEN Andre Kruth FE-I4 CLKGEN Jan. 25 th 2010
FEI4 CLKGEN
Feb 02, 2016
FEI4 CLKGEN. Andre Kruth FE-I4 CLKGEN Jan. 25 th 2010. Test Bench. CLKGEN TOP. Layout FEI4 CLKGEN. SimRes nom PEX C+CC. 80MHz single-ended CLK. 320MHz single-ended CLK. VSS current. SimRes nom PEX C+CC. Acquiring 320MHz. Acquiring 80MHz. SimRes slow PEX C+CC. 80MHz single-ended. - PowerPoint PPT Presentation
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FEI4 CLKGEN
Andre Kruth
FE-I4 CLKGEN Jan. 25th 2010
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 2
Test Bench
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 3
CLKGEN TOP
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 4
Layout FEI4 CLKGEN
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 5
SimRes nom PEX C+CC
VSS current
320MHz single-ended CLK
80MHz single-ended CLK
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 6
SimRes nom PEX C+CC
Acquiring 320MHz Acquiring 80MHz
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 7
SimRes slow PEX C+CC
VSS current
320MHz single-ended
80MHz single-ended
80MHz320MHz
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 8
SimRes fast PEX C+CC
VSS current
320MHz single-ended
80MHz single-ended
80MHz320MHz
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 9
Locking to 25ns +/- 0.5ns Reference CLK
320MHz mean 80MHz mean
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 10
Additionally
• … I checked that Adber‘s biasing gives me the biasing currents I need.
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 11
Thanks for your attention!
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 12
BACKUP
- Pixels/FE: 336x80, 50×250 μm²- Compatibility 3D, diamond, planar sensors- L1T max latency: 3.2 μs- Compatible with Serial Powering / DC-DC- Power Target: Analog: I~80 mA/cm²,
V=1.5V; Digital: I~80 mA/cm², V=1.2 V- Analog Front-End: Constant current
feedback preamp- Input Cap.: 300-500 fF- Q resolution (ToT): 4 bits
New FE-I4 Chip:20.2 mm
18.8
mm
Periphery
FE-I3
……
1.8
mm
Analog Analog
Analog Analog
0.5mm
0.1
mm 4 Pixel
Digital
- Digital architecture tuned to higher rate- 4 Pixels grouped to one digital region
with local storage memory- Output data stream: @ 160 MBit/s,
8b10b encoded- Local clock generation by on-chip PLL
data formatting (protocol) with error detection (hamming-code)
Asynch. FIFO
40 MHzMachine
Clock
clk select
160 MHz
aux: 80 MHz?
PLL, 40 MHz in, 160 MHz out
‘LVDS’-out160 Mb/s
2
Bypass-able
HGFEDCBAMSB LSB
1
Tran
smitter
8b to 10bEncoder
HighSpeed
Serializer
10
8
- Pixels/FE: 336x80, 50×250 μm²- Compatibility 3D, diamond, planar sensors- L1T max latency: 3.2 μs- Compatible with Serial Powering / DC-DC- Power Target: Analog: I~80 mA/cm²,
V=1.5V; Digital: I~80 mA/cm², V=1.2 V- Analog Front-End: Constant current
feedback preamp- Input Cap.: 300-500 fF- Q resolution (ToT): 4 bits
New FE-I4 Chip:20.2 mm
18.8
mm
Periphery
FE-I3
……
1.8
mm
20.2 mm18
.8m
m
Periphery
FE-I3
……
1.8
mm
20.2 mm18
.8m
m
Periphery
FE-I3
……
20.2 mm18
.8m
m
Periphery
FE-I3
……
1.8
mm
Analog Analog
Analog Analog
0.5mm
0.1
mm 4 Pixel
Digital
Analog Analog
Analog Analog
0.5mm0.5mm
0.1
mm
0.1
mm 4 Pixel
Digital
- Digital architecture tuned to higher rate- 4 Pixels grouped to one digital region
with local storage memory- Output data stream: @ 160 MBit/s,
8b10b encoded- Local clock generation by on-chip PLL
data formatting (protocol) with error detection (hamming-code)
Asynch. FIFO
40 MHzMachine
Clock
clk select
160 MHz
aux: 80 MHz?
PLL, 40 MHz in, 160 MHz out
‘LVDS’-out160 Mb/s
2
Bypass-able
HGFEDCBAMSB LSB
1
Tran
smitter
8b to 10bEncoder
HighSpeed
Serializer
10
8
data formatting (protocol) with error detection (hamming-code) data formatting (protocol) with error detection (hamming-code)
Asynch. FIFOAsynch. FIFO
40 MHzMachine
Clock
clk selectclk select
160 MHz
aux: 80 MHz?
PLL, 40 MHz in, 160 MHz out
PLL, 40 MHz in, 160 MHz out
‘LVDS’-out160 Mb/s
2
Bypass-able
HGFEDCBAMSB LSB
1
Tran
smitter
8b to 10bEncoder
HighSpeed
Serializer
10
8
‘LVDS’-out160 Mb/s‘LVDS’-out160 Mb/s
2
Bypass-able
HGFEDCBAMSB LSB
HGFEDCBAMSB LSB
1
Tran
smitter
8b to 10bEncoder
HighSpeed
Serializer
10
8
Type II PFD-CP PLL
• fref=40MHz
• fout=40/80/160/320MHz
• Simple loss of lock detection
X only ondemonstrator
Vctrl Settling
Loss of Lock Detection @ SET
Measurement Data
-Eye diagram of 160MBit/s serialized data stream using 80MHz PLL clock output with on-chip digital test logic
>5.6ns
284
mV
T= 6.25ns
Measurement Data
- MBit/s serialized data stream using 80MHz PLL clock output with on-chip digital test logic
>5.6ns
284
mV
T= 6.25ns
>5.6ns
284
mV>5.6ns
284
mV>5.6ns
284
mV
T= 6.25ns
Measurements on Demonstrator
Equipm. Test PLL
Frequency [MHz] 40 40 80 160 320 640
jitter pk-pk [ps] 44 82 74 94 70 * 106 *
freq [kHz] 6.5 19 79 2581710
*8100
*
period [ps] 4.1 12 12 11 17 * 20 *
Duty Cycle Deviation [0.1 %] x 2.4 3.3 1.0 x x
Pulser 81134A time jitter rms 2 ps, Scope TDS5104B 5 GS/s, 1 GHz*Measurement setup and equipment limit accurarcy
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 19
PLL TOP
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 20
PFD
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 21
CP
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 22
VCO
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 23
DIV16
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 24
DIV2
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 25
CONV_BUF
Andre Kruth, FEI4 CLKGEN, Jan. 25th 2010 26
MUX
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