FEATURES DESCRIPTIO U - Analog Devices · 2020. 2. 1. · 24 81214 1 0 6 I CCLO SUPPLY CURRENT (mA) VCCHI = 12V PIN FUNCTIONSUUU CON1 (Pin 1): TTL Level Input with a Pull-Up to VCCLO.

1

LTC1421/LTC1421-2.5

Hot Swap Controller

Allows Safe Board Insertion and Removal from aLive Backplane

System Reset and Power Good Control Outputs Programmable Electronic Circuit Breaker User Programmable Supply Voltage Power-Up Rate High Side Driver for Two External N-Channels Controls Supply Voltages from 3V to 12V Connection Inputs Detect Board Insertion or Removal Undervoltage Lockout Power-On Reset Input

Hot Board Insertion Electronic Circuit Breaker

The LTC®1421/LTC1421-2.5 are Hot SwapTM controllersthat allow a board to be safely inserted and removed from alive backplane. Using external N-channel pass transistors,the board supply voltages can be ramped up at a program-mable rate. Two high side switch drivers control the N-channel gates for supply voltages ranging from 3V to 12V.

A programmable electronic circuit breaker protects againstshorts. Warning signals indicate that the circuit breakerhas tripped, a power failure has occurred or that the switchdrivers are turned off. The reset output can be used togenerate a system reset when the power cycles or a faultoccurs. The two connect inputs can be used with stag-gered connector pins to indicate board insertion or re-moval. The power-on reset input can be used to cycle theboard power or clear the circuit breaker.

The trip point of the ground sense comparator is set at0.1V for LTC1421 and 2.5V for LTC1421-2.5.

The LTC1421/LTC1421-2.5 are available in 24-pin SO andSSOP packages.

10914138111567

RAMPCPON

COMP–

COMP+

REFFB

COMPOUTPWRGD

RESET

224

4

31

CON2AUXVCC

FAULT

PORCON1

VCCLO SETLO GATELO VOUTLO

LTC1421

GND DISABLE

VCCHI SETHI GATEHI VOUTHI

16 C20.1µF

C11µF

R516k5%

Q1MTB50N06E

R10.005Ω

171819202122

512

23

R31k

STAG

GERE

D CO

NNEC

TOR

D1

R620k1%

R420k5%

R77.15k1%

Q21/2 Si4936DY

Q31/2 Si4936DY

C30.47µF

R20.025Ω

+

CLOAD

CLOAD

CLOAD

VEE–12V1A

VDD12V1A

VCC5V5A

+

+

I/OI/ORESET

BEABEBGND

11312

µP

QS3384

QuickSwitch®QuickSwitch IS A REGISTERED TRADEMARKOF QUALITY SEMICONDUCTOR CORPORATION.

1421 TA01

DATA BUS

PC BOARDBACKPLANE

DATABUS

GND

POR

FAULT

VCC

VDD

VEE

VCC

1µF

43

21

43

21

10k

, LTC and LT are registered trademarks of Linear Technology Corporation.Hot Swap is a trademark of Linear Technology Corporation.

DESCRIPTIO

U

FEATURES

APPLICATIO SU

TYPICAL APPLICATIO

U

2

LTC1421/LTC1421-2.5

ABSOLUTE MAXIMUM RATINGS

W WW U WU U

PACKAGE/ORDER I FOR ATIO

Consult factory for parts specified with wider operating temperature ranges.

(Note 1)

Supply Voltage (VCCLO, VCCHI, AUXVCC) .............. 13.2VInput Voltage (Analog Pins) ..... – 0.3V to (VCCHI + 0.3V)Input Voltage (Digital Pins) ................... – 0.3V to 13.2VOutput Voltage (Digital Pins) .. – 0.3V to (VCCLO + 0.3V)Output Voltage (CPON) ......... – 13.2V to (VCCLO + 0.3V)Output Voltage (VOUTLO, VOUTHI) ........... –0.3V to 13.2VOutput Voltage (GATELO, GATEHI) ........... –0.3V to 20VOperating Temperature Range

LTC1421C ............................................... 0°C to 70°CLTC1421I ........................................... –40°C to 85°C

Storage Temperature Range ................ – 65°C to 150°CLead Temperature (Soldering, 10 sec)................. 300°C

ORDER PARTNUMBER

TJMAX = 125°C, θJA = 100°C/W (G)TJMAX = 125°C, θJA = 85°C/W (SW)

1

2

3

4

5

6

7

8

9

10

11

12

TOP VIEW

SW PACKAGE24-LEAD PLASTIC SO

G PACKAGE24-LEAD PLASTIC SSOP

24

23

22

21

20

19

18

17

16

15

14

13

CON1

CON2

POR

FAULT

DISABLE

PWRGD

RESET

REF

CPON

RAMP

FB

GND

AUXVCC

VCCLO

SETLO

GATELO

VOUTLO

VCCHI

SETHI

GATEHI

VOUTHI

COMPOUT

COMP–

COMP+

ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VCCHI = 12V, VCCLO = 5V unless otherwise noted (Note 2).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DC Characteristics

ICCLO VCCLO Supply Current CON1 = CON2 = GND, POR = VCCLO 1.5 3 mA

ICCHI VCCHI Supply Current CON1 = CON2 = GND, POR = VCCLO 0.6 1 mA

VLKO Undervoltage Lockout VCCLO and VCCHI 2.28 2.45 2.60 V

VLKH Undervoltage Lockout Hysteresis VCCLO and VCCHI 100 mV

VREF Reference Output Voltage No Load 1.220 1.232 1.244 V

∆VLNR Reference Line Regulation 3V ≤ VCCLO ≤ 12V, No Load 4 8 mV

∆VLDR Reference Load Regulation IO = 0mA to –5mA, Sourcing Only 1 3 mV

IRSC Reference Short-Circuit Current VREF = 0V – 45 mA

VCOF Comparator Offset Voltage 0V ≤ VCM ≤ (VCCLO − 1.3V) ±10 mV

VCPSR Comparator Power Supply Rejection 0V ≤ VCM ≤ (VCCLO − 1.3V), 3V ≤ VCCLO ≤ 12V 1 mV/V

VCHST Comparator Hysteresis 0V ≤ VCM ≤ (VCCLO − 1.3V) 7 mV

VRST Reset Voltage Threshold (VOUTLO) FB = VOUTLO 2.80 2.90 3.00 VFB = Floating 4.50 4.65 4.75 VFB = GND 5.75 5.88 6.01 V

VRHST Reset Threshold Hysteresis (VOUTLO) FB = VOUTLO 7 mVFB = Floating 12 mVFB = GND 15 mV

RFB FB Pin Input Resistance 0V ≤ VFB ≤ VCCLO 95 kΩVCB Circuit Breaker Trip Voltage VCB = (VCCLO – VSETLO) or VCB = (VCCHI – VSETHI) 40 50 60 mV

VTRIP Output Voltage for Re-Power-Up LTC1421 (Note 3) 0.1 VLTC1421-2.5 (Note 4) 2.5 V

LTC1421CGLTC1421CSWLTC1421CG-2.5LTC1421CSW-2.5LTC1421IGLTC1421ISWLTC1421IG-2.5LTC1421ISW-2.5

3

LTC1421/LTC1421-2.5

Note 3: After power-on reset, the VOUTLO and VOUTHI have to drop below theVTRIP point before the charge pump is restarted.Note 4: After power-on reset, the VOUTLO has to drop below the VTRIP pointbefore the charge pump is restarted.

Note 1: Absolute Maximum Ratings are those values beyond which the lifeof a device may be impaired.Note 2: All currents into device pins are positive; all currents out of devicepins are negative. All voltages are reference to ground unless otherwisespecified.

ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VCCHI = 12V, VCCLO = 5V unless otherwise noted (Note 2).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IRAMP RAMP Pin Output Current Charge Pump On, VRAMP = 0.4V 11 17 23 µA

ICP Charge Pump Output Current Charge Pump On, GATEHI = 0V –600 µAGATELO = 0V –300 µA

∆VGATEHI GATEHI N-Channel Gate Drive VGATEHI − VOUTHI 6 16 V

∆VGATELO GATELO N-Channel Gate Drive VGATELO − VOUTLO 10 16 V

VAUXVCC Auxiliary VCC Output Voltage VCCLO = 5V, Unloaded 4.5 V

VIL Input Low Voltage CON1, CON2, POR 0.8 V

VIH Input High Voltage CON1, CON2, POR 2 V

IIN Input Current CON1, CON2, POR = GND – 30 – 60 – 90 µA

VOL Output Low Voltage RESET, COMPOUT, PWRGD, DISABLE, FAULT, 0.4 VIO = 3mA

CPON, IO = 3mA 1.45 V

VOH Output High Voltage DISABLE, IO = – 3mA 4 V

CPON, IO = – 1mA 3.4 V

IPU Logic Output Pull-Up Current RESET, PWRGD, FAULT = GND – 15 µA

AC CHARACTERISTICS

t1 CON1 or CON2↓ to CPON↑ Figure 1, CL = 15pF 15 20 30 ms

t2 PWRGD↑ to RESET↑ Figure 1, RL = 10k to VCCLO, CL = 15pF 160 200 240 ms 140 200 280 ms

t3 PWRGD↑ to DISABLE↓ Figure 1, CL = 15pF 160 200 240 ms 140 200 280 ms

t4 POR↓ to CPON↓ Figure 1, CL = 15pF 15 20 30 ms

t5 PWRGD↓ to RESET↓ Figure 1, RL = 10k to VCCLO, CL = 15pF 32 µs

t6 POR↑ to CPON↑ Figure 1, CL = 15pF 50 ns

t7 CON1 or CON2↑ to CPON↓ Figure 1, CL = 15pF 50 ns

t9 Short-Circuit Detect to FAULT↓ Figure 1, RL = 10k to VCCLO, CL = 15pF 20 µsVCCLO – SETLO = 0mV to 100mV

t10 Short-Circuit Detect to CPON↓ Figure 2, CL = 15pF 20 µsVCCLO – SETLO = 0mV to 100mV

t11 POR↑ to FAULT↑ Figure 2, RL = 10k to VCCLO, CL = 15pF 20 ns

tCHL Comparator High to Low COMP – = 1.232V, 10mV Overdrive 0.25 0.5 µsRL = 10k to VCCLO, CL = 15pF

tCLH Comparator Low to High COMP – = 1.232V, 10mV Overdrive 1 1.5 µsRL = 10k to VCCLO, CL = 15pF

4

LTC1421/LTC1421-2.5

TYPICAL PERFORMANCE CHARACTERISTICS

UW

TEMPERATURE (°C)–50

1.232

1.234

1.238

25 75

1421 G01

1.230

1.228

–25 0 50 100 125

1.226

1.224

1.236

REFE

RENC

E VO

LTAG

E (V

)

VCCLO = 5VVCCHI = 12V

Reference Voltage vsTemperature

SOURCE CURRENT (mA)0

REFE

RENC

E VO

LTAG

E (V

)

1.235

1.240

1.245

8

1421 G03

1.230

1.225

1.2202 4 6 10


Reference Voltagevs Source CurrentGate Voltage vs Temperature


21

22

24

25 75

1421 G02

20

19

–25 0 50 100 125

18

17

23

GATE

VOL

TAGE

(V)


GATEHI

GATELO

GATELO Voltage vs VCCLO Voltage

VCCLO VOLTAGE (V)0

20

22

26

6 10

1421 G04

18

16

2 4 8 12 14

14

12

24

GATE

LO V

OLTA

GE (V

)

VCCHI = 12V

GATEHI Voltage vs VCCHI Voltage

VCCHI VOLTAGE (V)0

20

22

26

6 10

1421 G05

18

16

2 4 8 12 14

14

12

24

GATE

HI V

OLTA

GE (V

)

VCCLO = 5V

ICCLO Supply Currentvs Temperature


1400

25 75

1421 G06

1300

–25 0 50 100 1251200

1500

I CCL

O SU

PPLY

CUR

RENT

(µA)


VOL vs ISINK

CPON Voltage vs Sink Current(Charge Pump Off)

ICCHI Supply Currentvs Temperature


540

25 75

1421 G07

530

–25 0 50 100 125520

550

545

535

525

555

I CCH

I SUP

PLY

CURR

ENT

(µA)


SINK CURRENT (mA)0

0

VOLT

AGE

(mV)

100

200

300

400

500

FAULT

600

2 4 6 8

1421 G08

10


COMPOUTPWRGD

RESET

SINK CURRENT (mA)0

0

CPON

VOL

TAGE

(V)

0.5

1.0

1.5

2.0

2.5

0.5 1.0 1.5 2.0

1421 G09

2.5 3.0


5

LTC1421/LTC1421-2.5

TYPICAL PERFORMANCE CHARACTERISTICS

UW

CPON Voltage vs Source Current(Charge Pump On)

SOURCE CURRENT (mA)0

0

CPON

VOL

TAGE

(V)

1

2

3

4

5

–0.5 –1.0 –1.5 –2.0

1421 G10

–2.5 –3.0


ICCLO Supply Currentvs VCCLO Voltage

VCCLO VOLTAGE (V)0

4

5

7

6 10

1421 G11

3

2

2 4 8 12 14

1

0

6

I CCL

O SU

PPLY

CUR

RENT

(mA)

VCCHI = 12V

PIN FUNCTIONS

UUU

CON1 (Pin 1): TTL Level Input with a Pull-Up to VCCLO.Together with CON2, it is used to indicate board connec-tion. The pin must be tied to ground on the host side of theconnector. When using staggered connector pins, CON1and CON2 must be the shortest and must be placed atopposite corners of the connector. Board insertion isassumed after CON1 and CON2 are both held low for 20msafter power-up.

CON2 (Pin 2): TTL Level Input with a Pull-Up to VCCLO.Together with CON1 it is used to indicate board connec-tion.

POR (Pin 3): TTL Level Input with a Pull-Up to VCCLO.When the pin is pulled low for at least 20ms, a hard resetis generated. Both VOUTLO and VOUTHI will turn off at acontrolled rate. A power-up sequence will not start untilthe POR pin is pulled high. If POR is pulled high beforeVOUTLO and VOUTHI are fully discharged, a power-upsequence will not begin until the voltage at VOUTLO andVOUTHI are below VTRIP. The electronic circuit breaker willbe reset by pulling POR low.

FAULT (Pin 4): Open Drain Output to GND with a WeakPull-Up to VCCLO. The pin is pulled low when an overcur-rent fault is detected at VOUTLO or VOUTHI.

DISABLE (Pin 5): CMOS Output. The signal is used todisable the board’s data bus during insertion or removal.

PWRGD (Pin 6): Open Drain Output to GND with a WeakPull-Up to VCCLO. The pin is pulled low immediately afterVOUTLO falls below its reset threshold voltage. The pin ispulled high immediately after VOUTLO rises above its resetthreshold voltage.

RESET (Pin 7): Open Drain Output to GND with a WeakPull-Up to VCCLO. The pin is pulled low when a resetcondition is detected. A reset will be generated when anyof the following conditions are met: Either CON1 or CON2is high, POR is pulled low, VCCLO or VCCHI are below theirrespective undervoltage lockout thresholds, PWRGD goeslow or an overcurrent fault is detected at VOUTLO orVOUTHI. RESET will go high 200ms after PWRGD goeshigh. On power failure, RESET will go low 32µs afterPWRGD goes low.

REF (Pin 8): The Reference Voltage Output. VOUT = 1.232V±1%. The reference can source up to 5mA of current. A1µF bypass capacitor is recommended.

CPON (Pin 9): CMOS Output That Can Be Pulled BelowGround. CPON is pulled high when the internal chargepumps for GATELO and GATEHI are turned on. CPON ispulled low when the charge pumps are turned off. The pincan be used to control an external MOSFET for a –5V to–12V supply.

6

LTC1421/LTC1421-2.5

PIN FUNCTIONS

UUU

RAMP (Pin 10): Analog Power-Up Ramp Control Pin. Byconnecting an external capacitor between the RAMP andGATEHI, a positive linear voltage ramp on GATEHI andGATELO is generated on power-up with a slope equal to20µA/CRAMP. A 10k resistor in series with the capacitorenhances the ESD performance at the GATEHI pin.

FB (Pin 11): Analog Feedback Input. FB is used to set thereset threshold voltage on VCCLO. For a 5V supply leave FBfloating. For a 3.3V supply, short FB to VCCLO.

GND (Pin 12): Ground

COMP+ (Pin 13): Noninverting Comparator Input.

COMP– (Pin 14): Inverting Comparator Input.

COMPOUT (Pin 15): Open Drain Comparator Output.

VOUTHI (Pin 16): High Supply Voltage Output. This must bethe higher of the two supply voltage outputs.

GATEHI (Pin 17): The High Side Gate Drive for the HighSupply N-Channel. An internal charge pump guarantees atleast 6V of gate drive. The slope of the voltage rise atGATEHI is set by the external capacitor connected betweenGATEHI and RAMP. When the circuit breaker trips, GATEHIis immediately pulled to GND.

SETHI (Pin 18): The Circuit Breaker Set Pin for the HighSupply. With a sense resistor placed in the supply pathbetween VCCHI and SETHI, the circuit breaker will trip whenthe voltage across the resistor exceeds 50mV for morethan 20µs. To disable the circuit breaker, VCCHI and SETHIshould be shorted together.

VCCHI (Pin 19): The Positive Supply Input. This must be thehigher of the two input supply voltages. An undervoltagelockout circuit disables the chip until the voltage at VCCHIis greater than 2.45V.

VOUTLO (Pin 20): Low Supply Voltage Output. This must bethe lower of the two supply voltage outputs.

GATELO (Pin 21): The High Side Gate Drive for the LowSupply N-Channel Pass Transistor. An internal chargepump guarantees at least 10V of gate drive. The slope ofthe voltage rise at GATELO is set by the external capacitorconnected between GATEHI and RAMP. When the circuitbreaker trips GATELO is immediately pulled to GND.

SETLO (Pin 22): The Circuit Breaker Set Pin for the LowSupply. With a sense resistor placed in the supply pathbetween VCCLO and SETLO, the circuit breaker will tripwhen the voltage across the resistor exceeds 50mV formore than 20µs. To disable the circuit breaker, VCCLO andSETLO should be shorted together.

VCCLO (Pin 23): The Positive Supply Input. VCCLO must beequal to or lower voltage than VCCHI. An undervoltagelockout circuit disables the chip until the voltage at VCCLOis greater than 2.45V.

AUXVCC (Pin 24): The supply input for the GATELO andGATEHI discharge circuitry. Connect a 1µF capacitor toground. AUXVCC is powered from VCCLO via an internalSchottky diode and series resistor.

7

LTC1421/LTC1421-2.5

BLOCK DIAGRAM

WFigure 1. Nominal Operation Switching Waveforms Figure 2. Fault Detection Switching

CPON

CON1

t1

CON2

RESET

DISABLE

POR 1421 F01

PWRGD

t2

t3 t4t6

t5 t7

CPON

VCCLO – SETLO

t9

FAULT

RESET

POR1421 F02

PWRGD

t2t5 t11

t6t10

SWITCHI G TI E WAVEFOR SU W W

–

++

–

+

+– VTRIP

+–+– 50mV50mV

CPON

AUXVCC

VCCHISETLO

CP1 CP2

VCCLO SETHI GATELO RAMP GATEHI VOUTHI VOUTLO

192223 18 21 10 17 16 20

VCC

FAULT

CON1

CON2

POR

DISABLE

9

24

4

1

2

3

5

20µA

VCC

CP3

CP4

CP5

73.5k

N1N2

AUXVCC

FB

REF

11

8

PWRGD 6

RESET 7

COMPOUT 15

COMP– 14

COMP+ 13

1421 BD

71.5k

26.7k

20µA

20µA

1.232VREFERENCE

CHARGEPUMP

UNDERVOLTAGELOCKOUT

RESETTIMING

VCCVCC

VCC

–

+

GND

DIGITAL CONTROL

12

8

LTC1421/LTC1421-2.5

APPLICATIONS INFORMATION

WU UU

Hot Circuit Insertion

When circuit boards are inserted into a live backplane, thesupply bypass capacitors on the board can draw hugetransient currents from the backplane power bus as theycharge up. The transient currents can cause permanentdamage to the connector pins and cause glitches on thesystem supply, causing other boards in the system toreset. At the same time, the system data bus can bedisrupted when the board’s data pins make or breakconnection.

The LTC1421 is designed to turn a board’s supply voltageson and off in a controlled manner, allowing the board to besafely inserted or removed from a live backplane. The chipalso provides a disable signal for the board’s data busbuffer during insertion or removal and provides all thenecessary supply supervisory functions for the board.

Power Supply Ramping

The power supplies on a board are controlled by placingexternal N-channel pass transistors in the power path(Figure 3). R1 and R2 provide current fault detection. Byramping the gate of the pass transistor up at a controlledrate, the transient surge current (I = C • dV/dt) drawn fromthe main backplane supply can be limited to a safe valuewhen the board makes connection.

Figure 3: Supply Control Circuitry

23

1 10

5V

12V

2

R1 Q1

22 21 20 19 18 17 16

+R2 Q2

CLOAD

CLOAD

+


LTC1421

1421 F03

VCCHI SETHI GATEHI VOUTHI

RAMPCON1

CON2

CRAMP

VOUTHI

VOUTLO43

21

4321

RRAMP

When power is first applied to the chip, the gates of bothN-channels, GATELO and GATEHI are pulled low. After theconnection sense pins, CON1 and CON2 are both held lowfor at least 20ms, a 20µA reference current is connectedfrom the RAMP pin to GND. The voltage at GATEHI beginsto rise with a slope equal to 20µA/CRAMP (Figure 4), whereCRAMP is an external capacitor connected between the

Figure 4. Supplies Turning On

12V

5V

1421 F4at1 t2

VOUTHI

VOUTLO

SLOPE = 20µA/CRAMP

–12V

–12V

~1ms

0V

–12V

5V

CPON9

BR516k5%

B

VEE

0V

~1ms 1421 F05

R420k5%

C20.047µF

CLOAD

VEE–12V1A

Q31/2 MMDF3N0HD

–12V FROMCONNECTOR

+

CPON

LTC1421

Figure 5. Negative Supply Control

RAMP and GATEHI pins. The voltage at the GATEHI pin isclamped one Schottky diode drop below GATELO.

The ramp time for each supply is equal to: t = (VCC)(CRAMP)/20µA. During power down the gates are activelypulled down by two internal NFETs.

A negative supply voltage can be controlled using theCPON pin as shown in Figure 5.

When the board makes connection, the transistor Q3 isturned off because it’s gate is pulled low to –12V by R4.CPON is also pulled to –12V. When the charge pump isturned on, CPON is pulled to VCCLO and the gate of Q3 willramp up with a time constant determined by R4, R5 andC2. When the charge pump is turned off, CPON goes intoa high impedance state, the gate of Q3 is discharged to VEEwith a time constant determined by R4 and C2, and Q3turns off.

9

LTC1421/LTC1421-2.5


WU UU

PWRGD and RESET

The LTC1421 uses a 1.232V bandgap reference, internalresistive divider and a precision voltage comparator tomonitor VOUTLO (Figure 6).

The reset threshold voltage for VOUTLO is determined bythe FB pin connection as summarized in Table 1.

When VOUTLO drops below its reset threshold, the com-parator output goes high, and PWRGD is immediatelypulled low (time point 2). After a 32µs delay, RESET ispulled low. The RESET delay allows the PWRGD signal tobe used as an early warning that a reset is about to occur.If the PWRGD signal is used as a interrupt input to amicroprocessor, a short power-down routine can be runbefore the reset occurs.

If VOUTLO rises above the reset threshold for less than200ms, the PWRGD output will trip, but the RESET output isnot affected (time point 3). If VOUTLO drops below the resetthreshold for less than 32µs, the PWRGD output will trip, butagain the RESET output will not be affected (time point 5).

Voltage Comparator

The uncommitted voltage comparator (COMP2) can beused to monitor output voltages other than VOUTLO. Figure8a shows how the comparator can be used to monitor a12V supply (VOUTHI), while the 5V supply (VOUTLO) gener-ates a reset when it dips below 4.65V. When the 12Vsupply drops below 10.8V, COMPOUT will pull low. The FBpin is left floating.

Figure 8b shows how the comparator can be used tomonitor the 5V supply (VOUTHI) while the 3.3V supply(VOUTLO) generates a reset when it dips below 2.9V. Whenthe 5V supply drops below 4.65V, COMPOUT will pull low.The FB pin is tied to VOUTLO.

Figure 6. Supply Monitor Block Diagram

–

+

VCCLO

VCCLOVOUTLO

FB

1421 F06

1.232V

20µA

20µA

26.7k

PWRGD

RESET

COMP1

RESETTIMING

REF

73.5k71.5k

VOUTLO

PWRGD

RESET

32µs

V2 V2 V2 V2 V1V1V1

1 2 3 4 5

200ms <200ms 200ms1421 F07

<32µs

Table 1FEEDBACK PIN VOUTLO RESET VOLTAGE

Floating 4.65V

VOUTLO 2.90V

GND 5.88V

When the VOUTLO voltage rises above its reset thresholdvoltage, the comparator output goes low, and PWRGD isimmediately pulled high to VCCLO by a weak pull-upcurrent source or external resistor (Figure 7, time points1 and 4). After a 200ms delay, RESET is pulled high. Theweak pull-up current source to VCCLO on PWRGD andRESET have a series diode so the pins can be pulled aboveVCCLO by an external pull-up resistor without forcingcurrent back into VCCLO.

Figure 7. Power Monitor Waveforms Figure 8a. Monitor 12V, Reset 5V at 4.65V

1421 F08a

10k5%

107k1%

13.7k1%

5V 12V

–

+

–

+

VCCLO

VCCLO

1.232V

LTC1421

20µA

20µA

8

14

13

15

11

16

20

26.7k

COMP1

COMP2

RESETTIMING

73.5k

107k1%

6

7

71.5k

10

LTC1421/LTC1421-2.5


WU UU

A 5.1k resistor is tied from the FB pin to VOUTLO, setting theinternal threshold to about 2.9V. The new reset thresholdvoltage is set by the external resistive divider connected toCOMP2. When VOUTLO drops below the new threshold,COMPOUT pulls FB to ground, changing the internalthreshold at COMP1 to 5.88V and generating a reset.

Finally, the comparator may be used to monitor a negativesupply as shown in Figure 8e. The external resistor divider

Figure 8c shows how the comparator can be used togenerate a reset when the 12V supply (VOUTHI) dropsbelow 10.8V. The 5V supply (VOUTLO) also generates areset when it dips below 4.65V. When the 12V supplydrops below 10.8V, COMPOUT will pull the FB pin lowsetting the internal threshold voltage for comparator 1 to5.88V. Since VOUTLO is less than 5.88V, PWRGD immedi-ately goes low and a reset is generated 32µs later.

Figure 8d shows how the comparator can be used tooverride the internal reset voltage for a 5V supply onVOUTLO.

–

+

–

+

VCCLO

VCCLO

1421 F08c

1.232V

LTC1421

20µA

20µA

8

14

13

15

11

16

20

26.7k

COMP1

COMP2

RESETTIMING

73.5k

107k1%

13.7k1%

6

7

71.5k

5V 12V

Figure 8c. Reset 12V at 10.8V, Reset 5V at 4.65V Figure 8e. Monitor – 12V at –10.8V, Reset 5V at 4.65V

–

+

–

+

VCCLO

VCCLO

1421 F08e

1.232V

LTC1421

20µA

20µA

8

14

13

15

11

16

20

26.7k

COMP1

COMP2

RESETTIMING

73.5k

107k1%

10k5%

13.7k1%

6

7

71.5k

5V

12V

–12V

Figure 8d. Reset 5V at 4.5V

–

+

–

+

VCCLO

VCCLO

1421 F08d

1.232V

LTC1421

20µA

20µA

8

14

13

15

11

16

20

26.7k

COMP1

COMP2

RESETTIMING

73.5k

102k1%

5.1k5%

38.3k1%

6

7

71.5k

5V

12V

–

+

–

+

VCCLO

VCCLO

1421 F08b

1.232V

LTC1421

20µA

20µA

8

14

13

15

11

16

20

26.7k

COMP1

COMP2

RESETTIMING

73.5k

10k5%

107k1%

38.3k1%

6

7

71.5k

3.3V 5V

Figure 8b. Monitor 5V, Reset 3.3V at 2.9V

11

LTC1421/LTC1421-2.5


WU UU

is connected between REF (Pin 8) and the negative supplyand the trip point of Comparator 2 set to GND.

Soft Reset Generation

A soft reset that doesn’t cycle the supply voltage can begenerated externally using Pin 11 (FB) as shown in Figure9. For a 5V supply the FB pin is left floating to set theinternal supply monitor trip voltage to 4.65V. However, ifthe FB pin is pulled to ground for more than 32µs via a pushbutton or open-collector logic gate, the internal trip pointwill go to 5.88V and the RESET pin will pull low. RESET willremain low for 200ms after the FB pin is released. TheRESET signal will also be pulled low when the voltage atthe VOUTLO pin dips below 4.65V for more than 32µs.When using a 3.3V supply, a 1k resistor must be con-nected from the FB pin to VCCLO to set the internal trip pointto 2.90V.

sense resistor is greater than 50mV for more than 20µs.When the circuit breaker trips, both N-channel MOSFETsare quickly turned off, FAULT and PWRGD go low andRESET is pulled low 32µs later. FAULT can be connectedto a LED or a logic signal back to the host to indicate a faultyboard. The chip will remain in the tripped state until apower-on reset is generated, or the power on VCCHI andVCCLO is cycled. If the circuit breaker feature is not used,short VCCLO to SETLO and VCCHI to SETHI.

If more than 20µs of response time is needed to rejectsupply noise, an external resistor and capacitor can beadded to the sense circuit as shown in Figure 10.

Figure 9. Generating a Soft Reset

Undervoltage Lockout

On power-up, an undervoltage lockout circuit prevents theGATELO and GATEHI charge pumps from turning on untilVCCLO and VCCHI have both exceeded 2.45V.

Electronic Circuit Breaker

The LTC1421 features an electronic circuit breaker func-tion that protects against short circuits or excessive cur-rents on the supplies. By placing a sense resistor betweenthe supply input and set pin of either supply, the circuitbreaker will be tripped whenever the voltage across the

LTC1421

3.3V

5V

1/6 LS7404OPEN

COLLECTOR

GND

32µs200ms

FB11 7

12

1421 F09

R11k

R1 USED FOR 3.3VSUPPLY ONLY

RESET

RESET

FB

RESET

LOGIC

23

RSENSE

CF

Q1

22

RF

21 20


LTC1421

1421 F10

43

21

Figure 10. Short-Circuit Protection Circuit

Figure 11. AUXVCC Circuitry

GATE DRIVECIRCUITRY

10k

1µF

AUXVCC

1421 F11

VCCLO

24

LTC1421

23

GATELO GATEHI

21 17

Auxiliary VCC

When a short circuit occurs on the board, it is possible todraw enough current to cause the backplane supplyvoltage to collapse. If the input supply voltage collapses toa low enough voltage and the LTC1421 gate drive circuitryis unable to shut off the N-channel pass transistors, thesystem might freeze up in a permanent short condition.

To prevent this from occurring, the gate discharge cir-cuitry inside the LTC1421 is powered from AUXVCC,which is in turn powered from VCCLO through an internalSchottky diode and current limiting resistor (Figure 11).

12

LTC1421/LTC1421-2.5


WU UU

When VCCLO collapses, there is enough energy stored onthe 1µF capacitor connected to AUXVCC to keep the gatedischarge circuitry alive long enough to fully turn off theexternal N-channels.

Power N-Channel Selection

The RDS(ON) of the external pass transistor must be lowenough so that the voltage drop across it is about 200mVor less at full current. If the RDS(ON) is too high, the voltagedrop across the transistor might cause the output voltageto trip the reset circuit. Table 2 lists the transistors that arerecommended for use with the LTC1421.Table 2. N-Channel Selection GuideCURRENT PARTLEVEL (A) NUMBER MANUFACTURER DESCRIPTION

0 to 1 MMDF2N02E ON Semiconductor Dual N-Channel SO-8RDS(ON) = 0.1Ω

1 to 2 MMDF3NO2HD ON Semiconductor Dual N-Channel SO-8RDS(ON) = 0.09Ω

2 to 5 MTB30N06 ON Semiconductor Single 30AN-Channel DD PakRDS(ON) = 0.05Ω

5 to 10 MTB50N06E ON Semiconductor SingleN-Channel DD PakRDS(ON) = 0.025Ω

10 to 20 MTB75N05HD ON Semiconductor SingleN-Channel DD PakRDS(ON) = 0.0095Ω

Data Bus

When a board is inserted or removed from the host, caremust be given to prevent the system data bus from beingcorrupted when the data pins make or break contact. Oneproblem is that the fully discharged input or output capaci-tance of the logic gates on the board will draw an inrushcurrent when the data bus pins first make contact. Theinrush current can temporarily corrupt the data bus, butusually will not cause long term damage. The problem canbe minimized by insuring the input or output data buscapacitance is kept as small as possible.

The second, and more serious problem involves thediodes to VCC at the input and output of most logic families(Figure 12).

VCC

OUT

BACKPLANE BOARD

D1

D2

1421 F12

DATABUS

CONN

ECTO

R

Figure 12. Typical Logic Gate Loading the Data Bus

Figure 13: Buffering the Data Bus

+21 20

CLOAD2223

5

12

24

3

14

4

17

7

18

8

21

11

22

12

2

15

5

16

6SYSTEM

DATA BUSBOARDDATA BUS19

9

20

10

23

1

13

QS3384 VCC

GND

1421 F13

VCC5V

CONN

ECTO

R

LTC1421

R10.005Ω

Q1MTB50N06E

GNDDISABLE

43

21

With the board initially unpowered, the VCC input to thelogic gate is at ground potential. When the data bus pinsmake contact, the bus line is clamped to ground throughthe input diode D1 to VCC. Large amounts of current canflow through the diode and cause the logic gate to latch upand destroy itself when the power is finally applied. This

13

LTC1421/LTC1421-2.5


WU UU

signal is pulled high, turning off the switches. After theboard supply voltage ramps up and RESET goes high,DISABLE will pull low enabling the switches.

Board Insertion Timing

When the board is inserted, GND pin makes contact first,followed by VCCHI and VCCLO (Figure 14, time point 1).DISABLE is immediately pulled high, so the data busswitch is disabled. At the same time CON1 and CON2 makecontact and are shorted to ground on the host side (timepoint 3). Since most boards need to be rocked back andforth to get them in place, there is a period of time whenonly one side of the connector is making contact. CON1and CON2 should be located at opposite ends of theconnector.

Figure 14. Board Insertion Timing

can usually be prevented by using logic that does notinclude the clamping diodes such as the QSI 74FCTTfamily from Quality Semiconductor, or by using a data busswitch such as the 10-bit QS3384 QuickSwitch also fromQuality Semiconductor (Tel: 408-450-8000). TheQuickSwitch bus switch contains an N-channel placed inseries with the data bus. The switch is turned off when theboard is inserted and then enabled after the power isstable. The switch inputs and outputs do not have aparasitic diode back to VCC and have very low capacitance.

The LTC1421 is designed to work directly with theQuickSwitch bus switch as shown in Figure 13.

The DISABLE signal is connected to the enable pins of theQS3384, and each switch is placed in series with a databus signal. When the board is inserted, the DISABLE

VCCLO

1 2 3 4 5 6

VCCHI

DISABLE

CON1

CON2

CPON

GATEHI

PWRGD

VTH1

1421 F14

VOUTHI

VOUTLO

GATELO

RESET

FAULT

POR

200ms20ms

14

LTC1421/LTC1421-2.5


WU UU

When CON1 and CON2 are both forced to ground for morethan 20ms, the LTC1421 assumes that the board is fullyconnected to the host and power-up can begin. WhenVCCLO and VCCHI exceed the 2.45V undervoltage lockoutthreshold, the 20µA current reference is connected fromRAMP to GND, the charge pumps are turned on and CPONis forced high (time point 4). VOUTHI and VOUTLO begin toramp up. When VOUTLO exceeds the reset threshold volt-age, PWRGD will immediately be forced high (time point5). After a 200ms delay, RESET will be pulled high andDISABLE will be pulled low, enabling the data bus (timepoint 6).

Ground Sense Comparator

When POR is pulled low for more than 20ms, GATELO andGATEHI are pulled to ground and VOUTLO and VOUTHI willbe discharged. If POR is pulled back high while VOUTLOand VOUTHI are still ramping down, the discharge willcontinue. When they drop below the VTRIP point, a power-

up sequence will begin automatically. The trip point poten-tial for LTC1421 is set at 0.1V and 2.5V for LTC1421-2.5.

In applications, where either VOUTLO or VOUTHI might beforced above 100mV before power-up, the LTC1421-2.5should be used. This could occur when leakage throughthe body diode of the logic chips keeps VOUTLO high or inthe case where logic lines are precharged.

In other applications, where outputs need to drop to nearground potential before ramping up again to ensure properinitial state for the logic chips, the LTC1421 should beused.

Power-On Reset Timing

The POR input is used to completely cycle the powersupplies on the board or to reset the electronic circuitbreaker feature. The POR pin can be connected to agrounded push button, toggle switch or a logic signalfrom the host. When POR is pulled low for more than20ms, a power-on reset sequence begins (Figure 15,

Figure 15. Power-On Reset Timing

VCCHI

1 2 3 4 5 6 7

VCCLO

DISABLE

FAULT

POR

CON1

CON2

VOUTLO

VOUTHI

CPON

VTH2

1421 F15

VTH1

20ms 200ms32µs

GATEHI

GATELO

RESET

PWRGD

15

LTC1421/LTC1421-2.5


WU UU

time point 2). Pulses less than 20ms on POR are ignored.CPON goes low. Both GATEHI and GATELO will beactively pulled down to GND. When VOUTLO drops belowits reset threshold voltage, PWRGD will immediately pulllow (time point 3) followed by RESET and DISABLE 32µslater (time point 4). Both supplies will be discharged toground and stay there until POR is pulled high.

The circuit breaker can be reset by pulling POR low. AfterPOR is low for more than 20ms, the chip will immediatelytry to power up the supplies once the outputs are below theVTRIP point.

Circuit Breaker Timing

The waveforms for the circuit when a short occurs oneither supply during board insertion are shown in

Figure 16. Time points 1 to 4 are the same as the boardinsertion example, but at time point 5, a short circuit isdetected on one of the supplies. The charge pumps areimmediately turned off, the outputs VOUTHI and VOUTLO areactively pulled to GND and the CPON and FAULT pins arepulled low. At time point 6, the circuit breaker is reset bypulling POR low. After POR has been low for 20ms (timepoint 7), CPON and FAULT are pulled high, the 20µAreference current is connected to RAMP and the chargepumps are enabled. VOUTHI and VOUTLO ramp up at acontrolled rate. When VOUTLO has exceeded its resetthreshold, the PWRGD signal is pulled high (time point 8).After a 200ms delay, RESET is pulled high and DISABLEgoes low.

Figure 16. Circuit Breaker Timing

VCCLO

1 2 3 4 5 6

VCCHI

DISABLE

CON1

7 8 9

CON2

CPON

PWRGD

VTH1

1421 F16

VOUTHI

GATEHI

GATELO

VOUTLO

RESET

FAULT

POR

20ms 20ms 200ms

16

LTC1421/LTC1421-2.5


WU UU

VCCLO

1 2 3 4

VCCHI

DISABLE

CON1

CON2

CPON

PWRGD

VTH2

1421 F17

VOUTHI

GATEHI

GATELO

VOUTLO

RESET

FAULT

POR

32µs

Figure 17. Board Removal Timing

Board Removal Timing

When the board is removed from the host, the sequencehappens in reverse (Figure 17). Since CON1 and CON2 arethe shortest pins, they break connection first and areinternally pulled high (time point 1). The charge pumps areturned off, CPON is pulled low. VOUTLO and VOUTHI areactively pulled down. When VOUTLO falls below its resetthreshold (time point 2) PWRGD is pulled low. To allow

time for power fail information to be stored in nonvolatilememory, the falling edge of RESET (time point 3) isdelayed by 32µs from the falling edged of PWRGD.

Finally, the input supply pins VCCHI and VCCLO breakcontact (time point 4). If staggered pins are not used, theboard may be powered down prior to removal by switch-ing the POR pin to ground with a toggle switch.

17

LTC1421/LTC1421-2.5


WU UU

5V Only Applications

The LTC1421 may be used in 5V only applications as shownin Figure 18. A soft reset can be generated from thebackplane via an open-collector inverter driving the FB (Pin11) or by a push button to ground. A hard power reset isgenerated from the backplane via an open-collector inverterdriving the POR (Pin 3). A hard reset cycles the power onthe board or resets the electronic circuit breaker. Thecomparator is used to monitor the board supply voltage and

will pull the POWERGOOD signal low as long as the supplyremains above 4.65V. Note that a soft reset will not affectthe POWERGOOD signal. The FAULT signal is also moni-tored to determine that the circuit breaker has tripped.

–48V and 24V Applications

The LTC1421 may be used in –48V applications as shownin Figure 19. The LTC1421 provides the hot insertionprotection, while the 5V supply is generated by a power

Figure 19. –48V to 5V Hot Swappable Supply

10

714138

15

1

LTC1421

16

Q1MTB50N06E

C11µF

C21µF

R228k1%

5V

171819202122

5 9 6 3 S1

11

12

23

1421 F18

5V

5V

5VPOWERGOOD

FAULT

SOFT RESET

HARD RESET

R10.005Ω

1W

R310.2k1%

RESET

LOGIC

CLOAD

10k

10k

1/6LS7004

PC BOARDBACKPLANE

1µF

43

21R410k

Figure 18. 5V Only Application with Soft Reset

109

13148111567

224

4

31

16R4

300Ω1/8W

R356k1/2W

Q2MPSA06

Q1IRFR9110

C11µF

–48V

171819202122

512

23

STAG

GERE

D CO

NNEC

TOR

C22.2µF25V

R15.1k1W

D15.1V

+

C32.2µF

25V

+2

1

5

6

3

C4100µF16V

5V2A

+

C4100µF100V

+

1421 F19

PC BOARDBACKPLANE

– 48V

S1

–48V

–48V

R510k1/2W

R6402Ω1/8W

R215k1/8W

ASTRODYNEASD 10-48S5

CONTROL

+IN +OUT

–IN –OUT

LTC14211µF

18

LTC1421/LTC1421-2.5


WU UU

Figure 23 shows how to use the LTC1421 with a 5V supplyand an LTC1430CS8 synchronous step-down switchingregulator to generate 3.3V output at up to 10A for micro-processors. Resistors R4, R8 and R9 set the turn-onvoltage at 4.8V and the turn-off at 4.25V. Pushbuttonswitch S1 provides users a way to reset the output whileS2 is used to soft-reset the microprocessor only.

Figure 24 shows how to use the LTC1421 with a 5V supplyand a –48V supply that is used to generate a ±12V supplyusing a supply module. Resistors R3 and R4 are used tomonitor the input voltage to the supply module. Themodule is prevented from turning on via the optoisolatoruntil the input voltage reaches –36V. Zener diode D2prevents the CPON pin of the LTC1421 from being dam-aged by excessive voltage.

Figure 25 shows how to use the LTC1421 to do overvolt-age protection. Resistors R3 and R4 set the trip point at7V. When the input supply voltage rises above 7V, Q2 isturned on and Q1 turned off while Q3 helps to dischargethe output voltage.

Figure 26 shows how to use the LTC1421 to control boththe power-up and power-down sequence of the outputs.The 5V output would be powered up first followed by the3V output. At power-down sequence, the 3V output wouldgo down first followed by the 5V supply.

Figure 27 shows how to use the LTC1421 to switch 3.3V,5V, 12V and –12V supplies for PCI application. The ramp-up rate for 3.3V, 5V and 12V is determined by the rampcapacitor C2 while the –12V supply is controlled by R7 andC3. The internal comparator is being used to do theovercurrent protection for Q4 with the trip point set byresistors R6 and R8. The –12V supply does not haveovercurrent protection. R10 is used to set the power goodsignal trip point at 10V. When the 12V output rises above10V, the PCI controller gets a power good signal followedby RESET after 200ms.

module. The ground pin for the LTC1421 is connected to–48V; Zener diode D1 and resistor R1 provide the positivesupply for the chip. Bypass capacitor C4 is protectedagainst inrush current by P-channel Q1. When the boardis inserted into the backplane, transistor Q1 is turned offby resistor R2. When the connection sense pins, CON1and CON2 have been connected to –48V for more than20ms, CPON pulls high turning on Q2 and the gate of Q1starts to pull low with a time constant determined by R2,R3 and C3. At the same time, the voltage at the input to thepower module starts to ramp up. When the voltage acrossthe inputs to the power module reaches the comparatortrip level set by R5 and R6, in this case –32V, thecomparator output pulls high and turns on the 5V supply.

A cheaper solution is shown in Figure 20 using theLT®1170HV switcher. Again P-channel transistor Q1 pro-tects the bypass capacitors against inrush current andresistors R5 and R6 set the comparator trip voltage. TheLT1170HV is turned on via the VC pin. Resistors R11, R14and transistor Q4 provide a monitoring path for the RESETsignal which is level shifted up to 5V through an optoiso-lator.

The P-channel power FET is being replaced by anN-channel FET in Figure 21 for the –48V application.Again, Zener Diode D1 and resistor R1 provide the positivesupply for the chip. Capacitor C1 is to insure Q1 stays offwhen the board is being hot inserted into the backplane.The resistor divider R2 and R3, along with the internalcomparator, perform the undervoltage lock out function.Q1 would only be turned on when the input supply voltageis lower than –42V. The power module would then beturned on by the optoisolator, 4N25, when the module’sinput voltage reaches 47V.

Figure 22 shows how to use the LTC1421 with a 24Vsupply and a LT1074CT step-down switcher. Resistors R5and R6 set the turn-on threshold to 22V. All of thesupervisory signals can be used without level shifting.

19

LTC1421/LTC1421-2.5


WU UU

10 9 13 14 8 11 15 6 7

2 24 4 3 1

LTC1

421

16R4 300Ω

1/8W

R3 56k

1/2W

Q2 MPS

A06

Q1IR

FR91

10

C1 1µF

–48V

1718

1920

2122

5S1

12

23

STAGGERED CONNECTOR

C2 2.2µ

F25

V

R1 5.1k

1W

D15.

1V+

C32.

2µF

25V

C5 4.7µ

F50

V

C9 0.33

µF50

V

+

+

C4 4.7µ

F50

V

3

5

1

4

+C6 10

0µF

100V

L110

0µH

D4M

BR31

00Q3

2N54

01Q4

2N54

01

D3M

BR31

00D2 7.

5V+

1421

F20

PC B

OARD

BACK

PLAN

E

–48

V

–48V

–48V

R5 10k

1/2W

R6 402Ω

1/8W

R9 1k 1/8W

R8 1k 1/8W

R2 15k

1/8W

LT11

70HV

CT

V CC

V CSW

GND

FB

R10

4.32

k1/

8W

R11

4.32

k1/

8W

R13

1.24

k1/

8W

R14

4.64

k1/

8W

R12

10k

1/8WV C

C5V 3A RE

SET

C7 1000

µF25

V

++

C8 1000

µF25

V

1µF

Figu

re 2

0. –

48V

to 5

V Ho

t Sw

appa

ble

Supp

ly U

sing

the

LT11

70HV

CT

20

LTC1421/LTC1421-2.5


WU UU

Figure 21. – 48V to 5V Hot Swappable Supply

Figure 22. 24V to 5V Hot Swappable Supply Using the LT1074CT

109

13148111567

224

4

31

LTC1421

16R4

300Ω1/8W

R356k1/8W

Q2MPSA06

Q1IRFR9110

C11µF

171819202122

512

23

STAG

GERE

D CO

NNEC

TOR

C22.2µF25V

R15.1k1/4W

D15.1V

S1

+

C32.2µF

25V

+ C4200µF50V

D4MBR745

L150µH

2

5

1

3

4

++ C5

500µF25V

5V5A

C60.01µF

1421 F22

PC BOARDBACKPLANE

24V

POR

FAULT

R510k1/2W

R92.7k

R6620Ω1/8W

R215k1/8W

R72.8k1%

R82.21k1%

LT1074CT

GND

VIN VSW

VC FB

1µF

LTC1421

17

8

14

13

15

1811

1

24

12

3

2

192223

STAG

GERE

D CO

NNEC

TOR

4N25

5V10A

1421 F21

VICORVI-J30-CY

GATE IN

R15.1k

D14.3V

0.1µF

0.1µF

R310k

R2300Ω

100Ω

Q1

1N4148

4.7k

PC BOARDBACKPLANE

–48V

–48V

C10.1µF

100µF 100µF

+ +

– –1µF

21

LTC1421/LTC1421-2.5


WU UU

10 11 6 7 8 14 13 15 9

LTC1

421

1617

1819

2021

2223

1 24 4 5 3 2 12

STAGGERED CONNECTOR

S1

35

8

641

72

C1 1µF

16V

C3 220µ

F16

V×4

C4 0.1µ

F16

V

C5 10µF

16V

D1 1N41

48

Q2M

TD20

N03H

L

Q3 MTD

20N0

3HL

Q4 MTD

20N0

3HL

S2

S1: H

ARD

POW

ER/C

IRCU

IT B

REAK

ER R

ESET

S2: S

OFT

RESE

TLT

C143

0 PO

WER

-UP

THRE

SHOL

D: 4

.8V

ON 4

.25V

OFF

1421

F23

PC B

OARD

BACK

PLAN

E

5V

C2 0.1µ

F16

V

LTC1

430C

S8

V CC

PVCC

1

COM

PFB

SHDN

G1

GND

G2

R5 510Ω 5%

R8 100k

1%

R10.

003Ω

3W, 5

%Q1

MTD

20N0

3HL

C8 220p

FCE

RAM

IC

C747

00pF

CERA

MIC

C6 0.1µ

F16

V

C10

1µF

16V

R9 26.7

k1%

R10

10k

5%

R6 22Ω

5%

R7 7.5k

5%

R4 10k

1%

+

+

C933

0µF

10V ×6

+

2.7µ

H15

A

RESE

T

3.3V

10A

I MAX

= 1

5A

GND

µPV CC

1µF

43

21

10k

Figu

re 2

3. 5

V to

3.3

V Ho

t Sw

appa

ble

Supp

ly U

sing

the

LTC1

430C

S8

22

LTC1421/LTC1421-2.5


WU UU

109

1314811156

224

4

31

R10.005Ω

1WQ1

MTB50N06E

S1

LTC1421

IRF530

16

C11µF

171819202122

5 712

23

STAG

GERE

D CO

NNEC

TOR

2

1

5

6

3

C7100µF16V

5V8A

12V0.42A

–12V0.42A

+

1421 F24

ASTRODYNEASD10-48D12

CONTROL

+IN +OUT

–IN –OUT

C21µF

C5220µF100V

R3340Ω1/8W

R410k1/8W

R54.3k1/8W

R615k1/8W

C30.47µF

R71k1/8W

CLOAD

+

C6100µF16V

+

PC BOARDBACKPLANE

5V

–48V

Q32N5401

1µF

+

43

21

10k

Figure 24. 5V and –48V to ±12V Hot Swappable Supply

10

78141315

1

24

3

2

12

LTC1421

16

Q3VN2222

C20.1µF

C11µF

17181920212223

STAG

GERE

D CO

NNEC

TOR

CLOAD

+

100Ω

1k

12Ω

R10.005Ω1/2W

Q1MTB50N06E

Q2VN2222

S1

1421 F25

PC BOARDBACKPLANE

5V

R410k

R347.5k

5V8A

1µF

RESET

GND

µP

VCC

43

21

10k

Figure 25. Hot Swappable 5V Supply with Overvoltage Protection

23

LTC1421/LTC1421-2.5


WU UU

G Package24-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

Dimensions in inches (millimeters) unless otherwise noted.PACKAGE DESCRIPTIONU

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

0.037 – 0.045(0.940 – 1.143)

0.004 – 0.012(0.102 – 0.305)

0.093 – 0.104(2.362 – 2.642)

0.050(1.270)

BSC0.014 – 0.019

(0.356 – 0.482)TYP

0° – 8° TYP

NOTE 10.009 – 0.013

(0.229 – 0.330)0.016 – 0.050

(0.406 – 1.270)

0.291 – 0.299**(7.391 – 7.595)

× 45°0.010 – 0.029(0.254 – 0.737)

NOTE:1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDEDIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

***

S24 (WIDE) 1098

NOTE 1

0.598 – 0.614*(15.190 – 15.600)

22 21 20 19 18 17 16 15

1 2 3 4 5 6 7 8

0.394 – 0.419(10.007 – 10.643)

9 10

1314

11 12

2324

G24 SSOP 1098

0.13 – 0.22(0.005 – 0.009)

0° – 8°

0.55 – 0.95(0.022 – 0.037)

5.20 – 5.38**(0.205 – 0.212)

7.65 – 7.90(0.301 – 0.311)

1 2 3 4 5 6 7 8 9 10 11 12

8.07 – 8.33*(0.318 – 0.328)

2122 18 17 16 15 14 13192023241.73 – 1.99(0.068 – 0.078)

0.05 – 0.21(0.002 – 0.008)

0.65(0.0256)

BSC0.25 – 0.38

(0.010 – 0.015)NOTE: DIMENSIONS ARE IN MILLIMETERSDIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDEDIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

*

**

SW Package24-Lead Plastic Small Outline (Wide 0.300)

(LTC DWG # 05-08-1620)

Figure 26. Power-Up and Power-Down Sequence Controller

10116781413159

1

24

4

5

3

2

12

LTC1421

16 C20.1µF24V

C11µF16V

0.047µF

17181920212223

STAG

GERE

D CO

NNEC

TOR

+

C50.1µF25V

1k

R10.005Ω

1W

R31M5%,1/8W

Q1MTB50N06E

Q2MTB50N06E

S1

1421 F26

PC BOARDBACKPLANE

5V

3.3V

R6200k1%1/16W

R5330k1%1/16W

3.3V8A

5V8A

R20.005Ω

1W

CLOAD

CLOAD

+

RESET

GND

µP

VCC

R41k5%1/16W

1µF

43

21

43

21

10k

24

LTC1421/LTC1421-2.5

LINEAR TECHNOLOGY CORPORATION 1996

1421fc LT/LCG 0301 2K REV C • PRINTED IN USALinear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 www.linear-tech.com

TYPICAL APPLICATION

U

10116781413159

1

24

4

5

3

2

12

LTC1421

Q31/2 IRF7101

Q21/2 IRF7101

PCICONNECTOR

Q1IRF7413

1617

R1110Ω

C20.22µF25V

R430Ω

181920212223

Q4IRF7413

12V3.3A CIRCUIT BREAKER

3.3V11.5A CIRCUIT BREAKER

5V10A CIRCUIT BREAKER

R10100k

R135.1k

R520k

R1210Ω

C11µF16V

R10.005Ω

5%1/2W

R145.1k

R20.015Ω

5%1W

R85.62k1%1/16W

R30.005Ω

5%1W

POWER GOODRST #

SELECT BITS

BUS ENABLE

FAULT

12V500mA

3.3V7.5A

5V5A

ON/OFF

DATA BUS

–12V100mA

PCI POWERCONTROLLER

QuickSwitch

R7130k

R910Ω

Q5TP0610T

C31µF25V

R6100Ω1%1/16W

–12VNO CIRCUIT BREAKER

GND

1421 F27

ALL RESISTORS 5%, 1/16W EXCEPT WHERE NOTED

RST #

LOGIC

PCI PERIPHERALMOTHERBOARD OR BACKPLANE

1µF

43

21

43

21

4321

10k

Figure 27. PCI Power Controller

RELATED PARTSPART NUMBER DESCRIPTION COMMENTS

LTC1155 Dual High Side Switch Driver Short-Circuit Protection and Micropower Standby Operation

LTC1422 Hot Swap Controller in SO-8 System Reset Output with Programmable Delay

LTC1477/LTC1478 Single and Dual Protected High Side Switches Inrush Current Limited, Built-In 2A Short-Circuit Protection

LT1640L/LT1640H Negative Voltage Hot Swap Controller in SO-8 Operates from –10V to –80V

LT1641 High Voltage Hot Swap Controller in SO-8 Operates from 9V to 80V

LTC1642 Fault Protected Hot Swap Controller Operates Up to 16.5V, Protected to 33V

LTC1643L/LTC1643H PCI-Bus Hot Swap Controller 3.3V, 5V and ±12V in Narrow 16-Pin SSOP

LTC1645 2-Channel Hot Swap Controller Operates from 1.2V to 12V, Power Sequencing

LTC1647 Dual Hot Swap Controller Dual ON Pins for Supplies from 3V to 15V

FEATURES DESCRIPTIO U - Analog Devices · 2020. 2. 1. · 24 81214 1 0 6 I CCLO SUPPLY CURRENT (mA) VCCHI = 12V PIN FUNCTIONSUUU CON1 (Pin 1): TTL Level Input with a Pull-Up to VCCLO.

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