FDMS3604S - MOSFET – N-Channel, POWERTRENCH , Power … · • Notebook VCORE MARKING DIAGRAM PQFN8 5x6, 1.27P CASE 483AJ $Y = ON Semiconductor Logo &Z = Assembly Plant Code &3

© Semiconductor Components Industries, LLC, 2011

January, 2020 − Rev. 31 Publication Order Number:

FDMS3604S/D

FDMS3604S

MOSFET – N-Channel,POWERTRENCH�, PowerStage, Asymetric DualGeneral Description

This device includes two specialized N−Channel MOSFETs in adual PQFN package. The switch node has been internally connected toenable easy placement and routing of synchronous buck converters.The control MOSFET (Q1) and synchronous SyncFET™ (Q2) havebeen designed to provide optimal power efficiency.

FeaturesQ1: N−Channel• Max rDS(on) = 8 m� at VGS = 10 V, ID = 13 A

• Max rDS(on) = 11 m� at VGS = 4.5 V, ID = 11 AQ2: N−Channel• Max rDS(on) = 2.6 m� at VGS = 10 V, ID = 23 A

• Max rDS(on) = 3.5 m� at VGS = 4.5 V, ID = 21 A

• Low Inductance Packaging Shortens Rise/Fall Times, Resulting inLower Switching Losses

• MOSFET Integration Enables Optimum Layout for Lower CircuitInductance and Reduced Switch Node Ringing

• This Device is Pb−Free and is RoHS Compliant

Applications• Computing

• Communications

• General Purpose Point of Load

• Notebook VCORE

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MARKING DIAGRAM

PQFN8 5x6, 1.27PCASE 483AJ

$Y = ON Semiconductor Logo&Z = Assembly Plant Code&3 = Numeric Date Code&K = Lot Code22CA N7CC = Specific Device Code

See detailed ordering and shipping information on page 2 ofthis data sheet.

ORDERING INFORMATION

G1 D1D1 D1

G2S2

S2S2

D1

PHASE

(S1/D2)

PIN CONFIGURATION

4

3

2

1

5

6

7

Q18

Q2S2

S2

S2

G2

D1

D1

D1

G1

PHASE

$Y&Z&3&K

22CA

N7CC

Top Bottom

https://www.onsemi.com/PowerSolutions/parametrics/809/products

http://www.onsemi.com/

FDMS3604S

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MOSFET MAXIMUM RATINGS TA = 25°C Unless Otherwise Noted

Symbol Parameter Q1 Q2 Units

VDS Drain to Source Voltage 30 30 V

VDSt Drain to Source Transient Voltage ( tTransient < 100 ns) 33 33 V

VGS Gate to Source Voltage (Note 3) ±20 ±20 V

ID Drain Current−Continuous (Package limited) TC = 25 °C 30 40

A

−Continuous (Silicon limited) TC = 25 °C 60 130

−Continuous TA = 25 °C 13 (Note 1a) 23 (Note 1b)

−Pulsed 40 100

EAS Single Pulse Avalanche Energy 40 (Note 4) 60 (Note 5) mJ

PDPower Dissipation for Single Operation TA = 25 °C 2.2 (Note 1a) 2.5 (Note 1b)

WPower Dissipation for Single Operation TA = 25 °C 1.0 (Note 1c) 1.0 (Note 1d)

TJ, TSTG Operating and Storage Junction Temperature Range −55 to +150 °C

THERMAL CHARACTERISTICS

Symbol Parameter Q1 Q2 Unit

RθJA Thermal Resistance, Junction to Ambient 57 (Note 1a) 50 (Note 1b) °C/W

RθJA Thermal Resistance, Junction to Ambient 125 (Note 1c) 120 (Note 1d)

RθJC Thermal Resistance, Junction to Case 3.5 2

PACKAGE MARKING AND ORDERING INFORMATION

Device Marking Device Package Reel Size Tape Width Quantity

22CA N7CC FDMS3604S Power 56 13” 12 mm 3000 Units


FDMS3604S

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ELECTRICAL CHARACTERISTICS TJ = 25°C Unless Otherwise Noted

Symbol ParameterColumn Head

Test Conditions Type Min Typ Max Units

OFF CHARACTERISTICS

BVDSS Drain to Source Breakdown Voltage

ID = 250 �A, VGS = 0 V ID = 1 mA, VGS = 0 V

Q1Q2

3030

V

�BVDSS /�TJ

Breakdown Voltage Temperature Coefficient

ID = 250 �A, referenced to 25°C ID = 10 mA, referenced to 25°C

Q1Q2

1512

mV/°C

IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V Q1Q2

1500

�A

IGSS Gate to Source Leakage Current, Forwad

VGS = 20 V, VDS= 0 V Q1Q2

100100

nA

ON CHARACTERISTICS

VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 �A VGS = VDS, ID = 1 mA

Q1Q2

1.11.1

21.8

2.73

V

�VGS(th) /�TJ

Gate to Source Threshold VoltageTemperature Coefficient

ID = 250 �A, referenced to 25°C ID = 10 mA, referenced to 25°C

Q1Q2

−6−5

mV/°C

rDS(on) Drain to Source On Resistance VGS = 10 V, ID = 13 A VGS = 4.5 V, ID = 11 AVGS = 10 V, ID = 13 A , TJ = 125°C

Q1 5.88.57.8

811

10.8

m�

VGS = 10 V, ID = 23 A VGS = 4.5 V, ID = 21 AVGS = 10 V, ID = 23 A , TJ = 125°C

Q2 2.03.02.6

2.63.54

gFS Forward Transconductance VDS = 5 V, ID = 13 A VDS = 5 V, ID = 23 A Q1Q2

61130

S

DYNAMIC CHARACTERISTICS

Ciss Input Capacitance Q1:VDS = 15 V, VGS = 0 V, f = 1 MHzQ2:VDS = 15 V, VGS = 0 V, f = 1 MHz

Q1Q2

13403240

17854310

pF

Coss Output Capacitance Q1Q2

4851230

6451635

pF

Crss Reverse Transfer Capacitance Q1Q2

53103

80155

pF

Rg Gate Resistance Q1Q2

0.20.2

0.60.8

23

�

SWITCHING CHARACTERISTICS

td(on) Turn−On Delay Time Q1:VDD = 15 V, ID = 13 A, RGEN = 6 �Q2:VDD = 15 V, ID = 23 A, RGEN = 6 �

Q1Q2

8.213

1623

ns

tr Rise Time Q1Q2

2.54.8

1010

ns

td(off) Turn−Off Delay Time Q1Q2

2031

3250

ns

tf Fall Time Q1Q2

2.23.4

1010

ns

Qg Total Gate Charge VGS = 0 V to 10 V Q1VDD = 15 V, ID = 13 AQ2VDD = 15 V, ID = 23 A

Q1Q2

2147

2966

nC

Qg Total Gate Charge VGS = 0 V to 4.5 V Q1Q2

1022

1431

nC

Qgs Gate to Source Gate Charge Q1Q2

3.99

nC

Qgd Gate to Drain “Miller” Charge Q1Q2

3.15.5

nC


FDMS3604S

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ELECTRICAL CHARACTERISTICS TJ = 25°C Unless Otherwise Noted (continued)

Symbol UnitsMaxTypMinTypeColumn Head

Test ConditionsParameter

DRAIN−SOURCE DIODE CHARACTERISTICS

VSD Source to Drain Diode Forward Voltage

VGS = 0 V, IS = 13 A (Note 2)VGS = 0 V, IS = 23 A (Note 2)

Q1Q2

0.80.8

1.21.2

V

trr Reverse Recovery Time Q1IF = 13 A, di/dt = 100 A/�s Q2IF = 23 A, di/dt = 300 A/�s

Q1Q2

2532

4051

ns

Qrr Reverse Recovery Charge Q1Q2

939

1862

nC

1. R�JA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R�JC is guaranteedby design while R�CA is determined by the user’s board design.

a. 57 °C/W when mounted on a 1 in2 pad of 2 oz copper

c. 125 °C/W when mounted on a minimum pad of 2 oz copper

b. 50 °C/W when mounted on a 1 in2 pad of 2 oz copper

d. 120 °C/W when mounted on a minimum pad of 2 oz copper

2. Pulse Test: Pulse Width < 300 �s, Duty cycle < 2.0%.3. As an N−ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.4. EAS of 40 mJ is based on starting TJ = 25°C; N−ch: L = 1 mH, IAS = 9 A, VDD = 27 V, VGS = 10 V. 100% test at L = 0.3 mH, IAS = 14 A.5. EAS of 60 mJ is based on starting TJ = 25°C; N−ch: L = 1 mH, IAS = 11 A, VDD = 27 V, VGS = 10 V. 100% test at L = 0.3 mH, IAS = 18 A.


FDMS3604S

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TYPICAL CHARACTERISTICS (Q1 N−CHANNEL) TJ = 25°C Unless Otherwise Noted

Figure 1. On−Region Characteristics

0.0 0.2 0.4 0.6 0.8 1.00

10

20

30

40

VGS = 4.5 V

VGS = 3.5 V

VGS = 6 V

VGS = 4 V

PULSE DURATION = 80DUTY CYCLE = 0.5% MAX

VGS = 10 V

I D, D

RA

IN C

UR

RE

NT

(A

)

VDS, DRAIN TO SOURCE VOLTAGE (V)

0 10 20 30 400

1

2

3

4

VGS = 6 V

VGS = 3.5 V PULSE DURATION = 80DUTY CYCLE = 0.5% MAX

NO

RM

ALI

ZED

DR

AIN

TO

SO

UR

CE

ON−R

ES

ISTA

NC

E

ID, DRAIN CURRENT (A)

VGS = 4 V

VGS = 4.5 V

VGS = 10 V

−75 −50 −25 0 25 50 75 100 125 1500.6

0.8

1.0

1.2

1.4

1.6ID = 13 AVGS = 10 V

NO

RM

AL

IZE

D D

RA

IN T

O S

OU

RC

E O

N−R

ES

ISTA

NC

E

TJ, JUNCTION TEMPERATURE (oC)2 4 6 8 10

0

4

8

12

16

20

TJ = 125 oC

ID = 13 A

TJ = 25oC

VGS, GATE TO SOURCE VOLTAGE (V)

r DS

(on)

,D

RA

IN T

O

SO

UR

CE

ON−R

ES

IST

AN

CE

( mW

) PULSE DURATION = 80DUTY CYCLE = 0.5% MAX

Figure 5. Transfer Characteristics

1.5 2.0 2.5 3.0 3.5 4.00

10

20

30

TJ = 150 oCVDS = 5 V

PULSE DURATION = 80msDUTY CYCLE = 0.5% MAX

TJ = −55oC

TJ = 25 oC

I D, D

RA

IN C

UR

RE

NT

(A

)

VGS, GATE TO SOURCE VOLTAGE (V)0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.001

0.01

0.1

1

10

40

TJ = −55oC

TJ = 25 oC

TJ = 150 oC

VGS = 0 V

I S, R

EV

ER

SE

DR

AIN

CU

RR

EN

T (A

)

VSD, BODY DIODE FORWARD VOLTAGE (V)0.01 0.1 1 10 1000.01

0.1

1

10

100

DC

100 ms

10 ms

1 ms

1 s

I D, D

RA

IN C

UR

RE

NT

(A

)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA ISLIMITED BY rDS(on)

SINGLE PULSETJ = MAX RATED

= 125oC/W

TA = 25oC

10 s

100

200 10−4 10−3 10−2 10−1 1 10 100 10000.1

1

10

100

1000

SINGLE PULSER�JA = 125�C/W

TA = 25�C

P( P

K) ,

PE

AK

TR

AN

SIE

NT

PO

WE

R (W

)

t, PULSE WIDTH (sec)

Figure 2. Normalized On−Resistance vs DrainCurrent and Gate Voltage

Figure 3. Normalized On Resistancevs Junction Temperature

Figure 4. On−Resistance vs Gate to SourceVoltage

Figure 5. Transfer Characteristics Figure 6. Source to Drain DiodeForward Voltage vs Source Current

�s

�s

�s

�s

R�JA


FDMS3604S

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TYPICAL CHARACTERISTICS (Q1 N−CHANNEL) TJ = 25°C Unless Otherwise Noted (continued)

Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage

Figure 9. Unclamped Inductive SwitchingCapability

Figure 10. Maximum Continuous Drain Current vs Case Temperature

Figure 11. Forward Bias Safe Operating Area Figure 12. Single Pulse Maximum PowerDissipation

0 5 10 15 20 250

2

4

6

8

10ID = 13 A

VDD = 20 V

VDD = 10 V

VG

S, G

AT

E T

O S

OU

RC

E V

OL

TA

GE

(V

)

Qg, GATE CHARGE (nC)

VDD = 15 V

0.1 1 10 3010

100

1000

2000

f = 1 MHz

VGS = 0 V

CA

PA

CIT

AN

CE

(p

F)


Crss

Coss

Ciss

0.01 0.1 1 10 1001

10

20

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I AS, A

VA

LA

NC

HE

CU

RR

EN

T (

A)

25 50 75 100 125 1500

20

40

60

80

100

Limited by Package

VGS = 4.5 V

R�JC = 3.5 oC/W

VGS = 10 V

I D,D

RA

IN C

UR

RE

NT

(A

)

TC, CASE TEMPERATURE (oC)

0.01 0.1 1 10 1000.01

0.1

1

10

100

DC

100 ms

10 ms

1 ms

1 s

I D,

DR

AIN

CU

RR

EN

T (

A)


THIS AREA ISLIMITED BY

SINGLE PULSE

TJ = MAX RATED

= 125oC/W

TA = 25oC

10 s

100

200 10−4 10−3 10−2 10−1 1 10 100 10000.1

1

10

100

1000

SINGLE PULSE

R�JA = 125oC/W

TA = 25oC

P( P

K) ,

PE

AK

TR

AN

SIE

NT

PO

WE

R (W

)


rDS(on)

R�JA


FDMS3604S

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Figure 13. Junction−to−Ambient Transient Thermal Response Curve

10−4 10−3 10−2 10−1 11 0 100 10000.001

0.01

0.1

1

SINGLE PULSE

R�JA = 125 oC/W

DUTY CYCLE−DESCENDING ORDER

NO

RM

ALI

ZED

TH

ER

MA

LIM

PE

DA

NC

E,

Z�JA

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

2

PDM

t1t2

NOTES:DUTY FACTOR: D = t1/t2PEAK TJ = PDM x Z�JA x R�JA + TA(Note 1c)


FDMS3604S

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TYPICAL CHARACTERISTICS (Q2 N−CHANNEL) TJ = 25°C Unless Otherwise Noted

Figure 14. On−Region Characteristics Figure 15. Normalized On−Resistance vs DrainCurrent and Gate Voltage

Figure 16. Normalized On−Resistance vs JunctionTemperature

Figure 17. On−Resistance vs Gate to SourceVoltage

Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode Forward Voltagevs Source Current

0.0 0.2 0.4 0.6 0.8 1.00

20

40

60

80

100

VGS = 4.5 V

VGS = 3 V

VGS = 3.5 V

VGS = 4 V


VGS = 10 V

I D, D

RA

IN C

UR

RE

NT

(A

)


0 20 40 60 80 1000

2

4

6

8

VGS = 3 V

VGS = 3.5 V


NO

RM

AL

IZE

DD

RA

IN T

O S

OU

RC

E O

N−R

ES

ISTA

NC

E

ID, DRAIN CURRENT (A)

VGS = 4 V VGS = 4.5 V

VGS = 10 V

−75 −50 −25 0 25 50 75 100 125 1500.8

1.0

1.2

1.4

1.6ID = 23 AVGS = 10 V

NO

RM

ALI

ZED

DR

AIN

TO

SO

UR

CE

ON−R

ES

IST

AN

CE

TJ, JUNCTION TEMPERATURE (oC)

2 4 6 8 100

3

6

9

12

TJ = 125 oC

ID = 23 A

TJ = 25 oC

VGS, GATE TO SOURCE VOLTAGE (V)

r DS

(on)

,D

RA

IN T

O

SO

UR

CE

ON−R

ES

IST

AN

CE( m

�) PULSE DURATION = 80

DUTY CYCLE = 0.5% MAX

1.5 2.0 2.5 3.0 3.5 4.00

20

40

60

80

100

TJ = 125 oC

VDS = 5 V


TJ = −55oC

TJ = 25 oC

I D, D

RA

IN C

UR

RE

NT

(A

)

VGS, GATE TO SOURCE VOLTAGE (V)0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.001

0.01

0.1

1

10

100

TJ = −55oC

TJ = 25 oC

TJ = 125 oC

VGS = 0 V

I S, R

EV

ER

SE

DR

AIN

CU

RR

EN

T (A

)

VSD, BODY DIODE FORWARD VOLTAGE (V)

�s

�s

�s

�s


FDMS3604S

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Figure 20. Gate Charge Characteristics Figure 21. Capacitance vs Drain to Source Voltage

Figure 22. Unclamped Inductive SwitchingCapability

Figure 23. Maximum Continuous Drain Current vs Case Temperature

Figure 24. Forward Bias Safe Operating Area Figure 25. Single Pulse Maximum PowerDissipation

0 10 20 30 40 500

2

4

6

8

10

ID = 23 A

VDD = 20 V

VDD = 10 V

VG

S, G

AT

E T

O S

OU

RC

E V

OL

TA

GE

(V

)

Qg, GATE CHARGE (nC)

VDD = 15 V

0.1 1 10 3010

100

1000

10000

f = 1 MHz

VGS = 0 V

CA

PA

CIT

AN

CE

(pF)


Crss

Coss

Ciss

0.01 0.1 1 10 100 10001

10

50

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I AS, A

VA

LA

NC

HE

CU

RR

EN

T (

A)

25 50 75 100 125 1500

40

80

120

160

R�JC = 2 oC/W

VGS = 4.5 V

Limited by Package

VGS = 10 V

I D,D

RA

IN C

UR

RE

NT

(A

)

TC, CASE TEMPERATURE (oC)

0.01 0.1 1 10 1002000.01

0.1

1

10

100200

DC

100 ms

10 ms

1 ms

1s

I D, D

RA

IN C

UR

RE

NT

(A

)


THIS AREA ISLIMITED BY rDS(on)

SINGLE PULSE

TJ = MAX RATED

R�JA = 120 oC/W

TA = 25 oC

10s

10−3 10−2 10−1 1 10 100 10000.1

1

10

100

1000

SINGLE PULSE

R�JA = 120oC/W

TA = 25oC

P( P

K),

PE

AK

TR

AN

SIE

NT

PO

WE

R (

W)



FDMS3604S

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Figure 26. Junction−to−Ambient Transient Thermal Response Curve

10−3 10−2 10−1 1 10 100 10000.001

0.01

0.1

1

2

SINGLE PULSE

R�JA = 120 o

DUTY CYCLE−DESCENDING ORDER

NO

RM

AL

IZE

D T

HE

RM

AL

IMP

ED

AN

CE

,Z�JA

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

PDM

t1t2

NOTES:DUTY FACTOR: D = t1/t2PEAK TJ = PDM x Z�JA x R�JA + TA

C/W

(Note 1c)

SyncFET Schottky Body Diode CharacteristicsON Semiconductor’s SyncFET process embeds a

Schottky diode in parallel with PowerTrench MOSFET.This diode exhibits similar characteristics to a discreteexternal Schottky diode in parallel with a MOSFET.Figure 27 shows the reverse recovery characteristic of theFDMS3604S.

Schottky barrier diodes exhibit significant leakage at hightemperature and high reverse voltage. This will increase thepower in the device.

Figure 27. FDMS3604S SyncFET Body Diode Reverse Recovery Characteristics

Figure 28. SyncFET Body Diode Reverse Leakage versus Drain−source Voltage

0 50 100 150 200−5

0

5

10

15

20

25

didt = 300 A/�s

CU

RR

EN

T (

A)

TIME (ns)0 5 10 15 20 25 30

10−6

10−5

10−4

10−3

10−2

TJ = 125 oC

TJ = 100 oC

TJ = 25 oC

I DS

S, R

EV

ER

SE

LE

AK

AG

E C

UR

RE

NT

(A)

VDS, REVERSE VOLTAGE (V)


FDMS3604S

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APPLICATION INFORMATION

Switch Node Ringing SuppressionON Semiconductor’s Power Stage products incorporate a

proprietary design* that minimizes the peak overshoot,ringing voltage on the switch node (PHASE) without theneed of any external snubbing components in a buck

converter. As shown in the Figure 29, the Power Stagesolution rings significantly less than competitor solutionsunder the same set of test conditions.

Figure 29. Power Stage Phase Node Rising Edge, High Turn On

Power Stage Device Competitorrs Solution

*Patent Pending

Figure 30. Shows the Power Stage in a Buck Converter Topology


FDMS3604S

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Recommended PCB Layout GuidelinesAs a PCB designer, it is necessary to address critical issues

in layout to minimize losses and optimize the performanceof the power train. Power Stage is a high power densitysolution and all high current flow paths, such as VIN (D1),PHASE (S1/D2) and GND (S2), should be short and wide

for better and stable current flow, heat radiation and systemperformance. A recommended layout procedure isdiscussed below to maximize the electrical and thermalperformance of the part.

Figure 31. Recommended PCB Layout

Following is a guideline, not a requirement which the PCB designer should consider:1. Input ceramic bypass capacitors C1 and C2 must

be placed close to the D1 and S2 pins of PowerStage to help reduce parasitic inductance and HighFrequency conduction loss induced by switchingoperation. C1 and C2 show the bypass capacitorsplaced close to the part between D1 and S2. Inputcapacitors should be connected in parallel close tothe part. Multiple input caps can be connecteddepending upon the application

2. The PHASE copper trace serves two purposes; Inaddition to being the current path from the PowerStage package to the output inductor (L), it alsoserves as heat sink for the lower FET in the PowerStage package. The trace should be short and wideenough to present a low resistance path for thehigh current flow between the Power Stage and theinductor. This is done to minimize conductionlosses and limit temperature rise. Please note thatthe PHASE node is a high voltage and highfrequency switching node with high noisepotential. Care should be taken to minimizecoupling to adjacent traces. The reference layoutin Figure 31 shows a good balance between thethermal and electrical performance of Power Stage

3. Output inductor location should be as close aspossible to the Power Stage device for lowerpower loss due to copper trace resistance. Ashorter and wider PHASE trace to the inductorreduces the conduction loss. Preferably the PowerStage should be directly in line (as shown inFigure 32) with the inductor for space savings andcompactness

4. The POWERTRENCH Technology MOSFETsused in the Power Stage are effective atminimizing phase node ringing. It allows the partto operate well within the breakdown voltagelimits. This eliminates the need to have an externalsnubber circuit in most cases. If the designerchooses to use an RC snubber, it should be placedclose to the part between the PHASE pad and S2pins to dampen the high−frequency ringing

5. The driver IC should be placed close to the PowerStage part with the shortest possible paths for theHigh Side gate and Low Side gates through a widetrace connection. This eliminates the effect ofparasitic inductance and resistance between thedriver and the MOSFET and turns the devices onand off as efficiently as possible. At


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higher−frequency operation this impedance canlimit the gate current trying to charge theMOSFET input capacitance. This will result inslower rise and fall times and additional switchinglosses. Power Stage has both the gate pins on thesame side of the package which allows for backmounting of the driver IC to the board. Thisprovides a very compact path for the drive signalsand improves efficiency of the part

6. S2 pins should be connected to the GND planewith multiple vias for a low impedance grounding.Poor grounding can create a noise transient offsetvoltage level between S2 and driver ground. Thiscould lead to faulty operation of the gate driverand MOSFET

7. Use multiple vias on each copper area tointerconnect top, inner and bottom layers to helpsmooth current flow and heat conduction. Viasshould be relatively large, around 8 mils to 10mils, and of reasonable inductance. Critical highfrequency components such as ceramic bypasscaps should be located close to the part and on thesame side of the PCB. If not feasible, they shouldbe connected from the backside via a network oflow inductance vias

SyncFET IS trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or othercountries.


PQFN8 5X6, 1.27P (SAWN TYPE)CASE 483AJ

ISSUE ADATE 08 FEB 2021

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

98AON13659GDOCUMENT NUMBER:

DESCRIPTION:

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PAGE 1 OF 2PQFN8 5X6, 1.27P

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

PQFN8 5X6, 1.27P (PUNCHED TYPE)CASE 483AJ

ISSUE ADATE 08 FEB 2021

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

98AON13659GDOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2PQFN8 5X6, 1.27P

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

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FDMS3604S - MOSFET – N-Channel, POWERTRENCH , Power … · • Notebook VCORE MARKING DIAGRAM PQFN8 5x6, 1.27P CASE 483AJ $Y = ON Semiconductor Logo &Z = Assembly Plant Code &3

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