Fault Tolerant Computingmalaiya/530/4testgen.pdf · 2006. 9. 14. · – Tafertshofer 1997: x25057 • Test generation is an “np-complete problem”. No algorithm is known ,which

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September 14, 2006 1

Fault Tolerant ComputingFault Tolerant ComputingCS 530CS 530

Test GenerationTest Generation

Yashwant K. MalaiyaColorado State University

September 14, 2006 Fault Tolerant Computing©Y.K. Malaiya

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Test Generation: Combinational

•Algebraic: Boolean difference•Structural: D-notation•Sensitized path, single-path propagation•D-algorithm•Fault-collapsing, Test set minimization

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Test generation: Some Basics (1)

• Approaches:– Symbolic– Based on heuristics

• Needed:– Fault excitation– Error propagation

• Function: normal f, faulty fαααα with fault αααα• Vector â=(a1, a2, ..an) is a test if f(â)≠≠≠≠fαααα(â)• All tests are contained in expression T = f⊕⊕⊕⊕fαααα

Input Output


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Test generation: Some Basics (2)

• All tests are contained in expression T = f⊕⊕⊕⊕fαααα

A

B

S-a-1

011110

10A

011010

10A

fααααf

• AB (01) is a test. The only test.

B B

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Boolean Difference Method• Assume input xi has fault αααα which is s-a-0. Thenset of tests is given by

)1()0(

),,1,,(),,0,,(

),,,(),,,,(

111111

1,11111

ii

niinii

niiiniiii

ii

ff

xxxxfxxxxf

xxxxxfxxxxxfdxdf

where

dxdf

xT

⊕=⊕=

⊕=

=

+−+−

+−+−

��

��

• Note that Boolean Difference df/dxi represents conditions for which output is susceptible to input i.


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Boolean difference (2)

• Proof: – Using Shanon’s expansion theorem– f(xi)= xi fi(0)+ xi fi(1)– Note that fαααα(X)=fi(0)

))0()1((

)0()1()0()1(

)0())1()0((

)()(

iii

iiiiii

iiiii

ffx

ffxffx

ffxfx

XfXfT

⊕=+=

⊕+=⊕= α What about

xi s-a-1?

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Boolean Difference: ExampleAB

C

f(A,B,C)=AB+BC

• Consider fault B s-a-1

•Tests are T=B df/dB

df/dB = f(A,0,C) ⊕⊕⊕⊕ f(A,1,C)

=C⊕⊕⊕⊕A =AC+AC

Hence

T =B (AC+AC) = ABC+ABC

=(100,001)

x


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Boolean Difference: Internal Nodes

• Consider an internal node h=h(X) s-a-0. Express the original function f(X) as f’(X,h). Tests for h s-a-0 are given by h(X) df’(X,h)/dh.

AB

C

hS-a-1

f(A,B,C)=AB+BC h(A,B)=AB

F’(B,C,h)=h+BC

df’/dh = f’(0,B,C)⊕⊕⊕⊕f’(1,B,C) = (BC) ⊕⊕⊕⊕1

= BC =B+C

T = h df’/dh = (AB)(B+C) = (A+B)(B+C) = AB+AC+BC

=010, 011, 000, 100 (four vectors!)00011

11010

10110100BC

A

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D-Notation• Notation: Line has value D if it is 1 normally and 0

in presence of the fault.

1

1

s-a-0

DD

s-a-1

0 DD

1

Rules of propagation:

D

?? D

??

XOR

OR, NOR

AND, NAND

All other inputs

Gate


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Single Path Propagation

• Excitation: – h=0 normally. Need

A,B=0,0

• Propagation:– Other AND input:1– Other OR input: 0

• Justification: – C=1 already. E=x (don’t

care)

• Test is (0,0,1,x)

h S-a-1A

B

C

E

D

D

Write on diagram

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Schneider’s Counterexample• Try single path 2-6-8• Excitation: D at 2: b,c=0,0• Forward trace:

– D at 6: d=0– D at 8: 4,5,7=0,0,0

• Implication:– Since b=d=0, 3=1, 7=0

• Line Justification (backward trace): – For 5=0: a=1– Hence 1=0, 4=1 (!) – Inconsistency.

• Single path propagation fails.

ac

b

b

c

bd

c

1

2

3

4

5

6

7

8

a

dS-a-0

• Multiple path propagation thru 5 and 6 works!

• b,c=0,0; a,d=0,0 Thus (0,0,0,0) is a test.


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D-Algorithm

• Extension of single-path propagation• Applicable for any type of elements (inc. gates)• Info used:• Each normal element:

– position – functional description– How to drive a D orD through it

• Faulty element: – how to get a D orD at its output

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D-Algorithm: To find test for a given fault

• Excitation: Get D orD at a faulty element output– Implication*

• D-drive: move D-frontier forward– Implication*– Repeat until a D orD at one output*

• Line justification– Justify all specified outputs of elements by having

suitable inputs*

• * Backtrack to last point a choice existed

The ugly part


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D-Algo: example

D

1

2

3

4

5

6

7

8

9S-a-1

• Fault: NOR output s-a-1

• Excitation: 1,2 = 1,0 gets aD at 5

• Propagation to 9: through 7 or 8? (Choice)

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D-Algorithm Ex (2)

DD10D010φφφφ1,2←←←←4

DD10D01013←←←←6

DD10D0014←←←←7

DD10D018→→→→9

D0D015→→→→8

D01

987654321

1

2

3

4

5

6

7

8

9S-a-1

Try: 5-8-9

No!

Backtrack

D-drive

Justifi-

cation


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D-Algorithm Ex (3)

D1D1D10013←←←←6

D1D1D1016←←←←8

D1DD1017→→→→9

DD1015→→→→7

D01

987654321

1

2

3

4

5

6

7

8

9S-a-1

Try: 5-7-9

Yes!

D-drive

Justifi-

cation

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Combinational ATPG Algorithms

• Automatic Test Pattern Generation algorithms: searches are based on heuristics that generally work faster– PODEM 1981: x7 speedup relative to D-algorithm– FAN 1983: x23– SOCRATES: x1574– EST8765:x8765– Tafertshofer 1997: x25057

• Test generation is an “np-complete problem”. No algorithm is known which will solve it in polynomial time (i.e. in nr time,

n=number of elements, r is some finite constant)• It has been suggested that often computation time needed is of

the order of n3.


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Fault Collapsing (1)

• Fault Collapsing: reducing the number of faults to be considered.

• Equivalence: Faults αααα and ββββ are equivalent if fαααα=fββββ.

All s-a-0 equivalent

All s-a-1 equivalent

•For an N-input gate only n+2 faults need to be considered

•Ex: NAND gate:

•Any input s-a-0, output s-a-1 (1)

•One input s-a-1 (n)

•Output s-a-0 (0)

•Termed Equivalence fault collapsing

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• Dominance: A fault αααα dominates fault ββββ if Tββββ ⊂⊂⊂⊂Tαααα.

• For detection only fault ββββ needs to be considered. For location, both need to be considered separately (if distinguishable)

Tαααα

Tββββ

αααα s-a-1ββββ s-a-1x

x

Tαααα= 0xx, x0x, xx0

Tββββ= 011

∴∴∴∴Tββββ ⊂⊂⊂⊂Tαααα

(0,1,1) will test for both αααα and ββββ.

!

Example:


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• Equivalence + Dominance:– Only n+1 faults/gate for detection, n=# of inputs

• AND, NAND: Each input s-a-1 (n)Any input s-a-0 (1)

• OR, NOR: Each input s-a-0 (n)Any input s-a-1 (1)

• Theorem: In a fan-out free combinational circuit, any test set that detects all stuck faults on primary inputs will detect all stuck faults in the network.

• If there is fan-out?

SSFs=single stuck faults

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• Theorem: In a combinational circuit, any test set that detects all stuck faults on – all primary inputs and – All branches of fanout points

will detect all stuck faults in the network.

Checkpoints

We have applied & demonstrated it for software

testing


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Checkpoints

• 12 nodes, 24 faults• Checkpoints: a,b,c,d,e; g,h : 7x2=14 faults• a s-a-0 equi b s-a-0 �delete b s-a-0 • h s-a-0 equi d s-a-0 �delete h s-a-0• (g s-a-1 equi f s-a-1) and (f s-a-1 domi a s-a-1)

a s-a-1 covers g s-a-1 �delete g s-a-1• Find one more!

a

bc

d

e

f

g

h i

j

k

m

From 24 to 10 faults

E1i1 i1h1 e1

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Test Set Reduction

• Generally one pattern tests for several faults• On a sensitized path a s-a-0 (s-a-1) on all nodes

with D (D) will be detected.• With a given vector, several nodes will be critical.

a

b

c

d

e

f

g1c0c

1c

1c

100

(1100) will detect a s-a-0, b s-a-0,

e s-a-0 and g s-a-0

Example:


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Test Set Compaction

• Minimize the number of patterns.

Example:

a

bc

√√√√

c-0

√√√√√√√√11

√√√√√√√√10

√√√√√√√√01

√√√√00

c-1b-1b-0a-1a-0

Minim

um set

In practice heuristics are used, complete optimization is not needed.

faults

tests

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Coverage & Simulation• Coverage: fraction of all possible faults covered by a

test set. • Simulation can be used to determine coverage.• Complete (100%) coverage is not feasible for

complex systems.

Obtain coverage by simulation

Obtain a test set

Enough?

Get more tests

Done


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Redundancy

• A combinational circuit that contains an undetectable stuck-at fault is said to be redundant.Example:

0111

00110

10110100bc

a

c

b

F= ab+ ac +bc

a

ac

cb

S-a-1 untestable

redundant

b

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Redundancy: Why and How

• Redundancy is sometimes deliberately added.• Incomplete combinational or sequential minimization leaves

redundancy.• To avoid:

– Better minimization– If untestable faults spotted after design, do this

…Input s-a-1

Remove inputInput s-a-0OR (NOR)

Replace gate by 0 (1)Input s-a-0

Remove inputInput s-a-1AND (NAND)

How to spot redundancy? It is hard.


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Redundancy: (-) & (+)• Test generation algos spend a lot of time trying to

find a test for an untestable fault.• A detectable fault f may become undetectable in

presence of an undetectable fault g (below).• Two undetectable faults can become detectable if

simultaneously present.A

B

C

d Normal Z = ABZ

αααα: C s-a-1 untestable Z = AB

ββββ: d s-a-0 testable Z = ABC

(αααα,ββββ): untestable Z = AB

Example:

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Why redundancy is used

• To avoid glitches in asynchronous circuits• In CMOS (switch-level redundancy):

– Reduce power consumption– Symmetrical rise/fall times

• For fault tolerance• Absolute optimization may take too much CPU

time.


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Fault distinction

• Preset test set: no decision making during testing

• Adaptive: successive narrowing down

Example: There is a fault.

teststestsdoesn’tf3

doesn’tteststestsf2

testsdoesn’ttestsf1

Test t3Test t2Test t1Fault

•Preset: Get response to t1,t2,t3

Then Identify

•Adaptive:

Apply t1

No detection

∴∴∴∴f3

DetectionApply t3

Detectionf1

No det.

f2

Assuming equal probability, av. # of tests

to identify = 1x 1/3+2x1/3+2x1/3 = 1.7!

Also there is

guided probe

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Test Generation: Summary

• Boolean difference

• D (normally 1), excitation and propagation• D-algorithm: backtrack if needed• Equivalence/dominance collapsing, checkpoints• Test set compaction• Fault coverage and simulation• Redundancy: undesirable during testing• Fault distinction: preset vs. adaptive

)1()0( iiii

i ffdxdf

dxdf

xT ⊕==

Fault Tolerant Computingmalaiya/530/4testgen.pdf · 2006. 9. 14. · – Tafertshofer 1997: x25057 • Test generation is an “np-complete problem”. No algorithm is known ,which

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