Fault-Tolerant design of RF front- Fault-Tolerant design of RF front- end circuits end circuits P.R. Mukund, Ph.D. Gleason Professor of Electrical Engineering Director, RF/Analog/Mixed-signal Lab (RAMLAB) Rochester Institute of Technology Rochester, NY 14623
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Fault-Tolerant design of RF front-end circuits P.R. Mukund, Ph.D. Gleason Professor of Electrical Engineering Director, RF/Analog/Mixed-signal Lab (RAMLAB)
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Fault-Tolerant design of RF front-end circuitsFault-Tolerant design of RF front-end circuits
P.R. Mukund, Ph.D.Gleason Professor of Electrical Engineering
Director, RF/Analog/Mixed-signal Lab (RAMLAB)
Rochester Institute of TechnologyRochester, NY 14623
Fault-Tolerant Design of RF Front end Circuitry
FundingFunding
Henning Braunisch
Industry Liaisons
Hosam Haggag
Ronald McBean(Motorola)
This work was funded by the Semiconductor Research Corporation
Fault-Tolerant Design of RF Front end Circuitry
MotivationMotivation
SoC, SiP implementations High levels of integration
Complex interaction between RF, analog, & digital domains
Heightened sensitivity to package parasitics, wide tolerances
Current sensing: HF transient current has performance info
S21 & S22
degraded
No effect on S11
S22 & S21 degraded Resistor in return path!
Small value
S22 & S21 unaffected S11 degraded Regain by co-design! NF marginally Dynamic range marginally
√
Fault-Tolerant Design of RF Front end Circuitry
Non-intrusive sensingNon-intrusive sensing
Eliminate resistor for circuits with source-degenerative coils No measurable intrusion on LNA performance Over a narrow-frequency range, the source-coil can provide
similar current-information as the resistor
Gain and S22 sensed from source coil of mixer: accounts for matching network
of RF front end circuitry”, IEEE Transactions on Circuits and Systems, Dec 2005 Tejasvi Das, Anand Gopalan, Clyde Washburn and P.R. Mukund, “Towards
Fault-tolerant RF front-ends”, Journal of Electronic Testing (JETTA), Accepted for publication (Issue release Sep.06)
Anand Gopalan, M. Margala and P.R. Mukund, “A current based self-test methodology for RF front-end circuits”, Microelectronics Journal, No.36, Aug 2005
Anand Gopalan, Tejasvi Das, Clyde Washburn and P.R. Mukund, “BiST for Multi-GHz CMOS RF Front-ends”, IEEE Transactions on Circuits and Systems (Under review)
Conference Papers
“Self-calibration of Gain and Output match in LNAs”, IEEE ISCAS May 2006, Kos, Greece
“Towards Fault-Tolerant RF Front-Ends: On-Chip Input Match Self-Correction of LNAs”, The IEEE Mixed-signal Test Workshop, June 2005, Cannes, France.
“Dynamic Input match correction in RF Low Noise Amplifiers”, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 2004, Cannes, France
Fault-Tolerant Design of RF Front end Circuitry
PublicationsPublications (2)(2)
Conference papers (contd.)
“Use of Source Degeneration for Non-Intrusive BIST of RF Front-end Circuits”, Proceedings of the International Symposium on Circuits and Systems, Kobe, Japan, May 2005
An Ultra-fast, on-chip BiST for RF LNAs”, 18th IEEE International Conference on VLSI Design, India, Jan. 2005.
Fault-Tolerant Design of RF Front end Circuitry
References References (1)(1)
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[2] B. A. Floyd, C.-M. Hung, K. K. O, “Intra-Chip Wireless Interconnect for Clock Distribution Implemented With Integrated Antennas, Receivers, and Transmitters”, IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 543-552, May 2002.
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[4] J.M.V Santos Dos, J.M.M Ferreira, “Fault-tolerance: new trends for digital circuits”IEEE International Conference on Electronics, Circuits and Systems, Vol 3, pp. 237 – 240, Sept. 1998
[5] Michael S. Heutmaker, Duy K. Le, “Architecture for self-test of a wireless communication system using sampled IQ modulation and boundary scan”, IEEE Communications Magazine, Vol. 37, No. 6, pp. 98-102, June 1999.
[6] Madhuri Jarwala, Duy Le, Michael S Heutmaker, “End-to-end test strategy for wireless systems” Proceedings of the IEEE International Test Conference (TC), pp. 940-946, 1995.
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[8] Rajsuman R., “Iddq testing for CMOS VLSI”, Proceedings of the IEEE, Vol.88 No. 4, pp. 544 –568, April 2000.
Fault-Tolerant Design of RF Front end Circuitry
References References (2)(2)
[9] Isern E., Figueras J., “Test generation with high coverages for quiescent current testing of bridging faults in combinational systems”, Proceedings of the International Test Conference, pp. 73 -82, October 1993.
[10] A. Gopalan, T. Das, C. Washburn and P.R. Mukund, “An ultra-fast on-chip BiST for RF CMOS LNAs”, Proceedings of 18th International conference on VLSI Deign, January 2005, pp.485 – 490
[11] J.M.V Santos Dos, J.M.M Ferreira, “Fault-tolerance: new trends for digital circuits” IEEE International Conference on Electronics, Circuits and Systems, Vol 3, Sept.1998 pp. 237 - 240
[12] M. Soma, “Challenges and approaches in mixed signal RF testing” Proceedings of the Tenth Annual IEEE International ASIC Conference, Sept. 1997, pp. 33 – 37
[13] E. Liu, W. Kao, E. Felt, A. Sangiovanni-VIncentelli, “Analog testability analysis and fault diagnosis using behavioral modeling”, Proceedings of the IEEE Custom Integrated Circuits Conference, May 1994, pp. 413 – 416
[14] Yu.V Malyshenko, “Functional fault models for analog circuits”, IEEE Design & Test of Computers, Volume 15, Issue 2, April-June 1998, pp. 80 – 85
[15] Anand Gopalan, P.R.Mukund and Martin Margala, “A Non-Intrusive Self-Test Methodology for RF CMOS Low Noise Amplifiers”, IEEE Mixed-signal Test workshop, Portland, June 2004.
[16] Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits”, Cambridge University Press, 1998.
[17] John Ferrario, Randy Wolf, Steve Moss, Mustapha Slamani, “A low-cost test solution for wireless phone RFICs”, IEEE Communications Magazine, v 41, n 9, September, 2003, pp. 82-89