Fault Tolerance and Online Fault Tolerance and Online Testability of Reversible Testability of Reversible Logic Logic Presented by Kaynat Quayyum Roll: RH-209 Farzana Sharmin Farah Roll: RH-234 Department of Computer Science & Engineering University of Dhaka
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Fault Tolerance and Online Testability of Reversible Logic
Fault Tolerance and Online Testability of Reversible Logic. Presented by Kaynat Quayyum Roll: RH-209 Farzana Sharmin Farah Roll: RH-234. Department of Computer Science & Engineering University of Dhaka. Overview. Fault Tolerant System Reversible Fault Tolerant Gates - PowerPoint PPT Presentation
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Fault Tolerance and Online Testability Fault Tolerance and Online Testability of Reversible Logicof Reversible Logic
Presented by
Kaynat Quayyum
Roll: RH-209
Farzana Sharmin Farah
Roll: RH-234
Department of Computer Science & Engineering University of Dhaka
OverviewOverview•Fault Tolerant System•Reversible Fault Tolerant Gates•Online Testability•Gates with Built-in Testability•Online Testable Block•Railchecker•Online Testable Circuit•Constructing online testable 2 to 4 decoder•References
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Fault Tolerant SystemFault Tolerant System•Property that enables a system to continue operating properly in the event of the failure.•No single point of failure•Fault isolation to the failing component•Fault containment to prevent propagation of the failure•Availability of reversion modes
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Reversible Fault Tolerant Gates (1/2)Reversible Fault Tolerant Gates (1/2)•Solve the problem of bit error•Reversible•Parity preserving•
Fredkin Gate (2/2)Fredkin Gate (2/2)•Universal gate•Can be used as swapping gate
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0
B FredkinGate
C
P = 0
Q = B
R = C
1
B FredkinGate
C
P = 1
Q = C
R = B
Figure 12: Fredkin Gate as swapping gates
Online TestabilityOnline Testability
•Ability of a circuit to test a reversible block at computation time.•Testing in implementation phase saves time.
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Gates with Built-in TestabilityGates with Built-in Testability
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R2 Gate Gate
RR FEDRSFZEYDX
F
DE
P BCABCPQCBAT
BCABCBVBAU
C
AB
R1 Gate
•Online testable gate proposed by Dilip P. Vasudevan.•Used in pairs to make a testable block.
Online Testable BlockOnline Testable Block
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R 1 Gate
R 2 Gate
ABC0
ABC0
R 2 Gate
TB
Q1
1
XYZQS
X
ZY
S
If Q = S’ then R1 is fault free
Railchecker (1/4)Railchecker (1/4)•Used for the purpose of checking the output of online testable block.•First railchecker circuit proposed using R3 gate.
R 3 Gate
A
B
C ABCZAY
BAX
'
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Railchecker (2/4)Railchecker (2/4)
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Error checking function:
• e1=x0y1+y0x1
• e2=x0x1+y0y1
x0/y0 and x1/y1 are compliment of each other. So, for fault free circuit e1=e2’
x1
1
y0
1
y1
x1
1
1
x0
y0
1
e2
e1
1
R3
R3
R3
R3
R3
R3
Railchecker using R3
Railchecker (3/4)Railchecker (3/4)
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X0
X1
G
G
G1
C=0
10 XXA
CA'D
Feynman Gate
Fredkin Gate
A C D=A’+ C
0 0 1
0 1 1
1 0 0
1 1 1
In Improved railchecker (IRC) output D did the same task as e1 and e2 for pair railchecker
Step1:Convert each reversible gate to deduced reversible gateStep 2:Construction of testable reversible cellStep 3: Construct Testable cell TC when we have N TRC