Tony Givargis University of California, Riverside & NEC USA 1 Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design Tony D. Givargis & Frank Vahid Department of Computer Science University of California Riverside, CA 92521 {givargis,vahid}@cs.ucr.edu Jörg Henkel C&C Research Laboratories, NEC USA 4 Independence Way, Princeton, NJ 08540 [email protected]A DAC scholarship and a NSF grant in part supported this research.
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Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design. Tony D. Givargis & Frank Vahid Department of Computer Science University of California Riverside, CA 92521 {givargis,vahid}@cs.ucr.edu. Jörg Henkel C&C Research Laboratories, NEC USA - PowerPoint PPT Presentation
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Tony Givargis University of California, Riverside & NEC USA
1
Fast Cache and Bus Power Estimation for Parameterized
System-on-a-Chip Design
Tony D. Givargis & Frank VahidDepartment of Computer Science
A DAC scholarship and a NSF grant in part supported this research.
Tony Givargis University of California, Riverside & NEC USA
2
Introduction
• Systems-on-a-chip (SOC) era– increased chip capacity– parametrizable core based system design
• Large power/performance tradeoffs possible just by varying bus/cache parameter values [givargis99]
• But, simulation based cache/bus power evaluation is slow
Tony Givargis University of California, Riverside & NEC USA
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Introduction
• We present a two-step approach for fast cache power evaluation– collect intermediate data using simulation– use equations to rapidly predict power– couple with a fast bus estimation approach
• Our approach is– orders of magnitude faster than simulation– yields good accuracy
Tony Givargis University of California, Riverside & NEC USA
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Target Architecture
Bus ACPU I-Cache
D-Cache
Bridge
Peripheral 1
Peripheral Bus
Peripheral 2 Peripheral n
Memory
Bus B
Tony Givargis University of California, Riverside & NEC USA
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Focus on Cache/Bus Parameters
Bus A Bus B
Peripheral 1
Peripheral Bus
Bridge
CPUI-Cache
D-Cache
Peripheral 2 Peripheral n
Memory
CACHE40%
BUS20%
Others10%
CPU30%
Power dissipation breakdownin a Digital Camera example
Tony Givargis University of California, Riverside & NEC USA
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Cache Parameters
Bus A
Peripheral 1
CPU I-Cache
D-Cache
Bridge
Peripheral Bus
Peripheral 2 Peripheral n
Memory
Bus B
Tony Givargis University of California, Riverside & NEC USA
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Cache Parameters
Tag Index Offset
V T D V T D
== ==Mux
Data
• Associativity
• Cache Size
• Line Size
Tony Givargis University of California, Riverside & NEC USA
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Bus Parameters
Bus A
Peripheral 1
CPU I-Cache
D-Cache
Bridge
Peripheral Bus
Peripheral 2 Peripheral n
Memory
Bus B
Tony Givargis University of California, Riverside & NEC USA
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Bus Parameters
Bus A/BMuxDemux
MuxDemux
Bus A/BMuxDemux
MuxDemux
Change Bus Width [givargis98]
C1
C2
C1 < C2
Tony Givargis University of California, Riverside & NEC USA
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Bus Parameters
Bus A/BEncoderDecoder
EncoderDecoder
Change Data Representation (Bus Invert) [Stan95]
Bus A/BEncoderDecoder
EncoderDecoder
invert_ctr
Reduce Bus Switching
Tony Givargis University of California, Riverside & NEC USA
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Bus Parameters
01001011
10010110
Hamming Dist = 6
01001011
0
01101001
1 inverted_ctr
Binary Encoding Bus-Invert Encoding
Hamming Dist = 3
Tony Givargis University of California, Riverside & NEC USA
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Related Work
• Important to explore various cache and bus parameters for best performance and power [Wilton96][Li98][givargis99]
– large number of cache/bus configurations– need to estimate power/performance in constant time
• Trace stripping [Wolf99], configuration ordering, single pass simulation [Kirovski])
Tony Givargis University of California, Riverside & NEC USA
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Approach Overview• Given a trace of memory refs• Cache parameters
• Diesel application’s performance• Blue (light-gray) is obtained using full simulation• Red (dark-gray) is obtained using our equations
4% error320x faster
Tony Givargis University of California, Riverside & NEC USA
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Experiment Results• Diesel application’s energy consumption• Blue (light-gray) is obtained using full simulation• Red (dark-gray) is obtained using our equations
Tony Givargis University of California, Riverside & NEC USA
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Experiment Results• CKey application’s performance• Blue (light-gray) is obtained using full simulation• Red (dark-gray) is obtained using our equations
Tony Givargis University of California, Riverside & NEC USA
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Experiment Results• CKey application’s energy consumption• Blue (light-gray) is obtained using full simulation• Red (dark-gray) is obtained using our equations