1 Farhan Mohamed Ali (W2- 1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 11 MAD MAC 525 19 th April, 2006 Top-Level LVS W2 Project Objective: Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics. Design Manager: Zack Menegakis
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Project Objective:Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics.
Design Manager: Zack Menegakis
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MAD MAC 525 Status: Project chosen Specifications defined Architecture
Design Behavioral Verilog Testbenches Verilog : Gate Level Design Floor plan Schematics and Analog Verifications Layout of basic gates and small modules Top level layouts, Extractions, LVS, Simulations Full Chip Layout completed and LVSed
To be done Simulations and full chip verification
3
RegArray A RegArray B RegArray C
Multiplier Exp Calc Align
Adder/SubtractorControlLogic
&Sign
Dtrmin
Normalize
Round
Ovf Checker
Leading 0 Anticipator
10 10 10
5
55
1435225
4
36
14
101
5
5
Input Input Input
Output
16 16 16
16RegY
15
1
1
1
Block Diagram
4
Multiplier Layout with pipelining
5
Simulations Compared
6
Full Chip Layout
Exponent
AlignZero
Adder
MultiplierNormalize
Round
Ovf
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Design Specifications
• Register-to-register delay (worst case)= 2.25ns• Long buses are all buffered (not tested yet)• Estimated clocking speed = 400MHz• Height by width = 193.86 um * 301.545 um• Area = 58,458 um^2• Aspect ratio = 1:1.55• Total Transistor density = 0.22