Fall 2006 1 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Computer Organization Lecture 7 ALU design MIPS data path.

Fall 2006

Lillevik 333f06-l7 1University of Portland School of Engineering

EE 333

Computer OrganizationLecture 7

ALU designMIPS data path

Fall 2006


EE 333

ALU design with LS181’s

• Assume– 12-bit computer– Active high operands

• Must cascade three devices– Carry out must drive next carry in– Mode and select bused to all devices

Fall 2006


EE 333

One device

NOTE: Active low symbol

provided

Fall 2006


EE 333

ALU 12-bit design

Fall 2006


EE 333

Add operations

What is the propagation time?

Is it the same for all numbers?

NOTE: S = 9, M = 0

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Or operations

What is (0x555) or’d (0xaaa)?

NOTE: S = e, M = 1

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Project 2 overview

• Sixteen-bit ALU

• Use four LS181 plus some other logic

• Arithmetic: +, -

• Logical:– and, or– shift left, shift right

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Project 2 hints

• Use four LS181’s ALU

• Design shifter circuits

• Use muxes to select between ALU and shifters

• Design combinational logic to control muxes: consider a ROM

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ROM device

bit 0

bit 7

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Project 2 questions?

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Shifting operations

• Goal: shift n-bit number left and right• Definition: 1-bit shift

– Left: lsb = 0, else bitn = bitn-1

– Right: msb = 0, else bitn = bitn+1

• General function is to shifts n-bits

Fall 2006


EE 333

Shift left circuit

Could you design a right shifter?

Fall 2006


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Timing

What mathematical function does sll perform?

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Major Computer Components

Five classic computer components

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Computer Components

• Input: receives information from external world

• Output: transmits information to external world

• Memory: holds programs and data

• Data path: physical route that carries info

• Control: coordinates overall flow of infoDenoted Processor

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MIPS datapath overview

• Instruction read from memory• Registers selected for operation• ALU performs function• Result written to register

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Instruction fetch

• PC reset on power-up; e.g., 0x 0000 0000• PC clocked at some rate (~3.0 GHz today)• Instructions (usually) accessed sequentially

PC

Instruction

memory

Readaddress

Instruction

4

Add

32-bit number or instruction

Incremented by 4 for word alignment

Fall 2006


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Register file

• Contains– Thirty-two, one-word numbers or registers (32

by 32, D-type flip-flops)– Similar to a small memory

• Registers: denoted $0 - $31, alternate names too

• Operations– Read any two registers – Write to one register

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Register file symbol

Two read ports, one write port

NOTE: Orange denotes control signal

32

32

32

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R-format structure

• Instruction fields (rs, rt, rd) select registers and ALU operation (funct)

• Result written back into register file

rs

rt

rd 32

32

32

funct

Size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

R type op rs rt rd shamt funct

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Find the registers and operation?Inst = 0x00430820

=0000 0000 0100 0011 0000 1000 0010 0000

$2

$3

$1

add

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I-format structure: lw & sw

• Requirements– Calculate effective address (addition)– Perform load (read) or store (write)

• Components– Register file– ALU for effective address– Data memory

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I-type EA review

• Examples– lw $t1, offset ($t2)– sw $t1, offset ($t2)

• Effective address (EA) calculation– adr = base + offset

– adr = $t2 + Instr15-0 32-bit added to 16-bit ??

• Register $t1 (destination/load, source/store)

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Memory reference logic

Effective address = sum of (reg + immed)

5

32

32

32

3232

5

5

rs

rt

immed

add

Size 6 bits 5 bits 5 bits 16 bits

I type op rs rt address/immediate

Fall 2006


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Design sign extension?

Fall 2006


EE 333

Find the registers and immed?

5

32

32

32

3232

5

5

$2

$1

0x0064

add

Instr = 0x8c410064=1000 1100 0100 0001 0000 0000 0110 0100

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I-format structure: beq

• Example: beq $t1, $t2, offset– If $t1=$t2, then EA = PC + offset branch taken

– If $t1$t2, then EA = PC branch not taken

• Branch address– PC must first be incremented– Offset is word-aligned or shifted left 2 bits

Conditional jump instruction

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Beq instruction

• Requirements– Determine if two registers are equal (sub or

compare)– Calculate the branch/jump address

• Components– Register file– Adder to increment PC– ALU for branch address

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Branching logic

ALU tests for zeroAdder determines branch address

rs

rt

immed

Size 6 bits 5 bits 5 bits 16 bits

I type op rs rt address/immediate

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Find the regs & sign extend?

inst = 0x114cfff0

$0xa

$0xc

0xfff00001 0001 0100 1100 1111 1111 1111 0000

Fall 2006


EE 333

Fall 2006


EE 333

Find the registers and operation?Inst = 0x00430820

0000 0000 0100 0011 0000 1000 0010 0000

$2

$3

$1

addrs rt rd func

Fall 2006


EE 333

Design sign extention?

Fall 2006


EE 333

Find the registers and immed?

5

32

32

32

3232

5

5

$2

$1

0x0064

add

Instr = 0x8c410064

1000 1100 0100 0001 0000 0000 0110 0100

lw $1, 100($2)

rs rt immed

Fall 2006


EE 333

Find the regs and sign extend?

inst = 0x114cfff0

$10

$12

immed = -16

000100 01010 01100 1111 1111 1111 0000

inst = 0001 0001 0100 1100 1111 1111 1111 0000rs rt immed

Fall 2006 1 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Computer Organization Lecture 7 ALU design MIPS data path.

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