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FADC Time Study EJ, HD 10/09
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FADC Time Study EJ, HD 10/09. Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of.

Jan 08, 2018

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Eunice Bell

Test Setup delay 1 delay 2 delay 3 to FADC ch 6 to FADC ch 7 to FADC trigger (via TI) to FADC ch 5 Agilent 33250A Function / Arbitrary Waveform Generator to FADC ch 8 Phillips PS-715 Disc. Phillips PS-794 Gate/ Delay (delay = cable )
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Page 1: FADC Time Study EJ, HD 10/09. Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of.

FADC Time StudyEJ, HD 10/09

Page 2: FADC Time Study EJ, HD 10/09. Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of.

• Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing

algorithm• NOT meant to be a definitive study of timing resolution of the FADC250• This test uses pulse shapes that tend to enhance algorithm performance

(e.g. linear leading edge, large amplitude, at least one sample at peak value)

• The resolution results are probably close to the best that can be done with the current algorithm

Page 3: FADC Time Study EJ, HD 10/09. Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of.

Test Setup

delay 1

delay 2

delay 3

to FADC ch 6

to FADC ch 7

to FADC trigger(via TI)

to FADC ch 5

Agilent 33250A

Function /Arbitrary

Waveform Generator

to FADC ch 8

Phillips PS-715

Disc.

Phillips PS-794Gate/Delay

(delay = cable)

Page 4: FADC Time Study EJ, HD 10/09. Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of.

Part 1

• Runs taken with delay values:(delay 1, delay 2, delay 3) = (1, 2, 3) ns, (1, 4, 10) ns

• Test with two pulse shapes having different leading edge transition rates (see Figures 1 and 2)

• Study all available FADC time difference distributions (in counts):(ch6 – ch5), (ch7 – ch5), (ch8 – ch5), (ch7 – ch6), (ch8 – ch6), (ch8 – ch7)

• Distributions are tight, with no long tails or satellite peaks (see Figures 3 and 4)

• Time differences are roughly what was expected for the cable delays inserted (~16 counts/ns)

Page 5: FADC Time Study EJ, HD 10/09. Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of.

Pulse 1

Figure 1.

Page 6: FADC Time Study EJ, HD 10/09. Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of.

Pulse 2Figure 2.

Page 7: FADC Time Study EJ, HD 10/09. Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of.

SIGMA = 0.97

1 bin = 0.0625 ns

Figure 3.

Page 8: FADC Time Study EJ, HD 10/09. Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of.

1 bin = 0.0625 ns

Figure 4.

Page 9: FADC Time Study EJ, HD 10/09. Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of.

Part 2

• Use only ch5 and ch6• Insert precisely measured delays between ch5 and ch6• Delays measured with Stanford Research Systems Time Interval Counter (SR-

620, resolution = 25 ps)• Plots of FADC time difference (in counts) vs. delay show good linear behavior

across a 4 ns sample bin (see Figures 5 and 6)• However, the slope should not be a free parameter of the fit – it must be 16

counts/ns (250 MHz, 6-bit fine time bin)• Force 16 counts/ns and only allow a common time offset• Plots of (FADC time difference – delay) vs. delay show some systematic effects

across a 4 ns sample bin (see Figures 7 and 8)• Estimate of timing resolution: 140 ps for Pulse 1 230 ps for Pulse 2

Page 10: FADC Time Study EJ, HD 10/09. Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of.

Figure 5.

Page 11: FADC Time Study EJ, HD 10/09. Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of.

Figure 6.

Page 12: FADC Time Study EJ, HD 10/09. Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of.

Figure 7.

Page 13: FADC Time Study EJ, HD 10/09. Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of.

Figure 8.