FABRICATION of MOSFETs CMOS fabrication sequence -p-type silicon substrate wafer -creation of n-well regions for pMOS transistors, -impurity implantation into the substrate. -thick oxide is grown in the regions -surrounding the nMOS and pMOS active regions. -creation of n+ and p+ regions -final metallization & interconnects.
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FABRICATION of
MOSFETsCMOS fabrication sequence -p-type silicon substrate wafer-creation of n-well regions for pMOStransistors, -impurity implantation into the substrate. -thick oxide is grown in the regions -surrounding the nMOS and pMOS active regions. -creation of n+ and p+ regions -final metallization & interconnects.
CMOS Process
• PMOS transistors created in an n-well• Typically substrate has lower doping on
the surface
Fabrication –Patterning of
SiO2
• Grow SiO2 on Si by exposing to O2– high temperature accelerates
this process• Cover surface with
photoresist (PR)– Sensitive to UV light
(wavelength determines feature size)
– Positive PR becomes soluble after exposure
– Negative PR becomes insoluble after exposure
Fabrication –Patterning of
SiO2
• PR removed with a solvent
• SiO2 removed by etching (HF)
• Remaining PR removed with another solvent
Summary
• The result of a single lithographic patterning sequence on silicon dioxide, without showing the intermediate steps.
• unpatternedstructure (top)
• patterned structure (bottom)
Fabrication of nMOSTransistor
• Thick field oxide grown
• Field oxide etched to create area for transistor
• Gate oxide (high quality) grown
Fabrication of NMOS Transistor
• Polysilicon deposited (doped to reduce R)• Polysilicon etched to form gate• Gate oxide etched from source and drain
– Self-aligned process because source/drain aligned by gate
• Si doped with donors to create n+ regions
NMOS Transistor Fabrication
• Insulating SiO2 grown to cover surface/gate• Source/Drain regions opened• Aluminum evaporated to cover surface• Aluminum etched to form metal1 interconnects
Metallization
Device Isolation Techniques
• To prevent unwanted conduction• To avoid creation of inversion layers
outside channel regions• To reduce leakage currents
devices are made into Active areas…Surrounded by field oxide (thick oxide barrier)
CMOS n-well process
• P-type substrate• n-well region for PMOS• thin gate oxide is grown on
top of the active regions • thick field oxide is grown in
the areas surrounding the transistor active regions
• gate oxide thickness and quality affect the operational characteristics of the MOS transistor and reliability.
-polysilicon layer -deposited by chemical vapor deposition (CVD) -patterned by etching. -polysilicon lines will function as the gate of MOS - act as self-aligned masks for source and drain
• Masks • n+ and p+
regions implanted in its locations
• ohmiccontacts to substrate and to n-well
Contacts to Silicon needs toBe through heavily doped regionsTo avoid them as junctions
• Metal (aluminum) is deposited over the entire chip surface using metal evaporation, and the metal lines are patterned through etching. Since the wafer surface is non-planar, the quality and the integrity of the metal lines created in this step are very critical and are ultimately essential for circuit reliability
• Complete
mask sequence applied to create desired structures