FUJITSU SEMICONDUCTOR CONTROLLER MANUAL F 2 MC TM -8FX 8-bit Microcontroller MB95FV100 HARDWARE MANUAL
FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
F2MCTM-8FX8-bit Microcontroller
MB95FV100HARDWARE MANUAL
FUJITSU LIMITED
F2MCTM-8FX8-bit Microcontroller
MB95FV100HARDWARE MANUAL
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Preface
Purpose of this document and intended reader
Information to use software development support chip MB95FV100 of the F2MC-8FX family is explained
in this manual with information on each kind of the F2MC-8FX family.
All functions are included in MB95FV100 for the emulating of all the kinds to which development will be
done in the F2MC-8FX family. Therefore, the dedicatedÅ@MCU board is prepared in MB95FV100. The
targeting product can be selected by the switch and the jumper on this board.
Especially, the terminal mode can be set by the switch selection about the terminal function. The external
terminal of MB95FV100 is changed into the composition suitable for the targetting product (series).
The table below shows the relation between the terminal mode and the target series. Please keep the
selected target series in mind during using this manual.
And, the following setting can be done in the MCU board.
• Sub-clock ON/OFF
• Terminal switching for 5V or 3V product (C pin, etc.)
• Low power detection reset, clock supervisor ON/OFF (only for 5V product)
For detail, see the manual appended to MCU board.
Pin mode Target series
100-pin product without LCD SAXOPHONE
80-pin product without LCD RESERVE1
64-pin product without LCD BASSOON
48-pin product without LCD CLARINET
32-pin product without LCD OBOE
28-pin product without LCD FLUTE
20-pin product without LCD PICCOLO
Setting prohibited -
100-pin product with LCD TUBA
80-pin product with LCD RESERVE2
64-pin product with LCD TROMBONE
32-pin product with LCD TRUMPET
Setting prohibited -
Setting prohibited -
Setting prohibited -
Setting prohibited -
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Organization of this documentThis manual contains the following 29 chapters.
CHAPTER 1 Description (100-pin)
This chapter explains a feature and a basic specification of each series.
CHAPTER 2 Precautions when Handling Devices
This chapter describes points to note when using this series.
CHAPTER 3 CPU
This chapter describes functions and operations of the CPU.
CHAPTER 4 Clock Control Block
This chapter describes the functionality and behavior of the clock controller.
CHAPTER 5 I/O Port
This chapter describes the functionality and behavior of the I/O ports.
CHAPTER 6 Timebase Timer
This chapter describes the functions and operations of the timebase timer.
CHAPTER 6 Timebase Timer
This chapter describes the functions and operations of the timebase timer.
CHAPTER 7 Watchdog Timer
This chapter explains the functions and operation of the watchdog timer.
CHAPTER 8 Watch Prescaler
This chapter describes the function and operation of the watch prescaler.
CHAPTER 9 Watch Counter
This chapter describes the function and operation of the clock counter.
CHAPTER 10 Wild Register
This chapter describes the operation of the wild register function.
CHAPTER 11 Prescaler
This chapter describes the function and operation of the prescaler.
CHAPTER 12 8/16-bit Composite Timer
This chapter describes the functions and operations of an 8/16-bit composite timer.
CHAPTER 13 8/16-bit PPG
This chapter describes the functions and operation of the 8/16-bit PPG.
CHAPTER 14 16-bit PPG Timer
This chapter describes the function and operation of the 16-bit PPG timer.
CHAPTER 15 16-bit Reload Timer
The chapter describes the functions and operation of the 16-bit reload timer.
CHAPTER 16 External Interrupt Circuit
This chapter explains the function and the operation of external interrupt circuit.
CHAPTER 17 Interrupt Pin Selecting Circuit
This chapter describes the functions and operation of the interrupt pin selection circuit.
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CHAPTER 18 UART/SIO
This chapter explains the function and operation of the UART/SIO.
CHAPTER 19 Dedicated Baud Rate Generator
This chapter describes the function and operation of the dedicated baud rate generator.
CHAPTER 20 LIN-UART
This chapter describes the function and operation of the LIN-UART.
CHAPTER 21 I2C
This chapter describes the I2C functions and operation.
CHAPTER 22 A/D Converter
This chapter describes the functionality and behavior of the A/D converter.
CHAPTER 23 D/A Converter
This chapter explains function and operation of the D/A converter
CHAPTER 24 LCD Controller
This chapter describes the function and operation of the LCD controller.
CHAPTER 25 Low-Voltage Detection Reset Circuit
This chapter describes the function and operation of the low voltage detection reset circuit.
CHAPTER 26 Clock Supervisor
This chapter describes the functions and operation of the clock supervisor.
CHAPTER 27 480-Kbit Flash Memory
This chapter describes the function and operation of 480-Kbit flash memory.
CHAPTER 28 Dual Operation Flash
This chapter describes the functions and operation of dual operation flash.
CHAPTER 29 Basic Information
This chapter explains I/O map, interrupt list, memory map, pin status, instruction overview and mask
option.
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Copyright© 2004 FUJITSU LIMITED All rights reserved
• The contents of this document are subject to change without notice. Customers are advised to consult withFUJITSU sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presentedsolely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device;FUJITSU does not warrant proper operation of the device with respect to use based on such information. When youdevelop equipment incorporating the device based on such information, you must assume any responsibility arisingout of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of theuse of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not beconstrued as license of the use or exercise of any intellectual property right, such as patent right or copyright, orany other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party'sintellectual property right or other right by using such information. FUJITSU assumes no liability for anyinfringement of the intellectual property rights or other rights of third parties which would result from the use ofinformation contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for generaluse, including without limitation, ordinary industrial use, general office use, personal use, and household use, butare not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangersthat, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly todeath, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch controlin weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificialsatellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damagesarising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or lossfrom such failures by incorporating safety design measures into your facility and equipment such as redundancy,fire protection, and prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on exportunder the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government willbe required for export of those products from Japan.
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CONTENTS
CHAPTER 1 Description (100-pin) .................................................................................. 11.1 Feature of SAXOPHONE Series ........................................................................................................ 21.2 Product Lineup of SAXOPHONE Series ............................................................................................. 41.3 Notes on Difference Point between Products and Selecting Product ................................................. 61.4 Block Diagram of SAXOPHONE Series ............................................................................................. 71.5 Pin Assignment ................................................................................................................................... 81.6 Package Dimension ............................................................................................................................ 91.7 Pin Description .................................................................................................................................. 101.8 I/O Circuit Type ................................................................................................................................. 14
CHAPTER 1 Description (80-pin) .................................................................................. 171.1 Feature of RESERVE1 Series .......................................................................................................... 181.2 Product Lineup of RESERVE1 Series .............................................................................................. 201.3 Notes on Difference Point between Products and Selecting Product ............................................... 221.4 Block Diagram of RESERVE1 Series ............................................................................................... 231.5 Pin Assignment ................................................................................................................................. 241.6 Package Dimension .......................................................................................................................... 251.7 Pin Description .................................................................................................................................. 261.8 I/O Circuit Type ................................................................................................................................. 30
CHAPTER 1 Description (64-pin) .................................................................................. 331.1 Feature of BASSOON Series ........................................................................................................... 341.2 Product Lineup of BASSOON Series ................................................................................................ 361.3 Notes on Difference Point between Products and Selecting Product ............................................... 381.4 Block Diagram of the BASSOON Series .......................................................................................... 391.5 Pin Assignment ................................................................................................................................. 401.6 Package Dimension .......................................................................................................................... 411.7 Pin Description .................................................................................................................................. 421.8 I/O Circuit Type ................................................................................................................................. 45
CHAPTER 1 Description (48-pin) .................................................................................. 491.1 Features of CLARINET Series .......................................................................................................... 501.2 Product Lineup of CLARINET Series ................................................................................................ 521.3 Notes on Difference Point between Products and Selecting Product ............................................... 541.4 Block Diagram of CLARINET Series ................................................................................................ 551.5 Pin Assignment ................................................................................................................................. 561.6 Package Dimension .......................................................................................................................... 571.7 Pin Description .................................................................................................................................. 581.8 I/O Circuit Type ................................................................................................................................. 61
CHAPTER 1 Description (32-pin) .................................................................................. 631.1 Feature of OBOE Series ................................................................................................................... 641.2 Product Lineup of OBOE Series ....................................................................................................... 661.3 Notes on Difference Point between Products and Selecting Product ............................................... 68
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1.4 Block Diagram of OBOE Series ........................................................................................................ 691.5 Pin Assignment ................................................................................................................................. 701.6 Package Dimension .......................................................................................................................... 711.7 Pin Description .................................................................................................................................. 721.8 I/O Circuit Type ................................................................................................................................. 74
CHAPTER 1 Description (28-pin) .................................................................................. 771.1 Feature of FLUTE Series .................................................................................................................. 781.2 Product Lineup of FLUTE Series ...................................................................................................... 801.3 Notes on Difference Point between Products and Selecting Product ............................................... 821.4 Block Diagram of FLUTE Series ....................................................................................................... 831.5 Pin Assignment ................................................................................................................................. 841.6 Package Dimension .......................................................................................................................... 851.7 Pin Description .................................................................................................................................. 861.8 I/O Circuit Type ................................................................................................................................. 88
CHAPTER 1 Description (20-pin) .................................................................................. 911.1 Feature of PICCOLO Series ............................................................................................................. 921.2 Product Lineup of PICCOLO Series ................................................................................................. 931.3 Note on Difference Point between Products and Selecting Product ................................................. 951.4 Block Diagram of PICCOLO Series .................................................................................................. 961.5 Pin Assignment ................................................................................................................................. 971.6 Package Dimension .......................................................................................................................... 981.7 Pin Description .................................................................................................................................. 991.8 I/O Circuit Type ............................................................................................................................... 101
CHAPTER 1 Description (100-pin/LCD) ...................................................................... 1031.1 Feature of TUBA Series .................................................................................................................. 1041.2 Product Lineup of TUBA Series ...................................................................................................... 1061.3 Notes on Difference Point between Products and Selecting Product ............................................. 1081.4 Block Diagram of TUBA Series ....................................................................................................... 1091.5 Pin Assignment ............................................................................................................................... 1101.6 Package Dimension ........................................................................................................................ 1111.7 Pin Description ................................................................................................................................ 1121.8 I/O Circuit Type ............................................................................................................................... 117
CHAPTER 1 Description (80-pin/LCD) ........................................................................ 1211.1 Feature of RESERVE2 Series ........................................................................................................ 1221.2 Product Lineup of RESERVE2 Series ............................................................................................ 1241.3 Notes on Difference Point between Products and Selecting Product ............................................. 1261.4 Block Diagram of RESERVE2 Series ............................................................................................. 1271.5 Pin Assignment ............................................................................................................................... 1281.6 Package Dimension ........................................................................................................................ 1291.7 Pin Description ................................................................................................................................ 1301.8 I/O Circuit Type ............................................................................................................................... 134
CHAPTER 1 Description (64-pin/LCD) ........................................................................ 139
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1.1 Feature of TROMBONE Series ...................................................................................................... 1401.2 Product Lineup of TROMBONE Series ........................................................................................... 1421.3 Notes on Difference Point between Products and Selecting Product ............................................. 1441.4 Block Diagram of TROMBONE Series ........................................................................................... 1451.5 Pin Assignment ............................................................................................................................... 1461.6 Package Dimension ........................................................................................................................ 1471.7 Pin Description ................................................................................................................................ 1481.8 I/O Circuit Type ............................................................................................................................... 151
CHAPTER 1 Description (48-pin/LCD) ........................................................................ 1551.1 Feature of TRUMPET Series .......................................................................................................... 1561.2 Product Lineup of the TRUMPET Series ........................................................................................ 1581.3 Notes on Difference Point between Products and Selecting Product ............................................. 1601.4 Block Diagram of TRUMPET Series ............................................................................................... 1611.5 Pin Assignment ............................................................................................................................... 1621.6 Package Dimension ........................................................................................................................ 1631.7 Pin Description ................................................................................................................................ 1641.8 I/O Circuit Type ............................................................................................................................... 167
CHAPTER 2 Precautions when Handling Devices .................................................... 1712.1 Precautions when Handling Devices .............................................................................................. 172
CHAPTER 3 CPU .......................................................................................................... 1733.1 Memory Space ................................................................................................................................ 1743.2 Dedicated Registers ....................................................................................................................... 178
3.2.1 Register Bank Pointer (RP) ....................................................................................................... 1803.2.2 Direct Bank Pointer (DP) ........................................................................................................... 1813.2.3 Condition Code Register (CCR) ................................................................................................ 183
3.3 General-purpose Register .............................................................................................................. 1853.4 Interrupt .......................................................................................................................................... 187
3.4.1 Interrupt Level Setting Registers (ILR0 to ILR5) ........................................................................ 1893.4.2 Interrupt Processing .................................................................................................................. 1903.4.3 Multiple Interrupts ...................................................................................................................... 1923.4.4 Interrupt Processing Time ......................................................................................................... 1933.4.5 Stack Operation During Interrupt Handling ................................................................................ 1943.4.6 Interrupt Handling Stack Area ................................................................................................... 195
3.5 CPU Operation After A Reset (Mode Fetch Operation) .................................................................. 196
CHAPTER 4 Clock Control Block ................................................................................ 1974.1 Overview of Clock Controller .......................................................................................................... 1984.2 Oscillation Stabilization Wait Time .................................................................................................. 2014.3 System Clock Control Register (SYCC) ......................................................................................... 2054.4 PLL Control Register (PLLC) .......................................................................................................... 2074.5 Oscillation Stabilization Standby Time Assignment Register (WATR) ........................................... 2104.6 Standby Control Register (STBC) ................................................................................................... 2134.7 Reset Source Register (RSRR) ...................................................................................................... 2154.8 Reset Operation .............................................................................................................................. 217
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4.9 Clock Mode Operation .................................................................................................................... 2214.10 Operation of Standby Mode (Low-power Consumption Mode) ....................................................... 225
4.10.1 Notes on Using Standby Mode .................................................................................................. 2264.10.2 Sleep Mode ............................................................................................................................... 2304.10.3 Stop Mode ................................................................................................................................. 2314.10.4 Timebase Timer Mode ............................................................................................................... 2324.10.5 Watch Mode .............................................................................................................................. 233
4.11 Clock Oscillation Circuit .................................................................................................................. 234
CHAPTER 5 I/O Port ..................................................................................................... 2375.1 Overview of I/O Ports ...................................................................................................................... 2385.2 Port 0 .............................................................................................................................................. 240
5.2.1 Registers for Port 0 .................................................................................................................... 2465.2.2 Operation of Port 0 .................................................................................................................... 247
5.3 Port 1 .............................................................................................................................................. 2505.3.1 Registers for Port 1 .................................................................................................................... 2535.3.2 Operation of Port 1 .................................................................................................................... 254
5.4 Port 2 .............................................................................................................................................. 2565.4.1 Registers for Port 2 .................................................................................................................... 2595.4.2 Operation of Port 2 .................................................................................................................... 260
5.5 Port 3 .............................................................................................................................................. 2625.5.1 Registers for Port 3 .................................................................................................................... 2645.5.2 Operation of Port 3 .................................................................................................................... 265
5.6 Port 4 .............................................................................................................................................. 2675.6.1 Registers for Port 4 .................................................................................................................... 2695.6.2 Operation of Port 4 .................................................................................................................... 270
5.7 Port 5 .............................................................................................................................................. 2725.7.1 Registers for Port 5 .................................................................................................................... 2755.7.2 Operation of Port 5 .................................................................................................................... 276
5.8 Port 6 .............................................................................................................................................. 2785.8.1 Registers for Port 6 .................................................................................................................... 2825.8.2 Operation of Port 6 .................................................................................................................... 283
5.9 Port 7 .............................................................................................................................................. 2855.9.1 Registers for Port 7 .................................................................................................................... 2885.9.2 Operation of Port 7 .................................................................................................................... 289
5.10 Port 8 .............................................................................................................................................. 2915.10.1 Registers for Port 8 .................................................................................................................... 2935.10.2 Operation of Port 8 .................................................................................................................... 294
5.11 Port 9 .............................................................................................................................................. 2955.11.1 Registers for Port 9 .................................................................................................................... 2975.11.2 Operation of Port 9 .................................................................................................................... 298
5.12 Port A .............................................................................................................................................. 3005.12.1 Registers for Port A ................................................................................................................... 3025.12.2 Operation of Port A .................................................................................................................... 303
5.13 Port B .............................................................................................................................................. 3055.13.1 Registers for Port B ................................................................................................................... 3075.13.2 Operation of Port B .................................................................................................................... 308
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5.14 Port C .............................................................................................................................................. 3105.14.1 Registers for Port C ................................................................................................................... 3125.14.2 Operation of Port C .................................................................................................................... 313
5.15 Port D .............................................................................................................................................. 3155.15.1 Registers for Port D ................................................................................................................... 3175.15.2 Operation of Port D .................................................................................................................... 318
5.16 Port E .............................................................................................................................................. 3205.16.1 Registers for Port E ................................................................................................................... 3235.16.2 Operation of Port E .................................................................................................................... 324
5.17 Port F .............................................................................................................................................. 3265.17.1 Registers for Port F ................................................................................................................... 3285.17.2 Operation of Port F .................................................................................................................... 329
5.18 Port G ............................................................................................................................................. 3305.18.1 Registers for Port G ................................................................................................................... 3325.18.2 Operation of Port G ................................................................................................................... 333
CHAPTER 6 Timebase Timer ....................................................................................... 3356.1 Overview of Timebase Timer .......................................................................................................... 3366.2 Configuration of Timebase Timer ................................................................................................... 3386.3 Timebase Timer Control Register (TBTC) ...................................................................................... 3406.4 Explanation of Operations of Timebase Timer ............................................................................... 3426.5 Interrupt of Timebase Timer ........................................................................................................... 3446.6 Program Example of Timebase Timer ............................................................................................ 345
CHAPTER 7 Watchdog Timer ...................................................................................... 3477.1 Overview of Watchdog Timer ......................................................................................................... 3487.2 Configuration of Watchdog Timer ................................................................................................... 3497.3 Watchdog Control Register (WDTC) .............................................................................................. 3517.4 Explanation of Operations for Watchdog Timer .............................................................................. 3537.5 Program Examples of Watchdog Timer .......................................................................................... 355
CHAPTER 8 Watch Prescaler ...................................................................................... 3578.1 Overview of Watch Prescaler ......................................................................................................... 3588.2 Configuration of Watch Prescaler ................................................................................................... 3598.3 Watch Prescaler Control Register (WPCR) .................................................................................... 3618.4 Operations of Watch Prescaler ....................................................................................................... 3638.5 Interrupt of Watch Prescaler ........................................................................................................... 3658.6 Programming Example of Watch Prescaler .................................................................................... 366
CHAPTER 9 Watch Counter ........................................................................................ 3679.1 Overview of Watch Counter ............................................................................................................ 3689.2 Block Diagram Watch Counter ....................................................................................................... 3699.3 Register of Watch counter .............................................................................................................. 370
9.3.1 Watch Counter Data Register (WCDR) ..................................................................................... 3719.3.2 Watch Counter Status Register (WCSR) ................................................................................... 372
9.4 Interrupt of Watch Counter ............................................................................................................. 3749.5 Operations of Watch Counter ......................................................................................................... 375
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9.6 Notes on Using Watch Counter ...................................................................................................... 376
CHAPTER 10 Wild Register ........................................................................................... 37710.1 Overview of Wild Register .............................................................................................................. 37810.2 Structure of Wild Register ............................................................................................................... 37910.3 Wild Register Registers .................................................................................................................. 381
10.3.1 Data Setting Register (WRDR0 to WRDR2) .............................................................................. 38310.3.2 Address Setting Register (WRAR0 to WRAR2) ........................................................................ 38410.3.3 Address Compare Enable Register (WREN) ............................................................................. 38510.3.4 Data Test Setting Register (WROR) .......................................................................................... 386
10.4 Explanation of Wild Register Operation .......................................................................................... 38710.5 Typical Hardware Connection ......................................................................................................... 388
CHAPTER 11 Prescaler .................................................................................................. 38911.1 Overview of Prescaler ..................................................................................................................... 39011.2 Block Diagram of Prescaler ............................................................................................................ 39111.3 Operations of Prescaler .................................................................................................................. 39211.4 Notes on Using Prescaler ............................................................................................................... 393
CHAPTER 12 8/16-bit Composite Timer ....................................................................... 39512.1 Overview of 8/16-bit Composite Timer ........................................................................................... 39612.2 Configuration of 8/16-bit Composite Timer ..................................................................................... 39812.3 Channels of 8/16-bit Composite Timer ........................................................................................... 40112.4 Pins of 8/16-bit Composite Timer ................................................................................................... 40212.5 Register of 8/16-bit Composite Timer ............................................................................................. 403
12.5.1 Control Status Register 0 (T00CR0/T01CR0) ........................................................................... 40412.5.2 Control Status Register 1 (T00CR1/T01CR1) ........................................................................... 40612.5.3 Timer Mode Control Register (TMCR0) ..................................................................................... 40912.5.4 Data Register (T00DR/T01DR) ................................................................................................. 412
12.6 Operating Explanation of Interval Timer Function (One-shot Mode) .............................................. 41412.7 Operating Explanation of Interval Timer Function (Continuous Mode) ........................................... 41512.8 Operating Explanation of Interval Timer Function (Free-running Mode) ........................................ 41712.9 Operating Explanation of PWM Timer Function (Fixed-period Mode) ............................................ 41912.10 Operating Explanation of PWM Timer Function (Variable-period Mode) ........................................ 42112.11 Operating Explanation of PWC Timer Function .............................................................................. 42312.12 Operating Explanation of Input Capture Functions ......................................................................... 42512.13 Explanation of Noise Filter Operation ............................................................................................. 42712.14 States in Each Mode During Operation .......................................................................................... 42812.15 Interrupt of 8/16-bit Composite Timer ............................................................................................. 43012.16 Note on Using 8/16-bit Composite Timer ........................................................................................ 431
CHAPTER 13 8/16-bit PPG ............................................................................................. 43313.1 Overview of 8/16-Bit PPG ............................................................................................................... 43413.2 Block Diagram of 8/16-Bit PPG ...................................................................................................... 43513.3 Channel of 8/16-Bit PPG ................................................................................................................ 43613.4 Register of 8/16-bit PPG ................................................................................................................. 437
13.4.1 PPG1 Control Register (PC1) .................................................................................................... 438
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13.4.2 PPG0 Control Register (PC0) .................................................................................................... 44013.4.3 PPG Cycle Set Register 1(PPS1), 0(PPS0) .............................................................................. 44213.4.4 PPG Duty Setting Register 1(PDS1), 0(PDS0) ......................................................................... 44313.4.5 PPG Start Register (PPGS) ....................................................................................................... 44413.4.6 PPG Output Inversion Register (REVC) .................................................................................... 445
13.5 Interrupt of 8/16-Bit PPG ................................................................................................................ 44613.6 Operation of 8/16-BIt PPG .............................................................................................................. 447
13.6.1 8-bit PPG Independent Operation Mode ................................................................................... 45013.6.2 8-Bit Prescaler + 8-Bit PPG Mode ............................................................................................. 45113.6.3 16-bit PPG Mode ....................................................................................................................... 453
13.7 Precautions for Using 8/16-Bit PPG ............................................................................................... 45413.8 Example Program for 8/16-Bit PPG ................................................................................................ 455
CHAPTER 14 16-bit PPG Timer ..................................................................................... 45714.1 Overview of 16-bit PPG Timer ........................................................................................................ 45814.2 16-bit PPG Timer Block Diagram .................................................................................................... 45914.3 Channel and Pin of 16-bit PPG Timer ............................................................................................ 46014.4 Registers of 16-bit PPG Timers ...................................................................................................... 461
14.4.1 PPG Down Counter Register (PDCRH, PDCRL) ...................................................................... 46214.4.2 PPG Period Setting Buffer Register (PCSRH, PCSRL) ............................................................ 46314.4.3 PPG Duty Setting Buffer Register (PDUTH, PDUTL) ................................................................ 46414.4.4 PPG Status Control Register (PCNTH, PCNTL) ....................................................................... 465
14.5 16-Bit PPG Timer Interrupt ............................................................................................................. 46914.6 16-bit PPG timer operation ............................................................................................................. 47014.7 Precautions when Using 16-bit PPG Timer .................................................................................... 47414.8 Program Example for 16-bit PPG Timer ......................................................................................... 475
CHAPTER 15 16-bit Reload Timer ................................................................................. 47715.1 Overview of 16-bit Reload Timer .................................................................................................... 47815.2 Block Diagram of 16-bit Reload Timer ............................................................................................ 48015.3 Channel of 16-Bit Reload Timer ..................................................................................................... 48215.4 Registers of 16-Bit Reload Timer .................................................................................................... 483
15.4.1 Upper Timer Control Status Register (TMCSRH) ...................................................................... 48415.4.2 Lower Timer Control Status Register (TMCSRL) ...................................................................... 48615.4.3 Upper, Lower 16-bit Timer Register (TMRH, TMRL) ................................................................. 48815.4.4 Upper, Lower 16-bit Reload Register (TMRLRH, TMRLRL) ...................................................... 489
15.5 Interrupts of 16-Bit Reload Timer .................................................................................................... 49015.6 Operation of 16-bit reload timer ...................................................................................................... 491
15.6.1 Internal Clock Mode (Reload Mode) .......................................................................................... 49415.6.2 Internal Clock Mode (One Shot Mode) ...................................................................................... 49615.6.3 Event Count Mode ..................................................................................................................... 498
15.7 16-Bit Reload Timer Notes on Use ................................................................................................. 50015.8 Program Example of 16-Bit Reload Timer ...................................................................................... 501
CHAPTER 16 External Interrupt Circuit ........................................................................ 50316.1 Overview of External Interrupt Circuit ............................................................................................. 50416.2 Block Diagram of the External Interrupt Circuit ............................................................................... 505
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16.3 External Interrupt Circuit Channels ................................................................................................. 50616.4 Register for External Interrupt Circuit ............................................................................................. 507
16.4.1 External Interrupt Control Register (EIC) ................................................................................... 50816.5 Interrupt of External Interrupt Circuit ............................................................................................... 51016.6 Operation of External Interrupt Circuit ............................................................................................ 51116.7 Notes of Using External Interrupt Circuit ........................................................................................ 51216.8 Sample Program for External Interrupt Circuit ................................................................................ 513
CHAPTER 17 Interrupt Pin Selecting Circuit ............................................................... 51517.1 Overview of Interrupt Pin Selecting Circuit ..................................................................................... 51617.2 Block Diagram of Interrupt Pin Selecting Circuit ............................................................................. 51717.3 Pin Description of Interrupt Pin Selecting Circuit ............................................................................ 51817.4 Register for Interrupt Pin Selecting Circuit ...................................................................................... 519
17.4.1 Interrupt Pin Control Register (WICR) ....................................................................................... 52017.5 Operation of Interrupt Pin Selecting Circuit .................................................................................... 52317.6 Note on Using Interrupt Pin Selecting Circuit ................................................................................. 524
CHAPTER 18 UART/SIO ................................................................................................. 52518.1 Overview of UART/SIO ................................................................................................................... 52618.2 Configuration of UART/SIO ............................................................................................................ 52718.3 UART/SIO Channel ........................................................................................................................ 52918.4 UART/SIO Pin ................................................................................................................................. 53018.5 Register of UART/SIO .................................................................................................................... 531
18.5.1 Serial Mode Control Register 1 (SMC1) .................................................................................... 53218.5.2 Serial Mode Control Register 2 (SMC2) .................................................................................... 53418.5.3 Serial Status Register (SSR) ..................................................................................................... 53618.5.4 Serial Input Data Register (RDR) .............................................................................................. 53818.5.5 Serial Output Data Register (TDR) ............................................................................................ 539
18.6 UART/SIO Interrupt ........................................................................................................................ 54018.7 Explanation of Operation Mode 0 ................................................................................................... 54118.8 Explanation of Operation Mode 1 ................................................................................................... 548
CHAPTER 19 Dedicated Baud Rate Generator ............................................................ 55519.1 Dedicated Baud Rate Generator .................................................................................................... 55619.2 Channels of Dedicated Baud Rate Generator ................................................................................ 55719.3 Registers of Dedicated Baud Rate Generator ................................................................................ 558
19.3.1 UART/SIO Prescaler Selection Register (PSSR) ...................................................................... 55919.3.2 UART/SIO Baud Rate Setting Register (BRSR) ........................................................................ 561
19.4 Dedicated Baud Rate Generator .................................................................................................... 562
CHAPTER 20 LIN-UART ................................................................................................. 56320.1 Overview of LIN-UART ................................................................................................................... 56420.2 Configuration of LIN-UART ............................................................................................................. 56620.3 LIN-UART Pins ............................................................................................................................... 57120.4 Register of LIN-UART ..................................................................................................................... 572
20.4.1 Serial Control Register (SCR) ................................................................................................... 57320.4.2 LIN-UART Serial Mode Register (SMR) .................................................................................... 575
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20.4.3 Serial Status Register (SSR) ..................................................................................................... 57720.4.4 Receive Data Register, Transmit Data Register (RDR/TDR) .................................................... 57920.4.5 Extended Status Control Register (ESCR) ................................................................................ 58120.4.6 Extended Communication Control Register (ECCR) ................................................................. 58320.4.7 Baud Rate Generator Registers 0 and 1 (BGR0/1) ................................................................... 585
20.5 LIN-UART Interrupt ......................................................................................................................... 58620.5.1 Reception Interrupt Generation and Flag Set Timing ................................................................ 58920.5.2 Transmit Interrupt Generation and Flag Set Timing .................................................................. 591
20.6 LIN-UART Baud Rate ..................................................................................................................... 59320.6.1 Baud Rate Setting ..................................................................................................................... 59520.6.2 Reload Counter ......................................................................................................................... 598
20.7 Operation of LIN-UART .................................................................................................................. 60020.7.1 Operation of Asynchronous Mode (Operation Mode 0, 1) ......................................................... 60220.7.2 Operation of Synchronous Mode (Operation Mode 2) ............................................................... 60620.7.3 Operation of LIN Function (Operation Mode 3) ......................................................................... 60920.7.4 Serial Pins Direct Access .......................................................................................................... 61220.7.5 Bidirectional Communication Function (Normal Mode) ............................................................. 61320.7.6 Master/Slave Type Communication Function (Multi-processor Mode) ...................................... 61520.7.7 LIN Communication Function .................................................................................................... 61820.7.8 Example LIN Communications Flowchart for LIN-UART (Operating Mode 3) ........................... 619
20.8 Notes on Using LIN-UART .............................................................................................................. 621
CHAPTER 21 I2C ............................................................................................................. 62321.1 Overview of I2C ............................................................................................................................... 62421.2 I2C Block Diagram .......................................................................................................................... 62521.3 I2C Channel .................................................................................................................................... 62921.4 I2C Register .................................................................................................................................... 630
21.4.1 I2C Bus Control Register (IBCR0, IBCR1) ................................................................................. 63121.4.2 I2C Bus Status (IBSR) ............................................................................................................... 63721.4.3 I2C Data Register (IDDR) .......................................................................................................... 63921.4.4 I2C Address Register (IAAR) ..................................................................................................... 64021.4.5 I2C Clock Control Register (ICCR) ............................................................................................ 641
21.5 I2C Interrupt .................................................................................................................................... 64321.6 Explanation of Operation of I2C ...................................................................................................... 645
21.6.1 I2C Interface .............................................................................................................................. 64621.6.2 Function to Wakeup MCU from Standby Mode ......................................................................... 654
21.7 Notes on Using I2C ......................................................................................................................... 656
CHAPTER 22 A/D Converter .......................................................................................... 65922.1 Overview of A/D Converter ............................................................................................................. 66022.2 Block Diagram of A/D Converter ..................................................................................................... 66122.3 Pin of A/D Converter ....................................................................................................................... 66422.4 Registers of A/D Converter ............................................................................................................. 665
22.4.1 A/D Control Register 1 (ADC1) .................................................................................................. 66622.4.2 A/D Control Register 2 (ADC2) .................................................................................................. 66922.4.3 A/D Data Register (ADDH and ADDL) ...................................................................................... 671
22.5 Interrupt of A/D Converter ............................................................................................................... 672
xiv
22.6 Operation of A/D Converter ............................................................................................................ 67322.7 Notes on Using A/D Converter ....................................................................................................... 675
CHAPTER 23 D/A Converter .......................................................................................... 67723.1 Overview of D/A Converter ............................................................................................................. 67823.2 Block Diagram of D/A Converter ..................................................................................................... 67923.3 D/A Converter Pin ........................................................................................................................... 68023.4 Registers of D/A Converter ............................................................................................................. 681
23.4.1 D/A Converter Data Register (DAT) .......................................................................................... 68223.4.2 D/A Converter Control Data Register (DACR) ........................................................................... 683
23.5 Explanation of Operations of D/A Converter ................................................................................... 68423.6 Notes on Using D/A Converter ....................................................................................................... 685
CHAPTER 24 LCD Controller ........................................................................................ 68724.1 Overview of LCD Controller ............................................................................................................ 68824.2 Block Diagram of LCD Controller .................................................................................................... 689
24.2.1 LCD Controller Power Supply Voltage (Model with Internal Step-up Circuit) ............................ 69124.2.2 Internal Division Resistance for LCD Controller (Model with No-internal Step-up Circuit) ........ 69224.2.3 External Division Resistance of LCD Controller (Model with No-internal Step-up Circuit) ........ 695
24.3 Pins of LCD Controller .................................................................................................................... 69724.4 LCD Controller Registers ................................................................................................................ 698
24.4.1 LCDC Control Register (LCDCC) .............................................................................................. 69924.4.2 LCDC Enable Register 1 (LCDCE1) .......................................................................................... 70124.4.3 LCDC Enable Register 2 to 6 (LCDCE2 to 6) ............................................................................ 70324.4.4 LCDC Blinking Setting Register 1/2 (LCDCB1/2) ...................................................................... 704
24.5 LCD Controller Display RAM .......................................................................................................... 70524.6 Operation of LCD Controller ........................................................................................................... 707
24.6.1 Output Waveform of LCD Controller Operation (1/2 Duty) ........................................................ 70924.6.2 Output Waveform of LCD Controller Operation (1/3 Duty) ........................................................ 71124.6.3 Output Waveform of LCD Controller Operation (1/4 Duty) ........................................................ 713
24.7 Notes when Using LCD Controller .................................................................................................. 71524.8 Program Example of LCD Controller .............................................................................................. 716
CHAPTER 25 Low-Voltage Detection Reset Circuit .................................................... 71725.1 Overview of Low-Voltage Detection Reset Circuit .......................................................................... 71825.2 Block Diagram of Low-Voltage Detection Reset Circuit .................................................................. 71925.3 Low-Voltage Detection Reset Circuit Pin ........................................................................................ 72025.4 Operation of Low-Voltage Detection Reset Circuit ......................................................................... 721
CHAPTER 26 Clock Supervisor .................................................................................... 72326.1 Overview of Clock Supervisor ......................................................................................................... 72426.2 Block Diagram of Clock Supervisor ................................................................................................ 72526.3 Clock Supervisor Registers ............................................................................................................ 727
26.3.1 Clock Supervisor Control Register (CSVCR) ............................................................................ 72826.4 Operation of Clock Supervisor ........................................................................................................ 730
CHAPTER 27 480-Kbit Flash Memory ........................................................................... 731
xv
27.1 Overview of 480-Kbit Flash Memory ............................................................................................... 73227.2 Registers and Sector/Configuration of Flash Memory .................................................................... 73427.3 Flash Memory Status Register (FSR) ............................................................................................. 73627.4 Flash Memory Sector Write Control Register (SWRE0/1) .............................................................. 73827.5 Flash Memory Auto Algorithm Start-up Method .............................................................................. 74227.6 Check Execution State of Automatic Algorithm .............................................................................. 744
27.6.1 Data Polling Flag (DQ7) ............................................................................................................ 74627.6.2 Toggle Bit Flag (DQ6) ................................................................................................................ 74727.6.3 Timing Limit Over Flag (DQ5) .................................................................................................... 74827.6.4 Sector Deletion Timer Flag (DQ3) ............................................................................................. 74927.6.5 Toggle Bit 2 Flag (DQ2) ............................................................................................................. 750
27.7 Details of Programming/Erasing Flash Memory ............................................................................. 75127.7.1 Read/Reset State in Flash Memory ........................................................................................... 75227.7.2 Data Programming to Flash Memory ......................................................................................... 75327.7.3 Erasing All Data from Flash Memory (Chip Erase) .................................................................... 75527.7.4 Erasing Any Data in Flash Memory (Sector Erasing) ................................................................ 75627.7.5 Sector Erase Suspension in Flash Memory .............................................................................. 75827.7.6 Sector Erase Resumption in Flash Memory .............................................................................. 759
27.8 Features of Flash Security .............................................................................................................. 760
CHAPTER 28 Dual Operation Flash .............................................................................. 76128.1 Overview of Dual Operation Flash .................................................................................................. 76228.2 Access Sector Map of Dual Operation Flash .................................................................................. 76328.3 Operation of Dual Operation Flash ................................................................................................. 765
CHAPTER 29 Basic Information .................................................................................... 76729.1 I/O Map ........................................................................................................................................... 76829.2 Table of Interrupt Causes ............................................................................................................... 86429.3 Memory Map ................................................................................................................................... 87529.4 Instruction Overview ....................................................................................................................... 876
29.4.1 Addressing ................................................................................................................................. 87929.4.2 Special instruction ..................................................................................................................... 88329.4.3 Bit Manipulation Instructions (SETB, CLRB) ............................................................................. 88729.4.4 F2MC-8FX Instructions .............................................................................................................. 88829.4.5 Instruction map .......................................................................................................................... 893
xvi
CHAPTER 1Description (100-pin)
This chapter explains a feature and a basic specification of the SAXOPHONE series.
1.1 Feature of SAXOPHONE Series
1.2 Product Lineup of SAXOPHONE Series
1.3 Notes on Difference Point between Products and Selecting Product
1.4 Block Diagram of SAXOPHONE Series
1.5 Pin Assignment
1.6 Package Dimension
1.7 Pin Description
1.8 I/O Circuit Type
1
CHAPTER 1 Description (100-pin)
1.1 Feature of SAXOPHONE Series
In addition to a compact instruction set, the SAXOPHONE series is a general-purpose single-chip microcontroller built-in abundant peripheral functions.
Feature of SAXOPHONE Series
F2MC-8FX CPU core
Instruction system optimized for controllers
• Multiplication and division instructions
• 16-bit operation
• Bit test branch instruction
• Bit operation instructions etc.
Clock
• Main clock
• Main PLL clock
• Subclock (Note: At selecting the two-system product)
• Sub PLL clock (Note: At selecting the two-system product)
Timers
• 8/16-bit compound timer × 2 channels
• 16-bit reload timer × 2 channels
• 8/16-bit PPG × 2 channels
• 16-bit PPG × 3 channels
• Timebase timer
• Watch prescaler (Note: At selecting the two-system product)
LIN UART
• With full-duplex double buffer
• An asynchronous clock or a synchronous serial transfer can be used.
UART/serial interface
• Switch of UART/SIO is enabled.
I2C
• Within wake up improvement function
External interrupt
• Interrupt by the edge detection. (Select rising edge/falling edge/both edges)
• Can be used to recover from low-power consumption modes.
2
10-bit A/D converter
• 10-bit resolution
Low-power consumption (standby mode)
• Stop mode
• Sleep mode
• Watch mode * Only for two-system product
• Timebase timer mode
I/O port: Max 89
• General-purpose I/O ports (Nch open drain): 8
• General-purpose I/O ports (CMOS) :81
3
CHAPTER 1 Description (100-pin)
1.2 Product Lineup of SAXOPHONE Series
SAXOPHONE series is available in three types. Table 1.2-1 lists the product lineup and Table 1.2-3 lists the CPUs and peripheral functions.
Product Lineup of SAXOPHONE Series
On MASK products, specify single/dual version and whether to include LVD and CSV when issuing themask ROM order. (Specifying CSV without LVD is not available.)LVD: Low-voltage detection resetCSV: Clock supervisor*: No reset output at selected CSV.
Select of Oscillation Stabilization Wait TimeOn MASK products, you can specify the default oscillation stabilization wait time as a mask option whenissuing the mask ROM order.The default oscillation stabilization wait time of the EVA and FLASH products is fixed to maximum value.
Can be select one type from 4 types.
Table 1.2-1 Product lineup of the SAXOPHONE series
Model ROM/RAM Voltage Reset output Option
EVA productsMB95FV100-101 60KB/4KB 3V None 1/2 system selectable
MB95FV100-103 60KB/4KB 5V Yes*1/2 system selectable, LVD and CSV
selectable
3 V products
FLASH products
MB95FXXXS XXKB/XKB 3V None Single system
MB95FXXXW XXKB/XKB 3V None Two system
MASK products
MB95XXX XXKB/XKB 3V None 1/2 system selectable
5 V products
FLASH products
MB95FXXXHS XXKB/XKB 5V Yes Single system, LVD and CSV OFF
MB95FXXXH-100S XXKB/XKB 5V YesSingle system, LVD ON,
CSV OFF
MB95FXXXH-200S XXKB/XKB 5V None Single system, LVD and CSV ON
MB95FXXXHW XXKB/XKB 5V Yes Two-system, LVD and CSV OFF
MB95FXXXH-100W XXKB/XKB 5V Yes Two-system, LVD ON, CSV OFF
MB95FXXXH-200W XXKB/XKB 5V None Two-system, LVD and CSV ON
MASK products
MB95XXXH XXKB/XKB 5V Yes*1/2 system selectable,
LVD and CSV selectable
Table 1.2-2 Select oscillation Stabilization Wait Time (MASK products)
Select Oscillation Stabilization Wait Time Remark
22/FCH 1.0 µs (at external 4 MHz)
212/FCH 1.024 ms (at external 4 MHz)
213/FCH 2.048 ms (at external 4 MHz)
214/FCH 4.096 ms (at external 4 MHz)
4
Table 1.2-3 CPU and peripheral function of SAXOPHONE series
Item Specification
CPU function
Number of basic instructions: 136 instructionsInstruction bit length: 8 bitsInstruction length: 1 to 3 bytesData bit length: 1, 8, and 16 bitsMinimum instruction execution time: 0.1 µs (at internal 10 MHz)Interrupt processing time: 0.9 µs (at internal 10 MHz)
Peri
pher
al f
unct
ion
PortGeneral-purpose I/O ports (Nch open drain) : 8General-purpose I/O ports (CMOS) :81Total :89 (Max)
Timebase timer Interrupt cycle 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (at external 4 MHz)
Watchdog timerReset generation cycle: Main clock at external 10 MHz (105 ms Min)Subclock at 32.768 kHz (250 ms Min) *at selecting two-system product
Wild registers Data for three bytes can be replaced.
I2C bus
Master/slave sending/receivingBus error function, Arbitration functionForwarding direction detection functionGenerating repeatedly and detecting function of the start condition. Within wake up improvement function
UART/SIO
2ch, Data transfer is enabled at UART/SIO. Changeable data length (5/6/7/8 -bit), Built-in baud rate generatorTransfer rate (2400bps-125000bps@10 MHz), Built-in full-duplex double bufferNRZ method transfer format, Error detected functionLSB-first or MSB-first can be selected.Data is available for clock synchronous (SIO) and clock asynchronous (UART).
LIN UARTA wide-range communication speed can be set with the dedicated reload timer. Data transfer is available for clock synchronous and clock asynchronous. LIN function is usable as a LIN master and LIN slave.
A/D converter 16ch. 8-bit or 10-bit resolution can be selected.
16-bit reload timer2ch. Reload, one-shot, and event count mode can be selected. Internal 7 kinds + clock selected from external. Square wave output
8/16-bit composite timer2ch. Can be configured as a 2ch x 8-bit timer or 1ch x 16-bit timer. Built-in timer function, PWC function, PWM function and capture functionInternal 7 kinds + clock selected from external. Square wave output
16-bit PPG3ch. PWM mode or one-shot mode can be selected. Eight selectable clock sourcesSupport for external trigger activation.
8/16-bit PPG2ch. Can be configured as a 2ch x 8-bit PPG or 1ch x 16-bit PPG. Eight selectable clock sources
Watch counterFour selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)Counter value can be set within the range of 0 to 63. (countable one minute)*at selected two-system product
Watch prescalerFour selectable interval times (125 ms, 250 ms, 500 ms, 1 s)*at selected two-system product
External interrupt16ch. Interrupt by edge detection. (Select rising edge/falling edge/both edges)Can be used to recover from standby modes.
Standby Mode Sleep, stop, watch and timebase timer
5
CHAPTER 1 Description (100-pin)
1.3 Notes on Difference Point between Products and Selecting Product
The following describes differences between SAXOPHONE series models and points to note when selecting the device model.
Notes on Difference Point between Products and Selecting Product
Notes on using EVA products
The EVA product is intended to support software development for a number of different F2MC-8FX familyseries and models, and it therefore includes additional functions that may not be included in the targetmodel. Accordingly, access to I/O address of peripheral functions that are not used in the target model isprohibited.
Reading or writing to these prohibited addresses may cause these unused peripheral functions to operateand lead to unexpected hardware or software problems.
Take particular care not to use word, long word, or similar access to read or write odd numbered bytes inthe prohibited areas.
Also, as the read values of prohibited addresses on the EVA product are different to the values on the targetFLASH and MASK products, do not use this data in software processing.
The functions corresponding to certain bits in single-byte registers may not be supported on particularmodels. However, reading or writing to these bits will not cause misoperation of the hardware. Also, as theEVA, FLASH, and MASK products are designed to have identical hardware and software operation, noparticular precautions are required.
Difference of memory space
If the memory size on the EVA product is different to the target FLASH or MASK product, please ensureyou understand these differences when developing software.
A/D converter
The analog characteristics of the A/D converter analog input pins on the EVA product are slightly differentto the characteristics on the FLASH and MASK products. Please refer to the data sheet for the differencesin external analog input impedance before designing the external circuit.
Current consumption
• The current consumption of FLASH products is typically greater than for mask ROM products.
• For the details of current consumption, refer to "Electric characteristics" in data sheet.
• For detailed information on each package, see "1.6 Package Dimension".
• Operating voltage
- The operating voltage is different on different models.
- For the details, see the "data sheet".
Difference of RST/MOD pins
The RST and MOD pins are hysteresis inputs on the MASK products. A pull-down resistor is provided forthe MOD pin.
6
1.4 Block Diagram of SAXOPHONE Series
Figure 1.4-1 shows block diagram of all SAXOPHONE series.
Block Diagram of all SAXOPHONE Series
Figure 1.4-1 Block diagram of all SAXOPHONE series
VCC
P54/TO1
RST
X0,X1
PG2/(X1A)*1
PG0/(Cpin)*2
PG1/(X0A)*1
P00/INT00 to P07/INT07
P22/TO00
P10/UI0
P77/UI1
PE0/INT10 to PE7/INT17
P53/TRG1
VSS
P40/AN08 to P47/AN15
AVCC
P50/SCL0
MOD
P52/PPG1
* 1
P72/SCL1
P74
P75/UCK1
P76/UO1
P71/TI0
P62/TO10
P66/SOT
P70/TO0
PortPort
P11/UO0
P12/UCK0
P21/PPG01
P15,P16
P55/TI1
P23/TO01
P24/EC0
P25/PPG2
P61/PPG11
P60/PPG10
P65/SCK
P67/SIN
P63/TO11
P64/EC1
P14/PPG0
AVSS
AVR
P13/TRG0/ADTG
P20/PPG00
* 2
P51/SDA0
P73/SDA1
P80 to P84
PA0 to PA3
PD0 to PD7
P26/TRG2
P27
P30/AN00 to P37/AN07
Internal bus
External interrupt ch0-7
UART/SIO ch0
16-bit PPG ch0
8/16-bit PPG ch0
8/16-bit compound timer ch0
10-bit A/D
I 2C ch0
16-bit PPG ch1
LIN UART
8/16-bit PPG ch1
8/16-bit compound timer ch1
16-bit reload timer ch0
External interrupt ch8-15
F2MC-8FX CPU
16-bit PPG ch2
16-bit reload timer ch1
I 2C ch1
UART/SIO ch1
ROM
RAM
Interrupt control
Wild register
Reset control
Watch prescaler
Clock control
Watch counter
: One-system product is general-purpose port and two-system product is subclock oscillation. : 5 V-product is Cpin terminal.
7
CHAPTER 1 Description (100-pin)
1.5 Pin Assignment
Figure 1.5-1 are pin assignment of the SAXOPHONE series.
Pin Assignment of SAXOPHONE Series
Figure 1.5-1 Pin Assignment of the SAXOPHONE Series
Vcc
P67
/SIN
P66
/SO
TP
65/S
CK
P64
/EC
1P
63/T
O11
P62
/TO
10P
61/P
PG
11P
60/P
PG
10P
E7/
INT
17P
E6/
INT
16P
E5/
INT
15P
E4/
INT
14P
E3/
INT
13P
E2/
INT
12P
E1/
INT
11P
E0/
INT
10P
D7
PD
6P
D5
PD
4P
D3
PD
2P
D1
Vcc
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
Vss 1 75 PD0(Cpin)/PG0 2 74 PA3INT00/P00 3 73 PA2INT01/P01 4 72 PA1INT02/P02 5 71 PA0INT03/P03 6 70 P84INT04/P04 7 69 P83INT05/P05 8 68 P82INT06/P06 9 67 P81INT07/P07 10 66 P80
UI0/P10 11 65 P77/UI1UO0/P11 12 64 P76/UO1
UCK0/P12 13 63 P75/UCK1TRG0/ADTG/P13 14 62 P74
PPG0/P14 15 61 P73/SDA1P15 16 60 P72/SCL1P16 17 59 P71/TI0
SCL0/P50 18 58 P70/TO0SDA0/P51 19 57 P27PPG1/P52 20 56 P26/TRG2TRG1/P53 21 55 P25/PPG2
TO1/P54 22 54 MODTI1/P55 23 53 X0
AVR 24 52 X1AVcc 25 51 Vss
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
AV
ssA
N00
/P30
AN
01/P
31A
N02
/P32
AN
03/P
33A
N04
/P34
AN
05/P
35A
N06
/P36
AN
07/P
37A
N08
/P40
AN
09/P
41A
N10
/P42
AN
11/P
43A
N12
/P44
AN
13/P
45A
N14
/P46
AN
15/P
47P
PG
00/P
20P
PG
01/P
21T
O00
/P22
TO
01/P
23E
C0/
P24
RS
TP
G1/
X0A
PG
2/X
1A
TOP VIEW
100
8
1.6 Package Dimension
SAXOPHONE series is available in one type of package. The package dimensions below are for reference only. Contact Fujitsu for the nominal package dimensions.
Package Dimension of FPT-100P-M05
Figure 1.6-1 Package Dimension of FPT-100P-M05
100-pin plastic LQFP Lead pitch 0.50 mm
Package width × package length
14.0 × 14.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.70 mm MAX
Weight 0.65g
Code(Reference)
P-LFQFP100-14×14-0.50
100-pin plastic LQFP(FPT-100P-M05)
(FPT-100P-M05)
C 2003 FUJITSU LIMITED F100007S-c-4-6
14.00±0.10(.551±.004)SQ
16.00±0.20(.630±.008)SQ
1 2 5
26
51
76 50
75
100
0.50(.020) 0.20±0.05(.008±.002)
M0.08(.003)0.145±0.055
(.0057±.0022)
0.08(.003)
"A"
INDEX.059 –.004
+.008–0.10+0.20
1.50(Mounting height)
0˚~8˚
0.50±0.20(.020±.008)0.60±0.15
(.024±.006)
0.25(.010)
0.10±0.10(.004±.004)
Details of "A" part
(Stand off)
*
Dimensions in mm (inches).Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.
9
CHAPTER 1 Description (100-pin)
1.7 Pin Description
Table 1.7-1 shows pin description. The alphabet in the "Circuit Type" column of Table 1.7-1 corresponds to the one in the "Classification" column of Table 1.8-1 .
Pin Description
Table 1.7-1 Pin Description (1 / 4)
Pin No. Pin name Circuit
type Function description
1 VSS - Power supply (GND) pin.
2 PG0/(C pin) H General-purpose I/O port (at 3 V). Capacitance connection pin (at 5 V).
3 P00/INT00
CGeneral-purpose I/O port. These pins are also used for external interrupt input. The large current port.
4 P01/INT01
5 P02/INT02
6 P03/INT03
7 P04/INT04
8 P05/INT05
9 P06/INT06
10 P07/INT07
11 P10/UI0 GGeneral-purpose I/O port. These pins are also used for UART/SIO ch0 data input.
12 P11/UO0
H
General-purpose I/O port. These pins are also used for UART/SIO ch0 data output.
13 P12/UCK0General-purpose I/O port. These pins are also used for UART/SIO ch0 clock I/O.
14P13/TRG0/ADTG
General-purpose I/O port. These pins are also used for 16-bit PPG ch0 trigger input (TRG) and A/D trigger input (ADTG).
15 P14/PPG0General-purpose I/O port. These pins are also used for 16-bit PPG ch0 output.
16 P15General-purpose I/O port.
17 P16
18 P50/SCL0
I
General-purpose I/O port. These pins are also used for I2C ch0 clock I/O.
19 P51/SDA0General-purpose I/O port. These pins are also used for I2C ch0 data I/O.
10
20 P52/PPG1
H
General-purpose I/O port. These pins are also used for 16-bit PPG ch1 output.
21 P53/TRG1General-purpose I/O port. These pins are also used for 16-bit PPG ch1 trigger input.
22 P54/T01 General-purpose I/O port. These pins are also used for 16-bit reload timer ch1 output. 23 P55/TI1
24 AVR - A/D reference input pin.
25 AVCC - Power supply pin for A/D.
26 AVSS - Power supply (GND) pin for A/D.
27 P30/AN00
JGeneral-purpose I/O port. These pins are also used for A/D analog input.
28 P31/AN01
29 P32/AN02
30 P33/AN03
31 P34/AN04
32 P35/AN05
33 P36/AN06
34 P37/AN07
35 P40/AN08
JGeneral-purpose I/O port. These pins are also used for A/D analog input.
36 P41/AN09
37 P42/AN10
38 P43/AN11
39 P44/AN12
40 P45/AN13
41 P46/AN14
42 P47/AN15
43 P20/PPG00
H
General-purpose I/O port. These pins are also used for 8/16-bit PPG ch0 output. 44 P21/PPG01
45 P22/TO00 General-purpose I/O port. These pins are also used for 8/16-bit compound timer ch0 output. 46 P23/TO01
47 P24/EC0General-purpose I/O port. These pins are also used for 8/16-bit compound timer ch0 clock input.
48 RST B’ Reset pin.
49 X0A/PG1A/H Crystal oscillation pin (32 kHz). One-system product is general-purpose port.
50 X1A/PG2
51 VSS - Power supply (GND) pin.
52 X1A Crystal oscillation pin.
53 X0
Table 1.7-1 Pin Description (2 / 4)
Pin No. Pin name Circuit
type Function description
11
CHAPTER 1 Description (100-pin)
54 MOD B Operation mode specification pin.
55 P25/PPG2
H
General-purpose I/O port. These pins are also used for 16-bit PPG ch2 output.
56 P26/TRG2General-purpose I/O port. These pins are also used for 16-bit PPG ch2 trigger input.
57 P27 General-purpose I/O port.
58 P70/TO0
H
General-purpose I/O port. These pins are also used for 16-bit reload timer ch0 output.
59 P71/TI0General-purpose I/O port. These pins are also used for 16-bit reload timer ch0 input.
60 P72/SCL1
I
General-purpose I/O port. These pins are also used for I2C ch1 clock I/O.
61 P73/SDA1General-purpose I/O port. These pins are also used for I2C ch1 data I/O.
62 P74
H
General-purpose I/O port.
63 P75/UCK1General-purpose I/O port. These pins are also used for UART/SIO ch1 clock I/O.
64 P76/UO1General-purpose I/O port. These pins are also used for UART/SIO ch1 data output.
65 P77/UI1 GGeneral-purpose I/O port. These pins are also used for UART/SIO ch1 data input.
66 P80
OGeneral-purpose I/O port.
67 P81
68 P82
69 P83
70 P84 H
71 PA0
K General-purpose I/O port. 72 PA1
73 PA2
74 PA3
75 PD0 K General-purpose I/O port.
76 VCC - Power supply pin.
77 PD1
K General-purpose I/O port.
78 PD2
79 PD3
80 PD4
81 PD5
82 PD6
83 PD7
Table 1.7-1 Pin Description (3 / 4)
Pin No. Pin name Circuit
type Function description
12
84 PE0/INT10
PGeneral-purpose I/O port. These pins are also used for external interrupt input.
85 PE1/INT11
86 PE2/INT12
87 PE3/INT13
88 PE4/INT14
89 PE5/INT15
90 PE6/INT16
91 PE7/INT17
92 P60/PPG10
K
General-purpose I/O port. These pins are also used for 8/16-bit PPG ch1 output. 93 P61/PPG11
94 P62/TO10 General-purpose I/O port. These pins are also used for 8/16-bit compound timer ch1 output. 95 P63/TO11
96 P64/EC1General-purpose I/O port. These pins are also used for 8/16-bit compound timer ch1 clock input.
97 P65/SCKGeneral-purpose I/O port. These pins are also used for LIN UART clock I/O.
98 P66/SOTGeneral-purpose I/O port. These pins are also used for LIN UART data output.
99 P67/SIN LGeneral-purpose I/O port. These pins are also used for LIN UART data input.
100 VCC - Power supply pin.
Table 1.7-1 Pin Description (4 / 4)
Pin No. Pin name Circuit
type Function description
13
CHAPTER 1 Description (100-pin)
1.8 I/O Circuit Type
Table 1.8-1 lists the I/O circuit types. Also, the alphabet in the "Classification" column of Table 1.8-1 corresponds to the one in the "Circuit Type" column of Table 1.7-1 .
I/O Circuit Type
Table 1.8-1 I/O Circuit Type (1 / 3)
Classi-fication
Circuit Remark
A
Oscillation circuitFeedback resistor High-speed side: approx 1 MΩ. Low-speed side: approx 10 MΩ.Only for low-speed side oscillation of 3 V-product* Feedback resistor: approx 24 MΩ. Dumping resistor: approx 144 kΩ.*:Excluding for MB95FV100
BInput exclusive useHysteresis input (only mask product)Pull-down resistance supported (only mask product)
B'Hysteresis input (only mask product)Reset output supported (only 5 V product)
CCMOS outputHysteresis input
GCMOS outputHysteresis input
Standby control
X1 (X1A)
X0 (X0A)
Reset outputNch
Pch
Nch
Standby controlExternal interrupt enable
Pch
Nch
Standby control
Pull-up controlR
14
HCMOS outputHysteresis inputPull-up control
INch open drain outputCMOS inputHysteresis input
J
CMOS outputHysteresis inputAnalog inputPull-up control
KCMOS outputHysteresis input
LCMOS outputCMOS inputHysteresis input
Table 1.8-1 I/O Circuit Type (2 / 3)
Classi-fication
Circuit Remark
Pch
Nch
Standby control
Pull-up control R
Nch
Standby control
Pch
Nch
A/D control
Pull-up control R
Standby control
Analog input
Pch
Nch
Standby control
Pch
Nch
Standby control
15
CHAPTER 1 Description (100-pin)
ONch open drain outputHysteresis input
PCMOS outputHysteresis inputPull-up control
Table 1.8-1 I/O Circuit Type (3 / 3)
Classi-fication
Circuit Remark
Nch
Standby control
Pch
Nch
Pull-up control R
Standby control External interrupt control
16
CHAPTER 1Description (80-pin)
This chapter explains a feature and a basic specification of the RESERVE1 series.
1.1 Feature of RESERVE1 Series
1.2 Product Lineup of RESERVE1 Series
1.3 Notes on Difference Point between Products and Selecting Product
1.4 Block Diagram of RESERVE1 Series
1.5 Pin Assignment
1.6 Package Dimension
1.7 Pin Description
1.8 I/O Circuit Type
17
CHAPTER 1 Description (80-pin)
1.1 Feature of RESERVE1 Series
In addition to a compact instruction set, the RESERVE1 series of general-purpose, single-chip microcontrollers feature a wide range of internal peripheral functions.
Feature of RESERVE1 Series
F2MC-8FX CPU core
Instruction system optimized for controllers
• Multiplication and division instructions
• 16-bit operation
• Bit test branch instruction
• Bit operation instructions etc.
Clock
• Main clock
• Main PLL clock
• Sub clock *: Only two-system product
• Sub PLL clock *: Only two-system product
Timer
• 8/16-bit compound timer × 2 channels
• 16-bit reload timer × 2 channels
• 8/16-bit PPG × 2 channels
• 16-bit PPG × 3 channels
• Timebase timer
• Watch prescaler *:Only two-system product
LIN UART
• With full-duplex double buffer
• An asynchronous clock or a synchronous serial transfer can be used.
UART/serial interface
• Switch of UART/SIO is enabled.
I2C
• Within wake up improvement function
External interrupt
• Interrupt by the edge detection (Select rising edge/falling edge/both edges)
• Can be used to recover from low-power consumption modes.
18
10-bit A/D converter
• 10-bit resolution
Low-power consumption (standby mode)
• Stop mode
• Sleep mode
• Watch mode *: Only two-system product
• Timebase timer mode
I/O port: Max 71
• General-purpose I/O ports (Nch open drain): 6
• General-purpose I/O ports (CMOS): 65
19
CHAPTER 1 Description (80-pin)
1.2 Product Lineup of RESERVE1 Series
RESERVE1 series is available in three types. Table 1.2-1 lists the product lineup and Table 1.2-3 lists the CPUs and peripheral functions.
Product Lineup of RESERVE1 Series
On MASK products, specify single/dual version and whether to include LVD and CSV when issuing the
mask ROM order. (Specifying CSV without LVD is not available.)
LVD: Low-voltage detection reset
CSV: Clock supervisor
*: No reset output at selected CSV.
Selection of Oscillation Stabilization Wait TimeOn MASK products, you can specify the default oscillation stabilization wait time as a mask option when
issuing the mask ROM order.
The default oscillation stabilization wait time is fixed to the maximum value on the EVA and FLASH
products.
*:Can be selected one type from 4 types.
Table 1.2-1 Product lineup of the RESERVE1 series
Model ROM/RAM Voltage Reset Output Option
EVA productsMB95FV100-101 60KB/4KB 3V None 1/2 system selectable
MB95FV100-103 60KB/4KB 5V Yes *1/2 system selectable,
LVD and CSV selectable
3V products
FLASH products
MB95FXXXS XXKB/XKB 3V None Single system
MB95FXXXW XXKB/XKB 3V None Two-system
MASK products
MB95XXX XXKB/XKB 3V None 1/2 system selectable
5V products
FLASH products
MB95FXXXHS XXKB/XKB 5V Yes Single system, LVD and CSV OFF
MB95FXXXH-100S XXKB/XKB 5V YesSingle system, LVD ON,
CSV OFF
MB95FXXXH-200S XXKB/XKB 5V None Single system, LVD and CSV ON
MB95FXXXHW XXKB/XKB 5V Yes Two-system, LVD and CSV OFF
MB95FXXXH-100W XXKB/XKB 5V Yes Two-system, LVD ON, CSV OFF
MB95FXXXH-200W XXKB/XKB 5V None Two-system, LVD and CSV ON
MASK products
MB95XXXH XXKB/XKB 5V Yes *1/2 system selectable,
LVD and CSV selectable
Table 1.2-2 Selection of Oscillation Stabilization Wait Time (MASK product)
Selection of Oscillation Stabilization Wait Time Remark
22/FCH 1.0 µs (at external 4 MHz)
212/FCH 1.024 ms (at external 4 MHz)
213/FCH 2.048 ms (at external 4 MHz)
214/FCH 4.096 ms (at external 4 MHz)
20
Table 1.2-3 CPU and Peripheral Function of RESERVE1 Series
Item Specification
CPU function
Number of basic instructions: 136 instructionsInstruction bit length: 8 bitsInstruction length: 1 to 3 bytesData bit length: 1, 8, and 16 bitsMinimum instruction execution time: 0.1 µs (at internal 10 MHz)Interrupt processing time: 0.9 µs (at internal 10 MHz)
Peri
pher
al f
unct
ion
portGeneral-purpose I/O ports (Nch open drain) : 6General-purpose I/O ports (CMOS) :65Total :71 (Max)
Timebase timer Interrupt cycle 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (external 4 MHz)
Watchdog timerReset generation cycle: Main clock at external 10 MHz (Min 105 ms)
Subclock at 32.768 kHz (Min 250 ms) *: At selecting the two-system product.
Wild registers Data for three bytes can be replaced.
I2C bus
2ch. Master/slave sending/receivingBus error function and arbitration functionForwarding direction detection functionGenerating repeatedly and the detecting function of the start condition.Within wake up improvement function
UART/SIO
2ch. Data transfer is enabled at UART/SIO.Changeable data length (5/6/7/8 -bit), Built-in baud rate generatorTransfer rate (2400 bps to 125000 bps@10 MHz), Built-in full-duplex double bufferNRZ method transfer format, Error detected functionLSB-first or MSB-first can be selected.Data transfer is available for clock synchronous (SIO) and clock asynchronous (UART).
LIN UARTA wide-range communication speed can be set with the dedicated reload timer.Data transfer is available for clock synchronous and clock asynchronous.LIN function is usable as a LIN master and LIN slave.
A/D converter 16 ch. 8-bit or 10-bit resolution can be selected.
16-bit reload timer2ch. Reload, one-shot, and event count mode can be selectedInternal 7 kinds + clock selected from external. Square wave output.
8/16-bit composite timer2 ch. Can be configured as a 2 ch x 8-bit timer or 1 ch x 16-bit timer.Built-in timer function, PWC function, PWM function and capture functionInternal 7 kinds + clock selected from external. Square wave output.
16-bit PPG3 ch. PWM mode or one-shot mode can be selected.Eight selectable clock sourcesSupport for external trigger activation.
8/16-bit PPG2 ch. Can be configured as a 2 ch x 8-bit PPG or 1 ch x 16-bit PPG.Eight selectable clock sources
Watch counterFour selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)Counter value can be set within the range of 0 to 63. (countable one minute)*: At selecting the two-system product
Watch prescalerFour selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)*: At selecting the two-system product.
External interrupt16 ch. Interrupt by edge detection. (Select rising edge/falling edge/both edges)Can be used to recover from standby modes.
Standby Mode Sleep, stop, watch, timebase timer
21
CHAPTER 1 Description (80-pin)
1.3 Notes on Difference Point between Products and Selecting Product
The following describes differences between RESERVE1 series models and points to note when selecting the device model.
Notes on Selecting Product
Notes on using EVA products
The EVA product is intended to support software development for a number of different F2MC-8FX familyseries and models, and it includes additional functions that may not be included in the target model.Accordingly, access to peripheral functions and I/O addresses that are not used in the target model isprohibited.
Reading or writing to these prohibited addresses may cause these unused peripheral functions to operateand lead to unexpected hardware or software problems.
Take particular care not to use word, long word, or similar access to read or write odd numbered bytes inthe prohibited areas.
Also, as the read values of prohibited addresses on the EVA product are different to the values on the targetFLASH and MASK products, do not use this data in software processing.
The functions corresponding to certain bits in single-byte registers may not be supported on particularmodels. However, reading or writing to these bits will not cause misoperation of the hardware. Also, as theEVA, FLASH, and MASK products are designed to have identical hardware and software operation, noparticular precautions are required.
Differences of memory space
If the memory size on the EVA product is different to the target FLASH or MASK product, please ensureyou confirm these differences enough when developing software.
A/D converter
The analog characteristics of the A/D converter analog input pins on the EVA product are slightly differentto the ones on the FLASH and MASK products. Please refer to the data sheet for the differences in externalanalog input impedance enough before designing the external circuit.
Current consumption
• The current consumption of FLASH products is typically greater than for mask ROM products.
• For the details of current consumption, refer to "Electric characteristics" in data sheet.
• For detailed information on each package, see "1.6 Package Dimension".
• Operating voltage
- The operating voltage is different from each model.
- For the details, see the "data sheet".
Differences of RST/MOD Pins
The RST and MOD pins are hysteresis inputs on the MASK products. A pull-down resistor is provided forthe MOD pin.
22
1.4 Block Diagram of RESERVE1 Series
Figure 1.4-1 shows block diagram of all RESERVE1 series.
Block Diagram of All RESERVE1 Series
Figure 1.4-1 Block Diagram of All RESERVE1 Series
VCCVSS
P80 to P81
P54/TO1
MOD
P55/TI1
P52/PPG1
P64/EC1
P66/SOT
P25/PPG2
P26/TRG2
P73/SDA1
P13/TRG0/ADTG
P20/PPG00
P61/PPG11
P60/PG10
P63/TO11
X0,X1
PG2/(X1A)*1
PG1/(X0A)*1
P11/UO0
P12/UCK0
P62/TO10
RST
P40/AN08 to P47/AN15
P30/AN00 to P37/AN07
P21/PPG01
P22/TO00
P23/TO01
P24/EC0
P00/INT00 to P07/INT07
P10/UI0
PG0/(Cpin)* 2
P50/SCL0
P51/SDA0
P14/PPG0
P53/TRG1
P65/SCK
P67/SIN
P76/UO1
P77/UI1
P70/TO0
P72/SCL1
P74
P75/UCK1
P71/TI0
PE0/INT10 to PE7/INT17
AVCC
AVSS
AVR
UART/SIO ch0
16bit PPG ch0
8/16bit PPG ch0
10bit A/D
I 2C ch0
16bit PPG ch1
LIN UART
8/16bit PPG ch1
16bit Relordtimer ch0
F2MC-8FX CPU
16bit PPG ch2
16bit reload timer ch1
I 2C ch1
UART/SIO ch1
ROM
RAM
Interrupt control
Wild register
Reset control
Clock control
Watch prescaler
Watch counter
External interrupt ch0-7
8/16-bitcompound timer ch1
8/16-bitcompound timer ch0
Internal bus
External interrupt ch8-15
Port Port
* 1: One-system product is general-purpose port and two-system productis subclock oscillation.
* 2: 5V-product is Cpin terminal.
23
CHAPTER 1 Description (80-pin)
1.5 Pin Assignment
Figure 1.5-1 shows pin assignment of RESERVE1 series.
Pin Assignment of RESERVE1 Series
Figure 1.5-1 Pin Assignment of the RESERVE1 Series
AV
ssP
37/A
N0 7
P36
/AN
06P
35/A
N05
P34
/AN
04P
33/A
N03
P32
/AN
02P
31/A
N01
P30
/AN
00P
40/A
N08
P41
/AN
09P
42/A
N10
P43
/AN
11P
44/A
N12
P45
/AN
13P
46/A
N14
P47
/AN
15P
73/S
DA
1P
72/S
CL1
P71
/TI0
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AVcc 1 60 P70/TO0AVR 2 59 P67/SINP74 3 58 P66/SOT
UCK1/P75 4 57 P65/SCKUO1/P76 5 56 P64/EC1UI1/P77 6 55 P63/TO11
P81 7 54 P62/TO10P80 8 53 P61/PPG11
INT17/PE7 9 52 P60/PPG10INT16/PE6 10 51 P55/TI1INT15/PE5 11 50 P54/TO1INT14/PE4 12 49 P53/TRG1INT13/PE3 13 48 P52/PPG1INT12/PE2 14 47 P51/SDA0INT11/PE1 15 46 P50/SCL0INT10/PE0 16 45 P26/TRG2
MOD 17 44 P25/PPG2X0 18 43 P24/EC0X1 19 42 P23/TO01
Vss 20 41 P22/TO00
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Vcc
(Cpi
n)/P
G0
PG
2/X
1AP
G1/
X0A
RS
TIN
T00
/P00
INT
01/P
01IN
T02
/P02
INT
03/P
03IN
T04
/P04
INT
05/P
05IN
T06
/P06
INT
07/P
07U
I0/P
10U
O0/
P11
UC
K0/
P12
TR
G0/
AD
TG
/P13
PP
G0/
P14
PP
G00
/P20
PP
G01
/P21
TOP VIEW
80
24
1.6 Package Dimension
RESERVE1 series is available in one type of package.The package dimension below is for reference only.Contact Fujitsu for the nominal package dimension.
Package Dimension of FPT-80P-M11
Figure 1.6-1 Package Dimensions of FPT-80P-M11
80-pin plastic LQFP Lead pitch 0.65 mm
Package width × package length
14.00 × 14.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.70 mm MAX
Code(Reference)
P-LQFP80-14×14-0.65
80-pin plastic LQFP(FPT-80P-M11)
(FPT-80P-M11)
C 2003 FUJITSU LIMITED F80016S-c-3-6
1 2 0
21
4061
80
4160
14.00±0.10(.551±.004)SQ
16.00±0.20(.630±.008)SQ
INDEX
0.65(.026) 0.32±0.05(.013±.002)
M0.13(.005)
"A"
(.006±.002)0.145±0.055
0.10(.004)
0.50±0.20(.020±.008)0.60±0.15
(.024±.006)
0~8˚
.059 –.004+.008
–0.10+0.20
1.50(Mounting height)
0.25(.010)
0.10±0.10(.004±.004)(Stand off)
Details of "A" part
*
Dimensions in mm (inches).Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.
25
CHAPTER 1 Description (80-pin)
1.7 Pin Description
Table 1.7-1 shows pin description. The alphabet in the "Circuit Type" column of Table 1.7-1 corresponds to the one in the "Classification" column of Table 1.8-1 .
Pin Description
Table 1.7-1 Pin description (1 / 4)
PinNo.
Pin nameCircuittype
Function description
1 AVcc - Power supply pin for A/D.
2 AVR - A/D reference input pin.
3 P74 H General-purpose I/O port.
4 P75/UCK1
H
General-purpose I/O port.These pins are also used for UART/SIO ch1 clock I/O.
5 P76/UO1General-purpose I/O port.These pins are also used for UART/SIO ch1 data output.
6 P77/UI1 GGeneral-purpose I/O port.These pins are also used for UART/SIO ch1 data input.
7 P81O General-purpose I/O port.
8 P80
9 PE7/INT17
PGeneral-purpose I/O port.These pins are also used for external interrupt input.
10 PE6/INT16
11 PE5/INT15
12 PE4/INT14
13 PE3/INT13
14 PE2/INT12
15 PE1/INT11
16 PE0/INT10
17 MOD B Operation mode specification pin.
18 X0A Crystal oscillation pin.
19 X1
20 Vss - Power supply (GND) pin.
21 Vcc - Power supply pin.
22 PG0/(C pin) H General-purpose I/O port (at 3 V). Capacitance connection pin (at 5 V).
26
23 X1A/PG2A/H
Crystal oscillation pin (32 kHz).One-system product is general-purpose port.24 X0A/PG1
25 RST B’ Reset pin.
26 P00/INT00
CGeneral-purpose I/O port.These pins are also used for external interrupt input. The large current port.
27 P01/INT01
28 P02/INT02
29 P03/INT03
30 P04/INT04
31 P05/INT05
32 P06/INT06
33 P07/INT07
34 P10/UI0 GGeneral-purpose I/O port.These pins are also used for UART/SIO ch0 data input.
35 P11/U00
H
General-purpose I/O port.These pins are also used for UART/SIO ch0 data output.
36 P12/UCK0General-purpose I/O port.These pins are also used for UART/SIO ch0 clock I/O.
37P13/TRG0/ADTG
General-purpose I/O port.These pins are also used for 16-bit PPG ch0 trigger input (TRG0) andA/D trigger input (ADTG).
38 P14/PPG0General-purpose I/O port.These pins are also used for 16-bit PPG ch0 output.
39 P20/PPG00
H
General-purpose I/O port.These pins are also used for 8/16-bit PPG ch0 output.40 P21/PPG01
41 P22/T000 General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch0 output.42 P23/T001
43 P24/EC0General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch0 clock input.
44 P25/PPG2 General-purpose I/O port.These pins are also used for 16-bit PPG ch2 output.45 P26/TRG2
46 P50/SCL0
I
General-purpose I/O port.These pins are also used for I2C ch0 clock I/O.
47 P51/SDA0General-purpose I/O port.These pins are also used for I2C ch0 data I/O.
Table 1.7-1 Pin description (2 / 4)
PinNo.
Pin nameCircuittype
Function description
27
CHAPTER 1 Description (80-pin)
48 P52/PPG1
H
General-purpose I/O port.These pins are also used for 16-bit PPG ch1 output.
49 P53/TRG1General-purpose I/O port.These pins are also used for 16-bit PPG ch1 trigger input.
50 P54/TO1General-purpose I/O port.These pins are also used for 16-bit reload timer ch1 output.
51 P55/TI1General-purpose I/O port.These pins are also used for 16-bit reload timer ch1 output.
52 P60/PPG10
K
General-purpose I/O port.These pins are also used for 8/16-bit PPG ch1 output. 53 P61/PPG11
54 P62/TO10 General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch1 output. 55 P63/TO11
56 P64/EC1General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch1 clock input.
57 P65/SCKGeneral-purpose I/O port.These pins are also used for LIN UART clock I/O.
58 P66/SOTGeneral-purpose I/O port.These pins are also used for LIN UART data output.
59 P67/SIN LGeneral-purpose I/O port.These pins are also used for LIN UART data input.
60 P70/T00
H
General-purpose I/O port.These pins are also used for 16-bit reload timer ch0 output.
61 P71/TI0General-purpose I/O port.These pins are also used for 16-bit reload timer ch0 input.
62 P72/SCL1
I
General-purpose I/O port.These pins are also used for I2C ch1 clock I/O.
63 P73/SDA1General-purpose I/O port.These pins are also used for I2C ch1 data I/O.
Table 1.7-1 Pin description (3 / 4)
PinNo.
Pin nameCircuittype
Function description
28
64 P47/AN15
JGeneral-purpose I/O port.These pins are also used for A/D analog input.
65 P46/AN14
66 P45/AN13
67 P44/AN12
68 P43/AN11
69 P42/AN10
70 P41/AN09
71 P40/AN08
72 P37/AN07
JGeneral-purpose I/O port.These pins are also used for A/D analog input.
73 P36/AN06
74 P35/AN05
75 P34/AN04
76 P33/AN03
77 P32/AN02
78 P31/AN01
79 P30/AN00
80 AVss - Power supply (GND) pin for A/D.
Table 1.7-1 Pin description (4 / 4)
PinNo.
Pin nameCircuittype
Function description
29
CHAPTER 1 Description (80-pin)
1.8 I/O Circuit Type
Table 1.8-1 lists the I/O circuit types. Also, the alphabet in the "Classification" column of Table 1.8-1 corresponds to the one in the "Circuit Type" column of Table 1.7-1 .
I/O Circuit Type
Table 1.8-1 I/O Circuit Type (1 / 3)
Classi-
ficationCircuit Remark
A
• Oscillation circuit
• Feedback resistance value
High-speed side: approx. 1 MΩ
Low-speed side: approx. 10 MΩ
• Only low-speed side oscillation of 3 V*
Feedback resistance: approx. 24 MΩ
Dumping resistance: approx. 144 kΩ
*: Excluding MB95FV100
B
• Input exclusive use
• Hysteresis input (only mask product)
• Pull-down resistance (only mask product)
B'
• Hysteresis input (only mask product)
• Reset output supported (only 5 V product)
C
• CMOS output
• Hysteresis input
G
• CMOS output
• CMOS input
• Hysteresis input
• Pull-up control is available.
Standby control
X1 (X1A)
X0 (X0A)
Reset outputNch
Pch
Nch
Standby controlExternal interrupt enable
Pch
Nch
Standby control
Pull-up controlR
30
H
• CMOS output
• Hysteresis input
• Pull-up control is available.
I
• Nch open drain output
• CMOS input
• Hysteresis input
J
• CMOS output
• Hysteresis input
• Analog input
• Pull-up control is available.
K
• CMOS output
• Hysteresis input
L
• CMOS output
• CMOS input
• Hysteresis input
Table 1.8-1 I/O Circuit Type (2 / 3)
Classi-
ficationCircuit Remark
Pch
Nch
Standby control
Pull-up control R
Nch
Standby control
Pch
Nch
A/D control
Pull-up control R
Standby control
Analog input
Pch
Nch
Standby control
Pch
Nch
Standby control
31
CHAPTER 1 Description (80-pin)
O
• Nch open drain output
• Hysteresis input
P
• CMOS output
• Hysteresis input
• Pull-up control is available.
Table 1.8-1 I/O Circuit Type (3 / 3)
Classi-
ficationCircuit Remark
Nch
Standby control
Pch
Nch
Pull-up control R
Standby control External interrupt control
32
CHAPTER 1Description (64-pin)
This chapter describes the features and basic specifications of the BASSOON series.
1.1 Feature of BASSOON Series
1.2 Product Lineup of BASSOON Series
1.3 Notes on Difference Point between Products and Selecting Product
1.4 Block Diagram of the BASSOON Series
1.5 Pin Assignment
1.6 Package Dimension
1.7 Pin Description
1.8 I/O Circuit Type
33
CHAPTER 1 Description (64-pin)
1.1 Feature of BASSOON Series
In addition to a compact instruction set, the BASSOON series is general-purpose, single-chip microcontrollers with a wide range of internal peripheral functions.
Feature of BASSOON Series
F2MC-8FX CPU core
Instruction system optimized for controllers
• Multiplication and division instructions
• 16-bit operation
• Branch instruction by bit test
• Bit manipulation instructions etc.
Clock
• Main clock
• Main PLL clock
• Sub clock (Note: Only two-system product)
• Sub PLL clock (Note: Only two-system product)
Timer
• 8/16-bit compound timer × 2 channels
• 16-bit reload timer
• 8/16-bit PPG × 2 channels
• 16-bit PPG × 2 channels
• Timebase timer
• Watch prescaler (Note: Only two-system product)
LIN UART
• With full-duplex double buffer
• An asynchronous clock or a synchronous serial transfer can be used.
UART/serial interface
• Switch of UART/SIO is enabled.
I2C
• With wake up improvement function
External interrupt
• Interrupt by the edge detection (Select rising edge/falling edge/both edges)
• Can be used to recover from low-power consumption modes.
34
10-bit A/D converter
• 10-bit resolution
Low-power consumption (standby mode)
• Stop mode
• Sleep mode
• Watch mode *: Only two-system product
• Timebase timer mode
I/O port: Max 55
• General-purpose I/O ports (Nch open drain): 6
• General-purpose I/O ports (CMOS): 49
35
CHAPTER 1 Description (64-pin)
1.2 Product Lineup of BASSOON Series
BASOON series is available in three types. Table 1.2-1 lists the product lineup and Table 1.2-3 lists the CPUs and peripheral functions.
Product Lineup of BASSOON Series
On MASK products, specify single/dual version and whether to include LVD and CSV when issuing the
mask ROM order. (Specifying CSV without LVD is not available.)
LVD: Low-voltage detection reset
CSV: Clock supervisor
*: No reset output at selected CSV.
Selection of Oscillation Stabilization Wait TimeOn MASK products, you can specify the default value of oscillation stabilization wait time as a mask
option when issuing the mask ROM order.
The default oscillation stabilization wait time is fixed the maximum value on the EVA and FLASH
products.
*:Can be selected one from 4 types.
Table 1.2-1 Product Lineup of BASSOON Series
Model ROM/RAM Voltage Reset Output Option
EVA productsMB95FV100-101 60KB/4KB 3V None 1/2 system selectable
MB95FV100-103 60KB/4KB 5V Yes *1/2 system selectable,
LVD and CSV selectable
3V products
FLASH products
MB95F108S 60KB/2KB 3V None Single system
MB95F108W 60KB/2KB 3V None Two-system
MASK products
MB95107 48KB/2KB 3V None 1/2 system selectable
5V products
FLASH products
MB95F108HS 60KB/2KB 5V Yes Single system, LVD and CSV OFF
MB95F108H-100S 60KB/2KB 5V Yes Single system, LVD ON, CSV OFF
MB95F108H-200S 60KB/2KB 5V None Single system, LVD and CSV ON
MB95F108HW 60KB/2KB 5V Yes Two-system, LVD and CSV OFF
MB95F108H-100W 60KB/2KB 5V Yes Two-system, LVD ON, CSV OFF
MB95F108H-200W 60KB/2KB 5V None Two-system, LVD and CSV ON
MASK products
MB95108H 60KB/2KB 5V Yes *1/2 system selectable,
LVD and CSV selectable
Table 1.2-2 Selection of Oscillation Stabilization Wait Time (MASK product)
Selection of Oscillation Stabilization Wait Time Remark
22/FCH 1.0 µs (at external 4 MHz)
212/FCH 1.024 ms (at external 4 MHz)
213/FCH 2.048 ms (at external 4 MHz)
214/FCH 4.096 ms (at external 4 MHz)
36
Table 1.2-3 CPU and Peripheral Function of BASSOON Series
Item Specification
CPU function
Number of basic instructions: 136 instructionsInstruction bit length: 8 bitsInstruction length: 1 to 3 bytesData bit length: 1, 8, and 16 bitsMinimum instruction execution time: 0.1 µs (at internal 10 MHz)Interrupt processing time: 0.9 µs (at internal 10 MHz)
Peri
pher
al f
unct
ion
PortGeneral-purpose I/O ports (Nch open drain) : 6General-purpose I/O ports (CMOS) :49Total :55 (Max)
Timebase timer Interrupt cycle 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (external 4 MHz)
Watchdog timerReset generation cycle: Main clock at external 10 MHz (Min 105 ms)
Sub clock at 32.768 kHz (Min 250 ms) *: At selecting the two-system product.
Wild register Data for three bytes can be replaced.
I2C bus
Master/slave sending/receivingBus error function and arbitration functionForwarding direction detection functionGenerating repeatedly and detecting function of the start condition.Within wake up improvement function
UART/SIO
Data transfer is enabled at UART/SIO.Changeable data length (5/6/7/8 -bit), Built-in baud rate generatorTransfer rate (2400 bps to 125000 bps@10 MHz), Built-in full-duplex double bufferNRZ method transfer format, Error detected functionLSB-first or MSB-first can be selected.Data transfer is available for clock synchronous (SIO) and clock asynchronous (UART).
LIN UARTA wide-range communication speed can be set with the dedicated reload timer.Data transfer is available for clock synchronous and clock asynchronous.LIN function is usable as a LIN master and LIN slave.
A/D converter 12 ch. 8-bit or 10-bit resolution can be selected.
16-bit reload timerReload, one-shot, and event count mode can be selectedInternal 7 kinds + clock selected from external. Square wave output.
8/16-bit composite timer2 ch. Can be configured as a 2 ch x 8-bit timer or 1 ch x 16-bit timer.Built-in timer function, PWC function, PWM function and capture functionInternal 7 kinds + clock selected from external. Square wave output.
16-bit PPG2 ch. PWM mode or one-shot mode can be selected.Eight selectable clock sourcesSupport for external trigger activation
8/16-bit PPG2 ch. Can be configured as a 2 ch x 8-bit PPG or 1 ch x 16-bit PPG.Eight selectable clock sources
Watch counterFour selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)Counter value can be set within the range of 0 to 63. (countable one minute)*: At selecting the two-system product
Watch prescaler Four selectable interval times (125 ms, 250 ms, 500 ms, 1 s)
External interrupt12 ch. Interrupt by edge detection. (Select rising edge/falling edge/both edges)Can be used to recover from standby modes.
Standby Mode Sleep, stop, watch, timebase timer
37
CHAPTER 1 Description (64-pin)
1.3 Notes on Difference Point between Products and Selecting Product
The following describes the differences in each model of series and points to note when selecting the device model.
Notes on Difference Point between Products and Selecting Product
Notes on using EVA products
The EVA product is intended to support software development for a number of different F2MC-8FX familyseries and models, and it therefore includes additional functions that may not be included in the targetmodel. Accordingly, access to peripheral functions and I/O addresses that are not used in the target modelis prohibited.
Reading or writing to these prohibited addresses may cause these unused peripheral functions to operateand lead to unexpected hardware or software problems.
Take particular care not to use word, long word, or similar access to read or write odd numbered bytes inthe prohibited areas.
Also, as the read values of prohibited addresses on the EVA product are different to the values on the targetFLASH and MASK products, do not use this data in software processing.
The functions corresponding to certain bits in single-byte registers may not be supported on particularmodels. However, reading or writing to these bits will not cause misoperation of the hardware. Also, as theEVA, FLASH, and MASK products are designed to have identical hardware and software operation, noparticular precautions are required.
Differences of memory space
If the memory size on the EVA product is different to the target FLASH or MASK product, please ensure
you confirm these differences enough when developing software.
A/D converter
The analog characteristics of the A/D converter analog input pins on the EVA product are slightly different
to the ones on the FLASH and MASK products. Please refer to the data sheet for the differences in external
analog input impedance enough before designing the external circuit.
Current consumption
• The current consumption of FLASH products is typically greater than for mask ROM products.
• For the details of current consumption, refer to "Electric characteristics" in data sheet.
• For detailed information on each package, see "1.6 Package Dimension".
• Operating voltage
- The operating voltage is different from each model.
- For the details, see the "data sheet".
Difference of RST/MOD pins
The RST and MOD pins are hysteresis inputs on the MASK products. A pull-down resistor is provided for
the MOD pin.
38
1.4 Block Diagram of the BASSOON Series
Figure 1.4-1 shows block diagram of all BASSOON series.
Block Diagram of All BASSOON Series
Figure 1.4-1 Block Diagram of All BASSOON Series
VSS
P80toP83
P14/PPG0
P53/TRG1
P65/SCK
P67/SIN
PE0/INT10 to PE3/INT13
AVCC
AVSS
AVR
P52/PPG1
P50/SCL0
P51/SDA0
P40/AN08 to P43/AN11
P30/AN00 to P37/AN07
P21/PPG01
P22/TO00
P23/TO01
P24/EC0
P12/UCK0
P62/TO10
P61/PPG11
P60/PPG10
P63/TO11
P00/INT00 to P07/INT07
P10/UI0
P64/EC1
P71/TI0
P66/SOT
P70/TO0
RST
X0,X1
PG2/(X1A)*1
PG1/(X0A)*1
PG0/(Cpin)* 2
MOD
VCC
P13/TRG0/ADTG
P20/PPG00
P11/UO0
External interrupt ch0-7
UART/SIO
16bit PPG ch0
8/16bit PPG ch0
10bit A/D
I 2C
16bit PPG ch1
LIN UART
8/16bit PPG ch1
16bit reload timer
External interrupt ch8-11
F2MC-8FX CPU
ROM
RAM
Reset control
Clock control
Watch prescaler
Watch counter
Interrupt control
Wild register
8/16-bitcompound timer ch1
Internal bus8/16-bitcompound timer ch0
Port Port
* 1: One-system product is general-purpose port and two-system productis subclock oscillation.
* 2: 5V-product is Cpin terminal.
39
CHAPTER 1 Description (64-pin)
1.5 Pin Assignment
Figure 1.5-1 is pin assignment of BASSOON series.
Pin Assignment of BASSOON Series
Figure 1.5-1 Pin Assignment of BASSOON Series
AV
ssP
30/A
N00
P31
/AN
01P
32/A
N02
P33
/AN
03P
34/A
N04
P35
/AN
05P
36/A
N06
P37
/AN
07P
40/A
N08
P41
/AN
09P
42/A
N10
P43
/AN
11P
67/S
INP
66/S
OT
P65
/SC
K
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc 1 48 P64/EC1AVR 2 47 P63/TO11
INT13/PE3 3 46 P62/TO10INT12/PE2 4 45 P61/PPG11INT11/PE1 5 44 P60/PPG10INT10/PE0 6 43 P53/TRG1
P83 7 42 P52/PPG1P82 8 41 P51/SDA0P81 9 40 P50/SCL0P80 10 39 P24/EC0
TI0/P71 11 38 P23/TO01TO0/P70 12 37 P22/TO00
MOD 13 36 P21/PPG01X0 14 35 P20/PPG00X1 15 34 P14/PPG0
Vss 16 33 P13/TRG0/ADT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Vcc
(Cpi
n)/P
G0
PG
2/X
1AP
G1/
X0A
RS
TIN
T00
/P00
INT
01/P
01IN
T02
/P02
INT
03/P
03IN
T04
/P04
INT
05/P
05IN
T06
/P06
INT
07/P
07U
I0/P
10U
O0/
P11
UC
K0/
P12
64
TOP VIEW
40
1.6 Package Dimension
BASSOON series is available in one type of package.The package dimension below is for reference only.Contact Fujitsu for the nominal package dimension for the released product.
Package Dimension of FPT-64P-M03
Figure 1.6-1 Package Dimension of FPT-64P-M03
64-pin plastic LQFP Lead pitch 0.50 mm
Package width × package length
10.0 × 10.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.70 mm MAX
Weight 0.32g
Code(Reference)
P-LFQFP64-10×10-0.50
64-pin plastic LQFP(FPT-64P-M03)
(FPT-64P-M03)
LEAD No.
Details of "A" part
0.25(.010)
(Stand off)(.004±.004)0.10±0.10
(.024±.006)0.60±0.15
(.020±.008)0.50±0.20
1.50+0.20–0.10
+.008–.004.059
0˚~8˚
"A"
0.08(.003)
(.006±.002)0.145±0.055
0.08(.003) M(.008±.002)0.20±0.050.50(.020)
12.00±0.20(.472±.008)SQ
10.00±0.10(.394±.004)SQ
INDEX
49
64
3348
17
32
161
2003 FUJITSU LIMITED F64009S-c-5-8C
(Mounting height)
*
Dimensions in mm (inches).Note: The values in parentheses are reference values
Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.
41
CHAPTER 1 Description (64-pin)
1.7 Pin Description
Table 1.7-1 shows pin description. The alphabet in the "Circuit Type" column of Table 1.7-1 corresponds to the one in the "Classification" column of Table 1.8-1 .
Pin Description
Table 1.7-1 Pin Description (1 / 3)
Pin No. Pin name Circuit
type Function description
1 AVcc - Power supply pin for A/D.
2 AVR - A/D reference input pin.
3 PE3/INT13
PGeneral-purpose I/O port.These pins are also used for external interrupt input.
4 PE2/INT12
5 PE1/INT11
6 PE0/INT10
7 P83
O General-purpose I/O port.8 P82
9 P81
10 P80
11 P71/T10
H
General-purpose I/O port.These pins are also used for 16-bit reload timer ch0 output.
12 P70/T00General-purpose I/O port.These pins are also used for 16-bit reload timer ch0 input.
13 MOD B Operation mode specification pin.
14 X0A Crystal oscillation pin.
15 X1
16 Vss - Power supply (GND) pin.
17 Vcc - Power supply pin.
18 PG0/(C pin) H General-purpose I/O port (at 3 V). Capacitance connection pin (at 5 V).
19 X1A/PG2A/H
Crystal oscillation pin (32 kHz).One-system product is general-purpose port.20 X0A/PG1
21 RST B’ Reset pin.
42
22 P00/INT00
CGeneral-purpose I/O port.These pins are also used for external interrupt input. The large current port.
23 P01/INT01
24 P02/INT02
25 P03/INT03
26 P04/INT04
27 P05/INT05
28 P06/INT06
29 P07/INT07
30 P10/UI0 GGeneral-purpose I/O port.These pins are also used for UART/SIO ch0 data input.
31 P11/U00
H
General-purpose I/O port.These pins are also used for UART/SIO ch0 data output.
32 P12/UCK0General-purpose I/O port.These pins are also used for UART/SIO ch0 clock I/O.
33P13/TRG0/ADTG
General-purpose I/O port.These pins are also used for 16-bit PPG ch0 trigger input (TRG0) andA/D trigger input (ADTG).
34 P14/PPG0General-purpose I/O port.These pins are also used for 16-bit PPG ch0 output.
35 P20/PPG00
H
General-purpose I/O port.These pins are also used for 8/16-bit PPG ch0 output.36 P21/PPG01
37 P22/T000 General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch0 output.38 P23/T001
39 P24/EC0General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch0 clock input.
40 P50/SCL0
I
General-purpose I/O port.These pins are also used for I2C ch0 clock I/O.
41 P51/SDA0General-purpose I/O port.These pins are also used for I2C ch0 data I/O.
42 P52/PPG1
H
General-purpose I/O port.These pins are also used for 16-bit PPG ch1 output.
43 P53/TRG1General-purpose I/O port.These pins are also used for 16-bit PPG ch1 trigger input.
Table 1.7-1 Pin Description (2 / 3)
Pin No. Pin name Circuit
type Function description
43
CHAPTER 1 Description (64-pin)
44 P60/PPG10
K
General-purpose I/O port.These pins are also used for 8/16-bit PPG ch1 output. 45 P61/PPG11
46 P62/T010 General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch1 output.47 P63/T011
48 P64/EC1General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch1 clock input.
49 P65/SCKGeneral-purpose I/O port.These pins are also used for LIN UART clock I/O.
50 P66/SOTGeneral-purpose I/O port.These pins are also used for LIN UART data output.
51 P67/SIN LGeneral-purpose I/O port.These pins are also used for LIN UART data input.
52 P43/AN11
JGeneral-purpose I/O port.These pins are also used for A/D analog input.
53 P42/AN10
54 P41/AN09
55 P40/AN08
56 P37/AN07
57 P36/AN06
58 P35/AN05
59 P34/AN04
60 P33/AN03
61 P32/AN02
62 P31/AN01
63 P30/AN00
64 AVss - Power supply (GND) pin for A/D.
Table 1.7-1 Pin Description (3 / 3)
Pin No. Pin name Circuit
type Function description
44
1.8 I/O Circuit Type
Table 1.8-1 lists the I/O circuit types. Also, the alphabet in the "Classification" column of Table 1.8-1 corresponds to the one in the "Circuit Type" column of Table 1.7-1 .
I/O Circuit Type
Table 1.8-1 I/O Circuit Type (1 / 3)
Classi-fication
Circuit Remark
A
• Oscillation circuit
• Feedback resistance value
High-speed side: approx. 1 MΩ
Low-speed side: approx. 10 MΩ
• Only low-speed side oscillation of 3 V*
Feedback resistance: approx. 24 MΩ
Dumping resistance: approx. 144 kΩ
*: Excluding MB95FV100
B
• Input exclusive use
• Hysteresis input (only mask product)
• Pull-down resistance (only mask product)
B'
• Hysteresis input (only mask product)
• Reset output supported (only 5 V product)
C
• CMOS output
• Hysteresis input
G
• CMOS output
• CMOS input
• Hysteresis input
• Pull-up control is available.
Standby control
X1 (X1A)
X0 (X0A)
Reset outputNch
Pch
Nch
Standby controlExternal interrupt enable
Pch
Nch
Standby control
Pull-up controlR
45
CHAPTER 1 Description (64-pin)
H
• CMOS output
• Hysteresis input
• Pull-up control is available.
I
• Nch open drain output
• CMOS input
• Hysteresis input
J
• CMOS output
• Hysteresis input
• Analog input
• Pull-up control is available.
K
• CMOS output
• Hysteresis input
L
• CMOS output
• CMOS input
• Hysteresis input
Table 1.8-1 I/O Circuit Type (2 / 3)
Classi-fication
Circuit Remark
Pch
Nch
Standby control
Pull-up control R
Nch
Standby control
Pch
Nch
A/D control
Pull-up control R
Standby control
Analog input
Pch
Nch
Standby control
Pch
Nch
Standby control
46
O
• Nch open drain output
• Hysteresis input
P
• CMOS output
• Hysteresis input
• Pull-up control is available.
Table 1.8-1 I/O Circuit Type (3 / 3)
Classi-fication
Circuit Remark
Nch
Standby control
Pch
Nch
Pull-up control R
Standby control External interrupt control
47
CHAPTER 1 Description (64-pin)
48
CHAPTER 1Description (48-pin)
This chapter explains a feature and a basic specification of the CLARINET series.
1.1 Features of CLARINET Series
1.2 Product Lineup of CLARINET Series
1.3 Notes on Difference Point between Products and Selecting Product
1.4 Block Diagram of CLARINET Series
1.5 Pin Assignment
1.6 Package Dimension
1.7 Pin Description
1.8 I/O Circuit Type
49
CHAPTER 1 Description (48-pin)
1.1 Features of CLARINET Series
In addition to a compact instruction set, the CLARINET series is general-purpose, single-chip microcontrollers with a wide range of internal peripheral functions.
Feature of CLARINET Series
F2MC-8FX CPU core
Instruction system optimized for controllers
• Multiplication and division instructions
• 16-bit operation
• Branch instruction by bit test
• Bit manipulation instructions etc.
Clock
• Main clock
• Main PLL clock
• Sub clock *: Only two-system product
• Sub PLL clock *: Only two-system product
Timer
• 8/16-bit compound timer × 2 channels
• 8/16-bit PPG × 2 channels
• 16-bit PPG
• Timebase timer
• Watch prescaler *: Only two-system product
LIN UART
• With full-duplex double buffer
• An asynchronous clock or a synchronous serial transfer can be used.
UART/serial interface
• Switch of UART/SIO is enabled.
I2C
• Within wake improvement function
External interrupt
• Interrupt by the edge detection (Select rising edge/falling edge/both edges)
• Can be used to recover from low-power consumption modes.
50
10-bit A/D converter
• 10-bit resolution
Low-power consumption (standby mode)
• Stop mode
• Sleep mode
• Watch mode *: Only two-system product
• Timebase timer mode
I/O port: Max 40
• General-purpose I/O ports (Nch open drain): 2
• General-purpose I/O ports (CMOS): 38
51
CHAPTER 1 Description (48-pin)
1.2 Product Lineup of CLARINET Series
CLARINET series is available in three types. Table 1.2-1 lists the product lineup and Table 1.2-3 lists the CPUs and peripheral functions.
Product Lineup of CLARINET Series
On MASK products, specify single/dual system and whether to include LVD and CSV when issuing the
mask ROM order. (Specifying CSV without LVD is not available.)
LVD: Low-voltage detection reset
CSV: Clock supervisor
*: No reset output at selected CSV.
Selection of Oscillation Stabilization Wait TimeOn MASK products, you can specify the default value of oscillation stabilization delay time as a mask
option when issuing the mask ROM order.
The default oscillation stabilization delay time is fixed the maximum value on the EVA and FLASH
versions.
*Can be selected one from 4 types.
Table 1.2-1 Product Lineup of CLARINET Series
Model ROM/RAM Voltage Reset Output Option
EVA productsMB95FV100-101 60KB/4KB 3V None 1/2 system selectable
MB95FV100-103 60KB/4KB 5V Yes *1/2 system selectable, LVD and CSV
selectable
3V products
FLASH products
MB95F118S 60KB/2KB 3V None Single system
MB95F118W 60KB/2KB 3V None Two-system
MASK products
MB95116 32KB/1KB 3V None 1/2 system selectable
5V products
FLASH products
MB95F118HS XXKB/XKB 5V Yes Single system, LVD and CSV OFF
MB95F118H-100S XXKB/XKB 5V Yes Single system, LVD ON, CSV OFF
MB95F118H-200S XXKB/XKB 5V None Single system, LVD and CSV ON
MB95F118HW XXKB/XKB 5V Yes Two-system, LVD and CSV OFF
MB95F118H-100W XXKB/XKB 5V Yes Two-system, LVD ON, CSV OFF
MB95F118H-200W XXKB/XKB 5V None Two-system, LVD and CSV ON
MASK products
MB95116H XXKB/XKB 5V Yes *1/2 system selectable, LVD and CSV
selectable
Table 1.2-2 Selection of Oscillation Stabilization Wait Time (MASK product)
Selection of Oscillation Stabilization Wait Time Remark
22/FCH 1.0 µs (at external 4 MHz)
212/FCH 1.024 ms (at external 4 MHz)
213/FCH 2.048 ms (at external 4 MHz)
214/FCH 4.096 ms (at external 4 MHz)
52
Table 1.2-3 CPU and Peripheral Function of CLARINET Series
Item Specification
CPU function
Number of basic instructions: 136 instructionsInstruction bit length: 8 bitsInstruction length: 1 to 3 bytesData bit length: 1, 8, and 16 bitsMinimum instruction execution time: 0.1 µs (at internal 10 MHz)Interrupt processing time: 0.9 µs (at internal 10 MHz)
Peri
pher
al f
unct
ion
PortGeneral-purpose I/O ports (Nch open drain) : 2General-purpose I/O ports (CMOS) :38Total :40 (Max)
Timebase timer Interrupt cycle 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (external 4 MHz)
Watchdog timerReset generation cycle: Main clock at external 10 MHz (Min 105 ms)
Subclock at 32.768 kHz (Min 250 ms)
Wild register Data for three bytes can be replaced.
I2C bus
Master/slave sending/receivingBus error function and arbitration functionForwarding direction detection functionGenerating repeatedly and detecting function of the start condition.Within wake up improvement function
UART/SIO
Data transfer is enabled at UART/SIO.Changeable data length (5/6/7/8 -bit), Built-in baud rate generatorTransfer rate (2400 bps to 125000 bps@10 MHz), Built-in full-duplex double bufferNRZ method transfer format, error detected functionLSB-first or MSB-first can be selected.Data transfer is available for clock synchronous (SIO) and clock asynchronous (UART).
LIN UARTA wide-range communication speed can be set with the dedicated reload timer.Data transfer is available for clock synchronous and clock asynchronous.LIN function is usable as a LIN master and LIN slave.
A/D converter 8 ch. 8-bit or 10-bit resolution can be selected.
8/16-bit composite timer2 ch. Can be configured as a 2 ch x 8-bit timer or 1 ch x 16-bit timer.Built-in timer function, PWC function, PWM function and capture functionInternal 7 kinds + clock selected from external. Square wave output.
16-bit PPGPWM mode or one-shot mode can be selected.Eight selectable clock sourcesSupport for external trigger activation
8/16-bit PPG2 ch. Can be configured as a 2 ch x 8-bit PPG or 1 ch x 16-bit PPG.Eight selectable clock sources
Watch counterFour selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)Counter value can be set within the range of 0 to 63. (countable one minute)*: At selecting the two-system product
Watch prescalerFour selectable interval times (125 ms, 250 ms, 500 ms, 1 s) *:At selecting the two-system product
External interrupt8 ch. Interrupt by edge detection. (Select rising edge/falling edge/both edges)Can be used to recover from standby modes.
Standby mode Sleep, stop, watch, timebase timer
53
CHAPTER 1 Description (48-pin)
1.3 Notes on Difference Point between Products and Selecting Product
The following describes differences between CLARINET series models and points to note when selecting the device model.
Notes on Difference Point between Products and Selecting Product
Notes on using EVA products
The EVA product is intended to support software development for a number of different F2MC-8FX familyseries and models, and it includes additional functions that may not be included in the target model.Accordingly, access to peripheral functions and I/O addresses that are not used in the target model isprohibited.
Reading or writing to these prohibited addresses may cause these unused peripheral functions to operateand lead to unexpected hardware or software problems.
Take particular care not to use word, long word, or similar access to read or write odd numbered bytes inthe prohibited areas.
Also, as the read values of prohibited addresses on the EVA product are different to the values on the targetFLASH and MASK products, do not use this data in software processing.
The functions corresponding to certain bits in single-byte registers may not be supported on particularmodels. However, reading or writing to these bits will not cause misoperation of the hardware. Also, as theEVA, FLASH, and MASK products are designed to have identical hardware and software operation, noparticular precautions are required.
Differences of memory space
If the memory size on the EVA product is different to the target FLASH or MASK product, please ensure
you understand these differences when developing software.
A/D converter
The analog characteristics of the A/D converter analog input pins on the EVA product are slightly different
to the characteristics on the FLASH and MASK products. Please refer to the data sheet for the differences
in external analog input impedance enough before designing the external circuit.
Current consumption
• The current consumption of FLASH products is typically greater than for mask ROM products.
• For the details of current consumption, refer to "Electric characteristics" in data sheet.
• For detailed information on each package, see "1.6 Package Dimension".
• Operating voltage
- The operating voltage is different for each model.
- For the details, see the "data sheet".
Difference of RST/MOD pins
The RST and MOD pins are hysteresis inputs on the MASK products. A pull-down resistor is provided for
the MOD pin.
54
1.4 Block Diagram of CLARINET Series
Figure 1.4-1 shows the block diagram of all CLARINET series.
Block Diagram of All CLARINET Series
Figure 1.4-1 Block Diagram of All CLARINET Series
P50/SCL0
P10/UI0
P14/PPG0
AVCC
AVSS
P62/TO10
P13/TRG0/ADTG
P20/PPG00
P30/AN00 to P37/AN07
P21/PPG01
P22/TO00
P23/TO01
P24/EC0
VSS
P61/PPG11
P60/PPG10
P65/SCK
P67/SIN
P63/TO11
P64/EC1
P66/SOT
P11/UO0
RST
X0,X1
PG2/(X1A)*1
PG1/(X0A)*1
PG0/(Cpin)* 2
MOD * 1: One-system product is general-purpose port and two-system productis subclock oscillation.VCC
* 2: 5V-product is Cpin terminal.
P51/SDA0
P12/UCK0
P15
P00/INT00 to P07/INT07
UART/SIO
16-bit PPG
8/16-bit PPG ch0
8/16bitcompound timer ch0
10-bit A/D
I 2C
LIN UART
8/16-bit PPG ch1
8/16-bitcompound timer ch1
F2MC-8FX CPU
ROM
RAM
Reset control
Clock control
Watch prescaler
Watch timer
Port Port
Interrupt control
Wild register
External interrupt
Internal bus
55
CHAPTER 1 Description (48-pin)
1.5 Pin Assignment
Figure 1.5-1 shows the pin assignment of CLARINET series.
Pin Assignment of CLARINET Series
Figure 1.5-1 Pin Assignment of CLARINET Series
P64
/EC
1P
63/T
O11
P62
/TO
10P
61/P
PG
11P
60/P
PG
10P
15P
14/P
PG
0P
13/T
RG
0/A
DT
GP
12/U
CK
0P
11/U
O0
P10
/UI0
P07
/INT
07
47 46 45 44 43 42 41 40 39 38 37
SCK/P65 1 36 P06/INT06SOT/P66 2 35 P05/INT05SIN/P67 3 34 P04/INT04
AN07/P37 4 33 P03/INT03AN06/P36 5 32 P02/INT02AN05/P35 6 31 P01/INT01AN04/P34 7 30 P00/INT00AN03/P33 8 29 RSTAN02/P32 9 28 X0A/PG1AN01/P31 10 27 X1A/PG2AN00/P30 11 26 PG0/(Cpin)
AVss 12 25 Vcc
13 14 15 16 17 18 19 20 21 22 23 24
AV
ccE
C0/
P24
TO
01/P
23T
O00
/P22
PP
G01
/P21
PP
G00
/P20
SD
A0/
P51
SC
L0/P
50M
OD
X0
X1
Vss
48
TOP VIEW
56
1.6 Package Dimension
CLARINET series is available in one type of package.The package dimension below is for reference only. Contact Fujitsu for the nominal package dimension.
Package Dimension of FPT-48P-M13
Figure 1.6-1 Package Dimension of FPT-48P-M13
48-pin plastic QFP Lead pitch 0.80 mm
Package width × package length
10 × 10 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 2.35 mm MAX
Code(Reference)
P-QFP44-10×10-0.80
48-pin plastic QFP(FPT-48P-M13)
(FPT-48P-M13)
C 2003 FUJITSU LIMITED F48023S-c-3-4
(.013±.002)0.32±0.050.80(.031)
M0.20(.008)
0.10(.004)
(.007±.002)0.17±0.0610.00±0.20(.394±.008)SQ
13.10±0.40(.516±.016)SQ
1 1 2
13
2437
48
2536
INDEX
Details of "A" part
0.80±0.20(.031±.008)
0.88±0.15(.035±.006)
0.25(.010)
.008 –.008+.004
–0.20+0.10
0.20
(Stand off)
1.95+0.40–0.20
+.016–.008.077
(Mounting height)
0~8˚
"A"
0.10(.004)
*
Dimensions in mm (inches).Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.
57
CHAPTER 1 Description (48-pin)
1.7 Pin Description
Table 1.7-1 shows pin description. The alphabet in the "Circuit Type" column of Table 1.7-1 corresponds to the one in the "Classification" column of Table 1.8-1 .
Pin Description
Table 1.7-1 Pin Description (1 / 3)
Pin No. Pin name Circuit
type Function description
1 P65/SCK
K
General-purpose I/O port.These pins are also used for LIN UART clock I/O.
2 P66/SOTGeneral-purpose I/O port.These pins are also used for LIN UART data output.
3 P67/SIN LGeneral-purpose I/O port.These pins are also used for LIN UART data input.
4 P37/AN07
JGeneral-purpose I/O port.These pins are also used for A/D analog input.
5 P36/AN06
6 P35/AN05
7 P34/AN04
8 P33/AN03
9 P32/AN02
10 P31/AN01
11 P30/AN00
12 AVss - Power supply (GND) pin for A/D.
13 AVcc - Power supply pin for A/D.
14 P24/EC0
H
General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch0 clock input.
15 P23/T001 General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch0 output.16 P22/T000
17 P21/PPG01 General-purpose I/O port.These pins are also used for 8/16-bit PPG ch0 output.18 P20/PPG00
19 P51/SDA0
I
General-purpose I/O port.These pins are also used for I2C ch0 data I/O.
20 P50/SCL0General-purpose I/O port.These pins are also used for I2C ch0 clock I/O.
58
21 MOD B Operation mode specification pin.
22 X0A Crystal oscillation pin.
23 X1
24 Vss - Power supply (GND) pin.
25 Vcc - Power supply pin.
26 PG0/(C pin) H General-purpose I/O port (at 3 V). Capacitance connection pin (at 5 V).
27 X1A/PG2A/H
Crystal oscillation pin (32 kHz).One-system product is general-purpose port.28 X0A/PG1
29 RST B’ Reset pin.
30 P00/INT00
CGeneral-purpose I/O port.These pins are also used for external interrupt input. The large current port.
31 P01/INT01
32 P02/INT02
33 P03/INT03
34 P04/INT04
35 P05/INT05
36 P06/INT06
37 P07/INT07
38 P10/UI0 GGeneral-purpose I/O port.These pins are also used for UART/SIO ch0 data input.
39 P11/U00
H
General-purpose I/O port.These pins are also used for UART/SIO ch0 data output.
40 P12/UCK0General-purpose I/O port.These pins are also used for UART/SIO ch0 clock I/O.
41P13/TRG0/ADTG
General-purpose I/O port.These pins are also used for 16-bit PPG ch0 trigger input (TRG0) andA/D trigger input (ADTG).
42 P14/PPG0General-purpose I/O port.These pins are also used for 16-bit PPG ch0 output.
43 P15 General-purpose I/O port.
Table 1.7-1 Pin Description (2 / 3)
Pin No. Pin name Circuit
type Function description
59
CHAPTER 1 Description (48-pin)
44 P60/PPG10
K
General-purpose I/O port.These pins are also used for 8/16-bit PPG ch1 output.45 P61/PPG11
46 P62/T010 General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch1 output.47 P63/T011
48 P64/EC1General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch1 clock input.
Table 1.7-1 Pin Description (3 / 3)
Pin No. Pin name Circuit
type Function description
60
1.8 I/O Circuit Type
Table 1.8-1 lists the I/O circuit types. Also, the alphabet in the "Classification" column of Table 1.8-1 corresponds to the one in the "Circuit Type" column of Table 1.7-1 .
I/O Circuit Type
Table 1.8-1 I/O Circuit Type (1 / 2)
Classi-fication
Circuit Remark
A
• Oscillation circuit
• Feedback resistance value
High-speed side: approx. 1 MΩ
Low-speed side: approx. 10 MΩ
• Only low-speed side oscillation of 3 V*
Feedback resistance: approx. 24 MΩ
Dumping resistance: approx. 144 kΩ
*: Excluding MB95FV100
B
• Input exclusive use
• Hysteresis input (only mask product)
• Pull-down resistance (only mask product)
B'
• Hysteresis input (only mask product)
• Reset output supported (only 5 V product)
C
• CMOS output
• Hysteresis input
G
• CMOS output
• CMOS input
• Hysteresis input
• Pull-up control is available.
Standby control
X1 (X1A)
X0 (X0A)
Reset outputNch
Pch
Nch
Standby controlExternal interrupt enable
Pch
Nch
Standby control
Pull-up controlR
61
CHAPTER 1 Description (48-pin)
H
• CMOS output
• Hysteresis input
• Pull-up control is available.
I
• Nch open drain output
• CMOS input
• Hysteresis input
J
• CMOS output
• Hysteresis input
• Analog input
• Pull-up control is available.
K
• CMOS output
• Hysteresis input
L
• CMOS output
• CMOS input
• Hysteresis input
Table 1.8-1 I/O Circuit Type (2 / 2)
Classi-fication
Circuit Remark
Pch
Nch
Standby control
Pull-up control R
Nch
Standby control
Pch
Nch
A/D control
Pull-up control R
Standby control
Analog input
Pch
Nch
Standby control
Pch
Nch
Standby control
62
CHAPTER 1Description (32-pin)
This chapter explains a feature and a basic specification of the OBOE series.
1.1 Feature of OBOE Series
1.2 Product Lineup of OBOE Series
1.3 Notes on Difference Point between Products and Selecting Product
1.4 Block Diagram of OBOE Series
1.5 Pin Assignment
1.6 Package Dimension
1.7 Pin Description
1.8 I/O Circuit Type
63
CHAPTER 1 Description (32-pin)
1.1 Feature of OBOE Series
In addition to a compact instruction set, the OBOE series is general-purpose, single-chip microcontrollers with a wide range of internal peripheral functions.
Feature of OBOE Series
F2MC-8FX CPU core
Instruction system optimized for controllers
• Multiplication and division instructions
• 16-bit operation
• Bit test by branch instruction
• Bit operation instructions etc.
Clock
• Main clock
• Main PLL clock
• Sub clock *only two-system product
• Sub PLL clock *only two-system product
Timer
• 8/16-bit compound timer × 2 channels
• 8/16-bit PPG × 2 channels
• 16-bit PPG
• Timebase timer
• Watch prescaler *only two-system product
LIN UART
• With full-duplex double buffer
• An asynchronous clock or a synchronous serial transfer can be used.
UART/serial interface
• Switch of UART/SIO is enabled.
External interrupt
• Interrupt by the edge detection (Select rising edge/falling edge/both edges)
• Can be used to recover from low-power consumption mode.
10-bit A/D converter
• 10-bit resolution
64
Low-power consumption (standby mode)
• Stop mode
• Sleep mode
• Watch mode *only two-system product
• Timebase timer mode
I/O port: Max 24
• General-purpose I/O ports (CMOS): 24
65
CHAPTER 1 Description (32-pin)
1.2 Product Lineup of OBOE Series
OBOE series is available in three types. Table 1.2-1 lists the product lineup and Table 1.2-3 lists the CPUs and peripheral functions.
Product Lineup of OBOE Series
On MASK products, specify single/dual system and whether to include LVD and CSV when issuing the
mask ROM order. (Specifying CSV without LVD is not available.)
LVD: Low-voltage detection reset
CSV: Clock supervisor
*: No reset output at selected CSV
Selection of oscillation Stabilization Wait TimeOn MASK products, you can specify the default value of oscillation stabilization wait time as a mask
option when issuing the mask ROM order.
The default oscillation stabilization wait time is fixed to the maximum value on the EVA and FLASH
products.
*: Can be selected one from 4 types.
Table 1.2-1 Product Lineup of OBOE Series
Model ROM/RAM Voltage Reset Output Option
EVA products
MB95FV100-101 60KB/4KB 3V None 1/2 system selectable
MB95FV100-103 60KB/4KB 5V Yes *1/2 system selectable, LVD and CSV
selectable
3V products
FLASH products
MB95FXXXS XXKB/XKB 3V None Single system
MB95FXXXW XXKB/XKB 3V None Two-system
MASK products MB95XXX XXKB/XKB 3V None 1/2 system selectable
5V products
FLASH products
MB95FXXXHS XXKB/XKB 5V Yes Single system, LVD and CSV OFF
MB95FXXXH-100S XXKB/XKB 5V Yes Single system, LVD ON and CSV OFF
MB95FXXXH-200S XXKB/XKB 5V None Single system, LVD and CSV ON
MB95FXXXHW XXKB/XKB 5V Yes Two-system, LVD and CSV OFF
MB95FXXXH-100W XXKB/XKB 5V Yes Two-system, LVD ON, CSV OFF
MB95FXXXH-200W XXKB/XKB 5V None Two-system, LVD and CSV ON
MASK products MB95XXXH XXKB/XKB 5V Yes *1/2 system selectable, LVD and CSV
selectable
Table 1.2-2 Selection of oscillation Stabilization Wait Time (MASK products)
Selection of Oscillation Stabilization Wait Time Remarks
22/FCH 1.0 µs (at external 4 MHz)
212/FCH 1.024 ms (at external 4 MHz)
213/FCH 2.048 ms (at external 4 MHz)
214/FCH 4.096 ms (at external 4 MHz)
66
Table 1.2-3 CPU and Peripheral Function of OBOE Series
Item Specification
CPU function
Number of basic instructions: 136 instructionsInstruction bit length: 8 bitsInstruction length: 1 to 3 bytesData bit length: 1, 8, and 16 bitsMinimum instruction execution time: 0.1 µs (at internal 10 MHz)Interrupt processing time: 0.9 µs (at internal 10 MHz)
Peri
pher
al f
unct
ion
Port General-purpose I/O ports (CMOS): 24 (Max)
Timebase timer Interrupt cycle 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (external 4 MHz)
Watchdog timerReset generation cycle:
Main clock at external 10 MHz (Min 105 ms)Subclock at 32.768 kHz (Min 250 ms) *at selecting two-system product
Wild registers Data for three bytes can be replaced.
UART/SIO
Data transfer is enabled at UART/SIO.Changeable data length (5/6/7/8 -bit), Built-in baud rate generatorTransfer rate (2400 bps to 125000 bps@10 MHz), Built-in full-duplex double bufferNRZ method transfer format, Error detected functionLSB-first or MSB-first can be selected.Data transfer is available for clock synchronous (SIO) and clock asynchronous (UART).
LIN UARTA wide-range communication speed can be set with the dedicated reload timer.Data transfer is available for clock synchronous and clock asynchronous.LIN function is usable as a LIN master and LIN slave.
A/D converter 8ch. 8-bit or 10-bit resolution can be selected.
8/16-bit composite timer
2ch. Can be configured as a 2ch x 8-bit timer or 1ch x 16-bit timer.Built-in timer function, PWC function, PWM function and capture functionInternal 7 kinds + clock selected from external. Square wave output. Square wave output
16-bit PPGPWM mode or one-shot mode can be selected.Eight selectable clock sourcesSupport for external trigger activation
8/16-bit PPG2ch. Can be configured as a 2 ch x 8-bit PPG or 1 ch x 16-bit PPG.Eight selectable clock sources
Watch counterFour selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)Counter value can be set within the range of 0 to 63. (countable one minute)*: At selecting two-system product.
Watch prescalerFour selectable interval times (125 ms, 250 ms, 500 ms, or 1 s).*: At selecting two-system product.
External interrupt8ch. Interrupt by edge detection. (Select rising edge/falling edge/both edges)Can be used to recover from standby modes.
Standby Mode Sleep, stop, watch, timebase timer
67
CHAPTER 1 Description (32-pin)
1.3 Notes on Difference Point between Products and Selecting Product
The following describes the differences in OBOE series models and points to note when selecting the device model.
Notes on Difference Point between Products and Selecting Product
Notes on using EVA products
The EVA product is intended to support software development for a number of different F2MC-8FX familyseries and models, and it therefore includes additional functions that may not be included in the targetmodel. Accordingly, access to peripheral functions and I/O addresses that are not used in the target modelis prohibited.
Reading or writing to these prohibited addresses may cause these unused peripheral functions to operateand lead to unexpected hardware or software problems.
Take particular care not to use word, long word, or similar access to read or write odd numbered bytes inthe prohibited areas.
Also, as the read values of prohibited addresses on the EVA product are different to the values on the targetFLASH and MASK products, do not use this data in software processing.
The functions corresponding to certain bits in single-byte registers may not be supported on particularmodels. However, reading or writing to these bits will not cause misoperation of the hardware. Also, as theEVA, FLASH, and MASK products are designed to have identical hardware and software operation, noparticular precautions are required.
Differences of memory space
If the memory size on the EVA product is different to the target FLASH or MASK product, please ensure
you confirm these differences when developing software.
A/D converter
The analog characteristics of the A/D converter analog input pins on the EVA product are slightly different
to the characteristics on the FLASH and MASK products. Please refer to the data sheet for the differences
in external analog input impedance enough before designing the external circuit.
Current consumption
• The current consumption of FLASH products is typically greater than for mask ROM products.
• For the details of current consumption, refer to "Electric characteristics" in data sheet.
• For detailed information on each package, see "1.6 Package Dimension".
• Operating voltage
- The operating voltage is different for each model.
- For the details, see the "data sheet".
Difference of RST/MOD pins
The RST and MOD pins are hysteresis inputs on the MASK products. A pull-down resistor is provided for
the MOD pin.
68
1.4 Block Diagram of OBOE Series
Figure 1.4-1 shows block diagram of all OBOE series.
Block Diagram of All OBOE Series
Figure 1.4-1 Block Diagram of All OBOE Series
P00/INT00 to P07/INT07
P10/UI0
Port
(P02/SCK)
P11/UO0
P12/UCK0
P13/TRG0/ADTG
(P00/PPG00)
P61/PPG11
P60/PPG10
PF0 to PF2
P63/TO11
P64/EC1
PG0/(Cpin)
P62/TO10
VSS
(P00/AN00 to P07/AN07)
(P01/PPG01)
(P05/TO00)
(P06/TO01)
Internal bus
Port
RST
X0,X1
PG2/(X1A)*1
PG1/(X0A)*1
PG0/(Cpin)*2
MODVCC
P14/PPG0
AVCC
AVSS
(P03/SOT)
(P04/SIN)
External interrupt
UART/SIO
16 - bit PPG
8/16 - bit PPG ch0
8/16 - bit compound timer ch0
10 - bit A/D
LIN UART
8/16 - bit PPG ch1
8/16 - bit compound timer ch1
F2MC-8FX CPU
ROM
RAM
Interrupt control
Wild register
Reset control
Watch counter
Clock control
Watch prescaler
*1: One-system product is general-purpose port and two-system product is sub clock oscillation.*2: 5V product is Cpin terminal.
*: 5V product is Cpin terminal.
(P12/EC0)
69
CHAPTER 1 Description (32-pin)
1.5 Pin Assignment
Figure 1.5-1 shows the pin assignment of OBOE series.
Pin Assignment of OBOE Series
Figure 1.5-1 Pin Assignment of OBOE Series
P14
/PP
G0
P13
/TR
G0/
AD
TG
P12
/UC
K0/
EC
0P
11/U
O0
P10
/UI0
P07
/INT
07/A
N07
P06
/INT
06/A
N06
/TO
01P
05/IN
T05
/AN
05/T
O00
P04
/INT
04/A
N04
/SIN
P03
/INT
03/A
N03
/SO
TP
02/IN
T02
/AN
02/S
CK
P01
/INT
01/A
N01
/PP
G01
P00
/INT
00/A
N00
/PP
G00
AV
ssA
Vcc
PF
2
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
EC
1/P
64T
O11
/P63
TO
10/P
62P
PG
11/P
61M
OD X0
X1
Vss
Vcc
(Cpi
n)/P
G0
PG
2/X
1AP
G1/
X0A
RS
TP
PG
10/P
60P
F0
PF
1TOP VIEW
70
1.6 Package Dimension
OBOE series is available in one type of package. The package dimension below is for reference only.Contact Fujitsu for the nominal package dimension for the released product.
Package Dimension of FPT-32P-M02
Figure 1.6-1 Package Dimension of FPT-32P-M02
48-pin plastic QFP Lead pitch 0.80 mm
Package width × package length
10 × 10 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 2.35 mm MAX
Code(Reference)
P-QFP44-10×10-0.80
48-pin plastic QFP(FPT-48P-M13)
(FPT-48P-M13)
C 2003 FUJITSU LIMITED F48023S-c-3-4
(.013±.002)0.32±0.050.80(.031)
M0.20(.008)
0.10(.004)
(.007±.002)0.17±0.0610.00±0.20(.394±.008)SQ
13.10±0.40(.516±.016)SQ
1 1 2
13
2437
48
2536
INDEX
Details of "A" part
0.80±0.20(.031±.008)
0.88±0.15(.035±.006)
0.25(.010)
.008 –.008+.004
–0.20+0.10
0.20
(Stand off)
1.95+0.40–0.20
+.016–.008.077
(Mounting height)
0~8˚
"A"
0.10(.004)
*
Dimensions in mm (inches).Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.
The contents of this document are subject to change without notice.
EIAJ code : SOP032-P-0450-1
32-pin plastic SOP Lead pitch 1.27mm(50mil)
Nominal dimensions 11.43mm(450mil)
Standard Conforms with EIAJ:TYPE IV
Lead shape Gullwing
Sealing method Plastic mold
32-pin plastic SOP(FPT-32P-M02)
(FPT-32P-M02)
C 1994 FUJITSU LIMITED F32004S-2C-4
0.68(.027)MAX
0.18(.007)MAX
0.15(.006)
0.30(.012)
Details of "A" part
1.27(.050)TYP 0.45±0.10 0.15±0.05
8.60±0.20 11.80±0.30 10.20±0.30
"A"
19.05(.750)REF
0.10(.004)
0.80±0.20(.018±.004) (.006±.002) (.031±.008)
0(0)MIN(Stand Off)
(.339±.008) (.465±.012) (.402±.012)
20.29+0.25–0.20
+.010–.008.799
Ø0.13(.005) M
INDEX
2.50(.098)MAX(Mounting height)
Dimensions in mm (inches).
71
CHAPTER 1 Description (32-pin)
1.7 Pin Description
Table 1.7-1 shows pin description. The alphabet in the "Circuit Type" column of Table 1.7-1 corresponds to the one in the "Classification" column of Table 1.8-1 .
Pin Description
Table 1.7-1 Pin Description (1 / 2)
Pin No. Pin Name Circuit
Type Function Description
1 P64/EC1
K
General-purpose I/O port. These pins are also used for 8/16-bit compound timer ch1 clock input.
2 P63/TO11 General-purpose I/O port. These pins are also used for 8/16-bit compound timer ch1 output. 3 P62/TO10
4 P61/PPG11General-purpose I/O port. These pins are also used for 8/16-bit PPG ch1 output.
5 MOD B Operation mode specification pin
6 X0A Crystal oscillation pin.
7 X1
8 Vss - Power supply (GND) pin.
9 Vcc - Power supply pin.
10 PG0/(C pin) H General-purpose I/O port (at 3 V). Capacitance connection pin (at 5 V).
11 X1A/PG2A/H Crystal oscillation pin. (32KHz). One-system product is general-purpose port.
12 X0A/PG1
13 RST B’ Reset pin.
14 P60/PPG10 KGeneral-purpose I/O port. These pins are also used for 8/16-bit PPG ch1 output.
15 PF0
KGeneral-purpose I/O port. Large current port.
16 PF1
17 PF2
18 AVcc - A/D power supply pin.
19 AVss - A/D power supply (GND) pin.
72
20P00/INT00/AN00/PPG00
D
General-purpose I/O port. These pins are also used for external interrupt input (INT00, INT01), A/D analog input (AN00, AN01) and 8/16-bit PPG ch0 output (PPG00, PPG01). 21
P01/INT01/AN01/PPG01
22P02/INT02/AN02/SCK
General-purpose I/O port. These pins are also used for external interrupt input (INT02), A/D analog input (AN02) and LIN UART clock I/O (SCK).
23P03/INT03/AN03/SOT
General-purpose I/O port. These pins are also used for external interrupt input (INT03), A/D analog input (AN03) and LIN UART data output (SOT).
24P04/INT04/AN04/SIN
EGeneral-purpose I/O port. These pins are also used for external interrupt input (INT04), A/D analog input (AN04) and LIN UART data input (SIN).
25P05/INT05/AN05/T000
D
General-purpose I/O port. These pins are also used for external interrupt input (INT05, INT06), A/D analog input (AN05, AN06) and 8/16-bit compound timer ch0 output (TO00, TO01). 26
P06/INT06/AN06/T001
27P07/INT07/AN07
General-purpose I/O port. These pins are also used for external interrupt input (INT07) and A/D analog input (AN07).
28 P10/U10 GGeneral-purpose I/O port. These pins are also used for UART/SIO ch0 data input.
29 P11/U00
H
General-purpose I/O port. These pins are also used for UART/SIO ch0 data output.
30P12/UCK0/EC0
General-purpose I/O port. These pins are also used for UART/SIO ch0 clock I/O (UCK0) and 8/16-bit compound timer ch0 clock input (EC0).
31P13/TRG0/ADTG
General-purpose I/O port. These pins are also used for 16-bit PPG ch0 trigger input (TRG0) and A/D trigger input (ADTG).
32 P14/PPG0General-purpose I/O port. These pins are also used for 16-bit PPG ch0 output.
Table 1.7-1 Pin Description (2 / 2)
Pin No. Pin Name Circuit
Type Function Description
73
CHAPTER 1 Description (32-pin)
1.8 I/O Circuit Type
Table 1.8-1 lists the I/O circuit types. Also, the alphabet in the "Classification" column of Table 1.8-1 corresponds to the one in the "Circuit Type" column of Table 1.7-1 .
I/O Circuit Type
Table 1.8-1 I/O Circuit Type (1 / 2)
Classi-fication
Circuit Remark
A
• Oscillation circuit
• Feedback resistor value
High-speed side: approx 1 MΩ.Low-speed side: approx 10 MΩ.
• Only low-speed side oscillation of 3V *
Feedback resistor: approx 24 MΩ.Dumping resistor: approx 144 kΩ.
*: Without MB95FV100
B
• Input only
• Hysteresis input (only mask product)
• Pull-down resistor (only mask product)
B'
• Hysteresis input (only mask product)
• Reset output supported (only 5V product)
D
• CMOS output
• Hysteresis input
• Analog input
• Pull-up control is available.
Standby control
X1 (X1A)
X0 (X0A)
Reset outputNch
Pch
Nch
R
A/D controlStandby control
External interrupt control
Analog input
Pull-up control
74
E
• CMOS output
• CMOS input
• Hysteresis input
• Analog input
• Pull-up control is available.
G
• CMOS output
• CMOS input
• Hysteresis input
• Pull-up control is available.
H
• CMOS output
• Hysteresis input
• Pull-up control is available.
K
• CMOS output
• Hysteresis input
Table 1.8-1 I/O Circuit Type (2 / 2)
Classi-fication
Circuit Remark
Pch
Nch
R
A/D controlStandby control
External interrupt control
Analog input
Pull-up control
Pch
Nch
Standby control
Pull-up controlR
Pch
Nch
Standby control
Pull-up control R
Pch
Nch
Standby control
75
CHAPTER 1 Description (32-pin)
76
CHAPTER 1Description (28-pin)
This chapter explains a feature and a basic specification of the FLUTE series.
1.1 Feature of FLUTE Series
1.2 Product Lineup of FLUTE Series
1.3 Notes on Difference Point between Products and Selecting Product
1.4 Block Diagram of FLUTE Series
1.5 Pin Assignment
1.6 Package Dimension
1.7 Pin Description
1.8 I/O Circuit Type
77
CHAPTER 1 Description (28-pin)
1.1 Feature of FLUTE Series
In addition to a compact instruction set, the FLUTE series of general-purpose, single-chip microcontrollers feature a wide range of internal peripheral functions.
Feature of FLUTE Series
F2MC-8FX CPU Core
Instruction system optimized for controllers
• Multiplication and division instructions
• 16-bit operation
• Bit test branch instruction
• Bit manipulation instructions etc.
Clock
• Main clock
• Main PLL clock
• Sub clock *Only two-system product
• Sub PLL clock *Only two-system product
Timers
• 8/16-bit composite timer
• 8/16-bit PPG
• 16-bit PPG
• Timebase timer
• Watch prescaler *Only two-system product
LIN UART
• With full-duplex double buffer
• An asynchronous clock or a synchronous serial transfer can be used.
UART/serial interface
• Switch of UART/SIO is enabled.
External interrupt
• Interrupt by the edge detection (Select rising edge/falling edge/both edges)
• Can be used to recover from low-power consumption modes.
10-bit A/D converter
• 10-bit resolution
78
Low-power consumption (standby mode)
• Stop mode
• Sleep mode
• Watch mode *Only two-system product
• Timebase timer
I/O port: Max 20
• General-purpose I/O ports (CMOS): 20
79
CHAPTER 1 Description (28-pin)
1.2 Product Lineup of FLUTE Series
FLUTE series is available in three types. Table 1.2-1 lists the product lineup and Table 1.2-3 lists the CPUs and peripheral functions.
Product Lineup of FLUTE Series
For MASK products, specify single/dual version and whether to include LVD and CSV when issuing the
mask ROM order. (Specifying CSV without LVD is not available.)
LVD: Low-voltage detection reset
CSV: Clock supervisor
*: No reset output at selected CSV.
Selection of Oscillation Stabilization Wait TimeFor MASK products, you can specify the default oscillation stabilization wait time as a mask option when
issuing the mask ROM order.
The default oscillation stabilization wait time is fixed to maximum value on the EVA and FLASH products.
*: Can be selected one type from 4 types.
Table 1.2-1 Product Lineup of FLUTE Series
Model ROM/RAM Voltage Reset Output Option
EVA productsMB95FV100-101 60KB/4KB 3V None 1/2 system selectable
MB95FV100-103 60KB/4KB 5V Yes * 1/2 system selectable, LVD and CSV selectable
3V products
FLASH products
MB95FXXXS XXKB/XKB 3V None Single system
MB95FXXXW XXKB/XKB 3V None Two-system
MASK products
MB95XXX XXKB/XKB 3V None 1/2 system
5V products
FLASH products
MB95FXXXHS XXKB/XKB 5V Yes Single system, LVD and CSV OFF
MB95FXXXH-100S XXKB/XKB 5V Yes Single system, LVD ON, CSV OFF
MB95FXXXH-200S XXKB/XKB 5V None Single system, LVD and CSV ON
MB95FXXXHW XXKB/XKB 5V Yes Two-system, LVD and CSV OFF
MB95FXXXH-100W XXKB/XKB 5V Yes Two-system, LVD ON, CSV OFF
MB95FXXXH-200W XXKB/XKB 5V None Two-system, LVD and CSV ON
MASK products
MB95XXXH XXKB/XKB 5V Yes *1/2 system selectable, LVD and CSV
selectable
Table 1.2-2 Selection of Oscillation Stabilization Wait Time (MASK products)
Selection of Oscillation Stabilization Wait Time Remark
22/FCH 1.0 µs (at external 4 MHz)
212/FCH 1.024 ms (at external 4 MHz)
213/FCH 2.048 ms (at external 4 MHz)
214/FCH 4.096 ms (at external 4 MHz)
80
Table 1.2-3 CPU and Peripheral Function of FLUTE Series
Item Specification
CPU function
Number of basic instructions: 136 instructionsInstruction bit length: 8 bitsInstruction length: 1 to 3 bytesData bit length: 1, 8, and 16 bitsMinimum instruction execution time: 0.1 µs(at internal 10 MHz)Interrupt processing time: 0.9 µs (at internal 10 MHz)
Per
iphe
ral f
unct
ion
Port General-purpose I/O ports (CMOS): 20 (Max)
Timebase timer Interrupt cycle 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (external 4 MHz)
Watchdog timerReset generation cycle: Main clock at external 10 MHz (Min 105 ms)Subclock at 32.768 kHz (Min 250 ms) *at selecting two-system product
Wild registers Data for three bytes can be replaced.
UART/SIO
Data transfer is enabled at UART/SIO.Changeable data length (5/6/7/8 -bit), Built-in baud rate generatorTransfer rate (2400 bps to 125000 bps@10 MHz), Built-in full-duplex double bufferNRZ method transfer format, Error detected functionLSB-first or MSB-first can be selected.Data transfer is available for clock synchronous (SIO) and clock asynchronous (UART).
LIN UARTA wide-range communication speed can be set with the dedicated reload timer.Data transfer is available for clock synchronous and clock asynchronous.LIN function is usable as a LIN master and LIN slave.
A/D converter 8ch. 8-bit or 10-bit resolution can be selected.
8/16-bit composite timerCan be configured as a 2ch x 8-bit timer or 1ch x 16-bit timer.Built-in timer function, PWC function, PWM function and capture functionInternal 7 kinds + clock selected from external. Square wave output.
16-bit PPGPWM mode or one-shot mode can be selected.Eight selectable clock sourcesSupport for external trigger activation.
8/16-bit PPGCan be configured as a 2 ch x 8-bit PPG or 1 ch x 16-bit PPG.Eight selectable clock sources
Watch counterFour selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)Counter value can be set within the range of 0 to 63. (countable one minute)*at selecting two-system product
Watch prescalerFour selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)*at selecting two-system product
External interrupt8ch. Interrupt by edge detection. (Select rising edge/falling edge/both edges)Can be used to recover from standby modes.
Standby Mode Sleep, stop, watch, timebase timer
81
CHAPTER 1 Description (28-pin)
1.3 Notes on Difference Point between Products and Selecting Product
The following describes the differences between FLUTE series models and points to note when selecting the device model.
Notes on Difference Point between Products and Selecting Product
Notes on using EVA products
The EVA product is intended to support software development for a number of different F2MC-8FX familyseries and models, and it includes additional functions that may not be included in the target model.Accordingly, access to peripheral functions and I/O addresses that are not used in the target model isprohibited.
Reading or writing to these prohibited addresses may cause these unused peripheral functions to operateand lead to unexpected hardware or software problems.
Take particular care not to use word, long word, or similar access to read or write odd numbered bytes inthe prohibited areas.
Also, as the read values of prohibited addresses on the EVA product are different to the values on the targetFLASH and MASK products, do not use this data in software processing.
The functions corresponding to certain bits in single-byte registers may not be supported on particularmodels. However, reading or writing to these bits will not cause misoperation of the hardware. Also, as theEVA, FLASH, and MASK products are designed to have identical hardware and software operation, noparticular precautions are required.
Differences of memory space
If the memory size on the EVA product is different to the target FLASH or MASK product, please ensure
you confirm these differences when developing software.
A/D converter
The analog characteristics of the A/D converter analog input pins on the EVA product are slightly different
to the characteristics on the FLASH and MASK products. Please refer to the data sheet for the differences
for values in external analog input impedance before designing the external circuit.
Current consumption
• The current consumption of FLASH products is typically greater than for mask ROM products.
• For the details of current consumption, refer to "Electric characteristics" in data sheet.
• For detailed information on each package, see "1.6 Package Dimension".
• Operating voltage
- The operating voltage may be different on each model.
- For the details, see the "data sheet".
Difference of RST/MOD pins
The RST and MOD pins are hysteresis inputs on the MASK products. A pull-down resistor is provided for
the MOD pin.
82
1.4 Block Diagram of FLUTE Series
Figure 1.4-1 shows the block diagram of all FLUTE series.
Block Diagram of All FLUTE Series
Figure 1.4-1 Block Diagram of All FLUTE Series
AVCC
AVSS
MOD
(P06/TO01)
(P12/EC0)
PF0 to PF1
Port
Internal bus
Port
(P05/TO00)
(P04/SIN)
(P02/SCK)
(P00/AN00 to P07/AN07)
P15,P16
P11/UO0
P12/UCK0
P13/TRG0/ADTG
P14/PPG0
PG0/(Cpin)*2
(P01/PPG01)
(P00/PPG00)
(P03/SOT)
P00/INT00 to P07/INT07
P10/UI0
RST
X0,X1
PG2/(X1A)*1
PG1/(X0A)*1
VCCVSS
External interrupt
UART/SIO
16 - bit PPG
10 - bit A/D
LIN UART
8/16 - bit PPG
F2MC-8FX CPU
8/16 - bit compound timer
ROM
RAM
Interrupt control
Wild register
Reset control
Watch timer
Clock control
Watch prescaler
*1: One-system product is general-purpose port and two-system product is sub clock oscillation.*2: 5V product is Cpin terminal.
83
CHAPTER 1 Description (28-pin)
1.5 Pin Assignment
Figure 1.5-1 shows the pin assignment of the FLUTE series.
Pin Assignment of FLUTE Series
Figure 1.5-1 Pin Assignment of the FLUTE Series
P15
P14
/PP
G0
P13
/TR
G0/
AD
TG
P12
/UC
K0/
EC
0P
11/U
O0
P10
/UI0
P07
/INT
07/A
N07
P06
/INT
06/A
N06
/TO
01P
05/IN
T05
/AN
05/T
O00
P04
/INT
04/A
N04
/SIN
P03
/INT
03/A
N03
/SO
TP
02/IN
T02
/AN
02/S
CK
P01
/INT
01/A
N01
/PP
G01
P00
/INT
00/A
N00
/PP
G00
32 31 30 29 28 27 26 25 24 23 22 21 20 19
1 2 3 4 5 6 7 8 9 10 11 12 13 14
P16
PF
0P
F1
MO
D X0
X1
Vss
Vcc
(Cpi
n)/P
G0
PG
2/X
1AP
G1/
X0A
RS
TA
Vcc
AV
ss
TOP VIEW
84
1.6 Package Dimension
FLUTE series is available for one type of package. The package dimension below is for reference only. Contact Fujitsu for the nominal package dimension for the released product.
Package Dimension of FPT-28P-M01
Figure 1.6-1 Package Dimension of FPT-28P-M01
The contents of this document are subject to change without notice.
28-pin plastic SOP Lead pitch 1.27 mm
Package width ×package length
7.6 × 17.75 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 2.80 mm MAX
Weight 0.67 g
Code(Reference)
P-SOP28-7.6×17.75-1.27
28-pin plastic SOP(FPT-28P-M01)
(FPT-28P-M01)
C 2002 FUJITSU LIMITED F28005S-c-7-7
0.13(.005) M
Details of "A" part
INDEX
1.27(.050)
0.10(.004)
0.47±0.08(.019±.003)
–0.04+0.03
0.17
.007+.001–.002
"A"0.25(.010)
0~8˚
(Mounting height)
1
7.60±0.30 10.20±0.40(.402±.016)(.299±.012)
14
1528
17.75+0.25–0.20 .699
+.010–.008
2.55+0.25–0.15
.100+.010–.006
(Stand off)
0.10+0.10–0.05
–.002+.004
.004
(.024±.006)0.60±0.15(.020±.008)0.50±0.20
*1
*2
0.10(.004)
Dimensions in mm (inches).Note: The values in parentheses are reference values.
Note 1) *1 : These dimensions include resin protrusion.Note 2) *2 : These dimensions do not include resin protrusion.Note 3) Pins width and pins thickness include plating thickness.Note 4) Pins width do not include tie bar cutting remainder.
85
CHAPTER 1 Description (28-pin)
1.7 Pin Description
Table 1.7-1 shows pin description. The alphabet in the "Circuit Type" column of Table 1.7-1 corresponds to the one in the "Classification" column of Table 1.8-1 .
Pin Description
Table 1.7-1 Pin Description (1 / 2)
Pin No. Pin name Circuit
type Function description
1 P16 H General-purpose I/O port.
2 PF0/HC10K General-purpose I/O port. Large current port.
3 PF1/HC11
4 MOD B Operation mode specification pin.
5 X0A Crystal oscillation pin.
6 X1
7 Vss - Power supply (GND) pin.
8 Vcc - Power supply pin.
9 PG0/(Cpin) H General-purpose I/O port (at 3 V). Capacitance connection pin (at 5 V).
10 X1A/PG2A/H Crystal oscillation pin (32KHz). One-system product is general-purpose port.
11 X0A/PG1
12 RST B’ Reset pin.
13 AVcc - Power supply pin for A/D.
14 AVss - Power supply (GND) pin for A/D.
15P00/INT00/AN00/PPG00
D
General-purpose I/O port.These pins are also used for external interrupt input (INT00), A/D analog input (AN00) and 8/16-bit PPG ch0 output (PPG00).
16P01/INT01/AN01/PPG01
General-purpose I/O port.These pins are also used for external interrupt input (INT01), A/D analog input (AN01) and 8/16-bit PPG ch0 output (PPG01).
17P02/INT02/AN02/SCK
General-purpose I/O port.These pins are also used for external interrupt input (INT02), A/D analog input (AN02) and LIN UART clock I/O(SCK).
18P03/INT03/AN03/SOT
General-purpose I/O port.These pins are also used for external interrupt input (INT03), A/D analog input (AN03) and LIN UART data output (SOT).
86
19P04/INT04/AN04/SIN
EGeneral-purpose I/O port.These pins are also used for external interrupt input (INT04), A/D analog input (AN04) and LIN UART data input (SIN).
20P05/INT05/AN05/T000
D
General-purpose I/O port.These pins are also used for external interrupt input (INT05, INT06), A/D analog input (AN05, AN06) and 8/16-bit compound timer ch0 output (TO00, TO01). 21
P06/INT06/AN06/T001
22P07/INT07/AN07
General-purpose I/O port.These pins are also used for external interrupt input (INT07), A/D analog input (AN07).
23 P10/U10 GGeneral-purpose I/O port.These pins are also used for UART/SIO ch0 data input.
24 P11/U00
H
General-purpose I/O port.These pins are also used for UART/SIO ch0 data output.
25P12/UCK0/EC0
General-purpose I/O port.These pins are also used for UART/SIO ch0 clock I/O (UCK0) and 8/16-bit compound timer ch0 clock input (EC0).
26P13/TRG0/ADTG
General-purpose I/O port.These pins are also used for 16-bit PPG ch0 trigger input (TRG0) and A/D trigger input (ADTG).
27 P14/PPG0General-purpose I/O port.These pins are also used for 16-bit PPG ch0 output.
28 P15 General-purpose I/O port.
Table 1.7-1 Pin Description (2 / 2)
Pin No. Pin name Circuit
type Function description
87
CHAPTER 1 Description (28-pin)
1.8 I/O Circuit Type
Table 1.8-1 lists the I/O circuit types. Also, the alphabet in the "Classification" column of Table 1.8-1 corresponds to the one in the "Circuit Type" column of Table 1.7-1 .
I/O Circuit Type
Table 1.8-1 I/O Circuit Type (1 / 2)
Classi-fication
Circuit Remark
A
• Oscillation circuit
• Feedback resistance value
High-speed side: approx. 1 MΩLow-speed side: approx. 10 MΩ
• Only low-speed side oscillation of 3 V*
Feedback resistance: approx. 24 MΩ
Dumping resistance: approx. 144 kΩ
*: Except MB95FV100
B
• Input only
• Hysteresis input (only mask product)
• Pull-down resistance (only mask product)
B'
• Hysteresis input (only for mask product)
• Reset output supported (only for 5V product)
D
• CMOS output
• Hysteresis input
• Analog input
• Pull-up control is available.
Standby control
X1 (X1A)
X0 (X0A)
Reset outputNch
Pch
Nch
R
A/D controlStandby control
External interrupt control
Analog input
Pull-up control
88
E
• CMOS output
• CMOS input
• Hysteresis input
• Analog input
• Pull-up control is available.
G
• CMOS output
• CMOS input
• Hysteresis input
• Pull-up control is available.
H
• CMOS output
• Hysteresis input
• Pull-up control is available.
K
• CMOS output
• Hysteresis input
Table 1.8-1 I/O Circuit Type (2 / 2)
Classi-fication
Circuit Remark
Pch
Nch
R
A/D controlStandby control
External interrupt control
Analog input
Pull-up control
Pch
Nch
Standby control
Pull-up controlR
Pch
Nch
Standby control
Pull-up control R
Pch
Nch
Standby control
89
CHAPTER 1 Description (28-pin)
90
CHAPTER 1Description (20-pin)
This chapter explains a feature and a basic specification of the PICCOLO series.
1.1 Feature of PICCOLO Series
1.2 Product Lineup of PICCOLO Series
1.3 Note on Difference Point between Products and Selecting Product
1.4 Block Diagram of PICCOLO Series
1.5 Pin Assignment
1.6 Package Dimension
1.7 Pin Description
1.8 I/O Circuit Type
91
CHAPTER 1 Description (20-pin)
1.1 Feature of PICCOLO Series
In addition to a compact instruction set, the PICCOLO series of general-purpose, single-chip microcontrollers feature a wide range of internal peripheral functions.
Feature of PICCOLO Series
F2MC-8FX CPU core
Instruction system optimized for controllers
• Multiplication and division instructions
• 16-bit operation
• Bit test branch instruction
• Bit operation instructions etc.
Clock
• Main clock
• Main PLL clock
Timer
• 8/16-bit composite timer
• 8/16-bit PPG
• 16 -bit PPG
• Timebase timer
LIN UART
• With full-duplex double buffer
• An asynchronous clock or a synchronous serial transfer can be used.
UART/serial interface
• Switch of UART/SIO is enabled.
External interrupt
• Interrupt by the edge detection. (Select rising edge/falling edge/both edges)
• Can be used to recover from low-power consumption modes.
10-bit A/D converter
• 10-bit resolution
Low-power consumption (standby mode)
• Stop mode
• Sleep mode
• Timebase timer mode
I/O port: Max 14
• General-purpose I/O ports (CMOS): 14
92
1.2 Product Lineup of PICCOLO Series
PICCOLO series is available in three types. Table 1.2-1 lists the product lineup and Table 1.2-3 lists the CPUs and peripheral functions.
Product Lineup of PICCOLO Series
For MASK products, specify whether to include LVD and CSV when issuing the mask ROM order.
(Specifying CSV without LVD is not available.)
LVD: Low-voltage detection reset
CSV: Clock supervisor
*: No reset output at selected CSV.
Selection of Oscillation Stabilization Wait TimeOn MASK products, you can specify the default oscillation stabilization delay time as a mask option when
issuing the mask ROM order.
The default oscillation stabilization delay time is fixed to maximum value on the EVA and FLASH products.
*: Can be select one type from 4 types.
Table 1.2-1 Product Lineup of PICCOLO Series
Model ROM/RAM Voltage Reset Output Option
EVA productsMB95FV100-101 60KB/4KB 3V None 1/2 system selectable
MB95FV100-103 60KB/4KB 5V Yes* 1/2 system selectable, LVD and CSV ON
3V products
FLASH products
MB95FXXX XXKB/XKB 3V None Single system
MASK products
MB95XXX XXKB/XKB 3V None Single system
5V products
FLASH products
MB95FXXXH XXKB/XKB 5V Yes Single system, LVD and CSV OFF
MB95FXXXH-100 XXKB/XKB 5V Yes Single system, LVD ON and CSV OFF
MB95FXXXH-200 XXKB/XKB 5V None Single system, LVD and CSV ON
MASK products
MB95XXXH XXKB/XKB 5V Yes* Single system, LCD, CSV selectable
Table 1.2-2 Selection of Oscillation Stabilization Wait Time (MASK Product)
Selection of Oscillation Stabilization Wait Time Remark
22/FCH 1.0 µs (at external 4 MHz)
212/FCH 1.024 ms (at external 4 MHz)
213/FCH 2.048 ms (at external 4 MHz)
214/FCH 4.096 ms (at external 4 MHz)
93
CHAPTER 1 Description (20-pin)
Table 1.2-3 CPU and Peripheral Function of PICCOLO Series
Item Specification
CPU function
Number of basic instructions: 136 instructionsInstruction bit length: 8 bitsInstruction length: 1 to 3 bytesData bit length: 1, 8, and 16 bitsMinimum instruction execution time: 0.1 µs(at internal 10 MHz)Interrupt processing time: 0.9 µs(at internal 10 MHz)
Per
iphe
ral f
unct
ion
Port General-purpose I/O ports (CMOS): 14(Max)
Timebase timer Interrupt cycle 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (at external 4 MHz)
Watchdog timer Reset generation cycle: Main clock at external 10 MHz (Min 105 ms)
Wild register R data for three bytes can be replaced.
UART/SIO
Data transfer is enabled at UART/SIO. Changeable data length (7/8 -bit), Built-in baud rate generatorTransfer rate (2400 bps to 125000 bps@10 MHz), Built-in full-duplex double bufferNRZ method transfer format, Error detected functionLSB-first or MSB-first can be selected.Data transfer is available for clock synchronous (SIO) and clock asynchronous (UART).
LIN UARTA wide-range communication speed can be set with the dedicated reload timer. Data transfer is available for clock synchronous and clock asynchronous. LIN function is usable as a LIN master and LIN slave.
A/D converter 8 ch. 8-bit or 10-bit resolution can be selected.
8/16-bit composite timerCan be configured as a 2 ch x 8-bit timer or 1 ch x 16-bit timer.Built-in timer function, PWC function, PWM function and capture functionInternal 7 kinds + clock selected from external. Square wave output
16-bit PPGPWM mode or one-shot mode can be selected. Eight selectable clock sources
8/16-bit PPGCan be configured as a 2 ch x 8-bit PPG or 1 ch x 16-bit PPG. Eight selectable clock sourcesSupport for external trigger activation.
External interrupt8 ch. Interrupt by edge detection. (Select rising edge/falling edge/both edges)Can be used to recover from standby modes.
Standby mode Sleep, stop, timebase timer
94
1.3 Note on Difference Point between Products and Selecting Product
The following describes differences between PICCOLO series models and points to note when selecting the device model.
Note on Difference Point between Products and Selecting Product
Notes on using EVA products
The EVA product is intended to support software development for a number of different F2MC-8FX familyseries and models, and it therefore includes additional functions that may not be included in the targetmodel. Accordingly, access to peripheral functions and I/O addresses that are not used in the target modelis prohibited.
Reading or writing to these prohibited addresses may cause these unused peripheral functions to operateand lead to unexpected hardware or software problems.
Take particular care not to use word, long word, or similar access to read or write odd numbered bytes inthe prohibited areas.
Also, as the read values of prohibited addresses on the EVA product are different to the values on the targetFLASH and MASK products, do not use this data in software processing.
The functions corresponding to certain bits in single-byte registers may not be supported on particularmodels. However, reading or writing to these bits will not cause misoperation of the hardware. Also, as theEVA, FLASH, and MASK products are designed to have identical hardware and software operation, noparticular precautions are required.
Difference of memory space
If the memory size on the EVA product is different to the target FLASH or MASK product, please ensureyou understand these differences when developing software.
A/D converter
The analog characteristics of the A/D converter analog input pins on the EVA product are slightly differentto the characteristics on the FLASH and MASK products. Please refer to the data sheet for the differencesin external analog input impedance before designing the external circuit.
Current consumption
• The current consumption of FLASH products is typically greater than for mask ROM products.
• For the details of current consumption, refer to "Electric characteristics" in data sheet.
• For detailed information on each package, see "1.6 Package Dimension".
• Operating voltage
- The operating voltage is different on different models.
- For the details, see the "data sheet".
Difference of RST/MOD pins
The RST and MOD pins are hysteresis inputs on the MASK products. A pull-down resistor is provided forthe MOD pin.
95
CHAPTER 1 Description (20-pin)
1.4 Block Diagram of PICCOLO Series
Figure 1.4-1 shows block diagram of all PICCOLO series.
Block Diagram of All PICCOLO Series
Figure 1.4-1 Block Diagram of All PICCOLO Series
RST
(P01/PPG01)
(P00/PPG00)
Internal bus
Port
(P05/TO00)
X0,X1
(P02/SCK)
PG0(Cpin)*
MODVCC
(P00/AN00 to P07/AN07)
P00/INT00 to P07/INT07
Port
P14/PPG0
*: 5V products are Cpin terminals.
P10/UI0
P11/UO0
(P03/SOT)
(P06/TO01)
(P04/SIN)P13/TRG0/ADTG
P12/UCK0
VSS
(P12/EC0)
Reset control
Clock control
External interrupt
UART/SIO
16 - bit PPG
10 - bit A/D
ROM
RAM
Interrupt control
Wild register
LIN UART
8/16 - bit PPG
F2MC-8FX CPU
8/16 - bitcompound timer
96
1.5 Pin Assignment
Figure 1.5-1 shows pin assignment of the PICCOLO series.
Pin Assignment of PICCOLO Series
Figure 1.5-1 Pin Assignment of PICCOLO Series
P00
/INT
00/A
N00
/PP
G00
P01
/INT
01/A
N01
/PP
G01
P02
/INT
02/A
N02
/SC
KP
03/IN
T03
/AN
03/S
OT
P04
/INT
04/A
N04
/SIN
P05
/INT
05/A
N05
/TO
00P
06/IN
T06
/AN
06/T
O01
P07
/INT
07/A
N07
P10
/UI0
P11
/UO
020 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
RS
TM
OD X0
X1
Vss
Vcc
(C p
in)/
PG
0P
PG
0/P
14T
RG
0/A
DT
G/P
13U
CK
0/E
C0/
P12
TOP VIEW
97
CHAPTER 1 Description (20-pin)
1.6 Package Dimension
PICCOLO series is available in one type of package.The package dimension below is for reference only.Contact Fujitsu for the nominal package dimension.
Package Dimension of FPT-20P-M02
Figure 1.6-1 Package Dimension of FPT-20P-M02
20-pin plastic SOP Lead pitch 50 mil
Nominal dimensions 375 mil
Standard Conforms with EIAJ:TYPE III
Lead shape Gullwing
Sealing method Plastic mold
20-pin plastic SOP(FPT-20P-M02)
(FPT-20P-M02)
C 1994 FUJITSU LIMITED F20006S-4C-4
0.10(.004)
¯0.13(.005) M
"A"
0.68(.027)MAX
0.18(.007)MAX
0.20(.008)
0.60(.024)
Details of "A" part
.500 Ð.008+.010
Ð0.20+0.25
12.70
.006 Ð.001+.002
Ð0.02+0.05
0.15
1 PIN INDEX
1.27(.050)TYP
11.43(.450)REF
7.60±0.30 10.20±0.40
0.45±0.10(.018±.004)
(.299±.012) (.402±.016)9.20±0.30
(.362±.012)
0.50±0.20
0.05(.002)MIN(STAND OFF)
(.020±.008)
3.10(.122)MAX(Mounting height)
Dimensions in mm (inches).
98
1.7 Pin Description
Table 1.7-1 shows pin description. The alphabet in the "Circuit Type" column of Table 1.7-1 corresponds to the one in the "Classification" column of Table 1.8-1 .
Pin Description
Table 1.7-1 Pin Description (1 / 2)
Pin No. Pin Name Circuit
Type Function Description
1 RST B’ Reset pin.
2 MOD B Operation mode specification pin.
3 X0A Crystal oscillation pin.
4 X1
5 Vss - Power supply (GND) pin.
6 Vcc - Power supply pin.
7 PG0/(C pin) H General-purpose I/O port (at 3 V). Capacitance connection pin (at 5 V).
8 P14/PPG0
H
General-purpose I/O port. These pins are also used for 16-bit PPG ch0 output.
9P13/TRG0/ADTG
General-purpose I/O port. These pins are also used for 16-bit PPG ch0 trigger input (TRG0) and A/D trigger input (ADTG).
10P12/UCK0/EC0
General-purpose I/O port. These pins are also used for UART/SIO ch0 clock I/O (UCK0) and 8/16-bit compound timer ch0 clock input (EC0).
11 P11/UO0General-purpose I/O port. These pins are also used for UART/SIO ch0 data output.
12 P10/UI0 GGeneral-purpose I/O port. These pins are also used for UART/SIO ch0 data input.
13P07/INT07/AN07
D
General-purpose I/O port. These pins are also used for external interrupt input (INT07) and A/D analog input (AN07).
14P06/INT06/AN06/TO01 General-purpose I/O port.
These pins are also used for external interrupt input (INT05, INT06), A/D analog input (AN05, AN06), and 8/16-bit compound timer ch0 output (TO00, TO01). 15
P05/INT05/AN05/TO00
16P04/INT04/AN04/SIN
EGeneral-purpose I/O port. These pins are also used for external interrupt input (INT04), A/D analog input (AN04), and LIN UART data input (SIN).
99
CHAPTER 1 Description (20-pin)
17P03/INT03/AN03/SOT
D
General-purpose I/O port. These pins are also used for external interrupt input (INT03), A/D analog input (AN03), and LIN UART data output (SOT).
18P02/INT02/AN02/SCK
General-purpose I/O port. These pins are also used for external interrupt input (INT02), A/D analog input (AN02), and LIN UART clock I/O (SCK).
19P01/INT01/AN01/PPG01 General-purpose I/O port.
These pins are also used for external interrupt input (INT00, INT01), A/D analog input (AN00, AN01), and 8/16-bit PPG ch0 output (PPG00, PPG01). 20
P00/INT00/AN00/PPG00
Table 1.7-1 Pin Description (2 / 2)
Pin No. Pin Name Circuit
Type Function Description
100
1.8 I/O Circuit Type
Table 1.8-1 lists the I/O circuit types. Also, the alphabet in the "Classification" column of Table 1.8-1 corresponds to the one in the "Circuit Type" column of Table 1.7-1 .
I/O Circuit Type
Table 1.8-1 I/O Circuit Type (1 / 2)
Classi-fication
Circuit Remark
A
• Oscillation circuit
• Feedback resistor: approx. 1 MΩ
B
• Input exclusive use
• Hysteresis input (only mask product)
• Pull-down resistor (only mask product)
B'
• Hysteresis input (only mask product)
• Reset output supported (only 5V product)
D
• CMOS output
• Hysteresis input
• Analog input
• Pull-up control
Standby control
X1 (X1A)
X0 (X0A)
Reset outputNch
Pch
Nch
R
A/D controlStandby control
External interrupt control
Analog input
Pull-up control
101
CHAPTER 1 Description (20-pin)
E
• CMOS output
• CMOS input
• Hysteresis input
• Analog input
• Pull-up control
G
• CMOS output
• CMOS input
• Hysteresis input
• Pull-up control
H
• CMOS output
• Hysteresis input
• Pull-up control
Table 1.8-1 I/O Circuit Type (2 / 2)
Classi-fication
Circuit Remark
Pch
Nch
R
A/D controlStandby control
External interrupt control
Analog input
Pull-up control
Pch
Nch
Standby control
Pull-up controlR
Pch
Nch
Standby control
Pull-up control R
102
CHAPTER 1Description (100-pin/LCD)
This chapter explains a feature and a basic specification of the TUBA series.
1.1 Feature of TUBA Series
1.2 Product Lineup of TUBA Series
1.3 Notes on Difference Point between Products and Selecting Product
1.4 Block Diagram of TUBA Series
1.5 Pin Assignment
1.6 Package Dimension
1.7 Pin Description
1.8 I/O Circuit Type
103
CHAPTER 1 Description (100-pin/LCD)
1.1 Feature of TUBA Series
In addition to a compact instruction set, the TUBA series is a general-purpose single-chip microcontroller built-in abundant peripheral functions.
Feature of TUBA Series
F2MCTM-8FX CPU core
Instruction system optimized for controllers
• Multiplication and division instructions
• 16-bit operation
• Bit test branch instruction
• Bit operation instructions etc.
Clock
• Main clock
• Main PLL clock
• Sub clock
• Sub PLL clock
Timer
• 8/16-bit compound timer × 2 channels
• 16-bit reload timer
• 8/16-bit PPG × 2 channels
• 16-bit PPG × 2 channels
• Timebase timer
• Watch prescaler
LIN UART
• With full-duplex double buffer
• An asynchronous clock or a synchronous serial transfer can be used.
UART/serial interface
• Switch of UART/SIO is enabled.
I2C
• With wake up improvement function
External interrupt
• Interrupt by the edge detection (Select rising edge/falling edge/both edges).
• Can be used to recover from low-power consumption modes.
104
10-bit A/D converter
• 10-bit resolution
LCD controller/driver
• 40 SEG × 4 COM (Max 160 pixels)
• With blinking function
Low-power consumption (standby mode)
• Stop mode
• Sleep mode
• Watch mode
• Timebase timer mode
I/O port: Max 87
• General-purpose I/O ports (Nch open drain) : 2
• General-purpose I/O ports (CMOS) :85
105
CHAPTER 1 Description (100-pin/LCD)
1.2 Product Lineup of TUBA Series
TUBA series is available in three types. Table 1.2-1 lists the product lineup and Table 1.2-3 lists the CPUs and peripheral functions.
Product Lineup of TUBA Series
For MASK products specify whether to include LVD and CSV when issuing the mask ROM order.
(Specifying CSV without LVD is not available.)
LVD: Low voltage detection reset
CSV: Clock supervisor
*: No reset output at selected CSV.
Selection of Oscillation Stabilization Wait TimeOn MASK products, you can specify the default oscillation stabilization delay time as a mask option when
issuing the mask ROM order.
The default oscillation stabilization delay time for the EVA and FLASH products is fixed to maximum value.
*: Can be select one type from 4 types.
Table 1.2-1 Product Lineup of TUBA Series
Model ROM/RAM VoltageReset Output
LCDC Option
EVA products
MB95FV100-101 60KB/4KB 3V None3V, LCD internal
resistor1/2 system selectable
MB95FV100-102 60KB/4KB 3V None 3V, LCD voltage rise 1/2 system selectable
MB95FV100-103 60KB/4KB 5V Yes*5V, LCD internal
resistor1/2 system selectable, LVD
and CSV selectable
3 V products
FLASH products
MB95FXXX-001 XXKB/XKB 3V None LCD internal resistor Two-system
MB95FXXX-002 XXKB/XKB 3V None LCD voltage rise Two-system
MASK products
MB95XXX XXKB/XKB 3V NoneLCD internal resistor/
voltage riseTwo-system
5 V products
FLASH products
MB95FXXXH-001 XXKB/XKB 5V Yes LCD internal resistorTwo-system,
LVD, CSV OFF
MB95FXXXH-101 XXKB/XKB 5V Yes LCD internal resistorTwo-system, with LVD,
CSV OFF
MB95FXXXH-201 XXKB/XKB 5V None LCD internal resistorTwo-system,
LVD, CSV ON
MASK products
MB95XXXH XXKB/XKB 5V Yes* LCD internal resistorTwo-system,
LVD and CSV selectable
Table 1.2-2 Selection of Oscillation Stabilization Wait Time (MASK Products)
Selection of Oscillation Stabilization Wait Time Remark
22/FCH 1.0 µs (at external 4 MHz)
212/FCH 0.024 ms (at external 4 MHz)
213/FCH 2.048 ms (at external 4 MHz)
214/FCH 4.096 ms (at external 4 MHz)
106
Table 1.2-3 CPU and Peripheral Function of TUBA Series
Item Specification
CPU function
Number of basic instructions: 136 instructionsInstruction bit length: 8 bitsInstruction length: 1 to 3 bytesData bit length: 1, 8, and 16 bitsMinimum instruction execution time: 0.1 µs (at internal 10 MHz)Interrupt processing time: 0.9 µs (at internal 10 MHz)
Per
iphe
ral f
unct
ion
PortGeneral-purpose I/O ports (Nch open drain) : 2General-purpose I/O ports (CMOS) :85Total :87 (Max)
Timebase timer Interrupt cycle 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (external 4 MHz)
Watchdog timerReset generation cycle: Main clock at external 10 MHz (Min 105 ms)
Subclock at 32.768 kHz (Min 250 ms)
Wild registers R data for three bytes can be replaced.
I2C bus
Master/slave sending/receivingBus error function and arbitration functionForwarding direction detection functionGenerating repeatedly and the detecting function of the start condition.Within wake up improvement function
UART/SIO
Data transfer is enabled at UART/SIO.Changeable data length (5/6/7/8 -bit), Built-in baud rate generatorTransfer rate (2400 bps to 125000 bps@10 MHz), Built-in full-duplex double bufferNRZ method transfer format, Error detected functionLSB-first or MSB-first can be selected.Data transfer is available for clock synchronous (SIO) and clock asynchronous (UART).
LIN UARTA wide-range communication speed can be set with the dedicated reload timer.Data transfer is available for clock synchronous and clock asynchronous.LIN function is usable as a LIN master and LIN slave.
A/D converter 12 ch. 8-bit or 10-bit resolution can be selected.
16-bit reload timerReload, one-shot, and event count mode can be selectedInternal 7 kinds + clock selected from external. Square wave output.
8/16-bit composite timer2 ch. Can be configured as a 2 ch x 8-bit timer or 1 ch x 16-bit timer.Built-in timer function, PWC function, PWM function and capture functionInternal 7 kinds + clock selected from external. Square wave output.
16-bit PPG2 ch. PWM mode or one-shot mode can be selected.Eight selectable clock sourcesSupport for external trigger activation
8/16-bit PPG2 ch. Can be configured as a 2 ch x 8-bit PPG or 1 ch x 16-bit PPG.Eight selectable clock sources
Watch counterFour selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)Counter value can be set within the range of 0 to 63. (countable one minute)
Watch prescaler Four selectable interval times (125 ms, 250 ms, 500 ms, 1 s)
LCD controller driverMax. 40 SEG × 4 COMBlinking function
External interrupt12 ch. Interrupt by edge detection. (Select rising edge/falling edge/both edges)Can be used to recover from standby modes.
Standby mode Sleep, stop, watch and timebase timer
107
CHAPTER 1 Description (100-pin/LCD)
1.3 Notes on Difference Point between Products and Selecting Product
The following describes differences between TUBA series models and points to note when selecting the device model.
Notes on Difference Point between Products and Selecting Product
Notes on using EVA products
The EVA products is intended to support software development for a number of different F2MC-8FXfamily series and models, and it therefore includes additional functions that may not be included in thetarget model. Accordingly, access to peripheral functions and I/O addresses that are not used in the targetmodel is prohibited.
Reading or writing to these prohibited addresses may cause these unused peripheral functions to operateand lead to unexpected hardware or software problems.
Take particular care not to use word, long word, or similar access to read or write odd numbered bytes inthe prohibited areas.
Also, as the read values of prohibited addresses on the EVA product are different to the values on the targetFLASH and MASK products, do not use this data in software processing.
The functions corresponding to certain bits in single-byte registers may not be supported on particularmodels. However, reading or writing to these bits will not cause misoperation of the hardware. Also, as theEVA, FLASH, and MASK products are designed to have identical hardware and software operation, noparticular precautions are required.
Difference of memory space
If the memory size on the EVA product is different to the target FLASH or MASK product, please ensureyou understand these differences when developing software.
A/D converter
The analog characteristics of the A/D converter analog input pins on the EVA product are slightly differentto the characteristics on the FLASH and MASK products. Please refer to the data sheet for the differencesin external analog input impedance before designing the external circuit.
Current consumption
• The current consumption of FLASH products is typically greater than for mask ROM products.
• For the details of current consumption, refer to "Electric characteristics" in data sheet.
• For detailed information on each package, see "1.6 Package Dimension".
• Operating voltage
- The operating voltage is different on different models.
- For the details, see the "data sheet".
Difference of RST/MOD pins
The RST and MOD pins are hysteresis inputs on the MASK products. A pull-down resistor is provided forthe MOD pin.
108
1.4 Block Diagram of TUBA Series
Figure 1.4-1 shows block diagram of all TUBA series.
Block Diagram of All TUBA Series
Figure 1.4-1 Block Diagram of All TUBA Series
X0,X1
X0A,X1A
AVSS
AVR
P10/UI0
P11/UO0
AVCC
PG0/(Cpin)*
P30/AN00 to P37/AN07
P21/PPG01
P40/AN08 to P43/AN11
VCCVSS
MOD
P52/PPG1
P53/TRG1
PE5/S29/INT11
*:5V products are Cpin terminal.
Port
P13/TRG0/ADTG
P20/PPG00
P51/SDA0
Internal bus
Port
P50/SCL0
RST
P22/TO00
P23/TO01
P24/EC0
P00/INT00 to P07/INT07
P12/UCK0
P14/PPG0
PE7/S31/INT13
P70/TO0
P71/TI0
PC0/S08 to PC7/S15
PD0/S16 to PD7/S23
PE0/S24 to PE3/S27
PE4/S28/INT10
PB0/S00 to PB7/S07
P90/V3 to P93/V0
P94/C0 to P95/C1
P60/S32/PPG10
P65/S37/SCK
P66/S38/SOT
PE6/S30/INT12
P62/S34/TO10
P67/S39/SIN
P63/S35/TO11
P64/S36/EC1
P61/S33/PPG11
PA0/COM0 to PA3/COM3
External interrupt ch0-7
UART/SIO
16-bit PPG ch0
8/16-bit PPG ch0
8/16-bit compound timer
10-bit A/D
I 2C
16-bit PPG ch1
ROM
RAM
Interrupt control
Wild register
LIN UART
8/16bit PPG ch1
8/16-bit compound timer ch1
16-bit reload timer
LCDC
External interrupt ch8-11
F2MC-8FX CPU
Reset control
Watch prescaler
Clock control
Watch counter
109
CHAPTER 1 Description (100-pin/LCD)
1.5 Pin Assignment
Figure 1.5-1 are pin assignment of the TUBA series.
Pin Assignment of TUBA Series
Figure 1.5-1 Pin Assignment of TUBA SeriesV
ccP
90/V
3P
91/V
2P
92/V
1P
93/V
0P
94/C
0P
95/C
1P
A0/
CO
M0
PA
1/C
OM
1P
A2/
CO
M2
PA
3/C
OM
3P
B0/
S00
PB
1/S
01P
B2/
S02
PB
3/S
03P
B4/
S04
PB
5/S
05P
B6/
S06
PB
7/S
07P
C0/
S08
PC
1/S
09P
C2/
S10
PC
3/S
11P
C4/
S12
Vcc
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
Vss 1 75 PC5/S13(Cpin)/PG0 2 74 PC6/S14INT00/P00 3 73 PC7/S15INT01/P01 4 72 PD0/S16INT02/P02 5 71 PD1/S17INT03/P03 6 70 PD2/S18INT04/P04 7 69 PD3/S19INT05/P05 8 68 PD4/S20INT06/P06 9 67 PD5/S21INT07/P07 10 66 PD6/S22
UI0/P10 11 65 PD7/S23UO0/P11 12 64 PE0/S24
UCK0/P12 13 63 PE1/S25TRG0/ADTG/P13 14 62 PE2/S26
PPG0/P14 15 61 PE3/S27PPG00/P20 16 60 PE4/S28/INT10PPG01/P21 17 59 PE5/S29/INT11
TO00/P22 18 58 PE6/S30/INT12TO01/P23 19 57 PE7/S31/INT13
EC0/P24 20 56 P60/S32/PPG10SCL0/P50 21 55 P61/S33/PPG11SDA0/P51 22 54 MODPPG1/P52 23 53 X0
AVR 24 52 X1AVcc 25 51 Vss
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
AV
ssA
N00
/P30
AN
01/P
31A
N02
/P32
AN
03/P
33A
N04
/P34
AN
05/P
35A
N06
/P36
AN
07/P
37A
N08
/P40
AN
09/P
41A
N10
/P42
AN
11/P
43T
RG
1/P
53T
O0/
P70
TI0
/P71
S39
/SIN
/P67
S38
/SO
T/P
66S
37/S
CK
/P65
S36
/EC
1/P
64S
35/T
O11
/P63
S34
/TO
10/P
62
RS
TX
0AX
1ATOP VIEW
100
110
1.6 Package Dimension
TUBA series is available in one type of package. The package dimensions below are for reference only. Contact Fujitsu for the nominal package dimensions.
Package Dimension of FPT-100P-M05
Figure 1.6-1 Package Dimension of FPT-100P-M05
100-pin plastic LQFP Lead pitch 0.50 mm
Package width × package length
14.0 × 14.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.70 mm MAX
Weight 0.65g
Code(Reference)
P-LFQFP100-14×14-0.50
100-pin plastic LQFP(FPT-100P-M05)
(FPT-100P-M05)
C 2003 FUJITSU LIMITED F100007S-c-4-6
14.00±0.10(.551±.004)SQ
16.00±0.20(.630±.008)SQ
1 2 5
26
51
76 50
75
100
0.50(.020) 0.20±0.05(.008±.002)
M0.08(.003)0.145±0.055
(.0057±.0022)
0.08(.003)
"A"
INDEX.059 –.004
+.008–0.10+0.20
1.50(Mounting height)
0˚~8˚
0.50±0.20(.020±.008)0.60±0.15
(.024±.006)
0.25(.010)
0.10±0.10(.004±.004)
Details of "A" part
(Stand off)
*
Dimensions in mm (inches).Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.
111
CHAPTER 1 Description (100-pin/LCD)
1.7 Pin Description
Table 1.7-1 shows pin description. The alphabet in the "Circuit Type" column of Table 1.7-1 corresponds to the one in the "Classification" column of Table 1.8-1 .
Pin Description
Table 1.7-1 Pin Description (1 / 5)
Pin No. Pin name Circuit
type Function description
1 VSS - Power supply (GND) pin.
2 PG0/(C pin) H General-purpose I/O port (at 3 V). Capacitance connection pin (at 5 V).
3 P00/INT00
CGeneral-purpose I/O port.These pins are also used for external interrupt input. The large current port.
4 P01/INT01
5 P02/INT02
6 P03/INT03
7 P04/INT04
8 P05/INT05
9 P06/INT06
10 P07/INT07
11 P10/UI0 GGeneral-purpose I/O port.These pins are also used for UART/SIO ch0 data input.
12 P11/UO0
H
General-purpose I/O port.These pins are also used for UART/SIO ch0 data output.
13 P12/UCK0General-purpose I/O port.These pins are also used for UART/SIO ch0 clock I/O.
14P13/TRG0/ADTG
General-purpose I/O port.These pins are also used for 16-bit PPG ch0 trigger input (TRG0) and A/D trigger input (ADTG).
15 P14/PPG0General-purpose I/O port.These pins are also used for 16-bit PPG ch0 output.
16 P20/PPG00
H
General-purpose I/O port.These pins are also used for 8/16-bit PPG ch0 output. 17 P21/PPG01
18 P22/TO00 General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch0 output. 19 P23/TO01
20 P24/EC0General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch0 clock input.
112
21 P50/SCL0
I
General-purpose I/O port.These pins are also used for I2C ch0 clock I/O.
22 P51/SDA0General-purpose I/O port.These pins are also used for I2C ch0 data I/O.
23 P52/PPG1 HGeneral-purpose I/O port.These pins are also used for 16-bit PPG ch1 output.
24 AVR - A/D reference input pin.
25 AVCC - Power supply pin for A/D.
26 AVSS - Power supply (GND) pin for A/D.
27 P30/AN00
JGeneral-purpose I/O port.These pins are also used for A/D analog input.
28 P31/AN01
29 P32/AN02
30 P33/AN03
31 P34/AN04
32 P35/AN05
33 P36/AN06
34 P37/AN07
35 P40/AN08
JGeneral-purpose I/O port.These pins are also used for A/D analog input.
36 P41/AN09
37 P42/AN10
38 P43/AN11
39 P53/TRG1 HGeneral-purpose I/O port.These pins are also used for 16-bit PPG ch1 trigger input.
40 P70/TO0
H
General-purpose I/O port.These pins are also used for 16-bit reload timer ch0 output.
41 P71/TI0General-purpose I/O port.These pins are also used for 16-bit reload timer ch0 input.
42 P67/S39/SIN NGeneral-purpose I/O port.These pins are also used for LIN UART data input (SIN) and LCDC SEG output (S39).
Table 1.7-1 Pin Description (2 / 5)
Pin No. Pin name Circuit
type Function description
113
CHAPTER 1 Description (100-pin/LCD)
43 P66/S38/SOT
M
General-purpose I/O port.These pins are also used for LIN UART data output (SOT) and LCDC SEG output (S38).
44 P65/S37/SCKGeneral-purpose I/O port.These pins are also used for LIN UART clock I/O (SCK) and LCDC SEG output (S37).
45 P64/S36/EC1General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch1 clock input (EC1) and LCDC SEG output (S36).
46 P63/S35/TO11 General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch1 output (TO10, TO11) and LCDC SEG output (S34, S35). 47 P62/S34/TO10
48 RST B’ Reset pin.
49 X0AA Crystal oscillation pin (32 kHz).
50 X1A
51 VSS - Power supply (GND) pin.
52 X1A Crystal oscillation pin.
53 X0
54 MOD B Operation mode specification pin.
55 P61/S33/PPG11M
General-purpose I/O port.These pins are also used for 8/16-bit PPG ch1 output (PPG10, PPG11) and LCDC SEG output (S32, S33). 56 P60/S32/PPG10
57 PE7/S31/INT13
QGeneral-purpose I/O port.These pins are also used for external interrupt input (INT10 to INT13) and LCDC SEG output (S28 to S31).
58 PE6/S30/INT12
59 PE5/S29/INT11
60 PE4/S28/INT10
61 PE3/S27
MGeneral-purpose I/O port.These pins are also used for LCDC SEG output.
62 PE2/S26
63 PE1/S25
64 PE0/S24
Table 1.7-1 Pin Description (3 / 5)
Pin No. Pin name Circuit
type Function description
114
65 PD7/S23
MGeneral-purpose I/O port.These pins are also used for LCDC SEG output.
66 PD6/S22
67 PD5/S21
68 PD4/S20
69 PD3/S19
70 PD2/S18
71 PD1/S17
72 PD0/S16
73 PC7/S15
MGeneral-purpose I/O port.These pins are also used for LCDC SEG output.
74 PC6/S14
75 PC5/S13
76 VCC - Power supply pin.
77 PC4/S12
MGeneral-purpose I/O port.These pins are also used for LCDC SEG output.
78 PC3/S11
79 PC2/S10
80 PC1/S09
81 PC0/S08
82 PB7/S07
MGeneral-purpose I/O port.These pins are also used for LCDC SEG output.
83 PB6/S06
84 PB5/S05
85 PB4/S04
86 PB3/S03
87 PB2/S02
88 PB1/S01
89 PB0/S00
90 PA3/COM3
MGeneral-purpose I/O port.These pins are also used for LCDC COM output.
91 PA2/COM2
92 PA1/COM1
93 PA0/COM0
Table 1.7-1 Pin Description (4 / 5)
Pin No. Pin name Circuit
type Function description
115
CHAPTER 1 Description (100-pin/LCD)
94 P95/C1S
General-purpose I/O port.For products with LCDC voltage rise, these pins are dedicated capacitance connecting pins.95 P94/C0
96 P93/V0
RGeneral-purpose I/O port.These pins are also used for power supply pin for LCDC driving.
97 P92/V1
98 P91/V2
99 P90/V3
100 VCC - Power supply pin.
Table 1.7-1 Pin Description (5 / 5)
Pin No. Pin name Circuit
type Function description
116
1.8 I/O Circuit Type
Table 1.8-1 lists the I/O circuit types. Also, the alphabet in the "Classification" column of Table 1.8-1 corresponds to the one in the "Circuit Type" column of Table 1.7-1 .
I/O Circuit Type
Table 1.8-1 I/O Circuit Type (1 / 3)
Classi-fication
Circuit Remark
A
• Oscillation circuit
• Feedback resistance value
• High-speed side: approx. 1 MΩ• Low-speed side: approx. 10 MΩ• Only low-speed side oscillation of 3 V*
• Feedback resistance: approx. 24 MΩ• Dumping resistance: approx. 144 kΩ*: Excluding MB95FV100
B
• Input exclusive use
• Hysteresis input (only mask product)
• Pull-down resistance (only mask product)
B'
• Hysteresis input (only mask product)
• Reset output supported (only 5 V product)
C
• CMOS output
• Hysteresis input
G
• CMOS output
• CMOS input
• Hysteresis input
• Pull-up control
Standby control
X1 (X1A)
X0 (X0A)
Reset outputNch
Pch
Nch
Standby controlExternal interrupt enable
Pch
Nch
Standby control
Pull-up controlR
117
CHAPTER 1 Description (100-pin/LCD)
H
• CMOS output
• Hysteresis input
• Pull-up control
I
• Nch open drain output
• CMOS input
• Hysteresis input
J
• CMOS output
• Hysteresis input
• Analog input
• Pull-up control
M
• CMOS output
• LCD output
• Hysteresis input
Table 1.8-1 I/O Circuit Type (2 / 3)
Classi-fication
Circuit Remark
Pch
Nch
Standby control
Pull-up control R
Nch
Standby control
Pch
Nch
A/D control
Pull-up control R
Standby control
Analog input
Pch
Nch
LCD output
LCD control
Standby control
118
N
• CMOS output
• LCD output
• CMOS input
• Hysteresis input
Q
• CMOS output
• LCD output
• Hysteresis input
R
• CMOS output
• LCD power supply
• Hysteresis input
S
• CMOS output
• LCD power supply
• Hysteresis input
Table 1.8-1 I/O Circuit Type (3 / 3)
Classi-fication
Circuit Remark
Pch
Nch
LCD controlStandby control
LCD output
Pch
Nch
External interrupt control
LCD output
Standby controlLCD control
Pch
Nch
LCD controlStandby control
LCD internal divisionresistance I/O
LCD voltage rise I/O
Pch
Nch
Standby control
LCD voltage rise I/O
119
CHAPTER 1 Description (100-pin/LCD)
120
CHAPTER 1Description (80-pin/LCD)
This chapter explains a feature and a basic specification of the RESERVE2 series.
1.1 Feature of RESERVE2 Series
1.2 Product Lineup of RESERVE2 Series
1.3 Notes on Difference Point between Products and Selecting Product
1.4 Block Diagram of RESERVE2 Series
1.5 Pin Assignment
1.6 Package Dimension
1.7 Pin Description
1.8 I/O Circuit Type
121
CHAPTER 1 Description (80-pin/LCD)
1.1 Feature of RESERVE2 Series
In addition to a compact instruction set, the RESERVE2 series of general-purpose, single-chip microcontrollers feature a wide range of internal peripheral functions.
Feature of RESERVE2 Series
F2MC-8FX CPU core
Instruction system optimized for controllers
• Multiplication and division instructions
• 16-bit operation
• Bit test branch instruction
• Bit operation instructions etc.
Clock
• Main clock
• Main PLL clock
• Sub clock
• Sub PLL clock
Timer
• 8/16-bit compound timer × 2 channels
• 8/16-bit PPG × 2 channels
• 16-bit PPG × 2 channels
• Timebase timer
• Watch prescaler
LIN UART
• With full-duplex double buffer
• An asynchronous clock or a synchronous serial transfer can be used.
UART/serial interface
• Switch of UART/SIO is enabled.
I2C
• Within wake up improvement function
External interrupt
• Interrupt by the edge detection (Select rising edge/falling edge/both edges)
• Can be used to recover from low-power consumption modes.
122
10-bit A/D converter
• 10-bit resolution
LCD controller/driver
• 32 SEG × 4 COM (Max 128 pixels)
• With blinking function
Low-power consumption (standby mode)
• Stop mode
• Sleep mode
• Watch mode
• Timebase timer mode
I/O port: Max 69
• General-purpose I/O ports (Nch open drain) : 2
• General-purpose I/O ports (CMOS) : 67
123
CHAPTER 1 Description (80-pin/LCD)
1.2 Product Lineup of RESERVE2 Series
RESERVE2 series is available in 12 types. Table 1.2-1 lists the product range and Table 1.2-3 lists the CPUs and peripheral functions.
Product Lineup of RESERVE2 Series
For MASK products, specify whether to include LVD and CSV when issuing the mask ROM order.(Specifying CSV without LVD is not available.)
LVD: Low-voltage detection reset
CSV: Clock supervisor
*: No reset output at selected CSV.
Selection of Oscillation Stabilization Wait TimeOn MASK products, you can specify the default oscillation stabilization wait time as a mask option when
issuing the mask ROM order.
The default oscillation stabilization wait time is fixed to the maximum value on the EVA and FLASH
products.
*:Can be selected one type from 4 types.
Table 1.2-1 Product lineup of the RESERVE2 series
Model ROM/RAM VoltageReset Output
LCDC Option
EVA products
MB95FV100-101 60KB/4KB 3V None3V, LCD internal
resistor1/2 system selectable
MB95FV100-102 60KB/4KB 3V None 3V, LCD voltage rise 1/2 system selectable
MB95FV100-103 60KB/4KB 5V Yes *5V, LCD internal
resistor1/2 system selectable, LVD and
CSV selectable
3V products
FLASH products
MB95FXXX-001 XXKB/XKB 3V None LCD internal resistor Two-system
MB95FXXX-002 XXKB/XKB 3V None LCD voltage rise Two-system
MASK products
MB95XXX XXKB/XKB 3V NoneLCD internal
resistor/voltage riseTwo-system
5V products
FLASH products
MB95FXXXH-001 XXKB/XKB 5V Yes LCD internal resistorTwo-system,
LVD and CSV OFF
MB95FXXXH-101 XXKB/XKB 5V Yes LCD internal resistorTwo-system, LVD ON,
CSV OFF
MB95FXXXH-201 XXKB/XKB 5V None LCD internal resistorTwo-system,
LVD and CSV ON
MASK products
MB95XXXH XXKB/XKB 5V Yes * LCD internal resistorTwo-system,
LVD and CSV selectable
Table 1.2-2 Selection of Oscillation Stabilization Wait Time (MASK products)
Selection of Oscillation Stabilization Wait Time Remark
22/FCH 1.0 µs (at external 4 MHz)
212/FCH 1.024 ms (at external 4 MHz)
213/FCH 2.048 ms (at external 4 MHz)
214/FCH 4.096 ms (at external 4 MHz)
124
Table 1.2-3 CPU and peripheral function of RESERVE2 series
Item Specification
CPU function
Number of basic instructions: 136 instructionsInstruction bit length: 8 bitsInstruction length: 1 to 3 bytesData bit length: 1, 8, and 16 bitsMinimum instruction execution time: 0.1 µs (at internal 10 MHz)Interrupt processing time: 0.9 µs (at internal 10 MHz)
Per
iphe
ral f
unct
ion
PortGeneral-purpose I/O ports (Nch open drain) : 2General-purpose I/O ports (CMOS) :67Total :69 (Max)
Timebase timer Interrupt cycle 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (external 4 MHz)
Watchdog timerReset generation cycle: Main clock at external 10 MHz (Min 105 ms)
Subclock at 32.768 kHz (Min 250 ms)
Wild registers Data for three bytes can be replaced.
I2C bus
Master/slave sending/receivingBus error function and arbitration functionForwarding direction detection functionGenerating repeatedly and detecting function of the start condition.Within wake up improvement function
UART/SIO
Data transfer is enabled at UART/SIO.Changeable data length (5/6/7/8 -bit), Built-in baud rate generatorTransfer rate (2400 bps to 125000 bps@10 MHz), Built-in full-duplex double bufferNRZ method transfer format, Error detected functionLSB-first or MSB-first can be selected.Data transfer is available for clock synchronous (SIO) and clock asynchronous (UART).
LIN UARTA wide-range communication speed can be set with the dedicated reload timer.Data transfer is available for clock synchronous and clock asynchronous.LIN function is usable as a LIN master and LIN slave.
A/D converter 12 ch. 8-bit or 10-bit resolution can be selected.
8/16-bit composite timer2 ch. Can be configured as a 2 ch x 8-bit timer or 1 ch x 16-bit timer.Built-in timer function, PWC function, PWM function and capture functionInternal 7 kinds + clock selected from external. Square wave output.
16-bit PPG2 ch. PWM mode or one-shot mode can be selected.Eight selectable clock sourcesSupport for external trigger activation
8/16-bit PPG2 ch. Can be configured as a 2 ch x 8-bit PPG or 1 ch x 16-bit PPG.Eight selectable clock sources
Watch counterFour selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)Counter value can be set within the range of 0 to 63. (countable one minute)
Watch prescaler Four selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
LCD controller driverMax. 32 SEG × 4 COMBlinking function
External interrupt12ch.PWM mode or one-shot mode can be selected.Eight selectable clock sources Support for external trigger activation.
Standby Mode Sleep, stop, watch, timebase timer
125
CHAPTER 1 Description (80-pin/LCD)
1.3 Notes on Difference Point between Products and Selecting Product
The following describes differences between RESERVE2 series models and points to note when selecting the device model.
Notes on Difference Point between Products and Selecting Product
Notes on using EVA products
The EVA product is intended to support software development for a number of different F2MC-8FX familyseries and models, and it includes additional functions that may not be included in the target model.Accordingly, access to peripheral functions and I/O addresses that are not used in the target model isprohibited.
Reading or writing to these prohibited addresses may cause these unused peripheral functions to operateand lead to unexpected hardware or software problems.
Take particular care not to use word, long word, or similar access to read or write odd numbered bytes inthe prohibited areas.
Also, as the read values of prohibited addresses on the EVA product are different to the values on the targetFLASH and MASK products, do not use this data in software processing.
The functions corresponding to certain bits in single-byte registers may not be supported on particularmodels. However, reading or writing to these bits will not cause misoperation of the hardware. Also, as theEVA, FLASH, and MASK products are designed to have identical hardware and software operation, noparticular precautions are required.
Differences of memory space
If the memory size on the EVA product is different to the target FLASH or MASK product, please ensure
you confirm these differences enough when developing software.
A/D converter
The analog characteristics of the A/D converter analog input pins on the EVA product are slightly different
to the ones on the FLASH and MASK products. Please refer to the data sheet for the differences in external
analog input impedance enough before designing the external circuit.
Current consumption
• The current consumption of FLASH products is typically greater than for mask ROM products.
• For the details of current consumption, refer to "Electric characteristics" in data sheet.
• For detailed information on each package, see "1.6 Package Dimension".
• Operating voltage
- The operating voltage is different from each model.
- For the details, see the "data sheet".
Difference of RST/MOD pins
The RST and MOD pins are hysteresis inputs on the MASK products. A pull-down resistor is provided for
the MOD pin.
126
1.4 Block Diagram of RESERVE2 Series
Figure 1.4-1 shows block diagram of all RESERVE2 series.
Block Diagram of All RESERVE2 Series
Figure 1.4-1 Block Diagram of All RESERVE2 Series
VCCVSS
X0,X1
X0A,X1A
MOD
P53/TRG1
AVCC
AVSS
AVR
P52/PPG1
*:5V-product is Cpin terminal.
P62/S18/TO10
P13/TRG0/ADTG
P20/PPG00
P51/SDA0
P90/V3 to P93/V0
P94/C0 to P95/C1
PA0/COM0 to PA3/COM
PB0/S00 to PB7/S07
P14/PPG0
P50/SCL0
P00/INT00 to P07/INT07
P10/UI0
P11/UO0
P12/UCK0
PG0/(Cpin)*
RST
P40/AN08 to P43/AN11
(P00/AN00 to P07/AN07)
P21/PPG01
P22/TO00
P23/TO01
P24/EC0
P64/S20/EC1
PE6/S30/INT12
PE7/S31/INT13
PC0/S08 to PC7/S15
PE0/S24 to PE3/S27
PE5/S29/INT11
P61/S17/PPG11
P60/S16/PPG10
P65/S21/SCK
P66/S22/SOT
P67/S23/SIN
P63/S19/TO11
PE4/S28/INT10
UART/SIO
16bit PPG ch0
8/16bit PPG ch0
10bit A/D
I 2C
16bit PPG ch1
LIN UART
8/16bit PPG ch1
LCDC
F2MC-8FX CPU
ROM
RAM
Interrupt control
Wild register
Reset control
Clock control
Watch prescaler
Watch timer
External interrupt ch0-7
8/16-bitcompound timer ch1
8/16bitcompound timer ch0
External interrupt ch8-15
Port Port
Internal bus
127
CHAPTER 1 Description (80-pin/LCD)
1.5 Pin Assignment
Figure 1.5-1 shows pin assignment of the RESERVE2 series.
Pin Assignment of RESERVE2 Series
Figure 1.5-1 Pin Assignment of RESERVE2 Series
AV
ssP
00/IN
T00
/AN
00P
01/IN
T01
/AN
01P
02/IN
T02
/AN
02P
03/IN
T03
/AN
03P
04/IN
T04
/AN
04P
05/IN
T05
/AN
05P
06/IN
T06
/AN
06P
07/IN
T07
/AN
07P
40/A
N08
P41
/AN
09P
42/A
N10
P43
/AN
11P
E7/
S31
/INT
13P
E6/
S30
/INT
12P
E5/
S29
/INT
11P
E4/
S28
/INT
10P
E3/
S27
PE
2/S
26P
E1/
S25
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AVcc 1 60 PE0/S24AVR 2 59 P67/S23/SIN
PPG0/P14 3 58 P66/S22/SOTTRG0/ADTG/P13 4 57 P65/S21/SCK
UCK0/P12 5 56 P64/S20/EC1UO0/P11 6 55 P63/S19/TO11UI0/P10 7 54 P62/S18/TO10EC0/P24 8 53 P61/S17/PPG1
TO01/P23 9 52 P60/S16/PPG10TO00/P22 10 51 PC7/S15
PPG01/P21 11 50 PC6/S14PPG00/P20 12 49 PC5/S13TRG1/P53 13 48 PC4/S12PPG1/P52 14 47 PC3/S11SDA0/P51 15 46 PC2/S10SCL0/P50 16 45 PC1/S09
MOD 17 44 PC0/S08X0 18 43 PB7/S07X1 19 42 PB6/S06
Vss 20 41 PB5/S05
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Vcc
(Cpi
n)/P
G0
X1A
X0A
RS
TV
3/P
90V
2/P
91V
1/P
92V
0/P
93C
0/P
94C
1/P
95C
OM
0/P
A0
CO
M1/
PA
1C
OM
2/P
A2
CO
M3/
PA
3S
00/P
B0
S01
/PB
1S
02/P
B2
S03
/PB
3S
04/P
B4
TOP VIEW
80
128
1.6 Package Dimension
RESERVE2 series is available in one type of package.The package dimension below is for reference only.Contact Fujitsu for the nominal package dimension.
Package Dimension of FPT-80P-M11
Figure 1.6-1 Package Dimension of FPT-80P-M11
80-pin plastic LQFP Lead pitch 0.65 mm
Package width × package length
14.00 × 14.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.70 mm MAX
Code(Reference)
P-LQFP80-14×14-0.65
80-pin plastic LQFP(FPT-80P-M11)
(FPT-80P-M11)
C 2003 FUJITSU LIMITED F80016S-c-3-6
1 2 0
21
4061
80
4160
14.00±0.10(.551±.004)SQ
16.00±0.20(.630±.008)SQ
INDEX
0.65(.026) 0.32±0.05(.013±.002)
M0.13(.005)
"A"
(.006±.002)0.145±0.055
0.10(.004)
0.50±0.20(.020±.008)0.60±0.15
(.024±.006)
0~8˚
.059 –.004+.008
–0.10+0.20
1.50(Mounting height)
0.25(.010)
0.10±0.10(.004±.004)(Stand off)
Details of "A" part
*
Dimensions in mm (inches).Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.
129
CHAPTER 1 Description (80-pin/LCD)
1.7 Pin Description
Table 1.7-1 shows pin description. The alphabet in the "Circuit Type" column of Table 1.7-1 corresponds to the one in the "Classification" column of Table 1.8-1 .
Pin Description
Table 1.7-1 Pin description (1 / 4)
PinNo.
Pin nameCircuittype
Function description
1 AVcc - Power supply pin for A/D.
2 AVR - A/D reference input pin.
3 P14/PPG0
H
General-purpose I/O port.These pins are also used for 16-bit PPG ch0 output.
4 P13/TRG0/ADTGGeneral-purpose I/O port.These pins are also used for 16-bit PPG ch0 trigger input (TRG0) andA/D trigger input (ADTG).
5 P12/UCK0General-purpose I/O port.These pins are also used for UART/SIO ch0 clock I/O.
6 P11/UO0General-purpose I/O port.These pins are also used for UART/SIO ch0 data output.
7 P10/UI0 GGeneral-purpose I/O port.These pins are also used for UART/SIO ch0 data input.
8 P24/EC0
H
General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch0 clock input.
9 P23/T001 General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch0 output.10 P22/T000
11 P21/PPG01 General-purpose I/O port.These pins are also used for 8/16-bit PPG ch0 output.12 P20/PPG00
13 P53/TRG1
H
General-purpose I/O port.These pins are also used for 16-bit PPG ch1 trigger input.
14 P52/PPG1General-purpose I/O port.These pins are also used for 16-bit PPG ch1 output.
15 P51/SDA0
I
General-purpose I/O port.These pins are also used for I2C ch0 data I/O.
16 P50/SCL0General-purpose I/O port.These pins are also used for I2C ch0 clock I/O.
17 MOD B Operation mode specification pin.
130
18 X0A Crystal oscillation pin.
19 X1
20 Vss - Power supply (GND) pin.
21 Vcc - Power supply pin.
22 PG0/(C pin) H General-purpose I/O port (at 3 V). Capacitance connection pin (at 5 V).
23 X1AA Crystal oscillation pin (32 kHz).
24 X0A
25 RST B’ Reset pin.
26 P90/V3
RGeneral-purpose I/O port.These pins are also used for power supply pin for LCDC driving.
27 P91/V2
28 P92/V1
29 P93/V0
30 P94/C0S
General-purpose I/O port.For products with LCDC voltage rise, these pins are dedicated capacitance connecting pins.31 P95/C1
32 PA0/COM0
MGeneral-purpose I/O port.These pins are also used for LCDC COM output.
33 PA1/COM1
34 PA2/COM2
35 PA3/COM3
36 PB0/S00
MGeneral-purpose I/O port.These pins are also used for LCDC SEG output.
37 PB1/S01
38 PB2/S02
39 PB3/S03
40 PB4/S04
41 PB5/S05
42 PB6/S06
43 PB7/S07
Table 1.7-1 Pin description (2 / 4)
PinNo.
Pin nameCircuittype
Function description
131
CHAPTER 1 Description (80-pin/LCD)
44 PC0/S08
MGeneral-purpose I/O port.These pins are also used for LCDC SEG output.
45 PC1/S09
46 PC2/S10
47 PC3/S11
48 PC4/S12
49 PC5/S13
50 PC6/S14
51 PC7/S15
52 P60/S16/PPG10
M
General-purpose I/O port.These pins are also used for 8/16-bit PPG ch1 output (PPG10, PPG11) and LCDC SEG output (S16, S17).53 P61/S17/PPG11
54 P62/S18/TO10 General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch1 output (TO10, TO11) and LCDC SEG output (S18, S19).55 P63/S19/TO11
56 P64/S20/EC1General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch1 clock input (EC1) and LCDC SEG output (S20).
57 P65/S21/SCKGeneral-purpose I/O port.These pins are also used for LIN UART clock I/O (SCK) and LCDC SEG output (S21).
58 P66/S22/SOTGeneral-purpose I/O port.These pins are also used for LIN UART data output (SOT) and LCDC SEG output (S22).
59 P67/S23/SIN NGeneral-purpose I/O port.These pins are also used for LIN UART data input (SIN) and LCDC SEG output (S23).
60 PE0/S24
MGeneral-purpose I/O port.These pins are also used for LCDC SEG output.
61 PE1/S25
62 PE2/S26
63 PE3/S27
64 PE4/S28/INT10
QGeneral-purpose I/O port.These pins are also used for external interrupt input (INT10 to INT13) and LCDC SEG output (S28 to S31).
65 PE5/S29/INT11
66 PE6/S30/INT12
67 PE7/S31/INT13
Table 1.7-1 Pin description (3 / 4)
PinNo.
Pin nameCircuittype
Function description
132
68 P43/AN11
JGeneral-purpose I/O port.These pins are also used for A/D analog input.
69 P42/AN10
70 P41/AN09
71 P40/AN08
72 P07/INT07/AN07
DGeneral-purpose I/O port.These pins are also used for external interrupt input (INT00 to INT07) andA/D analog input (AN00 to AN07).
73 P06/INT06/AN06
74 P05/INT05/AN05
75 P04/INT04/AN04
76 P03/INT03/AN03
77 P02/INT02/AN02
78 P01/INT01/AN01
79 P00/INT00/AN00
80 AVss - Power supply (GND) pin for A/D.
Table 1.7-1 Pin description (4 / 4)
PinNo.
Pin nameCircuittype
Function description
133
CHAPTER 1 Description (80-pin/LCD)
1.8 I/O Circuit Type
Table 1.8-1 lists the I/O circuit types. Also, the alphabet in the "Type" column of Table 1.8-1 corresponds to the one in the "Circuit Type" column of Table 1.8-1 .
I/O Circuit Type
Table 1.8-1 I/O Circuit Type (1 / 4)
Classi-fication Circuit Remark
A
• Oscillation circuit
• Feedback resistance value
High-speed side: approx. 1 MΩ
Low-speed side: approx. 10 MΩ
• Only low-speed side oscillation of 3 V*
Feedback resistance: approx. 24 MΩ
Dumping resistance: approx. 144 kΩ
*: Excluding MB95FV100
B
• Input exclusive use
• Hysteresis input (only mask product)
• Pull-down resistance (only mask product)
B'
• Hysteresis input (only mask product)
• Reset output supported (only 5 V product)
D
• CMOS output
• Hysteresis input
• Analog input
• Pull-up control is available.
Standby control
X1 (X1A)
X0 (X0A)
Reset outputNch
Pch
Nch
R
A/D controlStandby control
External interrupt control
Analog input
Pull-up control
134
G
• CMOS output
• CMOS input
• Hysteresis input
• Pull-up control is available.
H
• CMOS output
• Hysteresis input
• Pull-up control is available.
I
• Nch open drain output
• CMOS input
• Hysteresis input
J
• CMOS output
• Hysteresis input
• Analog input
• Pull-up control is available.
Table 1.8-1 I/O Circuit Type (2 / 4)
Classi-fication Circuit Remark
Pch
Nch
Standby control
Pull-up controlR
Pch
Nch
Standby control
Pull-up control R
Nch
Standby control
Pch
Nch
A/D control
Pull-up control R
Standby control
Analog input
135
CHAPTER 1 Description (80-pin/LCD)
M
• CMOS output
• LCD output
• Hysteresis input
N
• CMOS output
• LCD output
• CMOS input
• Hysteresis input
Q
• CMOS output
• LCD output
• Hysteresis input
R
• CMOS output
• LCD power supply
• Hysteresis input
Table 1.8-1 I/O Circuit Type (3 / 4)
Classi-fication Circuit Remark
Pch
Nch
LCD output
LCD control
Standby control
Pch
Nch
LCD controlStandby control
LCD output
Pch
Nch
External interrupt control
LCD output
Standby controlLCD control
Pch
Nch
LCD controlStandby control
LCD internal divisionresistance I/O
LCD voltage rise I/O
136
S
• CMOS output
• LCD power supply
• Hysteresis input
Table 1.8-1 I/O Circuit Type (4 / 4)
Classi-fication Circuit Remark
Pch
Nch
Standby control
LCD voltage rise I/O
137
CHAPTER 1 Description (80-pin/LCD)
138
CHAPTER 1Description (64-pin/LCD)
This chapter explains a feature and a basic specification of the TROMBONE series.
1.1 Feature of TROMBONE Series
1.2 Product Lineup of TROMBONE Series
1.3 Notes on Difference Point between Products and Selecting Product
1.4 Block Diagram of TROMBONE Series
1.5 Pin Assignment
1.6 Package Dimension
1.7 Pin Description
1.8 I/O Circuit Type
139
CHAPTER 1 Description (64-pin/LCD)
1.1 Feature of TROMBONE Series
In addition to a compact instruction set, the TROMBONE series is general-purpose, single-chip microcontrollers with a wide range of internal peripheral functions.
Feature of TROMBONE Series
F2MC-8FX CPU core
Instruction system optimized for controllers
• Multiplication and division instructions
• 16-bit operation
• Branch instruction by bit test
• Bit manipulation instructions etc.
Clock
• Main clock
• Main PLL clock
• Sub clock
• Sub PLL clock
Timer
• 8/16-bit compound timer × 2 channels
• 8/16-bit PPG × 2 channels
• 16-bit PPG
• Timebase timer
• Watch prescaler
LIN UART
• With full-duplex double buffer
• An asynchronous clock or a synchronous serial transfer can be used.
UART/serial interface
• Switch of UART/SIO is enabled.
I2C
• With wake up improvement function
External interrupt
• Interrupt by the edge detection (Select rising edge/falling edge/both edges)
• Can be used to recover from low-power consumption modes.
140
10-bit A/D converter
• 10-bit resolution
LCD controller/driver
• 32SEG × 4COM (Max 128 pixels) *: Product without voltage rise option
• 24SEG × 4COM (Max 96 pixels) *: Product with voltage rise option
• With blinking function
Low-power consumption (standby mode)
• Stop mode
• Sleep mode
• Watch mode
• Timebase timer mode
I/O port: Max 53
• General-purpose I/O ports (Nch open drain): 2
• General-purpose I/O ports (CMOS): 51
141
CHAPTER 1 Description (64-pin/LCD)
1.2 Product Lineup of TROMBONE Series
TROMBONE series is available in 12 types. Table 1.2-1 lists the product lineup and Table 1.2-3 lists the CPUs and peripheral functions.
Product Lineup of TROMBONE Series
For MASK products, specify whether to include LVD and CSV when issuing the mask ROM order.(Specifying CSV without LVD is not available.)
LVD: Low-voltage detection reset
CSV: Clock supervisor
*: No reset output at selected CSV.
Selection of Oscillation Stabilization Wait TimeOn MASK products, you can specify the default value of oscillation stabilization wait time as a mask optionwhen issuing the mask ROM order.
The default oscillation stabilization delay time is fixed the maximum value on the EVA and FLASHproducts.
*:Can be selected one from 4 types.
Table 1.2-1 Product Lineup of TROMBONE Series
Model ROM/RAM Voltage Reset Output
LCD Option
EVA products
MB95FV100-101 60KB/4KB 3V None3V, LCD
internal resistor1/2 system selectable
MB95FV100-102 60KB/4KB 3V None3V, LCD
voltage rise1/2 system selectable
MB95FV100-103 60KB/4KB 5V Yes *5V, LCD
internal resistor1/2 system selectable, LVD and
CSV selectable
3V products
FLASH products
MB95FXXX-001 XXKB/XKB 3V NoneLCD internal
resistorTwo-system
MB95FXXX-002 XXKB/XKB 3V None LCD voltage rise Two-system
MASK products
MB95XXX XXKB/XKB 3V NoneLCD internal
resistor/voltage riseTwo-system
5V products
FLASH products
MB95FXXXH-001 XXKB/XKB 5V YesLCD internal
resistorTwo-system,
LVD and CSV OFF
MB95FXXXH-101 XXKB/XKB 5V YesLCD internal
resistorTwo-system, LVD ON,
CSV OFF
MB95FXXXH-201 XXKB/XKB 5V NoneLCD internal
resistorTwo-system,
LVD and CSV ON
MASK products
MB95XXXH XXKB/XKB 5V Yes *LCD internal
resistorTwo-system,
LVD and CSV selectable
Table 1.2-2 Selection of Oscillation Stabilization Wait Time (MASK products)
Selection of Oscillation Stabilization Wait Time Remark
22/FCH 1.0 µs (at external 4 MHz)
212/FCH 1.024 ms (at external 4 MHz)
213/FCH 2.048 ms (at external 4 MHz)
214/FCH 4.096 ms (at external 4 MHz)
142
Table 1.2-3 CPU and Peripheral Function of TROMBONE Series
Item Specification
CPU function
Number of basic instructions: 136 instructionsInstruction bit length: 8 bitsInstruction length: 1 to 3 bytesData bit length: 1, 8, and 16 bitsMinimum instruction execution time: 0.1 µs (at internal 10 MHz)Interrupt processing time: 0.9 µs (at internal 10 MHz)
Peripheral function
PortGeneral-purpose I/O ports (Nch open drain) : 2General-purpose I/O ports (CMOS) :51Total :53 (Max)
Timebase timer Interrupt cycle 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (external 4 MHz)
Watchdog timerReset generation cycle: Main clock at external 10 MHz (Min 105 ms)
Subclock at 32.768 kHz (Min 250 ms)
Wild registers Data for three bytes can be replaced.
I2C bus
Master/slave sending/receivingBus error function and arbitration functionForwarding direction detection functionGenerating repeatedly and detecting function of the start condition.Within wake up improvement function
UART/SIO
Data transfer is enabled at UART/SIO.Changeable data length (5/6/7/8 -bit), Built-in baud rate generatorTransfer rate (2400 bps to 125000 bps@10 MHz), Built-in full-duplex double bufferNRZ method transfer format, Error detected functionLSB-first or MSB-first can be selected.Data transfer is available for clock synchronous (SIO) and clock asynchronous (UART).
LIN UARTA wide-range communication speed can be set with the dedicated reload timer.Data transfer is available for clock synchronous and clock asynchronous.LIN function is usable as a LIN master and LIN slave.
A/D converter 8 ch. 8-bit or 10-bit resolution can be selected.
8/16-bit composite timer2 ch. Can be configured as a 2 ch x 8-bit timer or 1 ch x 16-bit timer.Built-in timer function, PWC function, PWM function and capture functionInternal 7 kinds + clock selected from external. Square wave output.
16-bit PPGPWM mode or one-shot mode can be selected.Eight selectable clock sourcesSupport for external trigger activation.
8/16-bit PPG2 ch. Can be configured as a 2 ch x 8-bit PPG or 1 ch x 16-bit PPG.Eight selectable clock sources
Watch counterFour selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)Counter value can be set within the range of 0 to 63. (countable one minute)
Watch prescaler Four selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
LCD controller driverMax. 32 SEG × 4 COMBlinking function
External interrupt8 ch. Interrupt by edge detection. (Select rising edge/falling edge/both edges)Can be used to recover from standby modes.
Standby Mode Sleep, stop, watch, timebase timer
143
CHAPTER 1 Description (64-pin/LCD)
1.3 Notes on Difference Point between Products and Selecting Product
The following describes the differences from each model of the TROMBONE series and the points to note when selecting the device model.
Notes on Difference Point between Products and Selecting Product
Notes on using EVA products
The EVA product is intended to support software development for a number of different F2MC-8FX familyseries and models, and it includes additional functions that may not be included in the target model.Accordingly, access to peripheral functions and I/O addresses that are not used in the target model isprohibited.
Reading or writing to these prohibited addresses may cause these unused peripheral functions to operateand lead to unexpected hardware or software problems.
Take particular care not to use word, long word, or similar access to read or write odd numbered bytes inthe prohibited areas.
Also, as the read values of prohibited addresses on the EVA product are different to the values on the targetFLASH and MASK products, do not use this data in software processing.
The functions corresponding to certain bits in single-byte registers may not be supported on particularmodels. However, reading or writing to these bits will not cause misoperation of the hardware. Also, as theEVA, FLASH, and MASK products are designed to have identical hardware and software operation, noparticular precautions are required.
Differences of memory space
If the memory size on the EVA product is different to the target FLASH or MASK product, please ensureyou confirm these differences thoroughly when developing software.
A/D converter
The analog characteristics of the A/D converter analog input pins on the EVA product are slightly differentto the characteristics on the FLASH and MASK products. Please refer to the data sheet for the differencesin external analog input impedance thoroughly before designing the external circuit.
Current consumption
• The current consumption of FLASH product is typically greater than for mask ROM products.
• For the details of current consumption, refer to "Electric characteristics" in data sheet.
• For detailed information on each package, see "1.6 Package Dimension".
• Operating voltage
- The operating voltage is different on each model.
- For the details, see the "data sheet".
Difference of RST/MOD pins
The RST and MOD pins are hysteresis inputs on the MASK products. A pull-down resistor is provided forthe MOD pin.
Segment pin
When a 3V product with a voltage rise option is selected, the P00/S31 to P07/S24 pins cannot be used assegment pin outputs.
144
1.4 Block Diagram of TROMBONE Series
Figure 1.4-1 shows block diagram of all TROMBONE series.
Block Diagram of All TROMBONE Series
Figure 1.4-1 Block Diagram of All TROMBONE Series
P13/TRG0/ADTG
P20/PPG00
P90/V3 to P93/V0
P94/C0 to P95/C1
P64/S20/EC1
P66/S22/SOT
AVR
P22/TO00
P23/TO01/SCL0PA0/COM0 to PA3/COM
PB0/S00 to PB7/S07
(P00/S31 to P07/S24)
RST
(P00/AN00toP07/AN07)
P21/PPG01
P00/INT00 to P07/INT07
P10/UI0
P11/UO0
P14/PPG0
PG0/(Cpin)*
P62/S18/TO10
P61/S17/PPG11
P60/S16/PPG10
P67/S23/SIN
P63/S19/TO11
PC0/S08 to PC7/S15
P65/S21/SCK
*: 5V-product is Cpin terminal.VCCVSS
X0,X1
X0A,X1A
P12/UCK0
MOD
P24/EC0/SDA0
AVCC
AVSS
UART/SIO
16bit PPG
8/16bit PPG ch0
10bit A/D
I 2C
LIN UART
8/16bit PPG ch1
LCDC
F2MC-8FX CPU
ROM
RAM
Reset control
Clock control
Watch prescaler
Watch counter
Interrupt control
Wild register
External interrupt
8/16-bitcompound timer ch1
8/16-bitcompound timer ch0
Port Port
Internal bus
145
CHAPTER 1 Description (64-pin/LCD)
1.5 Pin Assignment
Figure 1.5-1 shows pin assignment of TROMBONE series.
Pin Assignment of TROMBONE Series
Figure 1.5-1 Pin Assignment of TROMBONE Series
AV
ssP
00/IN
T00
/AN
00/S
3P
01/IN
T01
/AN
01/S
3P
02/IN
T02
/AN
02/S
2P
03/IN
T03
/AN
03/S
2P
04/IN
T04
/AN
04/S
2P
05/IN
T05
/AN
05/S
2P
06/IN
T06
/AN
06/S
2P
07/IN
T07
/AN
07/S
2P
67/S
23/S
INP
66/S
22/S
OT
P65
/S21
/SC
KP
64/S
20/E
C1
P63
/S19
/TO
11P
62/S
18/T
O10
P61
/S17
/PP
G11
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc 1 48 P60/S16/PPG1AVR 2 47 PC7/S15
PPG0/P14 3 46 PC6/S14TRG0/ADTG/P13 4 45 PC5/S13
UCK0/P12 5 44 PC4/S12UO0/P11 6 43 PC3/S11UI0/P10 7 42 PC2/S10
EC0/SDA0/P24 8 41 PC1/S09TO01/SCL0/P23 9 40 PC0/S08
TO00/P22 10 39 PB7/S07PPG01/P21 11 38 PB6/S06PPG00/P20 12 37 PB5/S05
MOD 13 36 PB4/S04X0 14 35 PB3/S03X1 15 34 PB2/S02
Vss 16 33 PB1/S01
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Vcc
(Cpi
n)/P
G0
X1A
X0A
RS
TV
3/P
90V
2/P
91V
1/P
92V
0/P
93C
0/P
94C
1/P
95C
OM
0/P
A0
CO
M1/
PA
1C
OM
2/P
A2
CO
M3/
PA
3S
00/P
B0
64
TOP VIEW
146
1.6 Package Dimension
TROMBONE series is available in one type of package.The package dimension below is for reference only.Contact Fujitsu for the nominal package dimension for the released product.
Package Dimension of FPT-64P-M03
Figure 1.6-1 Package Dimension of FPT-64P-M03
64-pin plastic LQFP Lead pitch 0.50 mm
Package width × package length
10.0 × 10.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.70 mm MAX
Weight 0.32g
Code(Reference)
P-LFQFP64-10×10-0.50
64-pin plastic LQFP(FPT-64P-M03)
(FPT-64P-M03)
LEAD No.
Details of "A" part
0.25(.010)
(Stand off)(.004±.004)0.10±0.10
(.024±.006)0.60±0.15
(.020±.008)0.50±0.20
1.50+0.20–0.10
+.008–.004.059
0˚~8˚
"A"
0.08(.003)
(.006±.002)0.145±0.055
0.08(.003) M(.008±.002)0.20±0.050.50(.020)
12.00±0.20(.472±.008)SQ
10.00±0.10(.394±.004)SQ
INDEX
49
64
3348
17
32
161
2003 FUJITSU LIMITED F64009S-c-5-8C
(Mounting height)
*
Dimensions in mm (inches).Note: The values in parentheses are reference values
Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.
147
CHAPTER 1 Description (64-pin/LCD)
1.7 Pin Description
Table 1.7-1 shows pin description. The alphabet in the "Circuit Type" column of Table 1.7-1 corresponds to the one in the "Classification" column of Table 1.8-1 .
Pin Description
Table 1.7-1 Pin Description (1 / 3)
Pin No. Pin name Circuit
type Function description
1 AVcc - Power supply pin for A/D.
2 AVR - A/D reference input pin.
3 P14/PPG0
H
General-purpose I/O port.These pins are also used for 16-bit PPG ch0 output.
4 P13/TRG0/ADTGGeneral-purpose I/O port.These pins are also used for 16-bit PPG ch0 trigger input (TRG0) andA/D trigger input (ADTG).
5 P12/UCK0General-purpose I/O port.These pins are also used for UART/SIO ch0 clock I/O.
6 P11/U00General-purpose I/O port.These pins are also used for UART/SIO ch0 data output.
7 P10/UI0 GGeneral-purpose I/O port.These pins are also used for UART/SIO ch0 data input.
8 P24/EC0/SDA0
I
General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch0 clock input (EC) and I2C ch0 data I/O (SDA).
9 P23/TO01/SCL0General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch0 output (TO) and I2C ch0 clock I/O (SCL).
10 P22/TO00
H
General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch0 output.
11 P21/PPG01 General-purpose I/O port.These pins are also used for 8/16-bit PPG ch0 output.12 P20/PPG00
13 MOD B Operation mode specification pin.
14 X0A Crystal oscillation pin.
15 X1
16 Vss - Power supply (GND) pin.
17 Vcc - Power supply pin.
148
18 PG0/(C pin) H General-purpose I/O port (at 3 V). Capacitance connection pin (at 5 V).
19 X1AA Crystal oscillation pin (32 kHz).
20 X0A
21 RST B’ Reset pin.
22 P90/V3
RGeneral-purpose I/O port.These pins are also used for power supply pin for LCDC driving.
23 P91/V2
24 P92/V1
25 P93/V0
26 P94/C0S
General-purpose I/O port.For products with LCDC voltage rise, these pins are dedicated capacitance connecting pins.27 P95/C1
28 PA0/COM0
MGeneral-purpose I/O port.These pins are also used for LCDC COM output.
29 PA1/COM1
30 PA2/COM2
31 PA3/COM3
32 PB0/S00
MGeneral-purpose I/O port.These pins are also used for LCDC SEG output.
33 PB1/S01
34 PB2/S02
35 PB3/S03
36 PB4/S04
37 PB5/S05
38 PB6/S06
39 PB7/S07
40 PC0/S08
41 PC1/S09
42 PC2/S10
43 PC3/S11
44 PC4/S12
45 PC5/S13
46 PC6/S14
47 PC7/S15
Table 1.7-1 Pin Description (2 / 3)
Pin No. Pin name Circuit
type Function description
149
CHAPTER 1 Description (64-pin/LCD)
48 P60/S16/PPG10M
General-purpose I/O port.These pins are also used for 8/16-bit PPG ch1 output (PPG10, PPG11) and LCDC SEG output (S16, S17).49 P61/S17/PPG11
50 P62/S18/TO10
M
General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch1 output (TO10, TO11) and LCDC SEG output (S18, S19).51 P63/S19/TO11
52 P64/S20/EC1General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch1 clock input (EC1) and LCDC SEG output (S20).
53 P65/S21/SCKGeneral-purpose I/O port.These pins are also used for LIN UART clock I/O (SCK) and LCDC SEG output (S21).
54 P66/S22/SOTGeneral-purpose I/O port.These pins are also used for LIN UART data output (SOT) and LCDC SEG output (S22).
55 P67/S23/SIN NGeneral-purpose I/O port.These pins are also used for LIN UART data input (SIN) and LCDC SEG output (S23).
56 P07/INT07/AN07/S24
FGeneral-purpose I/O port.These pins are also used for external interrupt input (INT00 to INT07), A/D analog input (AN00 to AN07) and LCDC SEG output (S24 to S31).
57 P06/INT06/AN06/S25
58 P05/INT05/AN05/S26
59 P04/INT04/AN04/S27
60 P03/INT03/AN03/S28
61 P02/INT02/AN02/S29
62 P01/INT01/AN01/S30
63 P00/INT00/AN00/S31
64 AVss - Power supply (GND) pin for A/D.
Table 1.7-1 Pin Description (3 / 3)
Pin No. Pin name Circuit
type Function description
150
1.8 I/O Circuit Type
Table 1.8-1 lists the I/O circuit types. Also, the alphabet in the "Classification" column of Table 1.8-1 corresponds to the one in the "Circuit Type" column of Table 1.7-1 .
I/O Circuit Type
Table 1.8-1 I/O Circuit Type (1 / 3)
Classi-fication
Circuit Remark
A
• Oscillation circuit
• Feedback resistance value
High-speed side: approx. 1 MΩ
Low-speed side: approx. 10 MΩ
• Only low-speed side oscillation of 3 V*
Feedback resistance: approx. 24 MΩ
Dumping resistance: approx. 144 kΩ
*: Excluding MB95FV100
B
• Input exclusive use
• Hysteresis input (only mask product)
• Pull-down resistance (only mask product)
B'
• Hysteresis input (only mask product)
• Reset output supported (only 5V product)
F
• CMOS output
• LCD output
• Hysteresis input
• Analog input
Standby control
X1 (X1A)
X0 (X0A)
Reset outputNch
Pch
Nch
A/D control
Analog Input
Standby control External Interrupt control
LCD output
LCD control
151
CHAPTER 1 Description (64-pin/LCD)
G
• CMOS output
• CMOS input
• Hysteresis input
• Pull-up control is available.
H
• CMOS output
• Hysteresis input
• Pull-up control is available.
I
• Nch open drain output
• CMOS input
• Hysteresis input
M
• CMOS output
• LCD output
• Hysteresis input
Table 1.8-1 I/O Circuit Type (2 / 3)
Classi-fication
Circuit Remark
Pch
Nch
Standby control
Pull-up controlR
Pch
Nch
Standby control
Pull-up control R
Nch
Standby control
Pch
Nch
LCD output
LCD control
Standby control
152
N
• CMOS output
• LCD output
• CMOS input
• Hysteresis input
R
• CMOS output
• LCD power supply
• Hysteresis input
S
• CMOS output
• LCD power supply
• Hysteresis input
Table 1.8-1 I/O Circuit Type (3 / 3)
Classi-fication
Circuit Remark
Pch
Nch
LCD controlStandby control
LCD output
Pch
Nch
LCD controlStandby control
LCD internal divisionresistance I/O
LCD voltage rise I/O
Pch
Nch
Standby control
LCD voltage rise I/O
153
CHAPTER 1 Description (64-pin/LCD)
154
CHAPTER 1Description (48-pin/LCD)
This chapter explains a feature and a basic specification of the TRUMPET series.
1.1 Feature of TRUMPET Series
1.2 Product Lineup of the TRUMPET Series
1.3 Notes on Difference Point between Products and Selecting Product
1.4 Block Diagram of TRUMPET Series
1.5 Pin Assignment
1.6 Package Dimension
1.7 Pin Description
1.8 I/O Circuit Type
155
CHAPTER 1 Description (48-pin/LCD)
1.1 Feature of TRUMPET Series
In addition to a compact instruction set, TRUMPET series is general-purpose, single-chip microcontrollers with a wide range of internal peripheral functions.
Feature of TRUMPET Series
F2MC-8FX CPU core
Instruction system optimized for controllers
• Multiplication and division instructions
• 16-bit operation
• Branch instruction by bit test
• Bit manipulation instructions etc.
Clock
• Main clock
• Main PLL clock
• Sub clock
• Sub PLL clock
Timers
• 8/16-bit compound timer × 2 channels
• 8/16-bit PPG × 2 channels
• 16-bit PPG
• Timebase timer
• Watch prescaler
LIN UART
• With full-duplex double buffer
• An asynchronous clock or a synchronous serial transfer can be used.
UART/serial interface
• Switch of UART/SIO is enabled.
External interrupt
• Interrupt by the edge detection (Select rising edge/falling edge/both edges)
• Can be used to recover from low-power consumption modes.
10-bit A/D converter
• 10-bit resolution
LCD controller/driver
• 16SEG × 4COM (Max 64 pixels)
156
• With blinking function
Low-power consumption (standby mode)
• Stop mode
• Sleep mode
• Watch mode
• Timebase timer mode
I/O port: Max 40
• General-purpose I/O ports (CMOS): 40
157
CHAPTER 1 Description (48-pin/LCD)
1.2 Product Lineup of the TRUMPET Series
TRUMPET series is available in twelve types. Table 1.2-1 lists the product lineup and Table 1.2-3 lists the CPUs and peripheral functions.
Product Lineup of TRUMPET Series
For MASK products, specify whether to include LVD and CSV when issuing the mask ROM order.
(Specifying CSV without LVD is not available.)
LVD: Low-voltage detection reset
CSV: Clock supervisor
*: No reset output at selected CSV
Selection of Oscillation Stabilization Wait TimeOn MASK products, you can specify the default oscillation stabilization wait time as a mask option when
issuing the mask ROM order.
The default oscillation stabilization wait time is fixed the maximum value on the EVA and FLASH
products.
*Can be selected one from 4 types.
Table 1.2-1 Product Lineup of TRUMPET Series
Model ROM/RAM VoltageReset Output
LCDC Option
EVA products
MB95FV100-101 60KB/4KB 3V None3V, LCD
internal resistor1/2 system selectable
MB95FV100-102 60KB/4KB 3V None3V, LCD
voltage rise1/2 system selectable
MB95FV100-103 60KB/4KB 5V Yes *5V, LCD
internal resistor1/2 system selectable, LVD and
CSV selectable
3V products
FLASH products
MB95FXXX-001 XXKB/XKB 3V None LCD internal resistor Two-system
MB95FXXX-002 XXKB/XKB 3V None LCD voltage rise Two-system
MASK products
MB95XXX XXKB/XKB 3V NoneLCD internal
resistor/voltage riseTwo-system
5V products
FLASH products
MB95FXXXH-001 XXKB/XKB 5V Yes LCD internal resistor Two-system, LVD and CSV OFF
MB95FXXXH-101 XXKB/XKB 5V Yes LCD internal resistor Two-system, LVD ON, CSV OFF
MB95FXXXH-201 XXKB/XKB 5V None LCD internal resistor Two-system, LVD and CSV ON
MASK products
MB95XXXH XXKB/XKB 5V Yes * LCD internal resistorTwo-system,
LVD and CSV selectable
Table 1.2-2 Selection of Oscillation Stabilization Wait Time (MASK product)
Selection of Oscillation Stabilization Wait Time Remark
22/FCH 1.0 µs (at external 4 MHz)
212/FCH 1.024 ms (at external 4 MHz)
213/FCH 2.048 ms (at external 4 MHz)
214/FCH 4.096 ms (at external 4 MHz)
158
Table 1.2-3 CPU and Peripheral Function of TRUMPET Series
Item Specification
CPU function
Number of basic instructions: 136 instructionsInstruction bit length: 8 bitsInstruction length: 1 to 3 bytesData bit length: 1, 8, and 16 bitsMinimum instruction execution time: 0.1 µs (at internal 10 MHz)Interrupt processing time: 0.9 µs (at internal 10 MHz)
Peri
pher
al f
unct
ion
Port General-purpose I/O ports (CMOS) :40 (Max)
Timebase timer Interrupt cycle 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (external 4 MHz)
Watchdog timerReset generation cycle: Main clock at external 10 MHz (Min 105 ms)
Subclock at 32.768 kHz (Min 250 ms)
Wild register Data for three bytes can be replaced.
UART/SIO
Data transfer is enabled at UART/SIO.Changeable data length (5/6/7/8 -bit), Built-in baud rate generatorTransfer rate (2400 bps to 125000 bps@10 MHz), Built-in full-duplex double bufferNRZ method transfer format, error detected functionLSB-first or MSB-first can be selected.Data transfer is available for clock synchronous (SIO) and clock asynchronous (UART).
LIN UARTA wide-range communication speed can be set with the dedicated reload timer.Data transfer is available for clock synchronous and clock asynchronous.LIN function is usable as a LIN master and LIN slave.
A/D converter 8 ch. 8-bit or 10-bit resolution can be selected.
8/16-bit composite timer2 ch. Can be configured as a 2 ch x 8-bit timer or 1 ch x 16-bit timer.Built-in timer function, PWC function, PWM function and capture functionInternal 7 kinds + clock selected from external. Square wave output.
16-bit PPGPWM mode or one-shot mode can be selected.Eight selectable clock sourcesSupport for external trigger activation
8/16-bit PPG2 ch. Can be configured as a 2 ch x 8-bit PPG or 1 ch x 16-bit PPG.Eight selectable clock sources
Watch counterFour selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)Counter value can be set within the range of 0 to 63. (countable one minute)
Watch prescaler Four selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
LCD controllerdriver
Max. 16 SEG × 4 COMBlinking function
External interrupt8 ch. Interrupt by edge detection. (Select rising edge/falling edge/both edges)Can be used to recover from standby modes.
Standby Mode Sleep, stop, watch, timebase timer
159
CHAPTER 1 Description (48-pin/LCD)
1.3 Notes on Difference Point between Products and Selecting Product
The following describes differences in TRUMPET series models and points to note when selecting the device model.
Notes on Difference Point between Products and Selecting Product
Notes on using EVA products
The EVA product is intended to support software development for a number of different F2MC-8FX familyseries and models, and it includes additional functions that may not be included in the target model.Accordingly, access to peripheral functions and I/O addresses that are not used in the target model isprohibited.
Reading or writing to these prohibited addresses may cause these unused peripheral functions to operateand lead to unexpected hardware or software problems.
Take particular care not to use word, long word, or similar access to read or write odd numbered bytes inthe prohibited areas.
Also, as the read values of prohibited addresses on the EVA product are different to the values on the targetFLASH and MASK products, do not use this data in software processing.
The functions corresponding to certain bits in single-byte registers may not be supported on particularmodels. However, reading or writing to these bits will not cause misoperation of the hardware. Also, as theEVA, FLASH, and MASK products are designed to have identical hardware and software operation, noparticular precautions are required.
Differences of memory space
If the memory size on the EVA product is different to the target FLASH or MASK product, please ensure
you confirm these differences enough when developing software.
A/D converter
The analog characteristics of the A/D converter analog input pins on the EVA product are slightly different
to the ones on the FLASH and MASK products. Please refer to the data sheet for the differences in external
analog input impedance enough before designing the external circuit.
Current consumption
• The current consumption of FLASH products is typically greater than for mask ROM products.
• For the details of current consumption, refer to "Electric characteristics" in data sheet.
• For detailed information on each package, see "1.6 Package Dimension".
• Operating voltage
- The operating voltage is different for each model.
- For the details, see the "data sheet".
Difference of RST/MOD pins
The RST and MOD pins are hysteresis inputs on the MASK products. A pull-down resistor is provided for
the MOD pin.
160
1.4 Block Diagram of TRUMPET Series
Figure 1.4-1 shows block diagram of all TRUMPET series.
Block Diagram of All TRUMPET Series
Figure 1.4-1 Block Diagram of All TRUMPET Series
P13/TRG0/ADTG
PB6/S06/TO01
PB7/S07/EC0
P63/S11/TO11
PB3/S03/PPG00
PB4/S04/PPG01
PB5/S05/TO00
P90/V3 to P93/V0
P94/C0 to P95/C1
PA0/COM0 to PA3/COM
P00/INT00 to P07/INT07
P10/UI0
P11/UO0
P12/UCK0
P14/PPG0
MOD
(P00/AN00 to P07/AN07)
P61/S09/PPG11
P60/S08/PPG10
P65/S13/SCK
PB0/S00 to PB2/S02
P66/S14/SOT
P67/S15/SIN
P62/S10/TO10
P64/S12/EC1
*:5V-product is Cpin terminal.VCCVSS
RST
X0,X1
X0A,X1A
PG0/(Cpin)*
Port Port
External interrupt
UART/SIO
16-bit PPG
8/16-bit PPG ch0
10-bit A/D
LIN UART
8/16-bit PPG ch1
8/16-bitcompound timer ch1
LCDC
F2MC-8FX CPU
8/16-bitcompound timer ch0
ROM
RAM
Interrupt control
Wild register
Reset control
Watch prescaler
Clock control
Watch counterInternal bus
161
CHAPTER 1 Description (48-pin/LCD)
1.5 Pin Assignment
Figure 1.5-1 shows pin assignment of TRUMPET series.
Pin Assignment of TRUMPET Series
Figure 1.5-1 Pin Assignment of TRUMPET Series
P60
/S08
/PP
G10
PB
7/S
07/E
C0
PB
6/S
06/T
O01
PB
5/S
05/T
O00
PB
4/S
04/P
PG
01P
B3/
S03
/PP
G00
PB
2/S
02P
B1/
S01
PB
0/S
00P
A3/
CO
M3
PA
2/C
OM
2P
A1/
CO
M1
47 46 45 44 43 42 41 40 39 38 37
S09/PPG11/P61 1 36 PA0/COM0S10/TO10/P62 2 35 P95/C1S11/TO11/P63 3 34 P94/C0S12/EC1/P64 4 33 P93/V0S13/SCK/P65 5 32 P92/V1S14/SOT/P66 6 31 P91/V2S15/SIN/P67 7 30 P90/V3
PPG0/P14 8 29 RSTTRG0/ADTG/P13 9 28 X0A
UCK0/P12 10 27 X1AUO0/P11 11 26 PG0/(Cpin)UI0/P10 12 25 Vcc
13 14 15 16 17 18 19 20 21 22 23 24
INT
07/A
N07
/P07
INT
06/A
N06
/P06
INT
05/A
N05
/P05
INT
04/A
N04
/P04
INT
03/A
N03
/P03
INT
02/A
N02
/P02
INT
01/A
N01
/P01
INT
00/A
N00
/P00
MO
DX
0X
1V
ss
48
TOP VIEW
162
1.6 Package Dimension
TRUMPET series is available in one type of package.The package dimension below is for reference only. Please consult about a formal version separately.
Package Dimension of FPT-48P-M13
Figure 1.6-1 Package Dimension of FPT-48P-M13
48-pin plastic QFP Lead pitch 0.80 mm
Package width × package length
10 × 10 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 2.35 mm MAX
Code(Reference)
P-QFP44-10×10-0.80
48-pin plastic QFP(FPT-48P-M13)
(FPT-48P-M13)
C 2003 FUJITSU LIMITED F48023S-c-3-4
(.013±.002)0.32±0.050.80(.031)
M0.20(.008)
0.10(.004)
(.007±.002)0.17±0.0610.00±0.20(.394±.008)SQ
13.10±0.40(.516±.016)SQ
1 1 2
13
2437
48
2536
INDEX
Details of "A" part
0.80±0.20(.031±.008)
0.88±0.15(.035±.006)
0.25(.010)
.008 –.008+.004
–0.20+0.10
0.20
(Stand off)
1.95+0.40–0.20
+.016–.008.077
(Mounting height)
0~8˚
"A"
0.10(.004)
*
Dimensions in mm (inches).Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.
163
CHAPTER 1 Description (48-pin/LCD)
1.7 Pin Description
Table 1.7-1 shows pin description. The alphabet in the "Circuit Type" column of Table 1.7-1 corresponds to the one in the "Classification" column of Table 1.8-1 .
Pin Description
Table 1.7-1 Pin Description (1 / 3)
Pin No. Pin name Circuit
type Function description
1 P61/S09/PPG11
M
General-purpose I/O port.These pins are also used for 8/16-bit PPG ch1 output (PPG11) and LCDC SEG output (S09).
2 P62/S10/T010 General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch1 output (TO10, TO11) and LCDC SEG output (S10, S11). 3 P63/S11/T011
4 P64/S12/EC1General-purpose I/O port.These pins are also used for 8/16-bit compound timer ch1 clock input (EC1) and LCDC SEG output (S12).
5 P65/S13/SCKGeneral-purpose I/O port.These pins are also used for LIN UART clock I/O (SCK) and LCDC SEG output (S13).
6 P66/S14/SOTGeneral-purpose I/O port.These pins are also used for LIN UART data output (SOT) and LCDC SEG output (S14).
7 P67/S15/SIN NGeneral-purpose I/O port.These pins are also used for LIN UART data input (SIN) and LCDC SEG output (S15).
8 P14/PPG0
H
General-purpose I/O port.These pins are also used for 16-bit PPG ch0 output.
9 P13/TRG0/ADTGGeneral-purpose I/O port.These pins are also used for 16-bit PPG ch0 trigger input (TRG0) and A/D trigger input (ADTG).
10 P12/UCK0General-purpose I/O port.These pins are also used for UART/SIO ch0 clock I/O.
11 P11/U00General-purpose I/O port.These pins are also used for UART/SIO ch0 data output.
12 P10/U10 GGeneral-purpose I/O port.These pins are also used for UART/SIO ch0 data input.
164
13 P07/INT07/AN07
DGeneral-purpose I/O port.These pins are also used for external interrupt input (INT00 to INT07) and A/D analog input (AN00 to AN07).
14 P06/INT06/AN06
15 P05/INT05/AN05
16 P04/INT04/AN04
17 P03/INT03/AN03
18 P02/INT02/AN02
19 P01/INT01/AN01
20 P00/INT00/AN00
21 MOD B Operation mode specification pin.
22 X0A Crystal oscillation pin.
23 X1
24 Vss - Power supply (GND) pin.
25 Vcc - Power supply pin.
26 PG0/(C pin) H General-purpose I/O port (at 3 V). Capacitance connection pin (at 5 V).
27 X1AA Crystal oscillation pin (32 kHz).
28 X0A
29 RST B’ Reset pin.
30 P90/V3
RGeneral-purpose I/O port.These pins are also used for power supply pin for LCDC driving.
31 P91/V2
32 P92/V1
33 P93/V0
34 P94/C0S
General-purpose I/O port.For products with LCDC voltage rise, these pins are dedicated capacitance connecting pins.35 P95/C1
36 PA0/COM0
MGeneral-purpose I/O port.These pins are also used for LCDC COM output.
37 PA1/COM1
38 PA2/COM2
39 PA3/COM3
Table 1.7-1 Pin Description (2 / 3)
Pin No. Pin name Circuit
type Function description
165
CHAPTER 1 Description (48-pin/LCD)
40 PB0/S00
M
General-purpose I/O port.These pins are also used for LCDC SEG output.
41 PB1/S01
42 PB2/S02
43 PB3/S03/PPG00 General-purpose I/O port.These pins are also used for LCDC SEG output (S03, S04) and 8/16-bit PPG ch0 output (PPG00, PPG01).44 PB4/S04/PPG01
45 PB5/S05/T000 General-purpose I/O port.These pins are also used for LCDC SEG output (S05, S06) and 8/16-bit compound timer ch0 output (TO00, TO01).46 PB6/S06/T001
47 PB7/S07/EC0General-purpose I/O port.These pins are also used for LCDC SEG output (S07) and 8/16-bit compound timer ch0 clock input (EC0).
48 P60/S08/PPG10 MGeneral-purpose I/O port.These pins are also used for 8/16-bit PPG ch1 output (PPG10) and LCDC SEG output (S08).
Table 1.7-1 Pin Description (3 / 3)
Pin No. Pin name Circuit
type Function description
166
1.8 I/O Circuit Type
Table 1.8-1 lists the I/O circuit types. Also, the alphabet in the "Classification" column of Table 1.8-1 corresponds to the one in the "Circuit Type" column of Table 1.7-1 .
I/O Circuit Type
Table 1.8-1 I/O Circuit Type (1 / 3)
Classi-fication
Circuit Remark
A
• Oscillation circuit
• Feedback resistance value
High-speed side: approx. 1 MΩ
Low-speed side: approx. 10 MΩ
• Only low-speed side oscillation of 3 V*
Feedback resistance: approx. 24 MΩ
Dumping resistance: approx. 144 kΩ
*: Excluding MB95FV100
B
• Input exclusive use
• Hysteresis input (only mask product)
• Pull-down resistance (only mask product)
B'
• Hysteresis input (only mask product)
• Reset output supported (only 5 V product)
D
• CMOS output
• Hysteresis input
• Analog input
• Pull-up control is available.
Standby control
X1 (X1A)
X0 (X0A)
Reset outputNch
Pch
Nch
R
A/D controlStandby control
External interrupt control
Analog input
Pull-up control
167
CHAPTER 1 Description (48-pin/LCD)
G
• CMOS output
• CMOS input
• Hysteresis input
• Pull-up control is available.
H
• CMOS output
• Hysteresis input
• Pull-up control is available.
M
• CMOS output
• LCD output
• Hysteresis input
N
• CMOS output
• LCD output
• CMOS input
• Hysteresis input
Table 1.8-1 I/O Circuit Type (2 / 3)
Classi-fication
Circuit Remark
Pch
Nch
Standby control
Pull-up controlR
Pch
Nch
Standby control
Pull-up control R
Pch
Nch
LCD output
LCD control
Standby control
Pch
Nch
LCD controlStandby control
LCD output
168
R
• CMOS output
• LCD power supply
• Hysteresis input
S
• CMOS output
• LCD power supply
• Hysteresis input
Table 1.8-1 I/O Circuit Type (3 / 3)
Classi-fication
Circuit Remark
Pch
Nch
LCD controlStandby control
LCD internal divisionresistance I/O
LCD voltage rise I/O
Pch
Nch
Standby control
LCD voltage rise I/O
169
CHAPTER 1 Description (48-pin/LCD)
170
CHAPTER 2Precautions when Handling
Devices
This chapter describes points to note when using this series.
2.1 Precautions when Handling Devices
171
CHAPTER 2 Precautions when Handling Devices
2.1 Precautions when Handling Devices
This section describes the precautions for the power supply voltage of the device and processing of pin.
Precautions when Handling Devices
Maximum rating voltage (preventing latch-up)
Ensure that the maximum voltage rating is never exceeded.
Latch-up may occur on CMOS ICs if voltage higher than Vcc or lower than Vss is applied to input oroutput pins other than the medium-and high-stand voltage pins or if voltage higher than the rating is appliedbetween Vcc and Vss.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.Ensure that the maximum ratings are never exceeded during operation.
When turning the analog power supply on or off, ensure that the analog power supply voltage (AVcc andAVR) and analog input voltages never exceed the digital power supply voltage (Vcc).
Supply voltage
Supply voltage should be stabilized.
Sudden changes in the power supply voltage may cause misoperation, even if the VCC supply voltage
remains within the guaranteed operating range.
The stability criteria are that the commercial frequency (50 to 60Hz) Vcc ripple fluctuation (P-P value)
must be less than 10% of the nominal Vcc voltage, and that the transient rate of change in the supply
voltage at times such as when the power is being turned on or off must be less than 0.1 V/ms.
Processing of unused input pin
An unused input pin may cause a malfunction if it is left open. Use pull-up or pull-down resistors for these
pins should be operated.
Processing for power supply pin of A/D converter
If not using the A/D converter, connect such that AVcc=Vcc, AVss=AVR=Vss.
External clock
Even if using an external clock, an oscillation stabilization wait time occurs after recovering from a power-
on reset, sub clock mode, and stop mode.
Precaution for noise to the external reset pin (RST)
An input of a reset pulse below the specified level to the external reset pin (RST) may cause malfunctions.
Be sure not to allow an input of a reset pulse below the specified level to the external reset pin (RST).
Vcc and Vss Pins
Multiple Vcc and Vss pins may be present.
Connect them to the same potential level.
172
CHAPTER 3CPU
This chapter describes functions and operations of the CPU.
3.1 Memory Space
3.2 Dedicated Registers
3.3 General-purpose Register
3.4 Interrupt
3.5 CPU Operation After A Reset (Mode Fetch Operation)
173
CHAPTER 3 CPU
3.1 Memory Space
The memory space on F2MC-8FX family is 64Kbytes, and this is divided into I/O, data, and program areas. The memory space includes special-purpose areas such as the general-purpose registers and vector table.
Memory Map
Figure 3.1-1 Memory Map
FFC0H
FFFFH
0000H
0100H
0200H
047FH
0080H
0F80H
0FFFH
I/O area
Register bank (general -purpose register area)
Data area
Extended directaddressing area
Extended I/O area
Program area
Vector table*
*: Vector table (reset, interrupt, and vector call instruction)
Directaddressing area
174
Configuration of Memory Space
I/O area (address: 0000H to 007FH)
• The space is assigned, for example, to control registers and data registers for internal peripheralfunctions.
• The I/O area is as accessible as the memory since the area is assigned to a part of the memory space.Also, direct addressing can be used for faster access than other addressing modes.
Extended I/O area (Address: 0F80H to 0FFFH)
• The space is assigned, for example, to control registers and data registers for internal peripheralfunctions.
• The extended I/O area is as accessible as the memory since the area is assigned to a part of the memoryspace.
Data area
• Static RAM is contained as the internal data area.
• The capacity of the internal RAM depends on the product.
• Direct addressing enables high-speed access to addresses 80H to FFH.
• 100H to 47FH is the extended direct addressing area. Direct addressing maps access to address range
80H to FFH onto this area based on the value set in the direct bank pointer.
• The area between 100H and 1FFH can be used for general-purpose registers.
Program area
• ROM is contained as the internal program area.
• The capacity of the internal ROM depends on the product.
• FFC0H to FFFFH is used for the vector table and similar.
Configuration of Memory Space For Specific Usage
General-purpose register area (address: 0100H to 1FFH)
• Contains the auxiliary registers used for 8-bit arithmetic or transfer operations.
• This area is allocated to part of the RAM area and can also be used as ordinary RAM.
• When the addresses are used as general-purpose registers, general-purpose register addressing enableshigh-speed access using short instructions.
See "3.2.1 Register Bank Pointer (RP)" and "3.3 General-purpose Register" for details.
Vector table area (address: FFC0H to FFFFH)
• Used as the vector table for vector call instructions, interrupts, and resets.
• The vector table are is assigned to the top of the ROM area and the address values in the table are set tothe entry addresses for the various handler routines.
Table 3.1-1 lists the vector table addresses that are referred for vector call instructions, interrupts, and resets
respectively.
See "3.4 Interrupt", "X.X Reset Operation", and "CALLV #vct" in "Appendix X.X Special Instructions"
for details.
175
CHAPTER 3 CPU
Note:
As IRQ22 and IRQ23 share addresses with CALLV #6 and CALLV #7, only use for one purpose at atime.
Table 3.1-1 Table of Vector
Vector Address in Vector Table
Interrupt Name Call Instruction High Low
Reset vectors FFFEH FFFFH
Mode data FFFCH FFFDH
IRQ0 - FFFAH FFFBH
IRQ1 - FFF8H FFF9H
IRQ2 - FFF6H FFF7H
IRQ3 - FFF4H FFF5H
IRQ4 - FFF2H FFF3H
IRQ5 - FFF0H FFF1H
IRQ6 - FFEEH FFEFH
IRQ7 - FFECH FFEDH
IRQ8 - FFEAH FFEBH
IRQ9 - FFE8H FFE9H
IRQ10 - FFE6H FFE7H
IRQ11 - FFE4H FFE5H
IRQ12 - FFE2H FFE3H
IRQ13 - FFE0H FFE1H
IRQ14 - FFDEH FFDFH
IRQ15 - FFDCH FFDDH
IRQ16 - FFDAH FFDBH
IRQ17 - FFD8H FFD9H
IRQ18 - FFD6H FFD7H
IRQ19 - FFD4H FFD5H
IRQ20 - FFD2H FFD3H
IRQ21 - FFD0H FFD1H
IRQ22 CALLV #7 FFCEH FFCFH
IRQ23 CALLV #6 FFCCH FFCDH
- CALLV #5 FFCAH FFCBH
- CALLV #4 FFC8H FFC9H
- CALLV #3 FFC6H FFC7H
- CALLV #2 FFC4H FFC5H
- CALLV #1 FFC2H FFC3H
- CALLV #0 FFC0H FFC1H
176
Location of 16-bit Data in Memory
Storage format for 16-bit data in RAM
When 16-bit data is written to memory, the upper byte of the data is stored at the lower address and the
lower byte at the next address. The same applies when reading.
Figure 3.1-2 shows the format of 16-bit data in memory.
Figure 3.1-2 Format of 16-bit Data in Memory
Storage format for a 16-bit operand
When the operand of an instruction specifies 16-bit data, the upper byte is located in the address following
the operation code (instruction) and the lower byte is located in the next address.
This equally applies to when the operand is a memory address and 16-bit immediate data.
Figure 3.1-3 shows the format of 16-bit data in instructions.
Figure 3.1-3 Format of 16-bit Data in Instruction
Storage format for 16-bit data on the stack
Data of 16-bit register pushed onto the stack by an interrupt or similar is also stored with the upper byte in
the location with the lower address value.
Memory MemoryBefore execution
After executionMOVW 0081H, A
A 1 2 3 4H 1 2 3 4HA
0080H
0081H
0082H
0083H
0080H
0081H
0082H
0083H
12H
34H
[Example] Extended address16-bit immediate data
Assemble
Extended address16-bit immediate data
MOV A, 5678HMOVW A, #1234H
;;
...XXX0H XX XXXXX2H 60 56 78XXX5H E4 12 34XXX8H XX...
;;
177
CHAPTER 3 CPU
3.2 Dedicated Registers
The special-purpose registers in the CPU consist of the program counter (PC), two arithmetic registers (A and T), three address pointers (IX, EP, and SP), and the program status (PS). All registers are 16-bit. The PS consists of the register bank pointer (RP), direct pointer (DP), and condition code register (CCR).
Configuration of Dedicated RegistersThe special-purpose registers in the CPU consist of seven 16-bit registers. Accumulator (A) and temporary
accumulator (T) can also use only for lower 8-bit.
Figure 3.2-1 shows the structure of the special-purpose registers.
Figure 3.2-1 Configuration of Dedicated Registers
Function of Dedicated Registers
Program counter (PC)
The program counter is a 16-bit counter which indicates the memory address of the instruction currently
being executed by the CPU. The contents of the program counter are updated by instruction execution,
interrupts, resets, and similar. The initial value during a reset is the read address for the mode data
(FFFDH).
Accumulator (A)
The accumulator is a 16-bit register for operation; it is used for a variety of arithmetic and transfer
operations of data in memory or data in other registers such as the temporary accumulator (T). The data in
the accumulator is treated either as word data (16-bit) or byte data (8-bit). Only the lower 8 bits of the
accumulator (AL) are used for byte-length arithmetic and transfer operations, and the upper 8 bits (AH) are
P S
P C
A
T
I X
E P
S P
Initial value
: Program counterIndicating the position stored current instruction
: Accumulator Storage registers such as the operations and forwarding temporarily
: Temporary accumulatorOperating between accumulators
: Index registerRegisters indicating the index address
: Extra pointerPointer indicating the memory address
16-bit
: Stack pointerIndicating the position of current stack
: Program statusRegister stored register bank pointer, direct bank pointer, and condition code
RP DP CCR
FFFDH
0030H
0000H
0000H
0000H
0000H
0000H
178
not used. The initial value after a reset is 0000H.
Temporary accumulator (T)
The temporary accumulator is a 16-bit auxiliary arithmetic register used to perform arithmetic operations
with the data in the accumulator (A). The data in the temporary accumulator is treated as word data for
word-length (16-bit) operations with the accumulator (A) and as byte data for byte-length (8-bit)
operations. Only the lower 8 bits of the temporary accumulator (TL) are used for byte-length operations
and the upper 8 bits (TH) are not used.
When a MOV instruction is used to transfer data to the accumulator (A), the previous contents of the
accumulator are automatically transferred to the temporary accumulator. When transferring byte-length
data, the upper 8 bits of the temporary accumulator (TH) remain unchanged. The initial value after a reset
is 0000H.
Index register (IX)
The index register is a 16-bit register used to store the index address. The index register is used with a
single byte offset (-128 to 127). The offset value is added to the index address to generate the memory
address for the data access. The initial value after a reset is 0000H.
Extra pointer (EP)
The extra pointer is a 16-bit register and the value of the register is used to indicate the memory address for
a data access. The initial value after a reset is 0000H.
Stack pointers (SP)
The stack pointer (SP) is a 16-bit register and stores an address that is used when an interrupt or subroutine
call occurs and by the stack push and pop instructions. During program execution, the value of the stack
pointer indicates the address of the most recent data to be pushed onto the stack. The initial value after a
reset is 0000H.
Program status (PS)
The program status is a 16-bit control register. The upper 8 bits contain the register bank pointer (RP) and
direct bank pointer (DP), and the lower 8 bits contain the condition code register (CCR).
In the upper 8 bits, the upper 5 bits contain the register bank pointer which is used to indicate the address of
the general-purpose register bank. The lower 3 bits contain the direct bank pointer which specifies the area
to which addresses in the range 0080H to 00FFH are mapped for instructions that use direct addressing.
The lower 8 bits contain the condition code register (CCR) which consists of flags that represent the state
of the CPU.
The instructions that access the program status are MOVW A,PS and MOVW PS,A. Also, the register bank
pointer (RP) and direct bank pointer (DP) can be read from or written to by accessing the register bank
pointer and direct bank pointer mirror address (0078H).
Furthermore, the condition code register (CCR) is part of the program status and cannot be accessed
independently.
Refer to the "F2MC-8FX Programming Manual" for details about how to use the special-purpose registers.
179
CHAPTER 3 CPU
3.2.1 Register Bank Pointer (RP)
The register bank pointer (RP) contained in bits 15 to 11 of the program status (PS) indicates the address of the general-purpose register bank that is currently in use and is converted to the actual address when general-purpose register addressing is used.
Configuration of Register Bank Pointer (RP)Figure 3.2-2 shows the structure of the register bank pointer.
Figure 3.2-2 Construction of Register Bank Pointer
The register bank pointer shows the address of register bank presently used. The relation between contents
of register bank pointer and actual address is the conversion rule as shown in Figure 3.2-3 .
Figure 3.2-3 Rule for Conversion of Actual Addresses in General-purpose Register Area
The register bank pointer specifies the memory block (register bank) used as general-purpose register in
RAM area. There are a total of 32 register banks. The current register bank is specified by setting a value
between 0 and 31 in the upper 5 bits of the register bank pointer. Each register bank consists of eight
general-purpose 8-bit registers which are selected by the lower 3 bits of the operation code.
The region between 0100H and 01FFH can be used as a general-purpose register area using the register
bank pointer. However, it should be note that there is a limit to the area that can be used depending on the
model. The initial value after a reset is 0000H.
Mirror Address For Register Bank Pointer And Direct Bank PointerThe write to program status (PS) by "MOVW A, PS" instruction, read of program status (PS) by "MOVW
PS, A" instruction and direct read/write by the access to mirror address 0078H of register bank pointer can
make the read/write of register bank pointer (RP) and direct bank pointer (DP).
R2 R1 DP2 IL1 N Z R3 DP1 DP0 IL0 V C R0 I R4 H PS
RP initial value
R P D P C C R
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00000B
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
R4 R3 R2 R1 R0 b2 b1 b0
RP upperLoweroperand code
Generating address
" 0 " " 0 " " 0 " " 0 " " 0 " " 0 " " 0 " " 1 "
180
3.2.2 Direct Bank Pointer (DP)
The direct bank pointer (DP) contained in bits 10 to 8 of the program status (PS) specifies the mapping area for instructions that use direct addressing in the range 0080H to 00FFH.
Structure of Direct Bank Pointer (DP)Figure 3.2-4 shows the structure of the direct bank pointer.
Figure 3.2-4 Structure of Direct Bank Pointer (DP)
The direct bank pointer (DP) specifies the mapping area for instructions that use direct addressing in the
range 0080H to 00FFH (16 instructions including MOV A, dir, etc.).
Table 3.2-1 shows the relationship between the direct bank pointer (DP) and mapped area, and Table 3.2-2
lists the direct addressing instructions.
*: Don’t Care
R2 R1 DP2 IL1 N Z R3 DP1 DP0 IL0 V C R0 I R4 H PS
DP initial value
R P D P C C R
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
000B
Table 3.2-1 Direct Bank Pointer and Mapping Area
Direct Bank Pointer (DP) [2:0] Specified Address Range Mapping Area
* 0000H to 007FH 0000H to 007FH(No mapping)
000B (Initial value)
0080H to 00FFH
0080H to 00FFH(No mapping)
001B 0100H to 017FH
010B 0180H to 01FFH
011B 0200H to 027FH
100B 0280H to 02FFH
101B 0300H to 037FH
110B 0380H to 03FFH
111B 0400H to 047FH
181
CHAPTER 3 CPU
Mirror Address for Register Bank Pointer And Direct Pointer AddressThe write to program status (PS) by "MOVW A, PS" instruction, read of program status (PS) by "MOVW
PS, A" instruction and direct read/write by the access to mirror address 0078H of register bank pointer can
make the read/write of register bank pointer (RP) and direct bank pointer (DP).
Table 3.2-2 Direct Addressing Instruction List
Instructions
CLRB dir:bit
SETB dir:bit
BBC dir:bit,rel
BBS dir:bit,rel
MOV A,dir
CMP A,dir
ADDC A,dir
SUBC A,dir
MOV dir,A
XOR A,dir
AND A,dir
OR A,dir
MOV dir,#imm
CMP dir,#imm
MOVW A,dir
MOVW dir,A
182
3.2.3 Condition Code Register (CCR)
The condition code register (CCR) contained in the lower 8 bits of the program status (PS) contains bits with information about the arithmetic result or transfer data (H, N, Z, V, and C), and bits used to control interrupt request handling (I, IL1, and IL0).
Structure of Condition Code Register (CCR)
Figure 3.2-5 Structure of Condition Code Register
Note:
The condition code register is part of the program status (PS) and therefore cannot be accessedindependently.
Bits That Indicate Information About Operation Result
Half carring flag (H)
Set to "1" when a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 occurs as the result of an
operation. Set to "0" otherwise. This flag is used for decimal-adjusted instructions. The flag cannot be used
for any other purpose.
Negative flag (N)
Set to "1" when the value of the most significant bit as the result of an operation is "1" and to "0" if the
value is "0".
Zero flag (Z)
Set to "1" when the result of an operation is "0" and set to "0" otherwise.
Overflow flag (V)
Indicates whether an overflow occurred as the result of an operation, where the operand used in the
R2 IL1 Z R3 DP1DP0 IL0 V C R0 IR4 HPS CCR initial value
Half carring flag
Interrupt enable flag
Interrupt level bit
Negative flag
Zero flag
Overflow flag
Carring flag
00110000BR1 DP2 N
RP DP CCR
bit15 bit0bit1bit2bit3bit4bit5bit6bit7bit8bit9bit10bit11bit12bit13bit14
183
CHAPTER 3 CPU
operation is treated as a twos complement integer. Set to "1" when overflow is occured and cleared to "0"
otherwise.
Carring flag (C)
Set to "1" when a carry from bit 7 or a borrow to bit 7 occurs as the result of an operation. Set to "0"
otherwise. In the case of a shift instruction, the flag is set to the shift-out value.
Figure 3.2-6 shows how the carry flag is modified by a shift instruction.
Figure 3.2-6 Change in Carry Flag Resulting from Shift Instruction
Bits Used to Control How Interrupts are Handled
Interrupt enable flag (I)
When this flag is set to "1", an interruption is enabled and the CPU accepts the interruption. When this flag
is set to "0", an interruption is disabled and the CPU accepts no interruption.
The initial value after a reset is "0" .
Normally set to "1" by the SETI instruction and cleared to "0" by the CLRI instruction.
Interrupt level bit (IL1,IL0)
This bit indicates the level of the interruption currently accepted by the CPU and is compared with the
value for the interruption level setting register (ILR0 to ILR5) that corresponds with the interruption
request (IRQ0 to IRQ23) of each peripheral function.
The CPU only processes interruption requests of interrupt levels defined by values smaller than the bit
value when the interruption-enable flag is enabled (CCR: I=1). Table 3.2-3 lists their level priorities. The
initial value after a reset is "1100B".
Reference:
The interrupt level bits (IL1, IL0) are usually 11B with the CPU not servicing an interrupt (with themain program running).For details of interrupt, refer to "3.4 Interrupt".
C C
Left shift (ROLC) Right shift (RORC)bit 7 bit 7bit 0 bit 0
Table 3.2-3 Interrupt Level
IL1 IL0 Interrupt Level High-Low
0 0 0 High
0 1 1
1 0 2
1 1 3 Low (no interrupt)
184
3.3 General-purpose Register
The general-purpose registers are memory blocks consisting of 8 x 8-bit registers per bank. Register bank pointer (RP) is used to specify the register bank.The function can use up to 32 register banks. Register banks are useful for interrupt processing, vector call processing, and subroutine calls.
Configuration of General-purpose Register• The general-purpose registers are 8-bit registers and are located in register banks in the general-purpose
register area (in RAM).
• Up to 32 banks can be used, where each bank consists of eight registers (R0 to R7)
• The register bank pointer (RP) specifies the register bank currently being used and the lower 3 bits ofthe opcode specify general-purpose register 0 (R0) to general-purpose register 7 (R7).
Figure 3.3-1 shows the structure of the register banks.
Figure 3.3-1 Construction of Register Bank
For more information on the general-purpose register area that can be used by each model, refer to
"Configuration of Memory Space For Specific Usage" in "3.1 Memory Space".
000
001
010
011
100
101
110
111
000
111
000
111RP " 11111--- B" )
RP = " 00001--- B" )
( RP = " 00000--- B ")
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
R 0
R 7
R 0
R 7
100H*
108H*
1F8H*
1FFH
Operand codelower 3-bit
Bank 0
32 banks (RAM area)Bank number is limited bythe usable RAM capacity. Bank 1
Bank 30
Bank 2
Bank 31
*: The heading address of register bank = 0100H + 8 × (upper 5 bits of RP)
:
:
:::
:::
:
: (
( =
185
CHAPTER 3 CPU
Features of General-purpose RegisterThe general-purpose registers have the following features.
• High-speed access to RAM using short instructions (general-purpose register addressing)
• This region is divided into register bank blocks to make it easy to backup the contents and separate byfunction.
As for the general register, a dedicated register bank is allocated to interrupt processing routine and vector
call (CALLV#0 to #7) processing routine respectively fixing. An example of how a short instruction is used
is "Use the 4th register bank for the 2nd interruption".
In the case of an interrupt, if the contents of the dedicated register bank corresponded to the interrupt
processing are never rewritten by other routines accidentally, you only need to specify the corresponding
register bank at the start of the interrupt handler routine to eff. As a result, the general register need not be
saved in the stack etc. , and the interruption is accepted at high speed without confusion.
For subroutine calls, in addition to protecting the general-purpose registers, the register banks can also be
used to implement reentrant programs (programs that do not use fixed addresses for variables and can be
entered more than once) usually created using index register (IX), etc.
Note:
To specify a register bank after rewriting the register bank pointer (RP) during an interruptionhandling routine, programming must ensure that no change is made to the interruption level bit(CCR: IL1, IL0) value of the condition code register. That is, either read the interrupt level bits prior towriting to RP, or write directly to the RP mirror address (0078H).
186
3.4 Interrupt
In the F2MC-8FX family, there are 24 interruption demand input corresponding to the function in the surrounding, and the interruption level can be set independently individually. When an interrupt request occurs in a peripheral function, the request is output to the interrupt controller. The interrupt controller checks the interrupt level for that interrupt request and then passes the interrupt to the CPU. The CPU handles an interrupt according to the interrupt acceptance status. Interrupt requests also recover the device from standby modes and return to RUN mode.
Interrupt Request from Peripheral FunctionTable 3.4-1 lists the interrupt requests and interrupt vectors for interrupt request of each peripheral
function. When an interrupt is received, the entry address of the interrupt handler routine is retrieved from
the interrupt vector table address for the interrupt request, and execution branches to the interrupt handler
routine.
The priority for each interrupt request can be set to one of four levels using the interrupt level setting
registers (ILR0, 1, 2, 3, 4, and 5).
If another interrupt request with the same or lower level occurs during execution of the interrupt handler
routine, the interrupt is normally processed after the current interrupt handler routine completes. Moreover,
IRQ0 becomes the highest as for the priority level when the interruption demand set at the same level is
generated at the same time.
187
CHAPTER 3 CPU
See "x.x.x Interrupt List" for a list of the factors of interrupts.
Table 3.4-1 Interrupt Request and Interrupt Vector
Interrupt RequestAddress in Vector Table Bit Name of Interrupt
Level Setting RegisterPriority Order of Same Level
(At Simultaneous Occurrence)High Low
IRQ0 FFFAH FFFBH L00 [1:0] High
IRQ1 FFF8H FFF9H L01 [1:0]
IRQ2 FFF6H FFF7H L02 [1:0]
IRQ3 FFF4H FFF5H L03 [1:0]
IRQ4 FFF2H FFF3H L04 [1:0]
IRQ5 FFF0H FFF1H L05 [1:0]
IRQ6 FFEEH FFEFH L06 [1:0]
IRQ7 FFECH FFEDH L07 [1:0]
IRQ8 FFEAH FFEBH L08 [1:0]
IRQ9 FFE8H FFE9H L09 [1:0]
IRQ10 FFE6H FFE7H L10 [1:0]
IRQ11 FFE4H FFE5H L11 [1:0]
IRQ12 FFE2H FFE3H L12 [1:0]
IRQ13 FFE0H FFE1H L13 [1:0]
IRQ14 FFDEH FFDFH L14 [1:0]
IRQ15 FFDCH FFDDH L15 [1:0]
IRQ16 FFDAH FFDBH L16 [1:0]
IRQ17 FFD8H FFD9H L17 [1:0]
IRQ18 FFD6H FFD7H L18 [1:0]
IRQ19 FFD4H FFD5H L19 [1:0]
IRQ20 FFD2H FFD3H L20 [1:0]
IRQ21 FFD0H FFD1H L21 [1:0]
IRQ22 FFCEH FFCFH L22 [1:0]
IRQ23 FFCCH FFCDH L23 [1:0] Low
188
3.4.1 Interrupt Level Setting Registers (ILR0 to ILR5)
The interrupt level setting registers (ILR0 to ILR5) contain 24 2-bit settings each of which corresponds to an interrupt request from a peripheral functions. Each interruption level is set to these two-bit data (interruption level setting bit).
Configuration of Interrupt Level Setting Register (ILR0 to ILR5)
Figure 3.4-1 Configuration of Interrupt Level Setting Register
The interrupt level setting registers contain separate 2-bit settings for each interrupt request. The value of
the interruption level setting bit set to these registers is strength of the interrupt processing (interruption
level 0 to 3).
The interrupt level setting bits are compared with the interrupt level bits in the condition code register
(CCR:IL1, IL0).
When the interruption level is set to "3", the CPU accepts no interruption request.
Table 3.4-2 lists the relationship between the interrupt level setting bits and the interrupt level.
Reference:
Interruption level bit (CCR:IL1,IL0) of the condition code register is usually "11B" while the mainprogram is executed.
L03 [ 1: 0 ] L 02 [ 1: 0 ] L 01 [ 1: 0 ] L 00 [ 1: 0 ] 11111111B ILR0 00079 R/W
L07 [ 1: 0 ] L 06 [ 1: 0 ] L 05 [ 1: 0 ] L 04 [ 1: 0 ] 11111111B ILR1 0007AH R/W
L11 [ 1: 0 ] L 10 [ 1: 0 ] L 09 [ 1: 0 ] L 08 [ 1: 0 ] 11111111B ILR2 0007BH R/W
L15 [ 1: 0 ] L 14 [ 1: 0 ] L 13 [ 1: 0 ] L 12 [ 1: 0 ] 11111111B ILR3 0007C R/W
L19 [ 1: 0 ] L 18 [ 1: 0 ] L 17 [ 1: 0 ] L 16 [ 1: 0 ] 11111111B ILR4 0007DH R/W
L23 [ 1: 0 ] L 22 [ 1: 0 ] L 21 [ 1: 0 ] L20 [ 1: 0 ] 11111111B ILR5 0007EH R/W
Register Address Initial valuebit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
H
H
Table 3.4-2 Relationship between Interrupt Level and Interrupt Level Setting Bits
LXX LXX Interrupt Request Level High-Low
0 0 0 High
0 1 1
1 0 2
1 1 3 Low (no interrupt)
X:0 to 23: Corresponding interrupt number
189
CHAPTER 3 CPU
3.4.2 Interrupt Processing
When an interrupt request is generated by a peripheral function, the interrupt controller passes the interrupt level to the CPU. When the CPU is in a state where it can accept interruption, it temporarily halts the program currently being executed and executes an interruption handling routine.
Interrupt Processing The procedure of the interrupt operation is done in order to the following; the generation of interrupt factorsfor the peripheral function, the execution of the main program, the set of the interruption demand flag bit,the judgment of interrupt request enable bit, the interrupt level (ILR0 to ILR5, CCR:IL1, and IL0) and thedemand of the same level simultaneously, and the judgment interrupt permission flags (CCR:I).
Figure 3.4-2 shows the sequence of interrupt operation.
Figure 3.4-2 Interrupt Processing
START
PC
AND
CPU
RAM
I IL
(1)
(2)
(3)
(4) (5)
(6)
(7)
(3)
(4)
(5)
(6)
(7)
NO
NO
NO
NO YES
YES
YES
YES
Inte
rnal
dat
a bu
s
Peripheral initialization
Is peripheral interrupt existant?
Is enabled peripheral interrupt
request output ?
Interrupt request flag
Interrupt request enabled
Each peripheral
Condition code register (CCR)
Check Comparator
Stop releasedSleep releasedTimebase time/ clock mode released
Interrupt controller
Leve
l co
mpa
rato
r
Judging priority order of interrupt and transferring corresponding level to CPU
Comparing corresponding level to IL bit in PS
Execution of main program
Recovering PC and PS
Is corresponding level
stronger than IL?
I flag = 1?
Interrupt processing routine
Clear interrupt request
Execution of interrupt processing
Save PC and PS to stack
Interrupt vector
Update of IL in PSRETI
190
(1) All interrupt requests are disabled after a reset. In the initialization program for the peripheral functions,
initialize those peripheral functions that generate interrupt and set the interrupt level in the appropriate
interrupt level setting register (ILR0 to ILR5) before starting operation. The interrupt level can be set to
0, 1, 2, or 3. Level 0 is given to priority most, and level 1 becomes the following strength. Setting level
3 specifies that the interrupt from the corresponding peripheral function is disabled.
(2) Execute the main program (or the interrupt handler routine in the case of multiple interrupts).
(3) When an interrupt is triggered in a peripheral function, the interrupt request flag bit in the peripheral
function is set to "1". At this time, if the interrupt request enable bit in the peripheral function is set to
enable, the interrupt request is then output to the interrupt controller.
(4) The interrupt controller always monitors interrupt requests from individual peripheral resources and
transfers the highest priority interrupt level, to the CPU, among the interrupt levels of the currently
generated interrupt requests. The relative priority if another request with the same interrupt level occurs
simultaneously is also determined at this time.
(5) If the received interrupt level checks the content of interrupt permission flag (CCR:I) when priority is
stronger than the levels set to interruption level bit (CCR:IL1,IL0) of the condition code register (The
level is low), and it becomes interrupt permission (CCR:I=1), CPU accepts the interrupt.
(6) After the content of program counter (PC) and program status (PS) is saved in the stack, the first
address of the interrupt processing routine is taken from the corresponding interruption vector table, and
it changes to the value at the interruption level by which the value of interruption level bit
(CCR:IL1,IL0) of the condition code register is accepted, CPU begins the execution of the interrupt
processing routine.
(7) Finally, CPU uses the RETI instruction to restore the program counter (PC) and program status (PS)
from the stack and continues execution from the next instruction after the instruction executed prior to
the interrupt.
Note:
The interrupt request flag bits in the peripheral functions are not automatically cleared to "0" after aninterrupt request is accepted. Accordingly, the bits must be cleared to "0" by the program in theinterrupt handler routine (typically by writing "0" to the interrupt request flag bit).
An interrupt causes the device to recover from standby mode (low power consumption mode). See "4.10
Operation of Standby Mode (Low-power Consumption Mode)" for details.
191
CHAPTER 3 CPU
3.4.3 Multiple Interrupts
Multiple interrupts are performed setting a different interrupt level to interrupt level setting register (ILR0 to ILR5) for two or more interrupt demands from the function in the surrounding.
Multiple InterruptsIf an interruption request of higher priority interrupt level occurs while an interruption handling routine is
being executed, the CPU halts interruption processing currently underway and accepts the interruption
request of higher priority. The interrupt level can be set to 0 to 3. If it is set to 3, the CPU will accept no
interrupt request.
[Example: Multiple interrupts]
In case higher priority is given to external interruptions over timer interruptions as an example multiple
interruption processing, set the timer interruption to Level 2 and the external interruption to Level 1. If an
external interruption occurs while a timer interruption is being processed when this setting is used, the
processing as shown in Figure 3.4-3 takes place.
Figure 3.4-3 Example of Multiple Interrupts
• While a timer interruption is being processed, the interruption level bit (CCR: IL1, IL0) value of thecondition code register becomes equal to the value of the interruption level setting register (ILR0 toILR5) for the timer interruption (2 in the example). If an interrupt request with a higher priority interruptlevel occurs (level 1 for example), the higher priority interrupt is processed first.
• To temporarily disable multiple interruptions while a timer interruption is being processed, set theinterruption-enable flag in the condition code register to interruption disable (CCR: I=0) or set theinterruption level bit (CCR: IL1, IL0) to "00B".
• Executing the interruption return instruction (RETI) after the interruption processing restores theprogram counter (PC) and program status (PS) values saved in a stack and the processing of theinterrupted program is resumed. Restoring the program status (PS) also restores the condition coderegister (CCR) to its value prior to the interrupt.
Main programTimer interrupt
processingExternal interrupt
processing
Peripheralinitialization
Timer interrupt generated
Main restart
Interrupt level 2 Interrupt level 1
Suspend
Restart
External interruptgenerated
Timer interruptprocessingTimer interruptrecovery
External interruptprocessing
External interruptrecovery
(1)
(2)
(8)
(3)
(6)
(7)
(4)
(5)
(CCR:IL1,IL0=10B) (CCR:IL1,IL0=01B)
192
3.4.4 Interrupt Processing Time
The time between an interrupt request being generated and control being passed to the interrupt handler routine is equal to the sum of the time until the currently executing instruction completes and the interrupt handling time (time required to initiate interrupt). This time consists of a maximum of 26 machine clock cycles.
Interrupt Processing TimeThe interruption request sample wait time and interruption handling time intervene between the occurrence
and acceptance of an interruption request and the execution of a interruption handling routine.
Interrupt request sampling delay time
Whether an interruption request has occurred is determined through the sampling of the interruption request
during the last cycle of each instruction. The maximum length of this delay occurs if the interrupt request is
generated immediately after the instruction with the most execution cycles (the DIVU instruction with 17
machine clock cycles) starts executing.
Interrupt handling time
After receiving an interrupt, the CPU requires 9 machine clock cycles to perform the following interrupt
processing setup.
• Backup the program counter (PC) and program status (PS).
• Set entry address (interrupt vector) of interrupt handler routine in PC.
• Updating the interrupt level bits in the program status (PS) (PS:CCR:IL1, IL0)
Figure 3.4-4 Interrupt Processing Time
When the interrupt demand is generated immediately after beginning of execution of the DIVU instruction
with the longest execution cycle (17 machine clock), it takes the interrupt processing time of 17+9=26
machine clock. However, if you do not use the DIVU or MULU instructions in your program, the
maximum interrupt processing time becomes 7 + 9 = 16 machine clock cycles.
The machine clock changes depending on the clock mode and main clock speed switching (gear function).
For the details, Refer to "Chapter xx clock control block".
Operation of CPU
Interrupt wait time
Normal instruction execution Interrupt handling Interrupt processing
routine
Interrupt request generated
Interrupt requestsampling wait time
Interrupt handling time(9 machine cycle)
: Instruction last cycle. Instruction request is sampled here.
193
CHAPTER 3 CPU
3.4.5 Stack Operation During Interrupt Handling
This explains how registers are saved and restored during interrupt processing.
Stack Operation at Start of Interrupt ProcessingOnce the CPU accepts an interruption, it automatically saves the current program counter (PC) and
program status (PS) values into a stack.
Figure 3.4-5 shows how the stack is used at the start of interrupt processing.
Figure 3.4-5 Stack Operation at Start of Interrupt Processing
Stack Operation when Returning From InterruptWhen the interrupt return instruction (RETI) is executed to end interrupt processing, the program status
(PS) and then the program counter (PC) are restored from the stack (this is the opposite of the order in
which they were saved to the stack when interrupt processing started. This restores PS and PC to their
states prior to starting interrupt processing.
Note:
As the accumulator (A) and temporary accumulator (T) are not saved on the stack automatically, usethe PUSHW and POPW instructions to save and restore A and T on the stack.
SP
PC
PS
PC
PS
SP
PC
PS
Immediate before instruction
Immediate after instructionAddress Memory Address Memory
0870H
E000H
0280H
X XH
X XH
X XH
X XH
X XH
X XH
027CH
027DH
027EH
027FH
0280H
0281H
027CH
027DH
027EH
027FH
0280H
0281H
0870H
E000H
027CH
X XH
X XH
0 8H
7 0H
E 0H
0 0H
194
3.4.6 Interrupt Handling Stack Area
The stack area in RAM is used when interrupt processing is executed. The stack pointer (SP) contains the top address of the stack area.
Interrupt Handling Stack AreaThe stack area is also used to save and restore the program counter when subroutine call (CALL) or vector
call (CALLV) instructions are executed and to temporarily save and restore the registers via the PUSHW
and POPW instructions.
• The stack area is located in RAM together with the data area.
• It is recommended that you initialize the stack pointer (SP) to the maximum RAM address and allocatedata areas starting from the minimum RAM address.
Figure 3.4-6 shows an example of setting the stack area.
Figure 3.4-6 Setting Example of Interrupt Handling Stack Area
New data is placed on the stack area by interrupts, subroutine calls, and the PUSHW instruction at
progressively lower addresses. Data is released from the stack by return instructions (RETI and RET) and
the POPW instruction at progressively higher address. If multiple interrupts or subroutine calls occur
simultaneously, the value of the stack area address decreases. Take care that the stack area does not overlap
the general-purpose register areas or other areas used to store data.
I / O
ROM
ROM
Data area
Stack area
General-purpose register
Access prohibited
Recommended setting value of SP(when the maximum value of RAM address is 0280H)
0000H
0080H
0100H
0200H
0280H
FFFFH
195
CHAPTER 3 CPU
3.5 CPU Operation After A Reset (Mode Fetch Operation)
After a reset is released, the CPU reads the mode data and reset vector from internal ROM.
Mode FetchAfter a reset is released, the CPU reads the mode data and reset vector from internal ROM. This operation
is called the mode fetch.
Mode data
After a reset is released, the CPU first fetches the mode data.
The address of the mode data is fixed at FFFDH. (Address FFFCH is not used.) Be sure to set 00H into the
mode data in internal ROM to select single-chip mode.
Figure 3.5-1 Setting Mode Data
Reset vectors
After the mode data, the CPU fetches the reset vector. The reset vector specifies the start address for
instruction execution.
The address of the reset vector is fixed at FFFEH (upper byte) and FFFFH (lower byte). Set the start address
for instruction execution at this address.
Mode pin (MOD)
Be sure to set the mode pin (MOD) to "VSS". This setting specifies reading the mode data and reset vector
from internal ROM after a reset.
Address
Data Operation
Selection of single-chip mode
Reserved. Setting is disabled. Other than 00H
00H
FFFFH
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Table 3.5-1 Setting of Mode Pins
Pin State MOD Description
VSS Read mode data and reset vector from internal ROM.
VCC Setting disabled
196
CHAPTER 4Clock Control Block
This chapter describes the functionality and behavior of the clock controller.
4.1 Overview of Clock Controller
4.2 Oscillation Stabilization Wait Time
4.3 System Clock Control Register (SYCC)
4.4 PLL Control Register (PLLC)
4.5 Oscillation Stabilization Standby Time Assignment Register (WATR)
4.6 Standby Control Register (STBC)
4.7 Reset Source Register (RSRR)
4.8 Reset Operation
4.9 Clock Mode Operation
4.10 Operation of Standby Mode (Low-power Consumption Mode)
4.11 Clock Oscillation Circuit
197
CHAPTER 4 Clock Control Block
4.1 Overview of Clock Controller
F2MC-8FX family has a built-in clock controller that optimally controls power consumption. Depending on the model, there are products with two clock systems, which support both a main oscillation clock and sub oscillation clock, and products with one clock system, which support only a main oscillation clock. The clock controller controls clock oscillation authorization/stopping, authorization/stop of clock supply to internal circuits, clock source selection, and PLL, and division circuit.
Overview of Clock ControllerThe clock controller controls clock oscillation authorization/stopping, authorization/stop of clock supply to
internal circuits, clock source selection, and PLL and division circuit.
Products with two clock system have four source clocks: a main clock, which is the main oscillation clock
divided by two, a sub clock, which is the sub oscillation clock divided by two, a main PLL clock, which is
the main oscillation clock multiplied by the PLL multiplier and a sub PLL clock, which is the sub
oscillation clock multiplied by the PLL multiplier.
Products with one clock system have two source clocks: a main clock, which is the main oscillation clock
divided by two; and a main PLL clock, which is the main oscillation clock multiplied by the PLL
multiplier.
The clock controller assigns the clock mode, assigns standby mode, and controls the internal clock in
accordance with reset behavior. The internal operation clock is selected via clock mode, and the
authorization/stop of clock oscillation and supply is selected via standby mode.
It is possible to select the optimum power consumption and functions via a combination of clock mode and
standby mode.
Overview of Clock ModeSelect the machine clock, which is the operating clock for the CPU and almost all peripheral circuits, via
clock mode.
Table 4.1-1 shows the relationship between clock mode and the machine clock.
In any of the clock modes, a division of the selected clock can also be performed. Additionally, in modes
using a PLL clock, a multiplier for the clock frequency can also be set.
Table 4.1-1 Clock Mode and Machine Mode Selection
Clock Mode Machine clock
Main clock mode The machine clock is generated from the main clock (main oscillation clock divided by 2).
Main PLL clock mode The machine clock is generated from the main PLL clock (PLL multiplication of main oscillation clock).
Sub clock mode(2 clock system products only)
The machine clock is generated from the sub clock (sub oscillation clock divided by 2).
Sub PLL clock mode(2 clock system products only)
The machine clock is generated from the sub PLL clock (PLL multiplication of sub oscillation clock).
198
Note that the peripheral functions listed in the table below generate the same interval time, regardless of the
clock mode, division, and PLL multiplier settings. Table 4.1-2 shows the peripheral functions not affected
by the clock mode.
For some peripheral functions other than the ones listed above, it may be possible to select a timebase timer
as a count clock or clock prescaler output. Please check the description of each peripheral function for
details.
Standby ModeThe authorization/stop of clock oscillation and of internal clock supply can be selected via standby mode.
With the exception of timebase timer mode and watch mode, the clock mode settings can be performed
independently.
Table 4.1-3 shows the relationship between standby mode and clock supply status.
Table 4.1-2 Peripheral Functions whose Interval is not Affected by Clock Mode
Resource Operation clock
Timebase timer Main clock (21/FCH: main oscillation clock divided by 2)
Watchdog timerMain clock (during timebase timer output selection)Sub clock (during clock prescaler output selection) (2-clock system products only)
Clock prescaler(2 clock system products only)
Sub clock (21/FCL: sub oscillation clock divided by 2)
Clock counter(2 clock system products only)
Sub clock (clock pre-scalar output)
Table 4.1-3 Standby Mode and Clock Supply Status
Standby Mode Clock supply status
Sleep modeStops clock supply to CPU and watchdog timer. As a result, the CPU stops operation, but other peripheral functions continue operating.
Timebase timer mode
Clocks are only supplied to the timebase timer, clock prescaler, and clock counter. Clock supply to other circuits is stopped. As a result, all functions of other than the timebase timer, clock prescaler, clock counter, external interrupt, and low-voltage detection reset (option) are stopped. Timebase timer mode is only the standby mode for main clock mode and PLL clock mode.
Watch mode(2 clock system products only)
The main clock oscillation stops, and clocks are only supplied to the clock pre-scalar, and clock counter. Clock supply to other circuits is stopped. As a result, all functions of the clock pre-scalar, clock counter, external interrupt, and low-voltage detection reset (option) are stopped. Clock mode is only the standby mode for sub clock mode and sub PLL clock mode.
Stop modeMain clock oscillation and sub clock oscillation stop, and supply of all clocks stops. As a result, all functions of other than the external interrupt and low-voltage detection reset (option) are stopped.
199
CHAPTER 4 Clock Control Block
Combinations of Clock Mode and Standby ModeTable 4.1-4 shows the relationship between combinations of clock mode and standby mode and internal
circuit operating status.
*1: Operates if "1" is assigned to the main PLL clock oscillation authorization bit of the PLL control register (PLLC:MPEN).
*2: Stops if "1" is assigned to the sub clock oscillation stop bit of the system control register (SYCC:SUBS). *3: Operates if "1" is assigned to the sub PLL clock oscillation authorization bit of the PLL control register
(PLLC:SPEN).
Table 4.1-4 Combination of Standby Mode, Clock Mode and Internal Operation Status
Function
RUN SleepTimebase
timer
Clock(Dual-line
model)Stop
Main clock mode
Main PLLclock mode
Sub clock mode(Dual-
line model)
Sub PLLclock mode
(Dual-line model)
Main clock mode
Main PLLclock mode
Sub clock mode(Dual-
line model)
Sub PLLclock mode
(Dual-line model)
Main clock mode
Main PLLclock mode
Sub clock mode(Dual-
line model)
Sub PLLclock mode
(Dual-line model)
Main (PLL) clock mode
Sub (PLL) clock mode
(Dual-line model)
Main clock Operation Stops Operation Stops Operation Stops Stops Stops
Main PLL clock Stops*1 Operation Stops Stops*1 Operation Stops Stops*1 Stops Stops Stops
Sub clock Operation*2 Operation Operation*2 Operation Operation*2 Operation Operation*2 Stops
Sub PLL clock Stops*3 Stops*3 Operation Stops*3 Stops*3 Operation Stops*3 Stops*3 Operation Stops*3 Stops
CPU Operation Operation Stops Stops Stops Stops Stops Stops
ROMOperation Operation Value storage Value storage Value storage Value storage Value storage
Value storageRAM
I/O port Operation Operation Output storage Output storage Output storage Output storageOutput storage/
Hi-Z
Output storage/
Hi-Z
Timebase timer Operation Stops Operation Stops Operation Stops Stops Stops
Clock prescaler
Operation*2 Operation Operation*2 Operation Operation*2 Operation Operation*2 Stops
Clock counter Operation*2 Operation Operation*2 Operation Operation*2 Operation Operation*2 Stops
External interrupt Operation Operation Operation Operation Operation Operation Operation Operation
Watchdog timer Operation Operation Stops Stops Stops Stops Stops Stops
Low-voltage detection reset
Operation Operation Operation Operation Operation Operation Operation Operation
Other peripheral functions
Operation Operation Operation Operation Stops Stops Stops Stops
200
4.2 Oscillation Stabilization Wait Time
The oscillation stabilization standby time is the time between when the oscillation circuit is stopped, and the time when the oscillator is stably oscillating at a fixed frequency. The clock controller obtains the oscillation stabilization standby time by counting a set number of oscillation clock cycles, and controls the supply of clocks to internal circuits.
Oscillation Stabilization Wait TimeThe clock controller obtains the oscillation stabilization standby time immediately after the initiation of
oscillation by counting a set number of oscillation clock cycles, and controls the supply of clocks to
internal circuits.
Therefore, the clock control part changes to the following state after automatically waiting for the passage
of the main clock or a sub-clock at the oscillation stability waiting time when the state transition demand
for the oscillation to begin from the oscillation halt condition is generated by the change in the clock mode
with the interrupt at the standby mode and reset in addition to turning on the power supply and software.
Figure 4.2-1 shows the oscillation behavior immediately after the start of oscillation.
Figure 4.2-1 Operation of Oscillator Immediately after Oscillation Starts
The main clock oscillation stabilization standby time is counted using the timebase timer. The sub clock
oscillation stabilization standby time is counted using the clock prescaler. The count can be set via the
oscillation stabilization standby time assignment register (WATR). Set it in keeping with the oscillator
characteristics.
In the case of a power-on reset, the oscillation stabilization standby time is locked to the initial value.
However, for mask products, the initial oscillation stabilization standby time value can be specified upon
ROM order. Table 4.2-1 shows the length of the oscillation stabilization standby time.
X1
Oscillataion start
Oscillation time of oscillator
Oscillation stabilization waiting time
Oscillation stabilization
Nomal operationRecovery or reset operation from stop mode
Table 4.2-1 Oscillation Stabilization Wait Time
Clock Factor Oscillation Stabilization Wait Time
Main clockPower-on reset
Initial value: 214/FCH, FCH is the main oscillation clock frequency
(Mask products specified upon ROM order)
Other than power-on reset Register setting value (WATR:MWT3,MWT2,MWT1,MWT0)
Sub clock(Products with two clock systems)
Power-on resetInitial value: 215/FCL, FCL is the sub oscillation clock frequency
(Mask products specified upon ROM order)
Other than power-on reset Register setting value (WATR:SWT3,SWT2,SWT1,SWT0)
201
CHAPTER 4 Clock Control Block
PLL Clock Oscillation Stabilization Wait TimeAs with the oscillation stabilization wait time of the oscillator, the clock controller automatically waits for
the PLL oscillation stabilization standby time to elapse after a request for transition from PLL oscillation
stopped state to oscillation start is generated via an interrupt at the standby mode and a change of clock
mode by software. The PLL clocks oscillation stabilization standby time also changes according to the PLL
startup timing, as shown in Table 4.2-2 .
Oscillation Stabilization Standby Time and Clock Mode/standby Mode TransitionThe clock controller automatically waits for the oscillation stabilization standby time to elapse as needed
when state-transition requests are received, but depending on the state transition, does not always wait for
the oscillation stabilization standby time.
See "4.9 Clock Mode Operation" and "4.10 Operation of Standby Mode (Low-power Consumption
Mode)" for details about state transitions.
Table 4.2-2 PLL Oscillation Stabilization Wait Time
PLL Oscillation Stabilization Wait Time
RemarkMinimum
timeMaximum
time
Main PLL clock 211/FCH x 2 211/FCH x 3The time between 2 count (Min) and 3 count (Max) for 211/FCH is the
stabilization standby time. FCH is the main oscillation clock frequency.
Sub PLL clock (Products with two clock systems)
28/FCL x 2 28/FCL x 3The time between 2 count (Min) and 3 count (Max) for 28/FCL is the
stabilization standby time. FCL is the sub oscillation clock frequency.
202
Clock Controller Block DiagramThis figure is a block diagram of the clock controller.
PLL control register (PLLC) Standby control register (STBC)
System clock selector
Prescaler
No division
Divide by 4
Divide by 8
Divide by 16
Sub clock oscillation
circuit
Sub clock control
Main clock oscillation
circuit
Divide by 2
Sub PLLoscillation circuit
Divide by 2
Main PLLoscillation circuit
Main clock control
Oscillationstabilizationwait circuit
Source clock selection
control circuit
Clockcontrolcircuit
Stop
SleepClock for clock prescalerWatch or timebase timer
Supply to CPU
Supply to peripheralfunction
Clock for timebase timer
From timebase timer
From clock prescaler
Oscillation stabilization wait time setting register (WATR)System clock control register (SYCC)
Main oscillator clockSub oscillator clockMain clockSub clock
Main PLL clockSub PLL clockSource clockMachine clock
MPEN MPMC1 MPMC0 MPRDY SPEN SPMC1 SPMC0 SPRDY STP SLP SPL SRST TMD
FCL
FCH
(FCH)(FCL)
(MCLK)
SCM1 SCM0 SCS1 SCS0 SRDY SUBS DIV1 DIV0 SWT3 SWT2 SWT1 SWT0 MWT3 MWT2 MWT1 MWT0
215
214
21
21FCH
FCL FCL
FCH
(1)
(2)
(3)
(4)
(5)
(6)(7)
(8)
(1)(2)(3)(4)
(5)(6)(7)(8)
::::
::::
203
CHAPTER 4 Clock Control Block
The clock controller is made up of the following blocks.
Main clock oscillation circuit
This is the oscillation circuit in the main clock
Sub clock oscillation circuit (2-system products)
This is the sub clock oscillation circuit.
Main PLL oscillation circuit
This is the main PLL oscillation circuit.
Sub PLL oscillation circuit (2-system products)
This is the sub PLL clock oscillation circuit.
System clock selector
Select one of the four source clocks for main clock, sub clock, main PLL clock, and sub PLL clock inaccordance with the clock mode. The clock created via pre-scalar division of the selected source clock iscalled the machine clock. It is supplied to the clock control circuit.
Clock controller circuit
The supply of the machine clock to the CPU and each peripheral function is controlled in accordance withstandby mode or oscillation stabilization standby time.
Oscillation stabilization standby circuit
The oscillation stabilization standby time signal for each clock is output from the 14 main-clock oscillationstabilization signals created by the timebase timer and the 15 sub-clock oscillation stabilization signalscreated by the clock prescaler.
System clock control register (SYCC)
Controls current clock mode display, clock mode selection, selection of machine clock division ratio, andsub-clock oscillation in main-clock and main PLL clock mode.
Standby control register (STBC)
Controls transition from RUN state to standby mode, the pin status assignment when in stop mode,timebase timer mode and watch mode, and the generation of software resets.
PLL control register (PLLC)
This register indicates the main PLL clock and sub PLL clock oscillation, stop control, multiplierassignment, and PLL oscillation stability state.
Oscillation stabilization standby time setting register (WATR)
This register sets the main clock and sub clock oscillation stabilization standby time.
Reset source register (RSRR) (block diagram is abbreviated).
This register shows the cause of a reset.
204
4.3 System Clock Control Register (SYCC)
The system clock control register (SYCC) switches the current clock mode display, and controls selection of machine clock division ratio, and sub-clock oscillation in main-clock and main PLL clock mode.
Structure of System Clock Control Register (SYCC)
Figure 4.3-1 Structure of System Clock Control Register (SYCC)
DIV1 DIV0 0 0 0 1 1 0 1 1
SUBS
0 1
SRDY
0
1
SCS1 SCS00 0 1 1 0 1 1
SCM1 SCM0
0 0 0 1 1 0 1 1
bit 0
R / WX R / W R / WX R / W R / WX R/W R / W R / W
bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
::
X : :
Address Initial value
Machine clock division ratio selection bit
Source clock
Source clock / 16
Source clock / 8
Source clock / 4
Sub clock oscillation stop bit
Oscillation of sub clock
Stop of sub clock
Sub clock oscillation stabilization bit
Sub clock oscillation stability waiting state or sub clock oscillation is stopping.
Sub clock oscillation stability state
Clock mode selection bit
Sub clock mode
Sub PLL clock mode
Main clock mode
Main PLL clock mode
Clock mode monitor bit
Sub clock mode
Sub PLL clock mode
Main clock mode
Main PLL clock mode
Read only (Read is enabled. As for writing, the influence is not in operation. )Both read and write are enabled (The reading value is the writing value.)UndefinedInitial value
SCM1 SCM0 SCS1 SCS0 SRDY SUBS DIV1 DIV0
0
R/WXR/W
0007H 1010x011B
205
CHAPTER 4 Clock Control Block
Table 4.3-1 Functional Description of Each Bit in System Clock Control Register (SYCC)
Bit name Functions
Bit7, Bit6
SCM1,SCM0:Clock mode monitor bit
Shows the current clock mode. • When SCM bits 1,0 are "00", indicates sub clock mode. • When SCM bits 1,0 are "01", indicates sub PLL clock mode. • When SCM bits 1,0 are "10", indicates main clock mode. • When SCM bits 1,0 are "11", indicates main PLL clock mode. This bit is read-only. The written value carries no significance, and does not affect the operation.
Bit5, Bit4
SCS1,SCS0:Clock mode selection bit
Specifies the clock mode. • When "00" is written to SCS bits 1,0, changes to sub clock mode (two-clock system products
only). • When "01" is written to SCS bits 1,0, changes to sub PLL clock mode (two-clock system products
only). • When "10" is written to SCS bits 1,0, changes to main clock mode. • When "11" is written to SCS bits 1,0, changes to main PLL clock mode. After the clock mode is selected via SCS bits 1,0, writing to SCS bits 1,0 is ignored until the transfer to the selected clock mode is completed. Writing of "00" or "01" to single-clock system products is ignored, that the values of these bits do not change.
Bit3
SRDY:Sub clock oscillation stabilization bit(two clock system products only)
Indicates that the oscillation of the sub clock is stable. • When the SRDY bit is "1", it indicates that the oscillation stabilization wait time for the sub clock
is completed. • When the SRDY bit is "0", it indicates sub-clock oscillation stabilization standby, or that
oscillation has halted. This bit is read-only. The written value carries no significance, and does not affect the operation. The value of this bit has no meaning in single-clock system products.
Bit2
SUBS:Sub clock oscillation stop bit(two clock system products only)
Sets sub-clock oscillation stop when in main clock mode or main PLL clock mode. • Writing "1" to the SUBS bit stops the sub clock. • Writing "0" to the SUBS bit begins sub clock oscillation. Note:• When in sub clock mode or sub PLL clock mode, the sub clock oscillates regardless of the value of
this bit, with the exception of stop mode. • When in main clock mode and main PLL clock mode as well, when the sub PLL clock is oscillated
via the sub PLL clock oscillation authorization bit of the PLL control register (PLLC:SPEN), thesub clock oscillates regardless of the value of this bit.
• The value of this bit has no effect on operation in single-clock system products.
Bit1, Bit0
DIV1,DIV0:Machine-clock division ratio selection bit
• Selects the division ratio for the machine clock in relation to the source clock. • The machine clock is generated from the source clock via the division ratio set by means of these
bits.
DIV1 DIV0Machine-clock division ratio
selection bitSCM1,0="10B"
0 0 Source clock (no division) Main clock divided by 2
0 1 Source clock/4 Main clock divided by 8
1 0 Source clock/8 Main clock divided by 16.
1 1 Source clock/16 Main clock divided by 32
206
4.4 PLL Control Register (PLLC)
The PLL control register controls the main PLL clock and sub PLL clock.
Makeup of PLL Control Register (PLLC)
Figure 4.4-1 Makeup of PLL Control Register (PLLC)
0
1
0 00 11 01 1
01
0
1
0 0 0 1 1 0 1 1
01
R/W R/WR/WR/WR/WR/W R/WX R /WX
R/ W :R/WX : :
Address Initial value
Sub PLL clock multiplication rate setting bit
Read only (Read is enabled. As for writing, the influence is not in operation. )Both read and write are enabled (The reading value is the writing value.)
Initial value
Sub PLL clock oscillation stability waiting state or sub PLL clock oscillation is stopping.
Sub PLL clock oscillation stability state
Sub PLL clock oscillation stability bit
Setting prohibited
Sub oscillation clock × 2
Sub oscillation clock × 3
Sub oscillation clock × 4
Sub PLL clock oscillation enable bit
Stop of sub PLL clock
Oscillation of sub PLL clock
Main PLL clock oscillation stability waiting state or main PLL clock oscillation is stopping.
Main PLL clock oscillation stability state
Main PLL clock oscillation stability bit
Main PLL clock multiplication rate setting bit
Setting prohibited
Main oscillation clock × 2
Main oscillation clock × 2.5
Main oscillation clock × 1
Main PLL clock oscillation enable bit
Stop of main PLL clock
Oscillation of main PLL clock
00000000B0006H
bit 0bit 1bit 2bit 3bit 4bit 5bit 6bit 7MPEN MPCM1 MPCM0 MPRDY SPEN SPMC1 SPMC0 SPRDY
SPRDY
SPMC1 SPMC0
SPEN
MPRDY
MPCM1 MPCM0
MPEN
207
CHAPTER 4 Clock Control Block
Table 4.4-1 Functional Description of Each Bit in PLL Control Register (PLLC)
Bit name Functions
Bit7MPEN:Main PLL clock oscillation authorization bit
When in main clock mode or timebase timer mode, this bit controls the oscillation/stopping of the main PLL clock. • Writing "1" to this bit begins main PLL clock oscillation. • Writing "0" to this bit stops main PLL clock oscillation. When in main PLL clock mode and in RUN status or sleep mode, the main PLL clock oscillates regardless of the value of this bit.
Bit6, Bit5
MPMC1,MPMC0:Main PLL clock multiplier assignment bit
Assigns the multiplier of the main PLL clock.
Note:• The value of these bits can only be changed when the main PLL clock is stopped. Therefore, please
do not change these bits when PLL clock oscillation enable bit (MPEN) is "1"or clock modeselection bit of system control register (SYCC: SCS1, 0) is "11"(It is also possible to set these bits atthe same time as setting MPEN to "1".).
Bit4MPRDY:Main PLL clock oscillation stabilization bit.
Indicates that the oscillation of the main PLL clock is stable. • When this bit is "1", it indicates that the main PLL clock oscillation stabilization wait time for the
main PLL clock is completed. • When this bit is "0", it indicates main PLL clock oscillation stabilization wait of the main PLL
clock, or that the oscillation of the main PLL clock is stopped. This bit is read-only. The written value carries no significance, and does not affect operation.
Bit3
SPEN:Sub PLL clock oscillation authorization bit(two clock system products only)
Sets sub PLL clock oscillation/stop when in main clock mode, PLL clock mode, sub clock mode, or clock mode. • Writing "1" to this bit begins sub PLL clock oscillation. • Writing "0" to this bit stops sub PLL clock oscillation. When in sub PLL clock mode, oscillates regardless of the value of this bit, with the exception of watch mode. When in sub PLL clock mode and in stop mode, oscillation is stopped regardless of the value of this bit. The value of this bit has no effect on operation in single-clock system products.
Bit2, Bit1
SPMC1,SPMC0:Sub PLL clock multiplier assignment bit(two clock system products only)
Assigns the multiplier of the sub PLL clock.
The value of this bit has no effect on operation in single-clock system products. Note:• Although the initial value of these bits is "00", the PLL does not operate normally with this setting.
Before setting the sub PLL clock oscillation authorization bit (SPEN) to "1", and before setting theclock mode selection bits of the system control register (SYCC:SCS 1,0) to "01", be sure to set thesebits to a value other than "00".
• The value of these bits can only be changed when the sub PLL clock is stopped. Consequently, youshould not change these bits when the sub PLL clock oscillation authorization bit (SPEN) is "1", orthe system clock selection bits of the system control register (SYCC:SCS1,0) are "01". (As soon asSPEN is set to "1", these bits become assignable.
MPMC1 MPMC0 Main PLL clock multiplier assignment bit.
0 0 Main oscillation clock × 1
0 1 Main oscillation clock × 2
1 0 Main oscillation clock × 2.5
1 1 Setting disabled
SPMC1 SPMC0 Sub PLL clock multiplier assignment bit
0 0Setting prohibited. Be sure to write a value other than thisbefore using the PLL.
0 1 Sub oscillation clock × 2
1 0 Sub oscillation clock × 3
1 1 Sub oscillation clock × 4
208
Bit0
SPRDY:Sub PLL clock oscillation stabilization bit(two clock system products only)
Indicates that the oscillation of the sub PLL clock is stable. • When this bit is "1", it indicates that the sub PLL clock oscillation stabilization wait time for the sub
PLL clock is completed. • When this bit is "0", it indicates sub PLL clock oscillation stabilization wait of the sub PLL clock, or
that the oscillation of the sub PLL clock is stopped. This bit is read-only. The written value carries no significance, and does not affect the operation. The value of this bit has no meaning in single-clock system products.
Table 4.4-1 Functional Description of Each Bit in PLL Control Register (PLLC)
Bit name Functions
209
CHAPTER 4 Clock Control Block
4.5 Oscillation Stabilization Standby Time Assignment Register (WATR)
Sets the main clock oscillation stabilization standby time and sub clock oscillation stabilization standby time.
Makeup of Oscillation Stabilization Standby Time Assignment Register (WATR)Figure 4.5-1 Makeup of Oscillation Stabilization Standby Time Assignment Register (WATR)
MWT3 MWT2 MWT1 MWT0 1 1 1 1 214 214/ FCH 4. 10ms1 1 1 0 213 213/ FCH 2. 05ms 1 1 0 1 212 212/ FCH 1. 02ms1 1 0 0 211 211/ FCH 512. 0 s 1 0 1 1 210 210/ FCH 256. 0 s 1 0 1 0 29 2 9/ FCH 128. 0 s 1 0 0 1 28 28/ FCH 64. 0 s1 0 0 0 27 27/ FCH 32. 0 s 0 1 1 1 26 26/ FCH 16. 0 s 0 1 1 0 25 25/ FCH 8. 0 s 0 1 0 1 24 24/ FCH 4. 0 s 0 1 0 0 23 23/ FCH 2. 0 s 0 0 1 1 22 22/ FCH 1. 0 s 0 0 1 0 21 21/ FCH 0. 5 s 0 0 0 1 21 21/ FCH 0. 5 s 0 0 0 0 21 21/ FCH 0. 5 s
SWT3 SWT2 SWT1 SWT0
1 1 1 1 215 215/ FCL 1. 00s1 1 1 0 214 214/ FCL 500ms1 1 0 1 213 213/ FCL 250ms1 1 0 0 212 212/ FCL 125ms1 0 1 1 211 211/ FCL 62. 5ms1 0 1 0 210 210/ FCL 31. 25ms1 0 0 1 29 29/ FCL 15. 63ms 1 0 0 0 28 2 8/ FCL 7. 81m s 0 1 1 1 27 2 7/ FCL 3. 91m s0 1 1 0 26 2 6/ FCL 1. 95ms 0 1 0 1 25 25/ FCL 976. 6 s 0 1 0 0 24 24/ FCL 488. 3 s 0 0 1 1 23 23/ FCL 244. 1 s0 0 1 0 22 22/ FCL 122.1 s0 0 0 1 21 21/ FCL 61.0 s0 0 0 0 21 21/ FCL 61.0 s
bit 7 it 6 bit 5 it 4 it 3 it 2 bit 1 bit 0 SWT2 11111111B SWT3
SC
SWT1 SWT0 MWT3 MWT2 MWT1 MWT0 R / W R/ W R/ W R/ W R/ W R / W R / W R / W
R / W:
Address Initial value
Both read and write are enabled (The reading value is the writing value.)Initial value (Mask ROM product can be specified the initial value when ROM is ordered.)
Main oscillation clock FCH = 4 MHzCycle number
Sub oscillation clock FCH = 32.768 KHzCycle number
0005H
µµ
µµ
µµµµµµµµµ
µµµµµµ
:
b b b b
210
Table 4.5-1 Functional Description of Each Bit in Oscillation Stabilization Standby Time Assignment Register (WATR)
Bit name Functions
Bit7 to Bit4
SWT3,SWT2,SWT1,SWT0:Sub clock Oscillation stabilization wait interval selection bits(two clock system products only)
Set the sub clock oscillation stabilization standby time.
The value of these bits has no meaning in single-clock system products. Note:
Do not write to these bits during sub clock oscillation stabilization standby time. Consequently, youshould rewrite to them when the sub clock oscillation stable bit of the system clock control register(SYCC:SRDY) is "1", or when in sub clock mode or sub PLL clock mode. You can also rewrite to themwhen in main clock mode or main PLL clock mode, the sub clock oscillation stop bit of the systemclock control register (SYCC:SUBS) is "1", and the sub oscillation clock is stopped.
SWT3 SWT2 SWT1 SWT0 Cycle count Sub oscillation clock FCL=32.768kHz
1111 215 215/FCL 1.00s
1110 214 214/FCL 500ms
1101 213 213/FCL 250ms
1100 212 212/FCL 125ms
1011 211 211/FCL 62.5ms
1010 210 210/FCL 31.25ms
1001 29 29/FCL 15.63ms
1000 28 28/FCL 7.81ms
0111 27 27/FCL 3.91ms
0110 26 26/FCL 1.95ms
0101 25 25/FCL 976.6 µs
0100 24 24/FCL 488.3 µs
0011 23 23/FCL 244.1 µs
0010 22 22/FCL 122.1 µs
0001 21 21/FCL 61.0 µs
0000 21 21/FCL 61.0 µs
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CHAPTER 4 Clock Control Block
Bit3 to Bit0
MWT3,MWT2,MWT1,MWT0:Main clock Oscillation stabilization wait interval selection bits
• Set the main clock oscillation stabilization standby time.
Note:Do not rewrite to these bits during main clock oscillation stabilization standby time. Consequently, youshould rewrite to them when in main clock mode or main PLL clock mode. You can also rewrite to themwhen in sub clock mode.
Table 4.5-1 Functional Description of Each Bit in Oscillation Stabilization Standby Time Assignment Register (WATR)
Bit name Functions
MWT3 MWT2 MWT1 MWT0 Cycle count Main oscillation clock FCH=4MHz
1111 214 214/FCH 4.10ms
1110 213 213/FCH 2.05ms
1101 212 212/FCH 1.02ms
1100 211 211/FCH 512.0 µs
1011 210 210/FCH 256.0 µs
1010 29 29/FCH 128.0 µs
1001 28 28/FCH 64.0 µs
1000 27 27/FCH 32.0 µs
0111 26 26/FCH 16.0 µs
0110 25 25/FCH 8.0 µs
0101 24 24/FCH 4.0 µs
0100 23 23/FCH 2.0 µs
0011 22 22/FCH 1.0 µs
0010 21 21/FCH 0.5 µs
0001 21 21/FCH 0.5 µs
0000 21 21/FCH 0.5 µs
212
4.6 Standby Control Register (STBC)
The standby control register (STBC) controls transition from RUN state to sleep mode/stop mode/timebase timer mode/watch mode, the pin status assignment when in stop mode, timebase timer mode, and clock mode, and the generation of software resets.
Standby Control Register (STBC)
Figure 4.6-1 Standby Control Register (STBC)
TMD
0
1
SRST
0 1
SPL
0
1
SLP
0 1
STP
0 1
bit 7 bit 6 it 5 it 4 bit 3 bit 2 it1 it 0
R0, W STP SLP
R0, W R/ W SPL
R0, W R0, W R0/WX R0/WX R0/WXSRST TMD
R0, WR/ WR0/WX
Address Initial value
Clock bitRead
Not effecting to operation
Write
Write only (Write is enabled. Reading value is "0". )Both read and write are enabled (The reading value is the writing value.)
UndefinedInitial value
"0" is always read.
Main clock modeMain PLL clock mode
Sub clock modeSub PLL clock mode
Transition to timebase timer mode
Transition to watchmode
Software reset bitRead
The influence is not in operation.
Write
"0" is always read.Reset signal of 3 machine clocks is generated.
Sleep bitRead
The influence is not in operation.
Write
"0" is always read.Transition to sleep mode
Stop bitRead
The influence is not in operation.
Write
"0" is always read.Transition to stop mode
Stop mode, timebase timer mode, watch mode, or external pin is maintained in the state immediately before.
Stop mode, timebase timer mode, watch mode, or external pin is in the state of high impedance.
Pin state specification bit
Un used bit (The reading value is "0". As for writing, the influence is not in operation.)
:::::
0008H 00000000B
b b b b
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CHAPTER 4 Clock Control Block
Note:
• You should set the standby mode after checking that the clock mode transition is completed, bycomparing the clock mode monitor bit (SYCC: SCM1, 0) and the clock mode assignment bit(SYCC:SCS1, 0) of the system control register.
• The priority when "1" is written to the stop bit (STP), sleep bit (SLP), software reset bit (SRST),and watch bit (TMD) simultaneously is as follows.
1) Software reset bit (SRST)
2) Stop Bit (STP)
3) Watch bit (TMD)
4) Sleep bit (SLP)
When standby mode is released, normal RUN status is restored.
Table 4.6-1 Functional Description of Each Bit in Standby Control Register (STBC)
Bit name Functions
Bit7STP:Stop bit
Assigns a shift to stop mode. • Writing "1" to this bit shifts to stop mode. • Writing "0" to this bit does not affect operation. • Reading operations always return "0" for this bit.Note:
If there is an interrupt request when "1" is written to this bit, writes to this bit are ignored. See the notes onusage for standby mode for details.
Bit6SLP:Sleep bit
Assigns a shift to sleep mode. • Writing "1" to this bit shifts to sleep mode. • Writing "0" to this bit does not affect operation. • Reading operations always return "0" for this bit.Note:
If there is an interrupt request when "1" is written to this bit, writes to this bit are ignored. See the notes onusage for standby mode for details.
Bit5SPL:Pin state specification bit
Sets the external pin statuses of stop mode, timebase timer mode, and watch mode. • Writing "0" to this bit stores the external-pin status (level) when in stop mode, timebase timer mode, or
watch mode.• Writing "1" to this bit sets the external pin to high impedance when in stop mode, timebase timer mode, or
watch mode (if pull-up resistance is selected in the pull-up assignment register, the pin goes into pull-upstatus).
Bit4SRST:Software reset bit
Assigns a software reset. • Writing "1" to this bit generates a 3 machine clock reset signal. • Writing "0" to this bit does not affect operation. • Reading operations always return "0" for this bit.
Bit3TMD:Watch bit
In products with two clock systems, assigns a shift to timebase timer mode or watch mode. In products with one clock system, assigns a shift to timebase timer mode. • Writing "1" to this bit while in main clock mode or main PLL clock mode shifts to timebase timer mode. • Writing "1" to this bit while in sub clock mode or sub PLL clock mode shifts to watch mode. • Writing "0" to this bit does not affect operation. • Reading operations always return "0" for this bit.Note:
If there is an interrupt request when "1" is written to this bit, writes to this bit are ignored. See the notes onusage for standby mode for details.
Bit2 to Bit0
Unused bit"0" is always read. This bit is read-only. The written value carries no significance, and does not affect the operation.
214
4.7 Reset Source Register (RSRR)
The reset source register indicates the reset generation cause of any reset that has been generated.
Makeup of Reset Source Register (RSRR)
Figure 4.7-1 Reset Source Register (RSRR)
SWR
0 1
HWR
0 1
PONR
0 1
WDTR
0 1
EXTS
0 1
CSVR
0
1
CSVR SWR HWR PONRWDTR EXTS bit 0
R0/WX R/WX R0 /WX R/ WX R /WX R/ WX R/WX R/WX
bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
R0/WXR/WX
X
Address Initial value
Unused bit (Reading value is "0". As for writing, the influence is not in operation.)Read only (Read is enabled. As for writing, the influence is not in operation.)
Undefined
Software reset flag bitRead
The influence is not in operation.
Write
The factor is software reset.
Unused bit
Hardware reset flag bitRead
The influence is not in operation.
Write
The factor is hardware reset.
Power-on reset flag bitRead
The influence is not in operation.
Write
The factor is power-on reset.
Watchdog reset flag bitRead
The influence is not in operation.
Write
The factor is watchdog reset.
External reset flag bitRead
The influence is not in operation.
Write
The factor is external reset.
Clock supervisor reset flag bitRead
The influence is not in operation.
Write
The factor is clock supervisor reset.
::::
0009H xxxxxxxxB
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CHAPTER 4 Clock Control Block
Note: Reading the reset source register clears it. For this reason, if you wish to use the reset sourceregister for operation, we recommend moving the contents of the register to RAM.
Table 4.7-1 Functional Description of Each Bit in Reset Source Register (RSRR)
Bit name Functions
Bit7, Bit6
Unused bit"0" is always read. This bit is read-only. The written value carries no significance, and does not affect the operation.
Bit5CSVR:Clock supervisory reset flag bit
When this bit is "1", indicates that a clock supervisory reset has been generated. Otherwise, retains the value before the reset occurred. • Read operations set this bit to "0". • This bit is read-only. The written value carries no significance, and does not affect the operation. • This bit is always "0" in products without clock supervisory. The written value carries no significance,
and does not affect the operation.
Bit4EXTS:External reset flag bit
When this bit is "1", indicates that an external reset has been generated. Otherwise, retains the value before the reset occurred. • Read operations set this bit to "0". • This bit is read-only. The written value carries no significance, and does not affect the operation.
Bit3WDTR:Watchdog reset flag bit
When this bit is "1", indicates that a watchdog reset has been generated. Otherwise, retains the value before the reset occurred. • Read operations set this bit to "0". • This bit is read-only. The written value carries no significance, and does not affect the operation.
Bit2PONR:Power-on reset flag bit
When this bit is "1", indicates that a power-on reset/low-voltage detection reset (option) has occurred. Otherwise, retains the value before the reset occurred. • The low-voltage detection reset function is an option on each model. • Read operations set this bit to "0". • This bit is read-only. The written value carries no significance, and does not affect the operation. Note:
In the event of a power-on reset, all reset source bits are set to "1", with the exception of software reset.
Bit1HWR:Hardware reset flag bit
When this bit is "1", indicates that a reset other than a software reset has been generated. Consequently, if any of bits 2 through 5 is "1", this bit will also be "1". Otherwise, retains the value before the reset occurred. • Read operations set this bit to "0". • This bit is read-only. The written value carries no significance, and does not affect the operation.
Bit0SWR:Software reset flag bit
When this bit is "1", indicates that a software reset has been generated. Otherwise, retains the value before the reset occurred. • Read operations and power-on resets set this bit to "0". • This bit is read-only. The written value carries no significance, and does not affect the operation.
216
4.8 Reset Operation
When a reset is released, the CPU reads the mode data and reset vector from internal ROM (mode fetch). Upon power-up, a mode fetch is performed after the oscillation stabilization standby time has elapsed, for the restoration of sub clock mode/sub PLL clock mode/stop mode via reset.
Reset FactorThere are 5 causes for resets.
External reset
An external reset is generated by entering "L" level into the external reset pin (RST).
Externally input reset signals generate internal reset signals in synchronization with the machine clock that
asynchronously accepted them, via the internal noise filter. Consequently, a clock is necessary for internal
circuit initialization. For this reason, clock input is necessary when operating via an external clock.
External pins (including I/O ports and peripheral functions), however, are reset asynchronously.
Additionally, there are standard pulse-width values for external reset input. If the value is below the
standard, the reset may not be accepted. The standard value is listed on the data sheet. Please design your
external reset circuit so that this standard is met.
Software reset
Writing "1" to the software reset bit of the standby control register (STBC:SRST) generates a software
reset.
Watchdog reset
After the watchdog timer starts, a watchdog reset is generated if the watchdog timer is not cleared within a
preset amount of time.
Table 4.8-1 Reset Factor
Reset Factor Reset condition
External reset "L" level input to external reset pin
Software reset Write "1" to the software reset bit (STBC: SRST) in the standby control register.
Watchdog reset Watchdog timer overflow
Power-on reset/low-voltage detection reset
Power on. Power voltage is lower than detect voltage (option).
Clock supervisory reset Abnormal stop of clock oscillation (option)
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CHAPTER 4 Clock Control Block
Power-on reset/low-voltage detection reset (option)
A power-on reset is generated by power-on events.
Some 5 V products have an on-board low-voltage detection reset circuit (option). Select a model with low-
voltage detection reset as needed.
The low-voltage detection reset circuit generates a reset if the power voltage falls below a predetermined
level.
The logical function of the low-voltage detection reset is completely equivalent to power-on reset. All the
text in this manual concerning power-on resets applies to low-voltage detection resets.
See Chapter 25 for details about low-voltage detection resets.
Clock supervisory reset (option)
Some 5 V products have an on-board clock supervisor (option).
The clock supervisor monitors the main oscillation clock and sub oscillation clock, and generates a reset if
oscillation stops abnormally, not caused by a predefined state transition. After reset, a clock generated by
the on-board RC oscillation circuit is supplied internally.
See Chapter 26 for details about the clock supervisor.
Reset TimeIn the case of a software reset or watchdog reset, the reset time consists of a total of three machine clocks:
one machine clock frequency selected before the reset, and two machine clock frequencies initially set after
the reset (1/32 of the main oscillation clock frequency). However, the reset time may be extended by the
machine clock unit of the currently selected frequency via the RAM access protection function, which
controls resets during RAM access. Additionally, when in main clock oscillation stabilization standby, the
reset time is further extended.
External resets and clock supervisory resets are also affected by the RAM access protection function and
main clock oscillation stabilization standby time.
In the case of a power-on reset or low-voltage detection reset, the reset continues during oscillation
stabilization standby time.
Reset OutputThe reset pin of 5 V products without a clock supervisor outputs "L" level during reset time.
The reset pin of 3 V and 5 V products with clock supervisors do not have an output function.
218
Overview of Reset Operation
Figure 4.8-1 Reset Operation Flow
In the case of power-on reset/low-voltage detection reset, and reset when in sub clock mode, sub PLL clock
mode, or stop mode, mode fetch is performed after the main clock oscillation stabilization standby time has
elapsed. If the external reset input is not cleared after the oscillation stabilization standby time has elapsed,
mode fetch is performed after the external reset is released.
Effect of Reset on RAM ContentsWhen a reset is generated, the CPU halts operation of the command currently being executed, and enters
reset status. During RAM access execution, however, RAM access protection causes an internal reset signal
to be generated in synchronization with the machine clock, after RAM access has ended. This function
prevents a word-data write operation from being cut off by reset after one byte.
During reset
Mode fetch
Normal operation(RUN state)
Software reset Watchdog reset
In RAM access Reset control
In operating atsub clock mode andsub PLL clock mode
Main clock oscillation stabilization wait time reset state
External reset inputClock supervisor reset
In RAM accessRest control
In the mode atsub clock, sub PLL clock
or stop
Main clock oscillation stabilization wait time reset state
Main clock oscillation stabilization wait time reset state
Power-on reset/low-voltage detection reset
External reset released
Capturing mode date
Capturing reset vector
Capturing instruction code from the address indicated by reset vector and executing the instrction
NO
NO
YES
YES
NO
YES
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CHAPTER 4 Clock Control Block
Pin Status during ResetWhen a reset occurs, setup is performed via software after the reset is released. Until this time, all I/O ports
and peripheral function pins go to high impedance.
Note:
Please connect pull-up resistance so that devices connected to pins that go to high impedanceduring reset do not malfunction.
See Chapter xx, Pin States for details about the states of all pins during reset.
220
4.9 Clock Mode Operation
There are the following types of clock mode: main clock mode, sub clock mode, main PLL clock mode, and sub PLL clock mode. The system switches between them via the assignments of the system clock control register (SYCC). There is no sub clock mode/sub PLL clock mode in products with one clock system.
Operation of Main Clock ModeIn main clock mode RUN status, the main clock is used as the machine clock for the CPU and peripheral
functions.
The timebase timer operates with the main clock.
The clock prescaler and clock counter operate with the sub clock. (products with two clock systems)
If standby mode is set while in main clock mode, it is possible to transit to sleep mode, stop mode, or
timebase timer mode.
After a reset, the mode is always set to main clock mode, regardless of the clock mode after the reset.
Sub Clock Mode Operation (Products with Two Clock Systems)In sub clock mode RUN status, the main clock oscillation stops, and the sub clock is used as the machine
clock for the CPU and peripheral functions. As the timebase timer uses the main clock, it stops.
If standby mode is set while in sub clock mode, it is possible to transit to sleep mode, stop mode, or watch
mode.
Operation of Main PLL Clock ModeIn main PLL clock mode RUN status, the main PLL clock is used as the machine clock for the CPU and
peripheral functions. The timebase timer and watchdog timer operate by the main clock.
The clock prescaler and clock counter operate by the sub clock (products with two clock systems).
If standby mode is set while in main PLL clock mode, it is possible to transit to sleep mode, stop mode, or
timebase timer mode.
Sub PLL Clock Mode Operation (Products with Two Clock Systems)In sub PLL clock mode RUN status, the main clock oscillation stops, and the sub PLL clock is used as the
machine clock for the CPU and peripheral functions. As the timebase timer uses the main clock, it stops.
The clock prescaler and clock counter operate with the sub clock.
If standby mode is set while in sub PLL clock mode, it is possible to transit to sleep mode, stop mode, or
watch mode.
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CHAPTER 4 Clock Control Block
Clock Mode State Transition DiagramThere are the following types of clock mode: main clock mode, main PLL clock mode, sub clock mode,
and sub PLL clock mode. The system switches between them via the assignments of the system clock
control register (SYCC).
Figure 4.9-1 Clock Mode State Transition Diagram (Products with Two Clock System)
(1) (2)
Power on
Reset state Generating reset in each state
Main clock oscillation stabilization wait time
Main clock mode
Main PLL clock oscillation
stabilization wait time
Main PLL clock mode
Sub clock oscillation stabilization wait time
Sub clock/sub PLL clock oscillation
stabilization wait time
Main clock oscillation stabilization wait time
Main clock/Main PLL clock oscillation stabilization wait time
Sub PLL clock oscillation
stabilization wait time
Sub clock mode Sub PLL clock mode
(3)
(4) (5)
(6)
(7)
(8)
(9)
(11)
(10)
(12)(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
222
Figure 4.9-2 Clock Mode State Transition Diagram (Products with One Clock System)
(1)(2)
Main PLL clock oscillation
stabilization wait time
Main clock mode Main PLL clock mode
Main clock oscillation stabilization wait time
Power on
Reset state Generating reset in each state
(7)
(8)
(9)
Table 4.9-1 Clock Mode State Transition Table
Current status Next status Description
(1)
Reset state Main clock
After reset, waits for main clock oscillation stabilization standby time, then transitions to mainclock mode. Note, however, that in the case of a watchdog reset, software reset, or external reset while inmain clock mode or main PLL clock mode, the passage of main clock oscillation stabilizationstandby time is not waited for.
(2)
(3)
Main clock
Sub clock
Setting the system clock selection bits of the system clock control register (SYCC:SCS1,0) to"00" shifts to sub clock mode. However, the passage at the sub-clock oscillation stability waiting time is waited for and itchanges to the sub-clock mode when the sub-clock oscillation stability waiting time has notbeen completed yet immediately after turning on of the power supply and when the suboscillation clock has stopped by setting sub-clock oscillation stop bit (SYCC:SUBS) of thesystem clock control register in the state of the main clock mode.
(4)
(5)
Sub PLL clock
Setting the system clock selection bits of the system clock control register (SYCC:SCS1,0) to"01" shifts to sub PLL clock mode after waiting the sub PLL clock oscillation stabilizationstandby time.If sub PLL clock is oscillating via the assignment of the sub PLL clock oscillation authorizationbit of the PLL control register (PLLC:SPEN) while in main PLL clock mode, however, the subPLL clock oscillation stabilization standby time is not waited. However, the passage at the sub-clock oscillation stability waiting time is waited for and itchanges to the sub PLL clock mode when the sub-clock oscillation stability waiting time has notbeen completed yet immediately after turning on of the power supply and when the suboscillation clock has stopped by setting sub-clock oscillation stop bit (SYCC:SUBS) of thesystem clock control register in the state of the main clock mode. If waiting the sub clock oscillation stabilization standby time and the sub PLL clock oscillationstabilization standby time, the longest of the times is waited.
(6)
(7)Main PLL clock
Assigning "11" to the system clock selection bits of the system clock control register(SYCC:SCS1,0) shifts to main PLL clock mode after waiting the main PLL clock oscillationstabilization standby time. If main PLL clock is oscillating via the main PLL clock oscillation authorization bit of the PLLcontrol register (PLLC:MPEN), however, the main PLL clock oscillation stabilization standbytime is not waited.
(8)
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CHAPTER 4 Clock Control Block
(9)
Main PLL clock
Main clock Assigning "10" to the system clock selection bits of the system clock control register(SYCC:SCS1,0) shifts to main clock mode.
(10)
Sub clock
Assigning "00" to the system clock selection bits of the system clock control register(SYCC:SCS1,0) shifts to sub clock mode. The passage at the sub-clock oscillation stability waiting time is waited for and it changes to thesub-clock mode when the sub-clock oscillation stability waiting time has not been completedyet immediately after turning on of the power supply and when the sub oscillation clock hasstopped by setting sub-clock oscillation stop bit (SYCC:SUBS) of the system clock controlregister in the state of the main PLL clock mode.
(11)
(12)
Sub PLL clock
Setting the system clock selection bits of the system clock control register (SYCC:SCS1,0) to"01" shifts to sub PLL clock mode after waiting the sub PLL clock oscillation stabilizationstandby time. If sub PLL clock is oscillating via the assignment of the sub PLL clock oscillation authorizationbit of the PLL control register (PLLC:SPEN) while in main PLL clock mode, however, the subPLL clock oscillation stabilization standby time is not waited. The passage at the sub-clock oscillation stability waiting time is waited for and it changes to thesub-clock mode when the sub-clock oscillation stability waiting time has not been completedyet immediately after turning on of the power supply and when the sub oscillation clock hasstopped by setting sub-clock oscillation stop bit (SYCC:SUBS) of the system clock controlregister in the state of the main PLL clock mode.If waiting the sub clock oscillation stabilization standby time and the sub PLL clock oscillationstabilization standby time, the longest of the times is waited.
(13)
(14)
Sub Clock
Main clock Assigning "10" to the system clock selection bits of the system clock control register(SYCC:SCS1,0) shifts to main clock mode after waiting the main clock oscillation stabilizationstandby time.
(15)
Sub PLL clock
Setting the system clock selection bits of the system clock control register (SYCC:SCS1,0) to"01" shifts to sub PLL clock mode after waiting the sub PLL clock oscillation stabilizationstandby time. If sub PLL clock is oscillating via the assignment of the sub PLL clock oscillation authorizationbit of the PLL control register (PLLC:SPEN) while in sub clock mode, however, the sub PLLclock oscillation stabilization standby time is not waited.
(16)
(17)Main PLL clock
Assigning "11" to the system clock selection bits of the system clock control register(SYCC:SCS1,0) shifts to main PLL clock mode after waiting the longer of the main PLL clockoscillation stabilization standby time and main PLL clock oscillation stabilization standby time.
(18)
Sub PLL clock
Sub clock Assigning "00" to the system clock selection bits of the system clock control register(SYCC:SCS1,0) shifts to sub clock mode.
(19)Main PLL clock
Assigning "11" to the system clock selection bits of the system clock control register(SYCC:SCS1,0) shifts to main PLL clock mode after waiting the longer of the main PLL clockoscillation stabilization standby time and main PLL clock oscillation stabilization standby time.
(20) Main clock Assigning "10" to the system clock selection bits of the system clock control register(SYCC:SCS1,0) shifts to main clock mode after waiting the main clock oscillation stabilizationstandby time.
Table 4.9-1 Clock Mode State Transition Table
Current status Next status Description
224
4.10 Operation of Standby Mode (Low-power Consumption Mode)
There are the following types of standby mode: sleep mode, stop mode, timebase timer mode, and watch mode. The system switches to RUN status via the assignments of the standby control register (STBC). Standby mode is released by a reset or an interrupt from a peripheral function.
Overview of Standby Mode Transition and RecoveryThere are the following types of standby mode: sleep mode, stop mode, timebase timer mode, and watch
mode. The system switches to RUN status via the assignments of the standby control register (STBC).
Standby mode is released via an interrupt or reset. When transiting to RUN status, the system automatically
waits until the oscillation stabilization standby time has elapsed, as needed.
When recovering from standby mode via a reset, the clock mode returns to clock mode, but if the recovery
is via an interrupt, the clock mode before entering standby mode is restored.
State of Pins in Standby ModeIt is possible to set the state of the stop mode, timebase timer mode, and watch mode I/O port/peripheral
function pin to retain their state immediately beforehand, or be set to high impedance, via the pin state
specification bit (STBC:SPL) of the standby control register.
See Appendix E Pin States of the MB95xxx Series for details about the states of all pins when in standby
mode.
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CHAPTER 4 Clock Control Block
4.10.1 Notes on Using Standby Mode
Even if the standby control register (STBC) sets standby mode, transition to standby mode is not allowed when a peripheral function generates an interrupt request. When an interruption causes a return from the standby mode to the normal operation state, the operation that follows varies depending on whether interruption requests can be accepted.
Immediately After Executing A Command To Set The Standby Mode, Enter Three Or More NOP Commands.
After setting the standby control register, it takes four machine-clock time to transition to standby mode.
For this reason, the CPU executes the program for the four machine clocks until transiting to standby mode.
In order to avoid program execution during this transition to standby, enter three or more NOP commands
immediately after executing the standby transition command.
Though operating normally even if excluding the NOP instruction is arranged. However, note that there are
two possibilities to be executed before the instruction that is sure to be executed after the standby mode is
made clear enters the standby mode and to be restarted during the instruction execution on the way after the
entering standby is released to the standby mode (The number of instruction execution cycles extends).
Make Sure That Clock-mode Transition Is Completed Before Setting Standby Mode. You should set the standby mode after checking that the clock mode transition is completed, by comparing
the clock mode monitor bit (SYCC: SCM1, 0) and the clock mode assignment bit (SYCC:SCS1, 0) of the
system control register.
An Interrupt Request Could Suppress The Transition To Standby Mode. When performing a standby mode setting, writing will be ignored if an interrupt request with an interrupt
level stronger than "11" is generated, and command execution will continue without a transition to standby
mode. There will be no transition to standby mode after interrupt processing.
This behavior is the same as when the interrupt authorization flag of the condition code register (CCR:I)
and the interrupt level bits of the condition code register (CCR:IL 1,0) for the CPU do not authorize an
interrupt.
Standby Mode Is Also Released When The CPU Does Not Accept The Interrupt. When the interruption demand whose interruption level is stronger than "11" in the standby mode is
generated, the standby mode is made clear regardless of the setting of interruption level bit (CCR:IL1,0)
and interruption permission flag (CCR:I) of the condition code register for CPU.
After it is released, if the settings of the CPUs condition code register accept interrupts, then interrupt
processing is performed. If they do not accept interrupts, execute the processing from the command
following the command executed immediately before the transition to standby mode.
226
State Transition in Standby ModeFigure 4.10-1 and Figure 4.10-2 show a standby mode state transition diagram.
Figure 4.10-1 Standby Mode State Transition Diagram (Products with Two Clock System)
Power on
Reset state Generating reset in each state
Main clock oscillation
stabilization wait time
Stop mode
Main PLL clock oscillation
stabilization wait time
Sub PLL clock oscillation
stabilization wait time
(2)
(1)
Timebase timer mode
Main clock/main PLL clock
sub clock/ sub PLL clock
oscillation stabilization
wait time
Normal operation(RAM state) Clock mode
Sleep mode
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
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CHAPTER 4 Clock Control Block
Figure 4.10-2 Standby Mode State Transition Diagram (Products with One Clock System)
(2)(1)
Power on
Reset state Generating reset in each state
Main clock oscillation
stabilization wait time
Stop mode
Main PLL clock oscillation
stabilization wait timeTimebase timer mode
Main clock/main PLL clock
oscillation stabilization
wait time
Normal operation(RAM state)
Sleep mode
(3)
(4)
(6)
(5)
(7)
(8)
(9)
228
Table 4.10-1 State Transition Diagram (Transition to and Release of Standby Mode)
State transition Description
(1)
Normal operation from resetstate
After reset, transitions to main clock mode. In the case of a power-on reset, always waits the main clock oscillation stabilization standby time. If the clock mode before the reset was sub clock mode or sub PLL clock mode, the main clockoscillation stabilization standby time is waited. Also waits the main clock oscillation stabilizationstandby time if standby mode was stop mode. If the clock mode before the reset was main clock mode or main PLL clock mode, and if thestandby mode was the mode other than stop mode when the transition to reset status was performedby the watchdog reset, software reset, or external reset, the main oscillation stabilization standbytime is not waited.
(2)
(3)Sleep mode
Writing "1" to the sleep bit of the standby control register (STBC:SLP) shifts to sleep mode.
(4) An interrupt from a peripheral function restores RUN status.
(5)
Stop mode
Writing "1" to the stop bit of the standby control register (STBC:STP) shifts to stop mode.
(6)
RUN status is restored via an external interrupt, after waiting the oscillation stabilization standbytime corresponding to the clock mode. When waiting PLL oscillation stabilization standby time, the longer of the correspondingoscillation stabilization standby time and PLL oscillation stabilization standby time is waited.
(7)
Timebase timer mode
Writing "1" to the clock bit of the standby control register (STBC:TMD) while in main clock modeor main PLL clock mode shifts to timebase timer mode.
(8)A timebase timer interrupt, clock prescaler, clock counter interrupt, or external interrupt restoresRUN state. In the case of main PLL clock mode, waits for main PLL clock oscillation stabilization standbytime. Even if in main PLL clock mode, however, if "1" is assigned to the main PLL oscillationauthorization bit of the PLL control register (PLLC:MPEN), the main PLL clock oscillationstabilization standby time is not waited.
(9)
(10)
Watch mode
Writing "1" to the clock bit of the standby control register (STBC:TMD) while in sub clock modeor sub PLL clock mode shifts to watch mode.
(11)A clock prescaler, clock counter interrupt, or external interrupt restores normal operation. In the case of sub PLL clock mode, waits for sub PLL clock oscillation stabilization standby time.Even if in sub PLL clock mode, however, if "1" is assigned to the sub PLL oscillation authorizationbit of the PLL control register (PLLC:SPEN), the sub PLL clock oscillation stabilization standbytime is not waited. (12)
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CHAPTER 4 Clock Control Block
4.10.2 Sleep Mode
Sleep mode stops the operation of the CPU and watchdog timer.
Operations Relating to Sleep ModeSleep mode stops the operation clock of the CPU and watchdog timer. Although the CPU stops storing data
in the registers and RAM used immediately before transition to sleep mode, peripheral functions, excepting
the watchdog timer, continue to operate.
Transition to sleep mode
Writing "1" to the sleep bit in the standby control register (STBC:SLP) changes to sleep mode.
Cancellation of sleep modes
Sleep mode is released by a reset or an interrupt from a peripheral function.
230
4.10.3 Stop Mode
Stop mode stops the operation of the main oscillation clock.
Operation in Stop ModeStop mode stops the operation of the main oscillation clock. The register and RAM contents immediately
before entering stop mode are retained, all functions stop with the exception of external interrupts and low-
voltage detection reset.
Note, however, that you can start/stop oscillation of the sub clock when in main clock mode or main PLL
clock mode, via assignment of the sub clock oscillation stop bit of the system clock control register
(SYCC:SUBS). If the sub clock is oscillating, the clock prescaler and clock counter operate.
Transition to stop mode
Writing "1" to the stop bit in the standby control register (STBC:STP) changes to stop mode. At this time,
the state of an external terminal is maintained when terminal state specification bit (STBC:SPL) of the
standby control register is "0", and the state of an external terminal becomes high impedance for "1" (The
terminal that has selected the pull-up resistor by the pull-up setting register and to exist enters the state of
the pull-up).
In the case of main clock mode and main PLL clock mode, a timebase timer interrupt request may be
generated after release of stop mode via an interrupt, while waiting for main clock oscillation to stabilize. If
the interrupt interval time of the timebase timer is shorter than the main clock oscillation stabilization
standby time, then we recommend prohibiting interrupt request output by the timebase timer before
transiting to stop mode, and the prevention of unexpected interrupts.
When in sub clock mode or sub PLL clock mode and transiting to stop mode as well, we recommend
prohibiting watch interrupt request output by the clock prescaler.
Release of stop mode
Stop mode is released via a reset or an external interrupt.
Note, however, that you can start/stop oscillation of the sub clock when in main clock mode or main PLL
clock mode, via assignment of the sub clock oscillation stop bit of the system clock control register
(SYCC:SUBS). If the sub clock is oscillating, clock prescaler and clock counter interrupts can release stop
mode.
Note:
When stop mode is released via an interrupt, peripheral functions placed into stop mode during anaction resume that action. Therefore, the initial interval time of the interval timer and other similarsettings are rendered unknown. After recovery from stop mode, initialize peripheral functions asnecessary.
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CHAPTER 4 Clock Control Block
4.10.4 Timebase Timer Mode
In timebase timer mode, only the main clock oscillation, sub clock oscillation, timebase timer, and clock prescaler operate. The operation clocks for the CPU and peripheral functions stop.
Timebase Timer Mode OperationIn timebase timer mode, the supply of the main clock to other than the timebase timer is stopped. The
register and RAM contents immediately before entering timebase timer mode are retained, all functions
stop with the exception of the timebase timer, external interrupts, and low-voltage detection reset.
Note, however, that you can start/stop oscillation of the sub clock via assignment of the sub clock oscillation
stop bit of the system clock control register (SYCC:SUBS). If the sub clock is oscillating, the clock prescaler
and clock counter operate.
Transition to timebase timer mode
You can only transit to timebase timer mode from main clock mode and PLL clock mode.
If the system clock monitor bits of the system clock control register (SYCC:SCM 1,0) are "10" or "11",
writing "1" to the clock bit of the standby control register (STBC:TMD) will transit to timebase timer
mode.
In the shift to the timebase timer mode, the state of an external terminal is maintained when terminal state
specification bit (STBC:SPL) of the standby control register is "0", and high impedance of the state for an
external terminal (The terminal that has selected "There is a pull-up resistor" by the pull-up setting register
is in the state of the pull-up) for "1".
Releasing of timebase timer mode
Timebase timer mode is released via a reset, timebase timer interrupt or an external interrupt.
Note, however, that you can start/stop oscillation of the sub clock via assignment of the sub clock
oscillation stop bit of the system clock control register (SYCC:SUBS). If the sub clock is oscillating, clock
prescaler and clock counter interrupts can release timebase timer mode.
Note:
When timebase timer mode is released via an interrupt, peripheral functions placed into timebasetimer mode during an action resume that action. Therefore, the initial interval time of the intervaltimer and other similar settings are rendered unknown. After recovery from timebase timer mode,initialize peripheral functions as necessary.
232
4.10.5 Watch Mode
In watch mode, only the sub clock and clock prescaler operate. The operation clocks for the CPU and peripheral circuits are stopped.
Watch Mode OperationWatch mode is stopped the operation clocks of the CPU and peripheral circuits. The register and RAM
contents immediately before entering watch mode are retained, and all functions stop with the exception of
clock prescaler, clock counter, external interrupts, and low-voltage detection reset.
Transition to watch mode
Watch mode can only be entered from sub clock mode and sub PLL clock mode. If the system clock
monitor bits of the system clock control register (SYCC:SCM 1,0) are "00" or "01", writing "1" to the clock
bit of the standby control register (STBC:TMD) will transit to watch mode.
In the shift to the watch mode, the state of an external terminal is maintained when terminal state
specification bit (STBC:SPL) of the standby control register is "0", and high impedance of the state for an
external terminal (The terminal that has selected "There is a pull-up resistor" by the pull-up setting register
is in the state of the pull-up) for "1".
Cancellation of watch mode
Watch mode is released by reset, watch interrupts and external interrupts.
Note:
When watch mode is released via an interrupt, peripheral functions placed into watch mode duringan action resume that action. Therefore, the initial interval time of the interval timer and other similarsettings are rendered unknown. After recovery from watch mode, initialize peripheral functions asnecessary.
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CHAPTER 4 Clock Control Block
4.11 Clock Oscillation Circuit
The clock oscillation circuit generates an internal clock via the connection of an oscillator to the clock oscillation pin or inputting a clock signal. In products with two clock systems, if only the main clock is used, without using the oscillation of the sub clock, if for some reason the system goes into sub clock mode, there will be no way to recover due to lack of a clock supply. Consequently, if you will only be using the main clock, you should be sure to select a product with one clock system.
Clock Oscillation Circuit
For a crystal or ceramic resonator
Connect as shown in Figure 4.11-1 .
Figure 4.11-1 Sample Connection of Crystal Oscillator and Ceramic Oscillator
X0 X1 X0A X1A X0 X 1 P63/ I NT13/ X0A P64/ X1X0 X1
C C C C C C
Two clock system One clock system
Main clock oscillation circuit
Sub clock oscillation circuit
Main clock oscillation circuit
234
External clock
Connect the external clock to the X0 pin and leave the X1 pin open, as shown in Figure 4.11-2 . If the subclock is externally supplied, connect the external clock to X0A pin, and leave X1A pin free.
Figure 4.11-2 Example of Connection for External Clock
X0 X1 X0 X1 X0A X1A
Main clock oscillation circuit
Sub clock oscillation circuit
Main clock oscillation circuit
Two clock system One clock system
Open Open Open
235
CHAPTER 4 Clock Control Block
236
CHAPTER 5I/O Port
This chapter describes the functionality and behavior of the I/O ports.
5.1 Overview of I/O Ports
5.2 Port 0
5.3 Port 1
5.4 Port 2
5.5 Port 3
5.6 Port 4
5.7 Port 5
5.8 Port 6
5.9 Port 7
5.10 Port 8
5.11 Port 9
5.12 Port A
5.13 Port B
5.14 Port C
5.15 Port D
5.16 Port E
5.17 Port F
5.18 Port G
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CHAPTER 5 I/O Port
5.1 Overview of I/O Ports
I/O ports are used to control general-purpose I/O pins. The available I/O ports and their numbers of bits differ for the MB95FV100, depending on the pin mode. Select the pin mode in accordance with your target series (see "INTRODUCTION"). Please read this chapter in accordance with the I/O port of your target series.
Overview of I/O PortsThe I/O port has functions to output data from the CPU and load inputted signals into the CPU, via the port
data register (PDR). It is also possible to set the input/output direction of the I/O pins as desired at the bit
level, via the port direction register (DDR).
See Table 5.1-1 for a list of registers for each port.
The available I/O ports and their numbers of bits differ for the MB95FV100, depending on the pin mode.
See the sections on each port following this section for details.
Table 5.1-1 -Registers of Each Port (1 / 2)
Register name Read/Write Initial value
Port 0 data register (PDR0) R,RM/W 00000000B
Port 0 direction register (DDR0) R/W 00000000B
Port 1 data register (PDR1) R,RM/W 00000000B
Port 1 direction register (DDR1) R/W 00000000B
Port 2 data register (PDR2) R,RM/W 00000000B
Port 2 direction register (DDR2) R/W 00000000B
Port 3 data register (PDR3) R,RM/W 00000000B
Port 3 direction register (DDR3) R/W 00000000B
Port 4 data register (PDR4) R,RM/W 00000000B
Port 4 direction register (DDR4) R/W 00000000B
Port5 data register (PDR5) R,RM/W 00000000B
Port 5 direction register (DDR5) R/W 00000000B
Port 6 data register (PDR6) R,RM/W 00000000B
Port 6 direction register (DDR6) R/W 00000000B
Port 7 data register (PDR7) R,RM/W 00000000B
Port 7 direction register (DDR7) R/W 00000000B
Port 8 data register (PDR8) R,RM/W 00000000B
Port 8 direction register (DDR8) R/W 00000000B
Port 9 data register (PDR9) R,RM/W 00000000B
Port 9 direction register (DDR9) R/W 00000000B
Port A data register (PDRA) R,RM/W 00000000B
Port A direction register (DDRA) R/W 00000000B
Port B data register (PDRB) R,RM/W 00000000B
Port B direction register (DDRB) R/W 00000000B
Port C data register (PDRC) R,RM/W 00000000B
Port C direction register (DDRC) R/W 00000000B
Port D data register (PDRD) R,RM/W 00000000B
238
R/W: Read/write enabled (read value is written value)
R,RM/W:Read/write enabled (read value and written value differ. During read-modify-write, the written
value is read)
Port D direction register (DDRD) R/W 00000000B
Port E data register (PDRE) R,RM/W 00000000B
Port E direction register (DDRE) R/W 00000000B
Port F data register (PDRF) R,RM/W 00000000B
Port F direction register (DDRF) R/W 00000000B
Port G data register (PDRG) R,RM/W 00000000B
Port G direction register (DDRG) R/W 00000000B
Register name Read/Write Initial valuePort 0 Pull-up register (PUL0) R/W 00000000B
Port 1 Pull-up register (PUL1) R/W 00000000B
Port 2 Pull-up register (PUL2) R/W 00000000B
Port 3 Pull-up register (PUL3) R/W 00000000B
Port 4 Pull-up register (PUL4) R/W 00000000B
Port 5 Pull-up register (PUL5) R/W 00000000B
Port 7 Pull-up register (PUL7) R/W 00000000B
Port 8 Pull-up register (PUL8) R/W 00000000B
Port E Pull-up register (PULE) R/W 00000000B
Port G Pull-up register (PULG) R/W 00000000B
A/D input disable register high order (AIDRH) R/W 00000000B
A/D input disable register low order (AIDRL) R/W 00000000B
Input level selection register (ILSR) R/W 00000000B
Table 5.1-1 -Registers of Each Port (2 / 2)
Register name Read/Write Initial value
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CHAPTER 5 I/O Port
5.2 Port 0
Port 0 is a general-purpose I/O port.This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port 0 ConfigurationPort 0 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 0 data register (PDR0)
• Port 0 direction register (DDR0)
• Port 0 pull-up register (PUL0)
• A/D input disable register low order (AIDRL)
• Input level selection register (ILSR)
Pin at Port 0Port 0 has eight CMOS I/O pins.
See Table 5.2-1 to Table 5.2-4 for port 0 pins.
OD: Open drain, PU: Pull-up
Table 5.2-1 -Port 0 Pins (SAXOPHONE,TUBA,RESERVE1,BASSOON and CLARINET Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P00/INT00 P00 general-purpose I/O INT00 external interrupt input Hysteresis CMOS - -P01/INT01 P01 general-purpose I/O INT01 external interrupt input Hysteresis CMOS - -P02/INT02 P02 general-purpose I/O INT02 external interrupt input Hysteresis CMOS - -P03/INT03 P03 general-purpose I/O INT03 external interrupt input Hysteresis CMOS - -P04/INT04 P04 general-purpose I/O INT04 external interrupt input Hysteresis CMOS - -P05/INT05 P05 general-purpose I/O INT05 external interrupt input Hysteresis CMOS - -P06/INT06 P06 general-purpose I/O INT06 external interrupt input Hysteresis CMOS - -P07/INT07 P07 general-purpose I/O INT07 external interrupt input Hysteresis CMOS - -
240
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.2-2 Port 0 Pins (RESERVE2 and TRUMPET Series)
Pin name Function Dual Use Peripheral FunctionsI/O Type
Input Output OD PU
P00/INT00/AN00 P00 general-purpose I/OAN00 analog input
Hysteresis/analog CMOS - INT00 external interrupt input
P01/INT01/AN01 P01 general-purpose I/OAN01 analog input
Hysteresis/analog CMOS - INT01 external interrupt input
P02/INT02/AN02 P02 general-purpose I/OAN02 analog input
Hysteresis/analog CMOS - INT02 external interrupt input
P03/INT03/AN03 P03 general-purpose I/OAN03 analog input
Hysteresis/analog CMOS - INT03 external interrupt input
P04/INT04/AN04 P04 general-purpose I/OAN04 analog input
Hysteresis/analog CMOS - INT04 external interrupt input
P05/INT05/AN05 P05 general-purpose I/OAN05 analog input
Hysteresis/analog CMOS - INT05 external interrupt input
P06/INT06/AN06 P06 general-purpose I/OAN06 analog input
Hysteresis/analog CMOS - INT06 external interrupt input
P07/INT07/AN07 P07 general-purpose I/OAN07 analog input
Hysteresis/analog CMOS - INT07 external interrupt input
Table 5.2-3 Port 0 Pins (OBOE,FLUTE and PICCOLO Series)
Pin name Function Dual Use Peripheral FunctionsI/O Type
Input Output OD PU
P00/INT00/AN00/PPG00 P00 general-purpose I/OAN00 analog input
Hysteresis/analog CMOS - INT00 external interrupt input8/16-bit PPG ch0-0 output
P01/INT01/AN01/PPG01 P01 general-purpose I/OAN01 analog input
Hysteresis/analog CMOS - INT01 external interrupt input8/16-bit PPG ch0-1 output
P02/INT02/AN02/SCK P02 general-purpose I/OAN02 analog input
Hysteresis/analog CMOS - INT02 external interrupt inputLIN UART clock I/O
P03/INT03/AN03/SOT P03 general-purpose I/OAN03 analog input
Hysteresis/analog CMOS - INT03 external interrupt inputLIN UART data output
P04/INT04/AN04/SIN P04 general-purpose I/OAN04 analog input
Hysteresis/analog CMOS - INT04 external interrupt inputLIN UART data input
P05/INT05/AN05/TO00 P05 general-purpose I/OAN05 analog input
Hysteresis/analog CMOS - INT05 external interrupt input8/16-bit timer ch0-0 output
P06/INT06/AN06/TO01 P06 general-purpose I/OAN06 analog input
Hysteresis/analog CMOS - INT06 external interrupt input8/16-bit timer ch0-1 output
P07/INT07/AN07 P07 general-purpose I/OAN07 analog input
Hysteresis/analog CMOS - INT07 external interrupt input
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CHAPTER 5 I/O Port
OD: Open drain, PU: Pull-up
Table 5.2-4 Port 0 Pins (TROMBONE Series)
Pin name Function Dual Use Peripheral FunctionsI/O type
Input Output OD PU
P00/INT00/AN00/S31 P00 general-purpose I/OAN00 analog input
Hysteresis/analog CMOS/LCD - -INT00 external interrupt inputS31 LCDC SEG31 output
P01/INT01/AN01/S30 P01 general-purpose I/OAN01 analog input
Hysteresis/analog CMOS/LCD - -INT01 external interrupt inputS30 LCDC SEG30 output
P02/INT02/AN02/S29 P02 general-purpose I/OAN02 analog input
Hysteresis/analog CMOS/LCD - -INT02 external interrupt inputS29 LCDC SEG29 output
P03/INT03/AN03/S28 P03 general-purpose I/OAN03 analog input
Hysteresis/analog CMOS/LCD - -INT03 external interrupt inputS28 LCDC SEG28 output
P04/INT04/AN04/S27 P04 general-purpose I/OAN04 analog input
Hysteresis/analog CMOS/LCD - -INT04 external interrupt inputS27 LCDC SEG27 output
P05/INT05/AN05/S26 P05 general-purpose I/OAN05 analog input
Hysteresis/analog CMOS/LCD - -INT05 external interrupt inputS26 LCDC SEG26 output
P06/INT06/AN06/S25 P06 general-purpose I/OAN06 analog input
Hysteresis/analog CMOS/LCD - -INT06 external interrupt inputS25 LCDC SEG25 output
P07/INT07/AN07/S24 P07 general-purpose I/OAN07 analog input
Hysteresis/analog CMOS/LCD - -INT07 external interrupt inputS24 LCDC SEG24 output
242
Block Diagram of Port 0
Figure 5.2-1 Block Diagram of Port 0 (SAXOPHONE,TUBA,RESERVE1,BASSOON and CLARINET Series)
Figure 5.2-2 Block Diagram of Port 0 (RESERVE2 and TRUMPET Series)
PDR read
PDR write
PDR
DDR read
DDR write
DDR
0
1
Peripheral function input enablePeripheral function input
Pin
Stop, watch (SPL=1)
Inte
rnal
bus
At bit operation instruction
PDR
DDR
PUL
AIDR
0
1PDR read
PDR write
DDR read
DDR write
Peripheral function input enablePeripheral function input
Stop, watch (SPL=1)Inte
rnal
bus
At bit operation instruction
PUL read
PUL write
AIDR read
AIDR write
A/D analog input
Pull-up
Pin
243
CHAPTER 5 I/O Port
Figure 5.2-3 Block Diagram of Port 0 (OBOE,FLUTE and PICCOLO Series)
PDR read
PDR write
PDR
DDR read
DDR write
DDR
PUL read
PUL write
PUL
AIDR read
AIDR write
AIDR
0
11
0
Peripheral function outputPeripheral function output enable
Peripheral function input enablePeripheral function input
Pin
Stop, watch (SPL=1)
At bit operation instruction
A/D analog input
Pull-up
ILSR read
ILSR write
ILSR
Hysteresis
CMOS
Slectable only P04
Selectable only P04
Inte
rna
l b
us
244
Figure 5.2-4 Block Diagram of Port 0 (TROMBONE Series)
PDR read
PDR write
PDR
DDR read
DDR write
DDR
AIDR read
AIDR write
AIDR
0
1
Peripheral function input enablePeripheral function input
Pin
Stop, watch (SPL=1)
At bit operation instruction
A/D analog input
LCD output
LCD output enable
Inte
rnal bus
245
CHAPTER 5 I/O Port
5.2.1 Registers for Port 0
This section describes the registers associated with port 0.
Port 0 Register FunctionSee Table 5.2-5 for a list of port 0 register functions.
See Table 5.2-6 for details about the relationship between the port 0 pins and each register bit.
Table 5.2-5 Port 0 Register Function
Register name Data When being read During read-modify-write reading When being written
PDR0 0 The pin state is Low level. Value of PDR register is "0". Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1". Outputs "H" level for output port
DDR0 0 Port input enabled
1 Port output enabled
PUL0 0 Pull-up disabled
1 Pull-up enabled
AIDRL 0 Analog input enabled
1 Port input enabled
ILSR 0 Hysteresis input level selection
1 CMOS input level selection
Table 5.2-6 Relation between Port 0 Registers and Pins
Bits of Related Registers and Corresponding Pins
Pin name P07 P06 P05 P04 P03 P02 P01 P00
PDR0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DDR0
PUL0
AIDRL
ILSR - - - bit2 - - - -
246
5.2.2 Operation of Port 0
Here is described the behavior of port 0.
Operation of Port 0
Operation in output port mode
• When setting the corresponding bit of DDR register to "1", it becomes output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• Prohibit output in pins jointly used by a peripheral function.
• When using a pin jointly used for analog input as an input port, set the bit corresponding to the A/Dinput disable register low order (AIDRL) to "1".
• When using a pin jointly used for LCD as an input port, set the port input control bit (PICTL) of theLCDC enable register (LCDCE1) to "1". However, when setting the PICTL bit to "1", the pin that doesnot select as common pin and segment pin using the LCDC enable register (LCDCE 1 to 6) becomes allinput port. Be sure to select all usable common pins and segment pins before setting the PICTL bit to"1".
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Behavior during peripheral function output
• When the output enable bit of a peripheral function is set to enabled, the corresponding pin goes toperipheral function output.
• When the output of the peripheral function is enabled, the pin value is read by reading the PDR register.Consequently, it is possible to read the output value of a peripheral function by reading the PDRregister. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Behavior during peripheral function input
• Sets the DDR register bit corresponding to the peripheral function input pin to "0" to change to an inputport.
• As with input port, when a pin jointly used for analog input or LCD is used as another peripheralfunction input, configure it as an input port.
• When a PDR register is read, the value of the pin can be read, regardless of whether the peripheralfunction uses an input pin. Note, however, that for read-modify-write commands, the value of the PDRregister is read.
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CHAPTER 5 I/O Port
Operation when a reset is performed
• When the CPU is reset, the value of the DDR register is initialized to "0", and port input becomesenabled. Note that for pins jointly used for analog input and LCD output, the A/D input disable registerlow order (AIDRL) and LCDC enable register port input control bit (LCDCE1:PICTL) are initialized to"0". For this reason, port input is disabled.
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input. If, however,peripheral function input is enabled for external interrupt (INT07 to INT00) or the interrupt pin selectioncircuits (SCK/SIN), input is enabled and not blocked.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O, and theoutput level is maintained.
Operation in analog input mode
• Write "0" to the DDR register bit and AIDRL register bit corresponding to analog input pins.
• Prohibit output in pins jointly used by other peripheral functions.
Also write "0" to the corresponding PUL register bit.
Behavior of external interrupt input pins
• Sets the DDR register bit corresponding to the external interrupt input pin to "0".
• Prohibit output in pins jointly used by other peripheral functions.
• The pin value is always inputted into the external interrupt circuit. When using functions other than pininterrupt, disable the corresponding external interrupt.
Behavior during LCDC segment output
• Sets the DDR register bit corresponding to the LCDC segment output pin to "0".
• Prohibit output in pins jointly used by other peripheral functions.
• In the LCDC enable registers (LCDCE 1 to 6), select all common pins and segment pins you will use.
Behavior of the pull-up register
• When "1" is written to the PUL register, a pull-up register is internally connected to the pin. Note,however, that during "L" level output, the pull-up register is blocked regardless of the value of the PULregister.
Operation of input selection register (OBOE,FLUTE,PICCOLO series only)
• Writing "1" to bits 2 of ILSR register changes the input level for P04 only from hysteresis input level toCMOS input level. When bit 2 of the ILSR register is "0", it becomes the hysteresis input level.
• Pins other than P04 cannot select CMOS input level. Consequently, it becomes the hysteresis input levelonly.
• When the input level of P04 is switched, switch it with the peripheral function (LIN-UART/externalinterrupt) stopped.
248
See Table 5.2-7 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.2-7 Port 0 Pin Status
Operating State
Normal OperationSleep
Stop (SPL=0) Watch (SPL=0)
Stop (SPL=1)Watch (SPL=1)
At a reset
Pin state I/O port/peripheral function I/O
Hi-Z(Note, however, that pull-up setting is in effect)Input cutoff(Note, however, that if external interrupts are enabled, only external interrupts can be input)
Hi-ZInput enabled (however, does not function) (SAXOPHONE, TUBA, RESERVE1, BASSOON, CLARINET series) Input disabled (RESERVE2, TRUMPET, OBOE,FLUTE, PICCOLO, TROMBONE series)
249
CHAPTER 5 I/O Port
5.3 Port 1
Port 5 is a general-purpose I/O port.This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port 1 ConfigurationPort 1 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 1 data register (PDR1)
• Port 1 direction register (DDR1)
• Port 1 pull-up register (PUL1)
• Input level selection register (ILSR)
Pin at Port 1See Table 5.3-1 to Table 5.3-5 for port 1 pins.
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.3-1 Port 1 Pins (SAXOPHONE Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P10/UI0 P10 general-purpose I/O UI0 UART/SIO ch0 data input Hysteresis/CMOS CMOS -
P11/UO0 P11 general-purpose I/O UO0 UART/SIO ch0 data output Hysteresis/CMOS CMOS -
P12/UCK0 P12 general-purpose I/O UCK0 UART/SIO ch0 clock I/O Hysteresis/CMOS CMOS -
P13/TRG0/ADTG P13 general-purpose I/OTRG0 16-bit PPG ch0 trigger input Hysteresis/CMOS
CMOS - ADTG A/D trigger start input Hysteresis/CMOS
P14/PPG0 P14 general-purpose I/O PPG0 16-bit PPG ch0 output Hysteresis/CMOS CMOS -
P15 P15 general-purpose I/O No dual use Hysteresis/CMOS CMOS -
P16 P16 general-purpose I/O No dual use Hysteresis/CMOS CMOS -
Table 5.3-2 Port 1 Pins (CLARINET Series)
Pin name Function Dual Use Peripheral FunctionsI/O type
Input Output OD PU
P10/UI0 P10 general-purpose I/O UI0 UART/SIO ch0 data input Hysteresis/CMOS CMOS -
P11/UO0 P11 general-purpose I/O UO0 UART/SIO ch0 data output Hysteresis CMOS -
P12/UCK0 P12 general-purpose I/O UO0 UART/SIO ch0 clock I/O Hysteresis CMOS -
P13/TRG0/ADTG P13 general-purpose I/OTRG0 16-bit PPG ch0 trigger input
Hysteresis CMOS - ADTG A/D trigger start input
P14/PPG0 P14 general-purpose I/O PPG0 16-bit PPG ch0 output Hysteresis CMOS -
P15 P15 general-purpose I/O No dual use Hysteresis CMOS -
250
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.3-3 Port 1 Pins (TUBA,RESERVE1,RESERVE2,BASSOON,TROMBONE and TRUMPET Series)
Pin name Function Dual Use Peripheral FunctionsI/O type
Input Output OD PU
P10/UI0 P10 general-purpose I/O UI0 UART/SIO ch0 data input Hysteresis/CMOS CMOS -
P11/UO0 P11 general-purpose I/O UO0 UART/SIO ch0 data output Hysteresis CMOS -
P12/UCK0 P12 general-purpose I/O UO0 UART/SIO ch0 clock I/O Hysteresis CMOS -
P13/TRG0/ADTG P13 general-purpose I/OTRG0 16-bit PPG ch0 trigger input
Hysteresis CMOS - ADTG A/D trigger start input
P14/PPG0 P14 general-purpose I/O PPG0 16-bit PPG ch0 output Hysteresis CMOS -
Table 5.3-4 Port 1 Pins (OBOE and PICCOLO Series)
Pin name Function Dual Use Peripheral FunctionsI/O type
Input Output OD PU
P10/UI0 P10 general-purpose I/O UI0 UART/SIO ch0 data input Hysteresis/CMOS CMOS -
P11/UO0 P11 general-purpose I/O UO0 UART/SIO ch0 data output Hysteresis CMOS -
P12/UCK0/EC0 P12 general-purpose I/OUO0 UART/SIO ch0 clock I/O
Hysteresis CMOS - EC0 8/16-bit TIM ch0 clock input
P13/TRG0/ADTG P13 general-purpose I/OTRG0 16-bit PPG ch0 trigger input
Hysteresis CMOS - ADTG A/D trigger start input
P14/PPG0 P14 general-purpose I/O PPG0 16-bit PPG ch0 output Hysteresis CMOS -
Table 5.3-5 Port 1 Pins (FLUTE Series)
Pin name Function Dual Use Peripheral FunctionsI/O Type
Input Output OD PU
P10/UI0 P10 general-purpose I/O UI0 UART/SIO ch0 data input Hysteresis/CMOS CMOS -
P11/UO0 P11 general-purpose I/O UO0 UART/SIO ch0 data output Hysteresis CMOS -
P12/UCK0/EC0 P12 general-purpose I/OUO0 UART/SIO ch0 clock I/O
Hysteresis CMOS - EC0 8/16-bit TIM ch0 clock input
P13/TRG0/ADTG P13 general-purpose I/OTRG0 16-bit PPG ch0 trigger input
Hysteresis CMOS - ADTG A/D trigger start input
P14/PPG0 P14 general-purpose I/O PPG0 16-bit PPG ch0 output Hysteresis CMOS -
P15 P15 general-purpose I/O No dual use Hysteresis CMOS -
P16 P16 general-purpose I/O No dual use Hysteresis CMOS -
251
CHAPTER 5 I/O Port
Block Diagram of Port 1
Figure 5.3-1 Block Diagram of Port 1
PDR read
PDR write
PDR
DDR read
DDR write
DDR
PUL read
PUL write
PUL
AIDR read
AIDR write
AIDR
0
11
0
Peripheral function outputPeripheral function output enable
Peripheral function input enablePeripheral function input
Pin
Stop, watch (SPL=1)
At bit operation instruction
Pull-up
ILSR read
ILSR write
ILSR
Hysteresis
CMOS
Selectable only P10
Selectable only P10
Selectable only P10,P12,P13
Inte
rna
l b
us
252
5.3.1 Registers for Port 1
This section describes the registers associated with port 3.
Port 1 Register FunctionSee Table 5.3-6 for a list of port 1 register functions.
See Table 5.3-7 for details about the relationship between the port 1 pins and each register bit.
Table 5.3-6 Function of Registers for Port 1
Register name Data When being read During read-modify-write reading When being written
PDR10 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port
DDR10 Port input enabled
1 Port output enabled
PUL10 Pull-up disabled
1 Pull-up enabled
ILSR0 Hysteresis input level selection
1 CMOS input level selection
Table 5.3-7 The Correspondence between the Registers and Pins of Port 1
Bits of Related Registers and Corresponding Pins
Pin name - P16 P15 P14 P13 P12 P11 P10
PDR1
- bit6 bit5 bit4 bit3 bit2 bit1 bit0DDR1
PUL1
ILSR - - - - - - - bit0
253
CHAPTER 5 I/O Port
5.3.2 Operation of Port 1
Here is described the behavior of port 1.
Operation of Port 1
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• Prohibit output in pins jointly used by a peripheral function.
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Behavior during peripheral function output
• When the output enable bit of a peripheral function is set to enabled, the corresponding pin goes toperipheral function output.
• When the output of the peripheral function is enabled, the pin value is read by reading the PDR register.Consequently, it is possible to read the output value of a peripheral function by reading the PDRregister. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Behavior during peripheral function input
• Sets the DDR register bit corresponding to the peripheral function input pin to "0" to change to an inputport.
• When a PDR register is read, the value of the pin can be read, regardless of whether the peripheralfunction uses an input pin. Note, however, that for read-modify-write commands, the value of the PDRregister is read.
Operation when a reset is performed
• When the CPU is reset, the value of the DDR register is initialized to "0", and port input becomesenabled.
254
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input. If, however,peripheral function input is enabled for the interrupt pin selection circuit (UI0,UCK0,TRG0/ADTG,EC0), input is enabled and not blocked.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O, and theoutput level is maintained.
Behavior of the pull-up register
• When "1" is written to the PUL register, a pull-up register is internally connected to the pin. Note,however, that during "L" level output, the pull-up register is blocked regardless of the value of the PULregister.
Behavior of the input level selection register
• Writing "1" to bit 0 of ILSR register changes the input level for P10 only from hysteresis input level toCMOS input level. When bit 0 of the ILSR register is "0", it becomes the hysteresis input level.
• Pins other than P10 cannot select CMOS input level. Consequently, it becomes the hysteresis input levelonly.
• When changing the P10 input level, change the peripheral function (UART/SIO) state to stopped.
See Table 5.3-8 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.3-8 Port 1 Pin Status
Operating State
Normal OperationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin state I/O port/peripheral function I/OHi-Z
(Note, however, that pull-up setting is in effect)Input cutoff
Hi-ZPossible to input
(However, do not function)
255
CHAPTER 5 I/O Port
5.4 Port 2
Port 2 is a general-purpose I/O port.This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port 2 ConfigurationPort 2 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 2 data register (PDR2)
• Port 2 direction register (DDR2)
• Port 2 pull-up register (PUL2)
• Input level selection register (ILSR)
Pin at Port 2See Table 5.4-1 to Table 5.4-4 for port 2 pins.
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.4-1 Port 2 Pins (SAXOPHONE Series)
Pin name Function Dual Use Peripheral FunctionsI/O type
Input Output OD PU
P20/PPG00 P20 general-purpose I/O PPG00 8/16-bit PPG ch0-0 data output Hysteresis CMOS -
P21/PPG01 P21 general-purpose I/O PPG01 8/16-bit PPG ch0-1 data output Hysteresis CMOS -
P22/TO00 P22 general-purpose I/O TO00 8/16-bit TIM ch0-0 clock output Hysteresis CMOS -
P23/TO01 P23 general-purpose I/O TO01 8/16-bit TIM ch0-1 clock output Hysteresis CMOS -
P24/EC0 P24 general-purpose I/O EC0 8/16-bit TIM ch0 external clock input Hysteresis CMOS -
P25/PPG2 P25 general-purpose I/O PPG2 16-bit PPG ch2 data output Hysteresis CMOS -
P26/TRG2 P26 general-purpose I/O PPG2 16-bit PPG ch2 trigger input Hysteresis CMOS -
P27 P27 general-purpose I/O No dual use Hysteresis CMOS -
Table 5.4-2 Port 2 Pins (RESERVE1 Series)
Pin name Function Dual Use Peripheral FunctionsI/O type
Input Output OD PU
P20/PPG00 P20 general-purpose I/O PPG00 8/16-bit PPG ch0-0 data output Hysteresis CMOS -
P21/PPG01 P21 general-purpose I/O PPG01 8/16-bit PPG ch0-1 data output Hysteresis CMOS -
P22/TO00 P22 general-purpose I/O TO00 8/16-bit TIM ch0-0 clock output Hysteresis CMOS -
P23/TO01 P23 general-purpose I/O TO01 8/16-bit TIM ch0-1 clock output Hysteresis CMOS -
P24/EC0 P24 general-purpose I/O EC0 8/16-bit TIM ch0 external clock input Hysteresis CMOS -
P25/PPG2 P25 general-purpose I/O PPG2 16-bit PPG ch2 data output Hysteresis CMOS -
P26/TRG2 P26 general-purpose I/O PPG2 16-bit PPG ch2 trigger input Hysteresis CMOS -
256
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.4-3 Port 2 Pins (TUBA,RESERVE2,BASSOON and CLARINET Series)
Pin name Function Dual Use Peripheral FunctionsI/O type
Input Output OD PU
P20/PPG00 P20 general-purpose I/O PPG00 8/16-bit PPG ch0-0 data output Hysteresis CMOS -
P21/PPG01 P21 general-purpose I/O PPG01 8/16-bit PPG ch0-1 data output Hysteresis CMOS -
P22/TO00 P22 general-purpose I/O TO00 8/16-bit TIM ch0-0 clock output Hysteresis CMOS -
P23/TO01 P23 general-purpose I/O TO01 8/16-bit TIM ch0-1 clock output Hysteresis CMOS -
P24/EC0 P24 general-purpose I/O EC0 8/16-bit TIM ch0 external clock input Hysteresis CMOS -
Table 5.4-4 Port 2 Pins (TROMBONE Series)
Pin name Function Dual Use Peripheral FunctionsI/O type
Input Output OD PU
P20/PPG00 P20 general-purpose I/O PPG00 8/16-bit PPG ch0-0 data output Hysteresis CMOS -
P21/PPG01 P21 general-purpose I/O PPG01 8/16-bit PPG ch0-1 data output Hysteresis CMOS -
P22/TO00 P22 general-purpose I/O TO00 8/16-bit TIM ch0-0 clock output Hysteresis CMOS -
P23/TO01/SCL0 P23 general-purpose I/OTO01 8/16-bit TIM ch0-1 clock output
Hysteresis/CMOS CMOS -SCL0 IIC ch0 clock I/O
P24/EC0/SDA0 P24 general-purpose I/OEC0 8/16-bit TIM ch0 external clock input
Hysteresis/CMOS CMOS -SDA0 IIC ch0 data I/O
257
CHAPTER 5 I/O Port
Block Diagram of Port 2
Figure 5.4-1 Block Diagram of Port 2 (SAXOPHONE,TUBA,RESERVE1,RESERVE2,BASSOON,CLARINET Series and without P23 and P24 in TROMBONE Series)
Figure 5.4-2 Block Diagram of Port 2 (Only P24 and P23 in TROMBONE Series)
PDR read
PDR write
PDR
DDR read
DDR write
DDR
PUL read
PUL write
PUL
0
11
0Pin
Stop, watch (SPL=1)
At bit operation instruction
Pull-up
Selectable only P24
Peripheral function inputPeripheral function input enable
Peripheral function outputPeripheral function output enable
Inte
rnal
bus
PDR read
PDR write
PDR
DDR read
DDR write
DDR
ILSR read
ILSR write
ILSR
0
11
0 ODP24 and P23 only
CMOS Pin
Stop, watch (SPL=1)
At bit operation instruction
Hysteresis
Peripheral function input
Peripheral function output enablePeripheral function output
Inte
rnal
bus
Peripheral function input enable
258
5.4.1 Registers for Port 2
This section describes the registers associated with port 2.
Port 2 Register FunctionSee Table 5.4-5 for a list of port 2 register functions.
*: For Nch open drain pin, this will be Hi-Z.
See Table 5.4-6 for details about the relationship between the port 2 pins and each register bit.
Table 5.4-5 Function of Registers for Port 2
Register name Data When being read During read-modify-write reading When being written
PDR20 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port*
DDR20 Port input enabled
1 Port output enabled
PUL20 Pull-up disabled
1 Pull-up enabled
ILSR0 Hysteresis input level selection
1 CMOS input level selection
Table 5.4-6 The Correspondence between the Registers and Pins of Port 2.
Bits of Related Registers and Corresponding Pins
Pin name P27 P26 P25 P24 P23 P22 P21 P20
PDR2
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0DDR2
PUL2
ILSR - - - bit4 bit3 - - -
259
CHAPTER 5 I/O Port
5.4.2 Operation of Port 2
Here is described the behavior of port 2.
Operation of Port 2
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When "0" is written for the corresponding bit of the DDR register, the pin functions as an input port.
• Prohibit output in pins jointly used by a peripheral function.
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Behavior during peripheral function output
• When the output enable bit of a peripheral function is set to enabled, the corresponding pin goes toperipheral function output.
• When the output of the peripheral function is enabled, the pin value is read by reading the PDR register.Consequently, it is possible to read the output value of a peripheral function by reading the PDRregister. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Behavior during peripheral function input
• Sets the DDR register bit corresponding to the peripheral function input pin to "0" to change to an inputport.
• When a PDR register is read, the value of the pin can be read, regardless of whether the peripheralfunction uses an input pin. Note, however, that for read-modify-write commands, the value of the PDRregister is read.
Operation when a reset is performed
• When the CPU is reset, the value of the DDR register is initialized to "0", and port input becomesenabled.
260
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input. If, however,peripheral function input is enabled for the interrupt pin selection circuit (EC0), input is enabled and notblocked.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O, and theoutput level is maintained.
Behavior of the pull-up register
• When "1" is written to the PUL register, a pull-up register is internally connected to the pin. Note,however, that during "L" level output, the pull-up register is blocked regardless of the value of the PULregister.
Behavior of the input level selection register (TROMBONE series only)
• Writing "1" to bits 4 and 3 of ILSR register changes the input level for P24 and P23 only from hysteresisinput level to CMOS input level. When bits 4 and 3 of the ILSR register is "0", it becomes the hysteresisinput level.
• Pins other than P24 and P23 cannot select CMOS input level. Consequently, it becomes the hysteresisinput level only.
• When changing the P24 and P23 input level, change the peripheral function (I2C0) state to stopped.
See Table 5.4-7 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.4-7 Port 2 Pin Status
Operating State
Normal OperationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin state I/O port/peripheral function I/OHi-Z
(Note, however, that pull-up setting is in effect)Input cutoff
Hi-ZPossible to input
(However, do not function)
261
CHAPTER 5 I/O Port
5.5 Port 3
Port 3 is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port 3 ConfigurationPort 3 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 3 data register (PDR3)
• Port 3 direction register (DDR3)
• Port 3 pull-up register (PUL3)
• A/D input disable register low order (AIDRL)
Pin at Port 3Port 3 has eight I/O pins.
See Table 5.5-1 for port 3 pins.
OD: Open drain, PU: Pull-up
Table 5.5-1 Port 3 Pins (SAXOPHONE,TUBA,RESERVE1,BASSOON and CLARINET Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P30/AN00 P30 general-purpose I/O AN00 analog input Hysteresis /analog/ CMOS -
P31/AN01 P31 general-purpose I/O AN01 analog input Hysteresis /analog/ CMOS -
P32/AN02 P32 general-purpose I/O AN02 analog input Hysteresis /analog/ CMOS -
P33/AN03 P33 general-purpose I/O AN03 analog input Hysteresis /analog/ CMOS -
P34/AN04 P34 general-purpose I/O AN04 analog input Hysteresis /analog/ CMOS -
P35/AN05 P35 general-purpose I/O AN05 analog input Hysteresis /analog/ CMOS -
P36/AN06 P36 general-purpose I/O AN06 analog input Hysteresis /analog/ CMOS -
P37/AN07 P37 general-purpose I/O AN07 analog input Hysteresis /analog/ CMOS -
262
Block Diagram of Port 3
Figure 5.5-1 Block Diagram of Port 3
PDR read
PDR write
PDR
DDR read
DDR write
DDR
PUL read
PUL write
PUL
AIDR read
AIDR write
AIDR
0
1
Pin
Stop, watch (SPL=1)
At bit operating instruction
Pull-up
A/D analog inputIn
tern
al b
us
263
CHAPTER 5 I/O Port
5.5.1 Registers for Port 3
This section describes the registers associated with port 3.
Port 3 Register FunctionSee Table 5.5-2 for a list of port 3 register functions.
See Table 5.5-3 for details about the relationship between the port 3 pins and each register bit.
Table 5.5-2 Function of Registers for Port 3
Register name Data When being read During read-modify-write reading When being written
PDR30 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port
DDR30 Port input enabled
1 Port output enabled
PUL30 Pull-up disabled
1 Pull-up enabled
AIDRL0 Analog input enabled
1 Port input enabled
Table 5.5-3 Correspondence between Registers and Pins for Port 3
Bits of Related Registers and Corresponding Pins
Pin name P37 P36 P35 P34 P33 P32 P31 P30
PDR3
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0DDR3
PUL3
AIDRL
264
5.5.2 Operation of Port 3
Here is described the behavior of port 3.
Operation of Port 3
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• Prohibit output in pins jointly used by a peripheral function.
• When using a pin jointly used for analog input as an input port, set the bit corresponding to the A/Dinput disable register low order (AIDRL) to "1".
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Operation when a reset is performed
• When the CPU is reset, the values of the DDR register and AIDRL register are initialized to "0", andport input becomes disabled.
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O, and theoutput level is maintained.
Operation in analog input mode
• Write "0" to the DDR register bit and AIDRL register bit corresponding to analog input pins.
• Prohibit output in pins jointly used by other peripheral functions. Also write "0" to the correspondingPUL register bit.
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CHAPTER 5 I/O Port
Behavior of the pull-up register
• When "1" is written to the PUL register, a pull-up register is internally connected to the pin. Note,however, that during "L" level output, the pull-up register is blocked regardless of the value of the PULregister.
See Table 5.5-4 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.5-4 Port 3 Pin Status
Operating State
Normal OperationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin state I/O port/analog inputHi-Z
(Note, however, that pull-up setting is in effect)Input cutoff
Hi-ZInput disabled
266
5.6 Port 4
Port 4 is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port 4 ConfigurationPort 4 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 4 data register (PDR4)
• Port 4 direction register (DDR4)
• Port 4 pull-up register (PUL4)
• A/D input disable register high order (AIDRH)
Pin at Port 4See Table 5.6-1 and Table 5.6-2 for port 4 pins.
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.6-1 Port 4 Pins (SAXOPHONE and RESERVE1 Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P40/AN08 P40 general-purpose I/O AN08 analog input Hysteresis/analog CMOS -
P41/AN09 P41 general-purpose I/O AN09 analog input Hysteresis/analog CMOS -
P42/AN10 P42 general-purpose I/O AN10 analog input Hysteresis/analog CMOS -
P43/AN11 P43 general-purpose I/O AN11 analog input Hysteresis/analog CMOS -
P44/AN12 P44 general-purpose I/O AN12 analog input Hysteresis/analog CMOS -
P45/AN13 P45 general-purpose I/O AN13 analog input Hysteresis/analog CMOS -
P46/AN14 P46 general-purpose I/O AN14 analog input Hysteresis/analog CMOS -
P47/AN15 P47 general-purpose I/O AN15 analog input Hysteresis/analog CMOS -
Table 5.6-2 Port 4 Pins (TUBA,RESERVE2 and BASSOON Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P40/AN08 P40 general-purpose I/O AN08 analog input Hysteresis/analog CMOS -
P41/AN09 P41 general-purpose I/O AN09 analog input Hysteresis/analog CMOS -
P42/AN10 P42 general-purpose I/O AN10 analog input Hysteresis/analog CMOS -
P43/AN11 P43 general-purpose I/O AN11 analog input Hysteresis/analog CMOS -
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CHAPTER 5 I/O Port
Block Diagram of Port 4
Figure 5.6-1 Block Diagram of Port 4
PDR read
PDR write
PDR
DDR read
DDR write
DDR
PUL read
PUL write
PUL
AIDR read
AIDR write
AIDR
0
1
Pin
Stop, watch (SPL=1)
At bit operation instruction
Pull-up
A/D analog input
Inte
rnal
bus
268
5.6.1 Registers for Port 4
This section describes the registers associated with port 4.
Port 4 Register FunctionSee Table 5.6-3 for a list of port 4 register functions.
See Table 5.6-4 for details about the relationship between the port 4 pins and each register bit.
Table 5.6-3 Function of Registers for Port 4
Register name Data When being read During read-modify-write reading When being written
PDR40 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "0" Outputs "H" level for output port
DDR40 Port input enabled
1 Port output enabled
PUL40 Pull-up disabled
1 Pull-up enabled
AIDRH0 Analog input enabled
1 Port input enabled
Table 5.6-4 Correspondence between Registers and Pins for Port 4
Bits of Related Registers and Corresponding Pins
Pin Name P47 P46 P45 P44 P43 P42 P41 P40
PDR4
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0DDR4
PUL4
AIDRH
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CHAPTER 5 I/O Port
5.6.2 Operation of Port 4
Here is described the behavior of port 4.
Operation of Port 4
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• Prohibit output in pins jointly used by a peripheral function.
• When using a pin jointly used for analog input as an input port, set the bit corresponding to the A/Dinput disable register high order (AIDRH) to "1".
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Operation when a reset is performed
• When the CPU is reset, the values of the DDR register and AIDRH register are initialized to "0", andport input becomes disabled.
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O, and theoutput level is maintained.
Operation in analog input mode
• Write "0" to the DDR register bit and AIDRL register bit corresponding to analog input pins.
• Prohibit output in pins jointly used by other peripheral functions. Also write "0" to the corresponding PUL register bit.
Behavior of the pull-up register
• When "1" is written to the PUL register, a pull-up register is internally connected to the pin. Note,however, that during "L" level output, the pull-up register is blocked regardless of the value of the PULregister.
270
See Table 5.6-5 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.6-5 Port 4 Pin Status
Operating state
Normal operationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin state I/O port/analog inputHi-Z
(Note, however, that pull-up setting is in effect)Input cutoff
Hi-ZInput disabled
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CHAPTER 5 I/O Port
5.7 Port 5
Port 5 is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port 5 ConfigurationPort 5 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 5 data register (PDR5)
• Port 5 direction register (DDR5)
• Port 5 pull-up register (PUL5)
• Input level selection register (ILSR)
Pin at Port 5See Table 5.7-1 to Table 5.7-3 for port 5 pins.
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.7-1 Port 5 Pins (SAXOPHONE and RESERVE1 Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P50/SCL0 P50 general-purpose I/O SCL0 IIC ch0 clock I/O Hysteresis/CMOS CMOS -
P51/SDA0 P51 general-purpose I/O SDA0 IIC ch0 data I/O Hysteresis/CMOS CMOS -
P52/PPG1 P52 general-purpose I/O PPG1 16-bit PPG ch1 output Hysteresis CMOS -
P53/TRG1 P53 general-purpose I/O TRG1 16-bit PPG ch1 trigger input Hysteresis CMOS -
P54/TO1 P54 general-purpose I/O TO1 16-bit TIM ch1 output Hysteresis CMOS -
P55/TI1 P55 general-purpose I/O TI1 16-bit TIM ch1 trigger input Hysteresis CMOS -
Table 5.7-2 Port 5 Pins (TUBA,RESERVE2 and BASSOON Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P50/SCL0 P50 general-purpose I/O SCL0 IIC ch0 clock I/O Hysteresis/CMOS CMOS -
P51/SDA0 P51 general-purpose I/O SDA0 IIC ch0 data I/O Hysteresis/CMOS CMOS -
P52/PPG1 P52 general-purpose I/O PPG1 16-bit PPG ch1 output Hysteresis CMOS -
P53/TRG1 P53 general-purpose I/O TRG1 16-bit PPG ch1 trigger input Hysteresis CMOS -
272
OD: Open drain, PU: Pull-up
Table 5.7-3 Port 5 Pins (CLARINET Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P50/SCL0 P50 general-purpose I/O SCL0 IIC ch0 clock I/O Hysteresis/CMOS CMOS -
P51/SDA0 P51 general-purpose I/O SDA0 IIC ch0 data I/O Hysteresis/CMOS CMOS -
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CHAPTER 5 I/O Port
Block Diagram of Port 5
Figure 5.7-1 Block Diagram of Port 5 (without P51 and P50)
Figure 5.7-2 Block Diagram of Port 5 (Only P51 and P50)
PDR read
PDR write
PDR
DDR read
DDR write
DDR
PUL read
PUL write
PUL
0
11
0Pin
Stop, watch (SPL=1)
At bit operation instruction
Pull-up
Peripheral function input
Peripheral function output enablePeripheral function output
Inte
rnal
bus
PDR read
PDR write
PDR
DDR read
DDR write
DDR
ILSR read
ILSR write
ILSR
0
11
0 ODP50 and P51 only
CMOS Pin
Stop, watch (SPL=1)
At bit operation instruction
Hysteresis
Peripheral function input
Peripheral function output enablePeripheral function output
Inte
rnal
bus
Peripheral function input enable
274
5.7.1 Registers for Port 5
This section describes the registers associated with port 5.
Port 5 Register FunctionSee Table 5.7-4 for a list of port 5 register functions.
*: For Nch open drain pin, this will be Hi-Z.
See Table 5.7-5 for details about the relationship between the port 5 pins and each register bit.
Table 5.7-4 Function of Registers for Port 5
Register name Data When being read During read-modify-write reading When being written
PDR50 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port*
DDR50 Port input enabled
1 Port output enabled
PUL50 Pull-up disabled
1 Pull-up enabled
ILSR0 Hysteresis input level selection
1 CMOS input level selection
Table 5.7-5 Correspondence between Registers and Pins for Port 5
Bits of related registers and corresponding pins
Pin name - - P55 P54 P53 P52 P51 P50
PDR5
- - bit5 bit4 bit3 bit2bit1 bit0
DDR5
PUL5 - -
ILSR - - - - - - bit4 bit3
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CHAPTER 5 I/O Port
5.7.2 Operation of Port 5
Here is described the behavior of port 5.
Operation of Port 5
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• Prohibit output in pins jointly used by a peripheral function.
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register.Note, however, that for read-modify-writecommands, the value of the PDR register is read.
Behavior during peripheral function output
• When the output enable bit of a peripheral function is set to enabled, the corresponding pin goes toperipheral function output.
• When the output of the peripheral function is enabled, the pin value is read by reading the PDR register.Consequently, it is possible to read the output value of a peripheral function by reading the PDRregister. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Behavior during peripheral function input
• Sets the DDR register bit corresponding to the peripheral function input pin to "0" to change to an inputport.
• When a PDR register is read, the value of the pin can be read, regardless of whether the peripheralfunction uses an input pin. Note, however, that for read-modify-write commands, the value of the PDRregister is read.
Operation when a reset is performed
• When the CPU is reset, the value of the DDR register is initialized to "0", and port input becomesenabled.
276
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input. If, however,peripheral function input (SCL0/SDA0) is enabled, input is enabled and not blocked.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O, and theoutput level is maintained.
Behavior of the pull-up register
• When "1" is written to the PUL register, a pull-up register is internally connected to the pin. Note,however, that during "L" level output, the pull-up register is blocked regardless of the value of the PULregister.
Behavior of the input level selection register
• Writing "1" to bits 4 and 3 of ILSR register changes the input level for P51/P50 only from hysteresisinput level to CMOS input level. When bits 4 and 3 of the ILSR register is "0", it becomes the hysteresisinput level.
• Pins other than P51 and P50 cannot select CMOS input level. Consequently, it becomes the hysteresisinput level only.
• When changing the P51 and P50 input levels, change the peripheral function (I2C0) state to stopped.
The state of the port pins shows in Table 5.7-6 .
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.7-6 Port 5 Pin Status
Operating State
Normal OperationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin state I/O port/peripheral function I/OHi-Z
(Note, however, that pull-up setting is in effect)Input cutoff
Hi-ZInput disabled
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CHAPTER 5 I/O Port
5.8 Port 6
Port 6 is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port 6 ConfigurationPort 6 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 6 data register (PDR6)
• Port 6 direction register (DDR6)
• Input level selection register (ILSR)
Pin at Port 6Port 6 has eight CMOS I/O pins.
See Table 5.8-1 to Table 5.8-5 for port 6 pins.
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.8-1 Port 6 Pins (SAXOPHONE,RESERVE1,BASSOON and CLARINET Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P60/PPG10 P60 general-purpose I/O PPG10 8/16-bit PPG ch1-0 output Hysteresis CMOS - -
P61/PPG11 P61 general-purpose I/O PPG11 8/16-bit PPG ch1-1 output Hysteresis CMOS - -
P62/TO10 P62 general-purpose I/O TO10 8/16-bit TIM ch1-0 output Hysteresis CMOS - -
P63/TO11 P63 general-purpose I/O TO11 8/16-bit TIM ch1-1 output Hysteresis CMOS - -
P64/EC1 P64 general-purpose I/O EC1 8/16-bit TIM ch1 clock input Hysteresis CMOS - -
P65/SCK P65 general-purpose I/O LIN UART clock I/O Hysteresis CMOS - -
P66/SOT P66 general-purpose I/O LIN UART data output Hysteresis CMOS - -
P67/SIN P67 general-purpose I/O LIN UART data input Hysteresis/CMOS CMOS - -
Table 5.8-2 Port 6 Pins (OBOE Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P60/PPG10 P60 general-purpose I/O PPG10 8/16-bit PPG ch1-0 output Hysteresis CMOS - -
P61/PPG11 P61 general-purpose I/O PPG11 8/16-bit PPG ch1-1 output Hysteresis CMOS - -
P62/TO10 P62 general-purpose I/O TO10 8/16-bit TIM ch1-0 output Hysteresis CMOS - -
P63/TO11 P63 general-purpose I/O TO11 8/16-bit TIM ch1-1 output Hysteresis CMOS - -
P64/EC1 P64 general-purpose I/O EC1 8/16-bit TIM ch1 clock input Hysteresis CMOS - -
278
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.8-3 Port 6 Pins (TUBA Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P60/PPG10/S32 P60 general-purpose I/OPPG10 8/16-bit PPG ch1-0 output
Hysteresis CMOS/LCD - -S32 LCDC SEG32 output
P61/PPG11/S33 P61 general-purpose I/OPPG11 8/16-bit PPG ch1-1 output
Hysteresis CMOS/LCD - -S33 LCDC SEG33 output
P62/TO10/S34 P62 general-purpose I/OTO10 8/16-bit TIM ch1-0 output
Hysteresis CMOS/LCD - -S34 LCDC SEG34 output
P63/TO11/S35 P63 general-purpose I/OTO11 8/16-bit TIM ch1-1 output
Hysteresis CMOS/LCD - -S35 LCDC SEG35 output
P64/EC1/S36 P64 general-purpose I/OEC1 8/16-bit TIM ch1 clock input
Hysteresis CMOS/LCD - -S36 LCDC SEG36 output
P65/SCK/S37 P65 general-purpose I/OLIN UART clock I/O
Hysteresis CMOS/LCD - -S37 LCDC SEG37 output
P66/SOT/S38 P66 general-purpose I/OLIN UART data output
Hysteresis CMOS/LCD - -S38 LCDC SEG38 output
P67/SIN/S39 P67 general-purpose I/OLIN UART data input
Hysteresis/CMOS CMOS/LCD - -S39 LCDC SEG39 output
Table 5.8-4 Port 6 Pins (RESERVE2 and TROMBONE Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P60/PPG10/S16 P60 general-purpose I/OPPG10 8/16-bit PPG ch1-0 output
Hysteresis CMOS/LCD - -S16 LCDC SEG16 output
P61/PPG11/S17 P61 general-purpose I/OPPG11 8/16-bit PPG ch1-1 output
Hysteresis CMOS/LCD - -S17 LCDC SEG17 output
P62/TO10/S18 P62 general-purpose I/OTO10 8/16-bit TIM ch1-0 output
Hysteresis CMOS/LCD - -S18 LCDC SEG18 output
P63/TO11/S19 P63 general-purpose I/OTO11 8/16-bit TIM ch1-1 output
Hysteresis CMOS/LCD - -S19 LCDC SEG19 output
P64/EC1/S20 P64 general-purpose I/OEC1 8/16-bit TIM ch1 clock input
Hysteresis CMOS/LCD - -S20 LCDC SEG20 output
P65/SCK/S21 P65 general-purpose I/OLIN UART clock I/O
Hysteresis CMOS/LCD - -S21 LCDC SEG21 output
P66/SOT/S22 P66 general-purpose I/OLIN UART data output
Hysteresis CMOS/LCD - -S22 LCDC SEG22 output
P67/SIN/S23 P67 general-purpose I/OLIN UART data input
Hysteresis/CMOS CMOS/LCD - -S23 LCDC SEG23 output
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CHAPTER 5 I/O Port
OD: Open drain, PU: Pull-up
Table 5.8-5 Port 6 Pins (TRUMPET Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P60/PPG10/S08 P60 general-purpose I/OPPG10 8/16-bit PPG ch1-0 output
Hysteresis CMOS/LCD - -S08 LCDC SEG08 output
P61/PPG11/S09 P61 general-purpose I/OPPG11 8/16-bit PPG ch1-1 output
Hysteresis CMOS/LCD - -S09 LCDC SEG09 output
P62/TO10/S10 P62 general-purpose I/OTO10 8/16-bit TIM ch1-0 output
Hysteresis CMOS/LCD - -S10 LCDC SEG10 output
P63/TO11/S11 P63 general-purpose I/OTO11 8/16-bit TIM ch1-1 output
Hysteresis CMOS/LCD - -S11 LCDC SEG11 output
P64/EC1/S12 P64 general-purpose I/OEC1 8/16-bitTIM ch1 clock input
Hysteresis CMOS/LCD - -S12 LCDC SEG12 output
P65/SCK/S13 P65 general-purpose I/OLIN UART clock I/O
Hysteresis CMOS/LCD - -S13 LCDC SEG13 output
P66/SOT/S14 P66 general-purpose I/OLIN UART data output
Hysteresis CMOS/LCD - -S14 LCDC SEG14 output
P67/SIN/S15 P67 general-purpose I/OLIN UART data input
Hysteresis/CMOS CMOS/LCD - -S15 LCDC SEG15 output
280
Block Diagram of Port 6
Figure 5.8-1 Block Diagram of Port 6 (SAXOPHONE,RESERVE1,BASSOON,CLARINET and OBOE Series)
Figure 5.8-2 Block Diagram of Port 6 (TUBA,RESERVE2,TROMBONE and TRUMPET Series)
PDR read
PDR write
PDR
DDR read
DDR write
DDR
0
11
0
ILSR read
ILSR write
ILSR
CMOS
Pin
Stop, watch (SPL=1)
At bit operation instruction
Hysteresis
Peripheral function input
Peripheral function output enablePeripheral function output
Inte
rnal
bus
Peripheral function input enable
Selectable only P67
Selectable only P67
PDR read
PDR write
PDR
DDR read
DDR write
DDR
0
11
0
ILSR read
ILSR write
ILSR
CMOS
Selectable only P67
Selectable only P67
LCD output
LCD output enable
Pin
Stop, watch (SPL=1)
At bit operation instruction
Hysteresis
Peripheral function input
Peripheral function output enablePeripheral function output
Inte
rnal
bus
Peripheral function input enable
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CHAPTER 5 I/O Port
5.8.1 Registers for Port 6
This section describes the registers associated with port 6.
Port 6 Register FunctionSee Table 5.8-6 for a list of port 6 register functions.
See Table 5.8-7 for details about the relationship between the port 6 pins and each register bit.
Table 5.8-6 Port 6 Register Function
Register name Data When being read During read-modify-write reading When being written
PDR60 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port *
DDR60 Port input enabled
1 Port output enabled
ILSR0 Hysteresis input level selection
1 CMOS input level selection
Table 5.8-7 Relation between Port 6 Registers and Pins
Bits of related registers and corresponding pins
Pin name P67 P66 P65 P64 P63 P62 P61 P60
PDR6bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DDR6
ILSR bit2 - - - - - - -
282
5.8.2 Operation of Port 6
Here is described the behavior of port 6.
Operation of Port 6
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• Prohibit output in pins jointly used by a peripheral function.
• When using a pin jointly used for LCD as an input port, set the port input control bit (PICTL) of theLCDC enable register (LCDCE1) to "1". However, when setting the PICTL bit to "1", the pin that doesnot select as common pin and segment pin using the LCDC enable register (LCDCE 1 to 6) becomes allinput port. Be sure to select all usable common pins and segment pins before setting the PICTL bit to"1".
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Behavior during peripheral function output
• When the output enable bit of a peripheral function is set to enabled, the corresponding pin goes toperipheral function output.
• Even if peripheral function output is enabled, it is possible to read the pin value when the PDR registeris read. Consequently, it is possible to read the output value of a peripheral function by reading the PDRregister. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Behavior during peripheral function input
• Sets the DDR register bit corresponding to the peripheral function input pin to "0" to change to an inputport.
• As with input port, when a pin jointly used for LCD is used as another peripheral function input,configure it as an input port.
• When a PDR register is read, the value of the pin can be read, regardless of whether the peripheralfunction uses an input pin. Note, however, that for read-modify-write commands, the value of the PDRregister is read.
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CHAPTER 5 I/O Port
Operation when a reset is performed
• When the CPU is reset, the value of the DDR register is initialized to "0", and port input becomesenabled. Note that for pins jointly used for LCD output, the port input control bit (PICTL) of the LCDCenable register (LCDCE1) is initialized to "0". For this reason, port input is disabled.
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input. If, however,peripheral function input is enabled for the interrupt pin selection circuit (SCK, SIN), input is enabledand not blocked.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O, and theoutput level is maintained.
Behavior during LCDC segment output
• Sets the DDR register bit corresponding to the LCDC segment output pin to "0".
• Prohibit output in pins jointly used by other peripheral functions.
• In the LCDC enable registers (LCDCE 1 to 6), select all common pins and segment pins you will use.
Behavior of the input level selection register (other than OBOE series)
• Writing "1" to bit 2 of ILSR register changes the input level for P67 only from hysteresis input level toCMOS input level. When bit 2 of the ILSR register is "0", it becomes the hysteresis input level.
• Pins other than P67 cannot select CMOS input level. Consequently, it becomes the hysteresis input levelonly.
• When changing the P67 input level, change the peripheral function (LIN-UART) state to stopped.
See Table 5.8-8 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.8-8 Port 6 Pin Status
Operating state
Normal operationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin stateI/O port/peripheral
function I/OHi-Z
Input cutoff
Hi-ZInput enabled (however, does not function) (SAXOPHONE, RESERVE1,
BASSOON, CLARINET and OBOE series) Input disabled (TUBA, RESERVE2, TROMBONE and TRUMPET series)
284
5.9 Port 7
Port 7 is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port 7 ConfigurationPort 7 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 7 data register (PDR7)
• Port 7 direction register (DDR7)
• Port 7 pull-up register (PUL7)
• Input level selection register (ILSR)
Pin at Port 7See Table 5.9-1 and Table 5.9-2 for port 7 pins.
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.9-1 Port 7 Pins (SAXOPHONE and RESERVE1 Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P70/TO0 P70 general-purpose I/O TO0 16-bit TIM ch0 output Hysteresis CMOS -
P71/TI0 P71 general-purpose I/O TI0 16-bit TIM ch0 trigger input Hysteresis CMOS -
P72/SCL1 P72 general-purpose I/O SCL1 IIC ch1 clock I/O Hysteresis/CMOS CMOS -
P73/SDA1 P73 general-purpose I/O SDA1 IIC ch1 data I/O Hysteresis/CMOS CMOS -
P74 P74 general-purpose I/O No dual use Hysteresis CMOS -
P75/UCK1 P75 general-purpose I/O UCK1 UART/SIO ch1 clock I/O Hysteresis CMOS -
P76/UO1 P76 general-purpose I/O UO1 UART/SIO ch1 data output Hysteresis CMOS -
P77/UI1 P77 general-purpose I/O UI1 UART/SIO ch1 data input Hysteresis/CMOS CMOS -
Table 5.9-2 Port 7 Pins (TUBA and BASSOON Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P70/TO0 P70 general-purpose I/O TO0 16-bit TIM ch0 output Hysteresis CMOS -
P71/TI0 P71 general-purpose I/O TI0 16-bit TIM ch0 trigger input Hysteresis CMOS -
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CHAPTER 5 I/O Port
Block Diagram of Port 7
Figure 5.9-1 Block Diagram of Port 7 (without P77, P73 and P72)
Figure 5.9-2 Block Diagram of Port 7 (Only P73 and P72)
PDR read
PDR write
PDR
DDR read
DDR write
DDR
PUL read
PUL write
PUL
0
11
0
Pull-up
Pin
Stop, watch (SPL=1)
At bit operation instruction
Peripheral function input
Peripheral function output enablePeripheral function output
Inte
rnal
bus
0
11
0 OD
CMOS
Inte
rnal
bus
ILSR write
ILSR
ILSR read
DDR write
DDR
Stop, watch (SPL=1)
DDR read
At bit operation instruction
PDR write
PDR
PDR read
Peripheral function input
Peripheral function output enablePeripheral function input enable
Peripheral function output
Pin
Hysteresis
P73 and P72 only
286
Figure 5.9-3 Block Diagram of Port 7 (Only P77)
PDR read
PDR write
PDR
DDR read
DDR write
DDR
PUL read
PUL write
PUL
0
1
ILSR read
ILSR write
ILSR
Hysteresis
CMOS
P77 only
Pin
Stop, watch (SPL=1)
At bit operation instruction
Pull-up
Peripheral function input
Inte
rnal
bus
287
CHAPTER 5 I/O Port
5.9.1 Registers for Port 7
This section describes the registers associated with port 7.
Port 7 Register FunctionSee Table 5.9-3 for a list of port 7 register functions.
*: For Nch open drain pin, this will be Hi-Z.
See Table 5.9-4 for details about the relationship between the port 7 pins and each register bit.
Table 5.9-3 Port 7 Register Function
Register name Data When being read During read-modify-write reading When being written
PDR70 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port *
DDR70 Port input enabled
1 Port output enabled
PUL70 Pull-up disabled
1 Pull-up enabled
ILSR0 Hysteresis input level selection
1 CMOS input level selection
Table 5.9-4 Relation between Port 7 Registers and Pins
Bits of related registers and corresponding pins
Pin name P77 P76 P75 P74 P73 P72 P71 P70
PDR7
bit7 bit6 bit5 bit4bit3 bit2
bit1 bit0DDR7
PUL7 - -
ILSR bit1 - - - bit6 bit5 - -
288
5.9.2 Operation of Port 7
Here is described the behavior of port 7.
Operation of Port 7
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• Prohibit output in pins jointly used by a peripheral function.
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Behavior during peripheral function output
• When the output enable bit of a peripheral function is set to enabled, the corresponding pin goes toperipheral function output.
• When the output of the peripheral function is enabled, the pin value is read by reading the PDR register.Consequently, it is possible to read the output value of a peripheral function by reading the PDRregister. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Behavior during peripheral function input
• Sets the DDR register bit corresponding to the peripheral function input pin to "0" to change to an inputport.
• When a PDR register is read, the value of the pin can be read, regardless of whether the peripheralfunction uses an input pin. Note, however, that for read-modify-write commands, the value of the PDRregister is read.
Operation when a reset is performed
• When the CPU is reset, the value of the DDR register is initialized to "0", and port input becomesenabled.
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CHAPTER 5 I/O Port
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input. If, however,peripheral function input (SCL1/SDA1) is enabled, input is enabled and not blocked.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O, and theoutput level is maintained.
Behavior of the pull-up register
• When "1" is written to the PUL register, a pull-up register is internally connected to the pin. Note,however, that during "L" level output, the pull-up register is blocked regardless of the value of the PULregister.
Operation of input level selection register (SAXOPHONE and RESERVE1 series only)
• Writing "1" to bits 6, 5 and 1 of ILSR register changes the input level for P73, P72 and P77 only fromhysteresis input level to CMOS input level. When bit 6, 5 and 1 of the ILSR register is "0", it becomesthe hysteresis input level.
• CMOS input level cannot be selected for pins other than P73, P72, and P77. Consequently, it becomesthe hysteresis input level only.
• When changing the P73, P72 and P77 input level, change the peripheral function (I2C1,UART/SIO1)state to stopped.
See Table 5.9-5 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.9-5 Port 7 Pin Status
Operating state
Normal operationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin stateI/O port/peripheral function
I/O
Hi-Z(Note, however, that pull-up setting is in effect)
Input cutoff
Hi-ZPossible to input
(However, do not function)
290
5.10 Port 8
Port 8 is a general-purpose I/O port.This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port 8 ConfigurationPort 8 is made up of the following elements.
• General-purpose I/O pins
• Port 8 data register (PDR8)
• Port 8 direction register (DDR8)
• Port 8 pull-up register (PUL8)
Pin at Port 8See Table 5.10-1 to Table 5.10-3 for port 8 pins.
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.10-1 Port 8 Pins (SAXOPHONE Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P80 P80 general-purpose I/O No dual use Hysteresis CMOS -
P81 P81 general-purpose I/O No dual use Hysteresis CMOS -
P82 P82 general-purpose I/O No dual use Hysteresis CMOS -
P83 P83 general-purpose I/O No dual use Hysteresis CMOS -
P84 P84 general-purpose I/O No dual use Hysteresis CMOS -
Table 5.10-2 Port 8 Pins (BASSOON Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P80 P80 general-purpose I/O No dual use Hysteresis CMOS -
P81 P81 general-purpose I/O No dual use Hysteresis CMOS -
P82 P82 general-purpose I/O No dual use Hysteresis CMOS -
P83 P83 general-purpose I/O No dual use Hysteresis CMOS -
Table 5.10-3 Port 8 Pins (RESERVE1 Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P80 P80 general-purpose I/O No dual use Hysteresis CMOS -
P81 P81 general-purpose I/O No dual use Hysteresis CMOS -
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CHAPTER 5 I/O Port
Block Diagram of Port 8
Figure 5.10-1 Block Diagram of Port 8 (without P84)
Figure 5.10-2 Block Diagram of Port 8 (Only P84)
PDR read
PDR write
PDR
DDR read
DDR write
DDR
0
1
Stop, watch (SPL=1)
Pin
OD
Inte
rna
l b
us
At bit operating instruction
PDR read
PDR write
PDR
DDR read
DDR write
DDR
PUL read
PUL write
PUL
0
1
Pin
Stop, watch (SPL=1)
At bit operating instruction
Pull-up
P84 only
Inte
rnal
bus
292
5.10.1 Registers for Port 8
This section describes the registers associated with port 8.
Port 8 Register FunctionSee Table 5.10-4 for a list of port 8 register functions.
*: For Nch open drain pin, this will be Hi-Z.
See Table 5.10-5 for details about port 8 registers.
Table 5.10-4 Port 8 Register Function
Register name Data When being read During read-modify-write reading When being written
PDR80 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port *
DDR80 Port input enabled
1 Port output enabled
PUL80 Pull-up disabled
1 Pull-up enabled
Table 5.10-5 Relation between Port 8 Registers and Pins
Bits of related registers and corresponding pins
Pin name - - - P84 P83 P82 P81 P80
PDR8
- - - bit4bit3 bit2 bit1 bit0
DDR8
PUL8 - - - -
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CHAPTER 5 I/O Port
5.10.2 Operation of Port 8
Here is described the behavior of port 8.
Operation of Port 8
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Operation when a reset is performed
• When the CPU is reset, the value of the DDR register is initialized to "0", and port input becomesenabled.
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input.
• If the pin state specification bit is "0", the state remains in port I/O, and the output level is maintained.
Behavior of the pull-up register
• When "1" is written to the PUL register, a pull-up register is internally connected to the pin. Note,however, that during "L" level output, the pull-up register is blocked regardless of the value of the PULregister.
See Table 5.10-6 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.10-6 Port 8 Pin Status
Operating state
Normal OperationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin state I/O portHi-Z
(Note, however, that pull-up setting is in effect)Input cutoff
Hi-ZPossible to input
(However, do not function)
294
5.11 Port 9
Port 9 is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port 9 ConfigurationPort 9 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 9 data register (PDR9)
• Port 9 direction register (DDR9)
Pin at Port 9Port 9 has six I/O pins.
See Table 5.11-1 for port 9 pins.
OD: Open drain, PU: Pull-up
C0/C1: Only products with LCD voltage rise (for products with voltage rise, C1/C0 (dedicated LCD) pins;
for products with on-board splitter resistance, P95/P94 (dedicated general-purpose port).
Table 5.11-1 Port 9 Pins (TUBA,RESERVE2,TROMBONE and TRUMPET Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
P90/V3 P90 general-purpose I/O V3 LCDC V3 pin Hysteresis CMOS - -
P91/V2 P91 general-purpose I/O V2 LCDC V2 pin Hysteresis CMOS - -
P92/V1 P92 general-purpose I/O V1 LCDC V1 pin Hysteresis CMOS - -
P93/V0 P93 general-purpose I/O V0 LCDC V0 pin Hysteresis CMOS - -
P94/C0 P94 general-purpose I/O C0 LCDC C0 pin * Hysteresis CMOS - -
P95/C1 P95 general-purpose I/O C1 LCDC C1 pin* Hysteresis CMOS - -
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CHAPTER 5 I/O Port
Block Diagram of Port 9
Figure 5.11-1 Block Diagram of Port 9
PDR read
PDR write
PDR
DDR read
DDR write
DDR
0
1
LCD enable
LCD I/O
Pin
Stop, watch (SPL=1)
At bit operating instruction
Inte
rnal
bus
296
5.11.1 Registers for Port 9
This section describes the registers associated with port 9.
Port 9 Register FunctionSee Table 5.11-2 for a list of port 9 register functions.
See Table 5.11-3 for details about the relationship between the port 9 pins and each register bit.
*: Only products with on-board splitter resistance
Table 5.11-2 Port 9 Register Function
Register name Data When being read During read-modify-write reading When being written
PDR90 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port
DDR90 Port input enabled
1 Port output enabled
Table 5.11-3 Relation between Port 9 Registers and Pins
Bits of related registers and corresponding pins
Pin name - - P95* P94* P93 P92 P91 P90
PDR9- - bit5 bit4 bit3 bit2 bit1 bit0
DDR9
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CHAPTER 5 I/O Port
5.11.2 Operation of Port 9
Here is described the behavior of port 9.
Operation of Port 9
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• Prohibit output in pins jointly used by a peripheral function.
• When using a pin jointly used for LCD as an input port, set the V0 to V3 selection bits (VE2/VE1) ofthe LCDC enable register (LCDCE1) to "0".
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Operation when a reset is performed
• For pins 93 to 90, when the CPU is reset, the value of the DDR register is initialized to "0", and thevalues of the VE2 and VE1 bits of the LCDCE1 register are initialized to "1", and port input becomesdisabled.
• For pins 95 and 94, when the CPU is reset, the value of the DDR register is initialized to "0", and portinput becomes enabled. Note that for products with LCD voltage rise, port I/O is always disabled.
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O, and theoutput level is maintained.
Behavior of LCDC pins
• Sets the DDR register bit corresponding to the dedicated LCDC pin to "0".
• Sets the V0 to V3 pin selection bits (VE2/VE1) of the LCDC enable register (LCDCE1) to "1".
• For products with LCD voltage rise, P95/C1 and P94/C0 are dedicated voltage rise pins.
298
See Table 5.11-4 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.11-4 Port 9 Pin Status
Operating state
Normal operationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin stateI/O port/peripheral function
I/OHi-Z
Input cutoff
Hi-ZInput disabled
(Input enabled for P95/P94 in products with no LCD voltage rise. (However, do not function)
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CHAPTER 5 I/O Port
5.12 Port A
Port A is a general-purpose I/O port.This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port A ConfigurationPort A is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port A data register (PDRA)
• Port A direction register (DDRA)
Pin at Port APort A has four I/O pins.
See Table 5.12-1 and Table 5.12-2 for port A pins.
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.12-1 Port A Pins (SAXOPHONE Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
PA0 PA0 general-purpose I/O No dual use Hysteresis CMOS - -
PA1 PA1 general-purpose I/O No dual use Hysteresis CMOS - -
PA2 PA2 general-purpose I/O No dual use Hysteresis CMOS - -
PA3 PA3 general-purpose I/O No dual use Hysteresis CMOS - -
Table 5.12-2 Port A Pins (TUBA,RESERVE2,TROMBONE and TRUMPET Series)
Pin name FunctionDual use peripheral
functions
I/O type
Input Output OD PU
PA0/COM0 PA0 general-purpose I/O COM0 LCDC COM0 output Hysteresis CMOS/LCD - -
PA1/COM1 PA1 general-purpose I/O COM1 LCDC COM1 output Hysteresis CMOS/LCD - -
PA2/COM2 PA2 general-purpose I/O COM2 LCDC COM2 output Hysteresis CMOS/LCD - -
PA3/COM3 PA3 general-purpose I/O COM3 LCDC COM3 output Hysteresis CMOS/LCD - -
300
Block Diagram of Port A
Figure 5.12-1 Block Diagram of Port A (SAXOPHONE Series)
Figure 5.12-2 Block Diagram of Port A (TUBA,RESERVE2,TROMBONE and TRUMPET Series)
PDR read
PDR write
PDR
DDR read
DDR write
DDR
0
1
Pin
Stop, watch (SPL=1)
At bit operating instruction
Inte
rnal
bus
0
1
At bit operating instruction
DDR read
DDR write
DDR
Stop, watch (SPL=1)
Inte
rnal
bus
PDR read
PDR write
PDR Pin
LCD output
LCD enable
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CHAPTER 5 I/O Port
5.12.1 Registers for Port A
This section describes the registers associated with port A.
Port A Register FunctionSee Table 5.12-3 for a list of port A register functions.
See Table 5.12-4 for details about the relationship between the port A pins and each register bit.
Table 5.12-3 Port A Register Function
Register name Data When being read During read-modify-write reading When being written
PDRA0 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port
DDRA0 Port input enabled
1 Port output enabled
Table 5.12-4 Relation between Port A Registers and Pins
Bits of related registers and corresponding pins
Pin name - - - - PA3 PA2 PA1 PA0
PDRA- - - - bit3 bit2 bit1 bit0
DDRA
302
5.12.2 Operation of Port A
Here is described the behavior of port A.
Operation of Port A
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• Prohibit output in pins jointly used by a peripheral function.
• When using a pin jointly used for LCD as an input port, set the port input control bit (PICTL) of theLCDC enable register (LCDCE1) to "1". However, when setting the PICTL bit to "1", the pin that doesnot select as common pin and segment pin using the LCDC enable register (LCDCE 1 to 6) becomes allinput port. Be sure to select all usable common pins and segment pins before setting the PICTL bit to"1".
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Operation when a reset is performed
• When the CPU is reset, the value of the DDR register is initialized to "0", and port input becomesenabled. Note that for pins jointly used for LCD output, the port input control bit (PICTL) of the LCDCenable register (LCDCE1) is initialized to "0". For this reason, port input is disabled.
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O, and theoutput level is maintained.
Behavior during LCDC common output
• Sets the DDR register bit corresponding to the LCDC common output pin to "0".
• Prohibit output in pins jointly used by other peripheral functions.
• In the LCDC enable registers (LCDCE 1 to 6), select all common pins and segment pins you will use.
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CHAPTER 5 I/O Port
See Table 5.12-5 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.12-5 Port A Pin Status
Operating state
Normal operationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin stateI/O port/peripheral function
I/OHi-Z
Input cutoff
Hi-ZInput enabled (SAXOPHONE series)
Input disabled (TUBA,RESERVE2, TROMBONE,TRUMPET series) (However, do not function)
304
5.13 Port B
Port B is a general-purpose I/O port. This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port B ConfigurationPort B is made up of the following elements.
• General-purpose I/O pins and resource I/O pins
• Port B data register (PDRB)
• Port B direction register (DDRB)
Pin at Port BPort B has eight CMOS I/O pins.
See Table 5.13-1 and Table 5.13-2 for port B pins.
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.13-1 Port B Pins (TRUMPET Series)
Pin name FunctionPeripherals for which a pin may
serveI/O type
Input Output OD PU
PB0/S00 PB0 general-purpose I/O S00 LCDC SEG0 output Hysteresis CMOS/LCD - -
PB1/S01 PB1 general-purpose I/O S01 LCDC SEG1 output Hysteresis CMOS/LCD - -
PB2/S02 PB2 general-purpose I/O S02 LCDC SEG2 output Hysteresis CMOS/LCD - -
PB3/S03/PPG00 PB3 general-purpose I/OS03LCDC SEG3 output
Hysteresis CMOS/LCD - -PPG00 8/16-bit PPG ch0-0 output
PB4/S04/PPG01 PB4 general-purpose I/OS04 LCDC SEG4 output
Hysteresis CMOS/LCD - -PPG01 8/16-bit PPG ch0-1 output
PB5/S05/TO00 PB5 general-purpose I/OS05 LCDC SEG5 output
Hysteresis CMOS/LCD - -TO00 8/16-bit TIM ch0-0 output
PB6/S06/TO01 PB6 general-purpose I/OS06 LCDC SEG6 output
Hysteresis CMOS/LCD - -TO01 8/16-bit TIM ch0-1 output
PB7/S07/EC0 PB7 general-purpose I/OS07LCDC SEG7 output
Hysteresis/CMOS CMOS/LCD - -EC0 8/16-bitTIM ch0 clock input
Table 5.13-2 Port B Pins (TUBA,RESERVE2 and TROMBONE Series)
Pin name FunctionPeripherals for which a pin
may serve
I/O type
Input Output OD PU
PB0/S00 PB0 general-purpose I/O S00 LCDC SEG0 output Hysteresis CMOS/LCD - -
PB1/S01 PB1 general-purpose I/O S01 LCDC SEG1 output Hysteresis CMOS/LCD - -
PB2/S02 PB2 general-purpose I/O S02 LCDC SEG2 output Hysteresis CMOS/LCD - -
PB3/S03 PB3 general-purpose I/O S03 LCDC SEG3 output Hysteresis CMOS/LCD - -
PB4/S04 PB4 general-purpose I/O S04 LCDC SEG4 output Hysteresis CMOS/LCD - -
PB5/S05 PB5 general-purpose I/O S05 LCDC SEG5 output Hysteresis CMOS/LCD - -
PB6/S06 PB6 general-purpose I/O S06 LCDC SEG6 output Hysteresis CMOS/LCD - -
PB7/S07 PB7 general-purpose I/O S07 LCDC SEG7 output Hysteresis CMOS/LCD - -
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CHAPTER 5 I/O Port
Block Diagram of Port B
Figure 5.13-1 Block Diagram of Port B (TRUMPET Series)
Figure 5.13-2 Block Diagram of Port B (TUBA,RESERVE2 and TROMBONE Series)
PDR read
PDR write
PDR
DDR read
DDR write
DDR
0
11
0
LCD outputenable
LCD output
Pin
Stop, watch (SPL=1)
At bit operation instruction
Peripheral function input
Peripheral function output enablePeripheral function output
Inte
rnal
bus
Peripheral function input enable
PDR read
PDR write
PDR
DDR read
DDR write
DDR
0
1
LCD enable
LCD output
Pin
Stop, watch (SPL=1)
At bit operation instruction
Inte
rnal
bus
306
5.13.1 Registers for Port B
This section describes the registers associated with port B.
Port B Register FunctionSee Table 5.13-3 for a list of port B register functions.
See Table 5.13-4 for details about the relationship between the port B pins and each register bit.
Table 5.13-3 Port B Register Function
Register name Data When being read During read-modify-write reading When being written
PDRB0 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port
DDRB0 Port input enabled
1 Port output enabled
Table 5.13-4 Relation between Port B Registers and Pins
Bits of related registers and corresponding pins
Pin name PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
PDRBbit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DDRB
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CHAPTER 5 I/O Port
5.13.2 Operation of Port B
Here is described the behavior of port B.
Operation of Port B
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• Prohibit output in pins jointly used by a peripheral function.
• When using a pin jointly used for LCD as an input port, set the port input control bit (PICTL) of theLCDC enable register (LCDCE1) to "1". However, when setting the PICTL bit to "1", the pin that doesnot select as common pin and segment pin using the LCDC enable register (LCDCE 1 to 6) becomes allinput port. Be sure to select all usable common pins and segment pins before setting the PICTL bit to"1".
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Behavior during peripheral function output
• When the output enable bit of a peripheral function is set to enabled, the corresponding pin goes toperipheral function output.
• When the output of the peripheral function is enabled, the pin value is read by reading the PDR register.Consequently, it is possible to read the output value of a peripheral function by reading the PDRregister. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Behavior during peripheral function input
• Sets the DDR register bit corresponding to the peripheral function input pin to "0" to change to an inputport.
• As with input port, when a pin jointly used for LCD is used as another peripheral function input,configure it as an input port.
• When a PDR register is read, the value of the pin can be read, regardless of whether the peripheralfunction uses an input pin. Note, however, that for read-modify-write commands, the value of the PDRregister is read.
308
Operation when a reset is performed
• When the CPU is reset, the values of the DDR register and PICT bit of the LCDCE1 register areinitialized to "0", and port input becomes disabled.
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input. If, however,peripheral function input is enabled for the interrupt pin selection circuit (EC0), input is enabled and notblocked.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O, and theoutput level is maintained.
Behavior during LCDC segment output
• Sets the DDR register bit corresponding to the LCDC segment output pin to "0".
• Prohibit output in pins jointly used by other peripheral functions.
• In the LCDC enable registers (LCDCE 1 to 6), select all common pins and segment pins you will use.
See Table 5.13-5 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.13-5 Port B Pin Status
Operating state
Normal operationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin stateI/O port/peripheral function
I/OHi-Z
Input cutoff
Hi-ZPossible to input
(However, do not function)
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CHAPTER 5 I/O Port
5.14 Port C
Port C is a general-purpose I/O port.This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port C ConfigurationPort C is made up of the following elements.
• General-purpose I/O pins and resource I/O pins
• Port C data register (PDRC)
• Port C direction register (DDRC)
Pin at Port CPort C has eight I/O pins.
See Table 5.14-1 for port C pins.
OD: Open drain, PU: Pull-up
Table 5.14-1 Port C Pins (TUBA,RESERVE2 and TROMBONE Series)
Pin name FunctionPeripherals for which a pin
may serve
I/O type
Input Output OD PU
PC0/S08 PC0 general-purpose I/O S08 LCDC SEG8 output Hysteresis CMOS/LCD - -
PC1/S09 PC1 general-purpose I/O S09 LCDC SEG9 output Hysteresis CMOS/LCD - -
PC2/S10 PC2 general-purpose I/O S10 LCDC SEG10 output Hysteresis CMOS/LCD - -
PC3/S11 PC3 general-purpose I/O S11 LCDC SEG11 output Hysteresis CMOS/LCD - -
PC4/S12 PC4 general-purpose I/O S12 LCDC SEG12 output Hysteresis CMOS/LCD - -
PC5/S13 PC5 general-purpose I/O S13 LCDC SEG13 output Hysteresis CMOS/LCD - -
PC6/S14 PC6 general-purpose I/O S14 LCDC SEG14 output Hysteresis CMOS/LCD - -
PC7/S15 PC7 general-purpose I/O S15 LCDC SEG15 output Hysteresis CMOS/LCD - -
310
Block Diagram of Port C
Figure 5.14-1 Block Diagram of Port C
PDR read
PDR write
PDR
DDR read
DDR write
DDR
0
1
LCD enable
LCD output
Pin
Stop, watch (SPL=1)
At bit operation instruction
Inte
rnal
bus
311
CHAPTER 5 I/O Port
5.14.1 Registers for Port C
This section describes the registers associated with port C.
Port C Register FunctionSee Table 5.14-2 for a list of port C register functions.
See Table 5.14-3 for details about the relationship between the port C pins and each register bit.
Table 5.14-2 Port C Register Function
Register name Data When being read During read-modify-write reading When being written
PDRC0 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port
DDRC0 Port input enabled
1 Port output enabled
Table 5.14-3 Relation between Port C Registers and Pins
Bits of related registers and corresponding pins
Pin name PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PDRCbit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DDRC
312
5.14.2 Operation of Port C
Here is described the behavior of port C.
Operation of Port C
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an outputted port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• Prohibit output in pins jointly used by a peripheral function.
• When using a pin jointly used for LCD as an input port, set the port input control bit (PICTL) of theLCDC enable register (LCDCE1) to "1". However, when setting the PICTL bit to "1", the pin that doesnot select as common pin and segment pin using the LCDC enable register (LCDCE 1 to 6) becomes allinput port. Be sure to select all usable common pins and segment pins before setting the PICTL bit to"1".
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Operation when a reset is performed
• When the CPU is reset, the values of the DDR register and PICTL bit of the LCDCE1 register areinitialized to "0", and port input becomes disabled.
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O, and theoutput level is maintained.
Behavior during LCDC segment output
• Sets the DDR register bit corresponding to the LCDC segment output pin to "0".
• Prohibit output in pins jointly used by other peripheral functions.
• In the LCDC enable registers (LCDCE 1 to 6), select all common pins and segment pins you will use.
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CHAPTER 5 I/O Port
See Table 5.14-4 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.14-4 Port C Pin Status
Operating state
Normal operationSleep
Stop (SPL = 0)Watch(SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin stateI/O port/peripheral function
I/OHi-Z
Input cutoffHi-Z
Input disabled
314
5.15 Port D
Port D is a general-purpose I/O port.This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port D ConfigurationPort D is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port D data register (PDRD)
• Port D direction register (DDRD)
Pin at Port DPort D has eight I/O pins.
See Table 5.15-1 and Table 5.15-2 for port D pins.
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.15-1 Port D Pins (SAXOPHONE Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
PD0 PD0 general-purpose I/O No dual use Hysteresis CMOS - -
PD1 PD1 general-purpose I/O No dual use Hysteresis CMOS - -
PD2 PD2 general-purpose I/O No dual use Hysteresis CMOS - -
PD3 PD3 general-purpose I/O No dual use Hysteresis CMOS - -
PD4 PD4 general-purpose I/O No dual use Hysteresis CMOS - -
PD5 PD5 general-purpose I/O No dual use Hysteresis CMOS - -
PD6 PD6 general-purpose I/O No dual use Hysteresis CMOS - -
PD7 PD7 general-purpose I/O No dual use Hysteresis CMOS - -
Table 5.15-2 Port D Pin (TUBA Series)
Pin name FunctionDual use peripheral
functions
I/O type
Input Output OD PU
PD0/S16 PD0 general-purpose I/O S16 LCDC SEG16 output Hysteresis CMOS/LCD - -
PD1/S17 PD1 general-purpose I/O S17 LCDC SEG17 output Hysteresis CMOS/LCD - -
PD2/S18 PD2 general-purpose I/O S18 LCDC SEG18 output Hysteresis CMOS/LCD - -
PD3/S19 PD3 general-purpose I/O S19 LCDC SEG19 output Hysteresis CMOS/LCD - -
PD4/S20 PD4 general-purpose I/O S20 LCDC SEG20 output Hysteresis CMOS/LCD - -
PD5/S21 PD5 general-purpose I/O S21 LCDC SEG21 output Hysteresis CMOS/LCD - -
PD6/S22 PD6 general-purpose I/O S22 LCDC SEG22 output Hysteresis CMOS/LCD - -
PD7/S23 PD7 general-purpose I/O S23 LCDC SEG23 output Hysteresis CMOS/LCD - -
315
CHAPTER 5 I/O Port
Block Diagram of Port D
Figure 5.15-1 Block Diagram of Port D (SAXOPHONE Series)
Figure 5.15-2 Block Diagram of Port D (TUBA Series)
PDR read
PDR write
PDR
DDR read
DDR write
DDR
0
1
Pin
Stop, watch (SPL=1)
At bit operation instruction
Inte
rnal
bus
PDR read
PDR write
PDR
DDR read
DDR write
DDR
0
1
LCD enable
LCD output
Pin
Stop, watch (SPL=1)
At bit operation instruction
Inte
rnal
bus
316
5.15.1 Registers for Port D
This section describes the registers associated with port D.
Port D Register FunctionSee Table 5.15-3 for a list of port D register functions.
See Table 5.15-4 for details about the relationship between the port D pins and each register bit.
Table 5.15-3 Port D Register Function
Register name Data When being read During read-modify-write reading When being written
PDRD0 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port
DDRD0 Port input enabled
1 Port output enabled
Table 5.15-4 Relation between Port D Registers and Pins
Bits of related registers and corresponding pins
Pin name PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PDRDbit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DDRD
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CHAPTER 5 I/O Port
5.15.2 Operation of Port D
Here is described the behavior of port D.
Operation of Port D
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• Prohibit output in pins jointly used by a peripheral function.
• When using a pin jointly used for LCD as an input port, set the port input control bit (PICTL) of theLCDC enable register (LCDCE1) to "1". However, when setting the PICTL bit to "1", the pin that doesnot select as common pin and segment pin using the LCDC enable register (LCDCE 1 to 6) becomes allinput port. Be sure to select all usable common pins and segment pins before setting the PICTL bit to"1".
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Operation when a reset is performed
• When the CPU is reset, the value of the DDR register is initialized to "0", and port input becomesenabled. Note that for pins jointly used for LCD output, the port input control bit (PICTL) of the LCDCenable register (LCDCE1) is initialized to "0". For this reason, port input is disabled.
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O, and theoutput level is maintained.
318
Behavior during LCDC segment output
• Sets the DDR register bit corresponding to the LCDC segment output pin to "0".
• Prohibit output in pins jointly used by other peripheral functions.
• In the LCDC enable registers (LCDCE 1 to 6), select all common pins and segment pins you will use.
See Table 5.15-5 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.15-5 Port D Pin Status
Operating state
Normal operationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin stateI/O port/peripheral function
I/OHi-Z
Input cutoff
Hi-ZInput enabled (however, does not function) (SAXOPHONE series)
Input disabled (TUBA series)
319
CHAPTER 5 I/O Port
5.16 Port E
Port E is a general-purpose I/O port.This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port E ConfigurationPort E is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port E data register (PDRE)
• Port E direction register (DDRE)
• Port E pull-up register (PULE)
Pin at Port ESee Table 5.16-1 to Table 5.16-3 for port E pins.
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.16-1 Port E Pins (SAXOPHONE and RESERVE1 Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
PE0/INT10 PE0 general-purpose I/O INT10 external interrupt input Hysteresis CMOS -
PE1/INT11 PE1 general-purpose I/O INT11 external interrupt input Hysteresis CMOS -
PE2/INT12 PE2 general-purpose I/O INT12 external interrupt input Hysteresis CMOS -
PE3/INT13 PE3 general-purpose I/O INT13 external interrupt input Hysteresis CMOS -
PE4/INT14 PE4 general-purpose I/O INT14 external interrupt input Hysteresis CMOS -
PE5/INT15 PE5 general-purpose I/O INT15 external interrupt input Hysteresis CMOS -
PE6/INT16 PE6 general-purpose I/O INT16 external interrupt input Hysteresis CMOS -
PE7/INT17 PE7 general-purpose I/O INT17 external interrupt input Hysteresis CMOS -
Table 5.16-2 Port E Pins (BASSOON Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
PE0/INT10 PE0 general-purpose I/O INT10 external interrupt input Hysteresis CMOS -
PE1/INT11 PE1 general-purpose I/O INT11 external interrupt input Hysteresis CMOS -
PE2/INT12 PE2 general-purpose I/O INT12 external interrupt input Hysteresis CMOS -
PE3/INT13 PE3 general-purpose I/O INT13 external interrupt input Hysteresis CMOS -
320
OD: Open drain, PU: Pull-up
Table 5.16-3 Port E Pins (TUBA and RESERVE2 Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
PE0/S24 PE0 general-purpose I/O S24 LCDC SEG24 output Hysteresis CMOS/LCD - -
PE1/S25 PE1 general-purpose I/O S25 LCDC SEG25 output Hysteresis CMOS/LCD - -
PE2/S26 PE2 general-purpose I/O S26 LCDC SEG26 output Hysteresis CMOS/LCD - -
PE3/S27 PE3 general-purpose I/O S27 LCDC SEG27 output Hysteresis CMOS/LCD - -
PE4/S28/INT10 PE4 general-purpose I/OS28 LCDC SEG28 output
Hysteresis CMOS/LCD - -INT10 external interrupt input
PE5/S29/INT11 PE5 general-purpose I/OS29 LCDC SEG29 output
Hysteresis CMOS/LCD - -INT11 external interrupt input
PE6/S30/INT12 PE6 general-purpose I/OS30 LCDC SEG30 output
Hysteresis CMOS/LCD - -INT12 external interrupt input
PE7/S31/INT13 PE7 general-purpose I/OS31 LCDC SEG31 output
Hysteresis CMOS/LCD - -INT13 external interrupt input
321
CHAPTER 5 I/O Port
Block Diagram of Port E
Figure 5.16-1 Block Diagram of Port E (SAXOPHONE,RESERVE1 and BASSOON Series)
Figure 5.16-2 Block Diagram of Port E (TUBA and RESERVE2 Series)
PDR read
PDR write
PDR
DDR read
DDR write
DDR
PUL read
PUL write
PUL
0
1
Pull-up
Pin
Stop, watch (SPL=1)
At bit operation instruction
Peripheral function input
Inte
rnal
bus
Peripheral function input enable
PDR read
PDR write
PDR
DDR read
DDR write
DDR
0
1
LCD output enable
LCD output
Pin
Stop, watch (SPL=1)
At bit operation instruction
Peripheral function input
Inte
rnal
bus
Peripheral function input enable
322
5.16.1 Registers for Port E
This section describes the registers associated with port E.
Port E Register FunctionSee Table 5.16-4 for a list of port E register functions.
See Table 5.16-5 for details about the relationship between the port E pins and each register bit.
Table 5.16-4 Port E Register Function
Register name Data When being read During read-modify-write reading When being written
PDRE0 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port
DDRE0 Port input enabled
1 Port output enabled
PULE0 Pull-up disabled
1 Pull-up enabled
Table 5.16-5 Relation between Port E Registers and Pins
Bits of related registers and corresponding pins
Pin Name PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
PDRE
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0DDRE
PULE
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CHAPTER 5 I/O Port
5.16.2 Operation of Port E
Here is described the behavior of port E.
Operation of Port E
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• Prohibit output in pins jointly used by a peripheral function.
• When using a pin jointly used for LCD as an input port, set the port input control bit (PICTL) of theLCDC enable register (LCDCE1) to "1". However, when setting the PICTL bit to "1", the pin that doesnot select as common pin and segment pin using the LCDC enable register (LCDCE 1 to 6) becomes allinput port. Be sure to select all usable common pins and segment pins before setting the PICTL bit to"1".
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Operation when a reset is performed
• When the CPU is reset, the value of the DDR register is initialized to "0", and port input becomesenabled. Note that for pins jointly used for LCD output, the port input control bit (PICTL) of the LCDCenable register (LCDCE1) is initialized to "0". For this reason, port input is disabled.
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input. If, however,peripheral function input is enabled for external interrupt, input is enabled and not blocked.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O, and theoutput level is maintained.
324
Behavior of external interrupt input pins
• Sets the DDR register bit corresponding to the external interrupt input pin to "0".
• As with input port, when a pin jointly used for LCD is used as an external interrupt input pin, configureit as an input port.
• Prohibit output in pins jointly used by other peripheral functions.
• The pin value is always inputted into the external interrupt circuit. When using functions other than pininterrupt, disable the corresponding external interrupt.
Behavior during LCDC segment output
• Sets the DDR register bit corresponding to the LCDC segment output pin to "0".
• Prohibit output in pins jointly used by other peripheral functions.
• In the LCDC enable registers (LCDCE 1 to 6), select all common pins and segment pins you will use.
Behavior of the pull-up register
• When "1" is written to the PUL register, a pull-up register is internally connected to the pin. Note,however, that during "L" level output, the pull-up register is blocked regardless of the value of the PULregister.
See Table 5.16-6 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.16-6 Port E Pin Status
Operating state
Normal OperationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin stateI/O port/peripheral
function I/O
Hi-Z(Note, however, that pull-up setting is in effect)
Input cutoff(Note, however, that if external interrupts are enabled, only external interrupts can be input)
Hi-ZInput enabled (however, does not function)
(SAXOPHONE,RESERVE1 and BASSOON series)
Input disabled (TUBA and RESERVE2 series)
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CHAPTER 5 I/O Port
5.17 Port F
Port F is a general-purpose I/O port.This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port F ConfigurationPort F is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port F data register (PDRF)
• Port F direction register (DDRF)
Pin at Port FSee Table 5.17-1 and Table 5.17-2 for port F pins.
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.17-1 Port F Pins (OBOE Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
PF0 PF0 general-purpose I/O No dual use Hysteresis CMOS - -
PF1 PF1 general-purpose I/O No dual use Hysteresis CMOS - -
PF2 PF2 general-purpose I/O No dual use Hysteresis CMOS - -
Table 5.17-2 Port F Pins (FLUTE Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
PF0 PF0 general-purpose I/O No dual use Hysteresis CMOS - -
PF1 PF1 general-purpose I/O No dual use Hysteresis CMOS - -
326
Block Diagram of Port F
Figure 5.17-1 Block Diagram of Port F
PDR read
PDR write
PDR
DDR read
DDR write
DDR
0
1
Pin
Stop, watch (SPL=1)
At bit operation instruction
Inte
rnal
bus
327
CHAPTER 5 I/O Port
5.17.1 Registers for Port F
This section describes the registers associated with port F.
Port F Register FunctionSee Table 5.17-3 for a list of port F register functions.
See Table 5.17-4 for details about the relationship between the port F pins and each register bit.
Table 5.17-3 Port F Register Function
Register name Data When being read During read-modify-write reading When being written
PDRF0 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port
DDRF0 Port input enabled
1 Port output enabled
Table 5.17-4 Relation between Port F Registers and Pins
Bits of related registers and corresponding pins
Pin name - - - - - PF2 PF1 PF0
PDRF- - - - - bit2 bit1 bit0
DDRF
328
5.17.2 Operation of Port F
Here is described the behavior of port F.
Operation of Port F
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Operation when a reset is performed
• When the CPU is reset, the value of the DDR register is initialized to "0", and port input becomesenabled.
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input.
• If the pin state specification bit is "0", the state remains in port I/O, and the output level is maintained.
See Table 5.17-5 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.17-5 Port F Pin Status
Operating state
Normal operationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin state I/O PortsHi-Z
Input cutoff
Hi-ZPossible to input
(However, do not function)
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CHAPTER 5 I/O Port
5.18 Port G
Port G is a general-purpose I/O port.This section focuses on functions as a general-purpose I/O port. See the chapters on each peripheral function for details about peripheral functions.
Port G ConfigurationPort G is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port G data register (PDRG)
• Port G direction register (DDRG)
• Port G pull-up register (PULG)
Pin at Port GSee Table 5.18-1 and Table 5.18-2 for port G pins.
OD: Open drain, PU: Pull-up
OD: Open drain, PU: Pull-up
Table 5.18-1 Port G Pin (All series with exception of PICCOLO Series)
Pin name Function Dual Use Peripheral FunctionsI/O type
Input Output OD PU
PG0 PG0 general-purpose I/O No dual use Hysteresis CMOS -
PG1 PG1 general-purpose I/O No dual use Hysteresis CMOS -
PG2 PG2 general-purpose I/O No dual use Hysteresis CMOS -
Table 5.18-2 Port G Pins (PICCOLO Series)
Pin name Function Dual use peripheral functionsI/O type
Input Output OD PU
PG0 PG0 general-purpose I/O No dual use Hysteresis CMOS -
330
Block Diagram of Port G
Figure 5.18-1 Block Diagram of Port G
PDR read
PDR write
PDR
DDR read
DDR write
DDR
PUL read
PUL write
PUL
0
1
Pull-up
Pin
Stop, watch (SPL=1)
At bit operation instruction
Inte
rnal
bus
331
CHAPTER 5 I/O Port
5.18.1 Registers for Port G
This section describes the registers associated with port G.
Port G Register FunctionSee Table 5.18-3 for a list of port G register functions.
See Table 5.18-4 for details about the relationship between the port G pins and each register bit.
Table 5.18-3 Port G Register Function
Register name Data When being read During read-modify-write reading When being written
PDRG0 The pin state is Low level. Value of PDR register is "0" Outputs "L" level for output port
1 The pin state is High level. Value of PDR register is "1" Outputs "H" level for output port
DDRG0 Port input enabled
1 Port output enbled
PULG0 Pull-up disabled
1 Pull-up enabled
Table 5.18-4 Relation between Port G Registers and Pins
Bits of related registers and corresponding pins
Pin name - - - - - PG2 PG1 PG0
PDRG
- - - - - bit2 bit1 bit0DDRG
PULG
332
5.18.2 Operation of Port G
Here is described the behavior of port G.
Operation of Port G
Operation in output port mode
• Sets the corresponding DDR register bit to "1" to change to an output port.
• Prohibit output in pins jointly used by a peripheral function.
• When acting as an output port, the value of the PDR register is outputted to the pins.
• When data is written to the PDR register, the value is stored in the output latch, then output to the pin asit is.
• When the PDR register is read, the value of the PDR register is read.
Operation in input port mode
• When setting the corresponding bit of DDR register to "0", it becomes input port.
• When data is written to the PDR register, the value is stored in the output latch, but not output to the pin.
• The pin value can be read out by reading out the PDR register. Note, however, that for read-modify-write commands, the value of the PDR register is read.
Operation when a reset is performed
• When the CPU is reset, the value of the DDR register is initialized to "0", and port input becomesenabled.
Behavior of stop mode and watch mode
• After moving to stop mode or watch mode, setting the standby control register pin state specification bit(STBC:SPL) to "1" forces the pin into high impedance, regardless of the value of the DDR register.Note that input is locked to "L" and blocked, in order to prevent leaks from freed input.
• If the pin state specification bit is "0", the state remains in port I/O, and the output level is maintained.
Behavior of the pull-up register
• When "1" is written to the PUL register, a pull-up register is internally connected to the pin. Note,however, that during "L" level output, the pull-up register is blocked regardless of the value of the PULregister.
See Table 5.18-5 for details about port pin states.
SPL: Pin state designating bit of standby control register (STBC:SPL)
Hi-Z: High impedance
Table 5.18-5 Port G Pin Status
Operating state
Normal operationSleep
Stop (SPL = 0)Watch (SPL=0)
Stop (SPL = 1)Watch (SPL=1)
At a reset
Pin state I/O PortsHi-Z
Input cutoff
Hi-ZPossible to input
(However, do not function)
333
CHAPTER 5 I/O Port
334
CHAPTER 6Timebase Timer
This chapter describes the functions and operations of the timebase timer.
6.1 Overview of Timebase Timer
6.2 Configuration of Timebase Timer
6.3 Timebase Timer Control Register (TBTC)
6.4 Explanation of Operations of Timebase Timer
6.5 Interrupt of Timebase Timer
6.6 Program Example of Timebase Timer
335
CHAPTER 6 Timebase Timer
6.1 Overview of Timebase Timer
The timebase timer is a 22-bit down-counting, free-run counter which is synchronized with the main oscillation clock divided by two. The timebase timer has an interval timer function which can be set to four different interval times. In addition, it provides timer output for oscillation stabilization wait time and an operation clock for the watchdog timer.The timebase timer stops operating in modes when the main oscillation clock halts.
Interval Timer FunctionThe interval timer function generates repeated interrupt requests at a fixed interval set by counting the main
oscillation clock divided by two.
• The timebase timer counts down and sets the timebase timer interrupt request flag bit in the timebasetimer control register (TBTC:TBIF) to "1" each time the selected interval time elapses.
• The interval time can be selected from four different options.
Table 6.1-1 shows the interval time of timebase timer
Table 6.1-1 Interval Time of Timebase Timer
Internal count clock cycle Interval Time
2/FCH(0.5 µs) 210 × 2/FCH(512.0 µs)
212 × 2/FCH(2.05 ms)
214 × 2/FCH(8.19 ms)
216 × 2/FCH(32.77 ms)
FCH: Main source oscillation clock
The values in ( ) are for a 4 MHz main source oscillation clock operation.
336
Function of Clock SupplyThe clock supply function of the timebase timer provides the timer output for generating the main clock
oscillation stabilization wait time and supplies the operating clock to the watchdog timer and to the
prescaler used by some peripheral functions.
When timebase timer output is stopped, the clock supplied by timebase timer is stopped.
Table 6.1-2 shows the clock cycle supplied from the timebase timer.
Table 6.1-2 Clock Signal Supplied from the Timebase Timer
Destination of Supply Clock Clock Cycle Remark
Oscillation stabilization wait time of main clock
213 × 2/FCH(4.10 ms)
to2/FCH(0.5 µs)
Set by oscillation stabilization wait time setting register (WATR).
Oscillation stabilization wait time of main PLL clock
210 × 2/FCH(512.0 µs)* The time between 2 count (Min) and 3 count (Max) for
210 × 2/FCH is the stabilization standby time.
Watchdog timer220 × 2/FCH(524.29 ms)
219 × 2/FCH(262.14 ms)Count clock for watchdog timer
Prescaler27 × 2/FCH(64.0 µs)
26 × 2/FCH(32.0 µs)Operating clock of prescaler used by peripheral functions
LCD controller
218 × 2/FCH(131.07 ms)
to
215 × 2/FCH(16.38 ms)
Operation clock which LCD controller operates
FCH: Main source oscillation clock
The values in ( ) are for a 4 MHz main source oscillation clock operation.
337
CHAPTER 6 Timebase Timer
6.2 Configuration of Timebase Timer
The timebase timer consists of the following four blocks.• Timebase timer counter• Counter clear circuit• Interval timer selector• Timebase timer control register (TBTC)
Block Diagram of Timebase Timer
Figure 6.2-1 Block Diagram of Timebase Timer
× 21 × 22 × 23 × 24 × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
Timebase timer counter
Counter clear
To prescaler To watchdog timer
Counter clear circuit
Interval timer selector
Reset, Stop the main oscillation clock
Watchdog timer clear
Timebase timerinterrupt
213× 2/ FCH to 2/FCH
FCH
× 219 × 221 × 220 × 222
218× 2/ FCH to 215× 2/ FCH To LCD controller
To clock control block (Main PLL oscillation stabilization wait)
Two dividing of FCH
To clock control blockoscillation stabilizationwait time selector
Timebase timer control register (TBTC)
: Main source oscillation clock
TBIF TBIE TBC1 TBC0 TCLR
338
Timebase timer counter
22-bit down-counter which uses the main oscillation clock divided by two as its count clock.
Counter clear circuit
Controls clearing of the timebase timer counter.
Interval timer selector
This circuit selects one of 4 different bits from the 22 bits that make up the counter of the timebase timer to
use for the interval timer.
Timebase timer control register (TBTC)
Selects the interval time, clears the counter, controls interrupts, and checks the status.
339
CHAPTER 6 Timebase Timer
6.3 Timebase Timer Control Register (TBTC)
The timebase timer control register (TBTC) selects the interval time, clears the counter, controls interrupts, and checks the status.
Timebase Timer Control Register (TBTC)
Figure 6.3-1 Timebase Timer Control Register (TBTC)
Timebase timer initialization bit Read Write
0
1
Interval time select bit
(Main oscillation clock FCH = 4MHz)
0 0 0 11 01 1
TBIE Timebase timer interrupt request enable bit
0 1
Timebase timer interrupt request flag bit
TBIFRead Write
0 Unpassage of interval timer
Clear bit
1 Passage of interval timer
No change, No effect to operation
Address
Initial value
00000000B
R(RM1),W : Read and write enabled (One reading when read modify-write instruction is used as reading value and writing value are different)
R/W : Read and write enabled (Reading value is writing value. ) R0/WX : Undefined bit (Reading value is 0. Writing is no effect to operation. )R0,W : Write only (Writing is enabled. Reading value is 0. )
: Unused : Initial value
"0" is always read. No change, No effect to operation
Clear counter of timebase timer
Interrupt request output is disabled. Interrupt request output is enabled.
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0Bit7TBIF TBIE TBC1 TBC0 TCLR
R(RM1),W R/W R 0/WX R 0/WX R/W R0,W
TCLR
TBC1 TBC0
210 × 2/FCH (512.0 µs)212 × 2/FCH (2.05 ms)214 × 2/FCH (8.19 ms)216 × 2/FCH (32.77 ms)
000AHR 0/WX R/W
340
Table 6.3-1 Functional Description of Each Bit in Timebase Timer Control Register (TBTC)
Bit name Functions
bit7TBIF:interrupt request flag bit of timebase timer
• Becomes to "1" when the interval time selected for the timebase timer elapses. • When this bit and the interruption request enable bit (TBIE) are set to "1", an interruption request is
outputted. • Writing "0" to this bit sets it to "0".• Writing "1" is ignored and has no effect on the operation.• Always read "1" when operating read-modify-write instruction.
bit6TBIE:Interrupt request enable bit of timebase timer
• This bit is used to allow and prohibit interrupt request output to the CPU.• Writing "1" to this bit enables output of timebase timer interrupt requests.• Writing "0" to this bit disables output of timebase timer interrupt requests.• An interrupt request is outputted if this bit and the timebase timer interrupt request flag bit (TBIF) are
"1".
bit5to
bit3Unused bit
• Reading value is always "0". • Write has no effect to operation.
bit2bit1
TBC1, TBC0:Interval time select bits
• This bit selects the interval time.
bit0TCLR:Timebase timer initialization bit
• This bit clears the timebase timer counter. • Writing "1" to this bit initializes all counter bits to "1".• Writing "0" is ignored and has no effect on the operation.• Reading value is always "0". Note:
When the output of the timebase timer is selected as the count clock for the watchdog timer, using this bit to clear the timebase timer also clears the watchdog timer.
TBC1 TBC0Interval time select bits
(at main oscillation clock FCH=4 MHz)
0 0 210 × 2/FCH(512.0 µs)
0 1 212 × 2/FCH(2.05 ms)
1 0 214 × 2/FCH(8.19 ms)
1 1 216 × 2/FCH(32.77 ms)
341
CHAPTER 6 Timebase Timer
6.4 Explanation of Operations of Timebase Timer
The timebase timer operates as an interval timer function.
Operations of Timebase TimerThe counter of the timebase timer is initialized to "3FFFFF" after a reset and starts counting synchronizedwith the main oscillation clock divided by two.
The timebase timer continues to down-count continuously while the main clock is operating. If the mainclock halts, the count stops and the counter is initialized to "3FFFFF".
The settings shown in Figure 6.4-1 are required to use the interval timer function.
Figure 6.4-1 Settings of Interval Timer Function
Setting the timebase timer initialization bit in the timebase timer control register (TBTC:TCLR) to "1"
initializes the counter of the timebase timer to "3FFFFF" and continues counting down. When the selected
interval time has elapsed, the timebase timer interrupt request flag bit in the timebase timer control register
(TBTC:TBIF) becomes "1". In other words, interrupt requests are generated repeatedly at the selected time
intervals based on the time when the counter was last cleared.
Clearing Timebase TimerClearing the timebase timer causes the length of time that the timebase timer output is at the "L" level to
become shorter by up to one half period, or for the "H" level to become longer by up to one half period. If
using the output of the timebase timer in other peripheral functions, this will have effects to such as
changing the count time.
Set up the other peripheral functions such that clearing the counter using the timebase timer initialization
bit (TBTC:TCLR) does not have any unexpected effects.
When the output of the timebase timer is selected as the count clock for the watchdog timer, clearing the
timebase timer also clears the watchdog timer.
In addition to using the timebase timer initialization bit (TBTC:TCLR) to clear the timebase timer, the
timer is also cleared when the main clock is halted and a count for the oscillation stabilization wait time is
required.
• On changing to stop mode from main clock mode or main PLL clock mode.
• On changing to sub clock mode or sub PLL clock mode from main clock mode or main PLL clockmode.
• At power on
• At low-voltage detection reset
The counter of the timebase timer is also cleared and operation halts if a reset occurs while the main clock
is running after the main clock oscillation stabilization wait time has elapsed. However, the counter
continues to operate during a reset if an oscillation stabilization wait time count is required.
0
1 0
: Using bit10
TBTC : Set 1.: set 0.
TBIF TBIE TBC1 TBC0 TCLRBit7 Bit6 Bit5 Bit4 Bit3 Bit0Bit1Bit2
342
Operating Example of Base TimerFigure 6.4-2 shows examples of operation in the following states.
1) When power-on reset generated
2) When transferring to sleep mode during operating of interval timer function in main clock mode and
main PLL clock mode
3) When transferring to stop mode at main clock mode and main PLL clock mode
4) A request to clear the counter is issued.
Changing to the timebase timer is the same as changing to sleep mode.
The timebase timer is cleared and operation halts during stop mode in sub clock mode, sub PLL clock
mode, main clock mode, and main PLL clock mode. On recovering from stop mode, the timebase timer is
used to count the oscillation stabilization wait time.
Figure 6.4-2 Operations of Timebase Timer
000000H
3FFFFF
Counter value(count down)
Count value detectedin WATR: MWT3,2,1,0
Count value detectedin TBTC: TBC1,0
Interval cycle(TBTC: TBC1,0=11H)
Clear by transferringto stop mode
Oscillation stabilization wait time
Oscillation stabilization wait time
4) Counter clear(TBTC: TCLR=1)
Clear at setting interval Clear with interrupt routine
1) Power on reset
TBIF bit
TBIE bitSleep
StopSleep release by timebase timer interrupt (TIRQ)
Stop release by external interrupt
2) SLP bit (STBC register)
3) STP bit (STBC register)
When setting "11" to interval time select bit (TBTC: TBC1,0) of timebase timer control register (216 × 2/FCH)
: Interval time select bit of timebase timer control register: Timebase timer initialization bit of timebase timer control register: Timebase timer interrupt request flag bit of timebase timer control register: Timebase timer interrupt request enable bit of timebase timer control register: Sleep bit of standby control register: Stop bit of standby control register: Main clock oscillation stabilization wait time select bit of oscillation stabilization wait time setting register
TBTC: TBC1,0TBTC: TCLRTBTC: TBIFTBTC, TBIESTBC, SLPSTBC, STPWATR, MWT
343
CHAPTER 6 Timebase Timer
6.5 Interrupt of Timebase Timer
An interrupt is triggered when the selected interval time for the timebase timer elapses (interval timer function).The interrupt number and interrupt vector are listed in the interrupt source table in section XX.
Interrupt of Timebase Timer
Oscillation Stabilization Wait Time and Timebase Timer InterruptsIf the interval time set for the timebase timer is shorter than the main clock oscillation stabilization wait
time, a timebase timer interrupt request will be generated during the main clock oscillation stabilization
wait when changing to clock mode or standby mode.
In this case, before transferring to the mode (stop mode, sub clock mode, sub PLL clock mode) which the
main clock oscillation stops, set the timebase interrupt request enable bit of the timebase timer control
register (TBTC: TBIE) to "0" and disable the timebase timer interrupt.
Table 6.5-1 Timebase Timer Interrupt
Interrupt source Interval passage
Interrupt condition Interval time set in TBTC:TBC1,TBC0 elapsed.
Interrupt flag TBTC:TBIF
Interrupt enable TBTC:TBIE
344
6.6 Program Example of Timebase Timer
Programming examples for the timebase timer are shown below.
Program Example of Timebase Timer
Processing specification
Generates timebase timer interrupts at 216×2/FCH (FCH: main oscillation clock) repeatedly.
Coding example
TBTC EQU 0000AH ;Address of timebase timer control registerTBIF EQU TBTC:7 ;Definition of interrupt request flag bitILR4 EQU 007DH ;Address of the interrupt level set register 4INT_V DSEG ABS ; [DATA SEGMENT]
ORG 0FFDEHTIRQ DW WARI ;Interrupt vector settingINT_V ENDS;----------Main Program------------------------------------------------------
CSEG ; [CODE SEGMENT];Stack pointer(SP), etc.should have been initialized.
: CLRI ;Disables the interrupt.
MOV ILR4,#01111111B ;Interrupt level setting (Level 1)
MOV TBTC,#01000111B ;Interrupt request flag clear, interrupt request output enable, 216 × 2/FCH select, timebase timer clear
SETI ;Interruption permission :
;----------Interrupt Program------------------------------------------------------WARI CLRB TBIF ;Interrupt request flag clear
PUSHW AXCHW A,TPUSHW A :User processing :POPW AXCHW A,TPOPW ARETI
; ------------------------------------------------------------------------------- ENDS
END
345
CHAPTER 6 Timebase Timer
346
CHAPTER 7Watchdog Timer
This chapter explains the functions and operation of the watchdog timer.
7.1 Overview of Watchdog Timer
7.2 Configuration of Watchdog Timer
7.3 Watchdog Control Register (WDTC)
7.4 Explanation of Operations for Watchdog Timer
7.5 Program Examples of Watchdog Timer
347
CHAPTER 7 Watchdog Timer
7.1 Overview of Watchdog Timer
The watchdog timer is a single-bit counter that can use the output of either the timebase timer (which operates on the main clock) or the watch prescaler (which operates on the sub clock) as its count clock. Once started, the watchdog timer generates a reset when it is not cleared over the specified intervals.
Functions of Watchdog TimerThe watchdog timer is a counter for preventing programs from hanging up. The timer should be cleared at
specified intervals regularly after being activated. A watchdog reset is generated if the timer is not cleared
within a fixed time due to a problem such as the program entering an infinite loop.
The output of either the timebase timer or watch prescaler can be selected as the count clock for the
watchdog timer.
Interval time of watchdog timer is shown in Table 7.1-1 . If the counter of the watchdog timer is not
cleared, a watchdog reset is generated between the minimum time and maximum time. Always clear the
counter of the watchdog timer within the minimum time.
*: WDTC: CS1, 0: count clock switching bit for watchdog control register
See "7.4 Explanation of Operations for Watchdog Timer" for details of the minimum
and maximum interval times for the watchdog timer.
Note
• The watchdog timer is also cleared if the timer (timebase timer or watch prescaler) selected as thecount clock for the watchdog timer is cleared. Accordingly, if the software repeatedly clears theselected timer within the interval time set for the watchdog timer, this may unintentionally preventthe watchdog timer from functioning.
Table 7.1-1 Intervals times of watchdog timer
Count clock switch setting bit (WDTC:CS1, 0)*
Minimum time
Maximum time
Timebase timer output(at main oscillation clock =4 MHz)
00 524 ms 1.05 s
01 262 ms 524 ms
at watch prescaler output(at sub oscillation clock=32.768 kHz)
10 500 ms 1.00 s
11 250 ms 500 ms
348
7.2 Configuration of Watchdog Timer
The watchdog timer consists of the following 6 blocks:• Count clock selector• Watchdog timer counter• Reset control circuit• Watchdog timer clear selector• Counter clear control circuit• Watchdog control register (WDTC)
Block Diagram of Watchdog Timer
Figure 7.2-1 Block Diagram of Watchdog Timer
Watchdog control register (WDTC)
221/FCH, 220/FCH(Timebase timer output)
214/FCL, 213/FCL(Watch prescaler output)
Count clockselector
Watchdog timer
Clear Activation
Resetcontrolcircuit
Watchdogtimer counter
OverflowWatchdog timerclear selector
Counter clearcontrol circuit
Clear signal from timebase timer
Clear signal from watch prescaler
Sleep mode startStop mode startTimebase timer/watch mode start
FCH: Main oscillation clockFCL: Sub oscillation clock
RST
CS1 CS0 WTE3 WTE2 WTE1 WTE0
349
CHAPTER 7 Watchdog Timer
Count clock selector
Selects the count clock of watchdog timer counter.
Watchdog timer counter
It is an one-bit counter.
Reset control circuit
Generates a reset signal when the counter of the watchdog timer overflows.
Watchdog timer clear selector
Selects the watchdog timer clear signal.
Counter clear control circuit
Controls the clearing and stopping of the watchdog timer counter.
Watchdog control register (WDTC)
Sets to select the count clock and activates and clears the watchdog timer counter
350
7.3 Watchdog Control Register (WDTC)
The watchdog control register (WDTC) activates and clears the watchdog timer.
Watchdog Control Register (WDTC)
Figure 7.3-1 Watchdog Control Register (WDTC)
Address Bit7
CS1 CS0R/W
Bit0Bit1Bit2Bit3Bit4Bit5Bit6
000CHR/W R0,WR0,WR0,WR0,WR 0/WXR 0/WX
WTE3 WTE0WTE1WTE2
Initial value
00000000B
Watchdog control bitWTE3 WTE0WTE1WTE2
0 1 0 1
Excluding the above-mentioned
• Activating watchdog timer (at first writing after reset)• Clear watchdog timer (at second or more writing after reset)
No effect to operation
CS1 CS00 00 11 01 1
Count clock switching bitOutput cycle of timebase timer (221/FCH)Output cycle of timebase timer (220/FCH)Output cycle of watch prescaler (214/FCL)Output cycle of watch prescaler (213/FCL)
R/WR0,WR0/WX
: Read and write enabled (Reading value is writing value.): Write only (Write is enabled. Reading value is 0.): Undefined bit (Reading value is 0. Writing has no effect to operation.): Unused: Initial value: Main oscillation clock: Sub oscillation clock
FCHFCL
351
CHAPTER 7 Watchdog Timer
Table 7.3-1 Functional Description of Each Bit in Watchdog Control Register (WDTC)
bit name Functions
bit7bit6
CS1, CS0:Count clock switching bit
• This bit selects the count clock for the watchdog timer.
• This is the watchdog control bit. Write to this bit at the same time as you activate the watchdog timer.
• After starting the watchdog timer, change is disabled.Note:
As the timebase timer halts in sub clock mode and sub PLL clock mode, always select the output of the watch prescaler in these modes. Do not select the output of the watch prescaler in single clock models.
bit5bit4
Unused bit• Reading value is "00".• Writing has no effect on the operation.
bit3to
bit0
WTE3, WTE2,WTE1, WTE0:Watchdog timer control bit
• Writing "0101B" starts (first write after a reset) or clears (second and subsequent writes
after a reset) the watchdog timer.• Writing other than "0101B" has no effect on the operation.
• These bits indicate 0000B at reading.
• Read-modify-write instructions cannot be used.
CS1 CS0 Count clock switching bit
0 0 Output cycle of timebase timer (221/FCH)
0 1 Output cycle of timebase timer (220/FCH)
1 0 Output cycle of watch prescaler (214/FCL)
1 1 Output cycle of watch prescaler (213/FCL)
352
7.4 Explanation of Operations for Watchdog Timer
The watchdog timer generates a watchdog reset when a watchdog timer counter overflow occurs.
Operations of Watchdog Timer
Activating watchdog timer
• The watchdog timer is activated the first time "0101B" is written to the watchdog control bits of thewatchdog control register (WDTC: WTE3 to 0). In this case, set the count clock switching bits in thewatchdog control register (WDTC:CS1, 0) simultaneously.
• The watchdog timer cannot be stopped without accepting a reset upon activation.
Clearing watchdog timer
• If the counter is not cleared within the watchdog timer interval time, the counter overflows and awatchdog reset is generated.
• Writing "0101B" to the watchdog control bits in the watchdog control register (WDTC:WTE3 to 0) forthe second and subsequent times clears the watchdog timer counter.
• The watchdog timer is also cleared if the timer (timebase timer or watch prescaler) selected as the countclock for the watchdog timer is cleared.
Operation in Standby Mode
The counter of the watchdog timer is cleared and operation halts when the device enters a standby mode
(sleep, stop, timebase timer, or watch mode) regardless of the clock mode.
Operation restarts when the standby mode is cleared.
353
CHAPTER 7 Watchdog Timer
Interval Time
The interval time varies with the timing of clearing the watchdog timer. Figure 7.4-1 shows the
relationship between the interval time and watchdog timer clear timing when the 221 /FCH (FCH: main
oscillation clock) output of the timebase timer is selected as the count clock (for main oscillation clock = 4
MHz).
Figure 7.4-1 Clearing Watchdog Timer and Interval Time
Minimum time
Maximum time
Timebase timer count clock output
Watchdog 1-bitcounter
Watchdog reset
Timebase timer count clock output
Watchdog 1-bitcounter
Watchdog reset
524 ms
1.05 s
Watchdog clear Overflow
Watchdog clear Overflow
354
7.5 Program Examples of Watchdog Timer
Watchdog timer programming examples are shown below.
Program Examples of Watchdog Timer
Processing specification
• Set the watch prescaler as the count clock immediately after starting the program and then start thewatchdog timer.
• The watchdog timer is cleared each time in loop of the main program.
• Each iteration of the main loop must execute in less than the minimum watchdog timer interval time(500 ms or 250 ms for a 32.768 kHz sub oscillation clock), including interrupt processing time. Theminimum interval time is set by the count clock switching bits in the watchdog control register(WDTC:CS1, 0), such that for a 32.768 kHz sub oscillation clock, "10" specifies 500 ms and "11"specifies 250 ms.
Coding example
WDTC EQU 000CH ;Address of watchdog control registerWDT_CLREQU 10000101B
VECT DSEG ABS ; [DATA SEGMENT]ORG 0FFFEH
RST_V DW PROG ;Reset vector settingVECT ENDS;----------Main Program------------------------------------------------------
CSEG ; [CODE SEGMENT]PROG ;Initializing routine at reset
MOVW SP,#0280H ;Initial value setting of stack pointer (for interrupt processing) :Initialization of peripheral function and interrupt, etc. :
INIT MOV WDTC,#WDT_CLR ;Activating watchdog timer: ;Select the watch prescaler as the count clock.
MAIN MOV WDTC,#WDT_CLR ;Clearing watchdog timer :User processing (Meanwhile, the interrupt processing might be generated.) :JMP MAIN ;The loop must execute in less than the minimum interval time for
the watchdog timer.ENDS
;--------------------------------------------------------------------------------END
355
CHAPTER 7 Watchdog Timer
356
CHAPTER 8Watch Prescaler
This chapter describes the function and operation of the watch prescaler.
8.1 Overview of Watch Prescaler
8.2 Configuration of Watch Prescaler
8.3 Watch Prescaler Control Register (WPCR)
8.4 Operations of Watch Prescaler
8.5 Interrupt of Watch Prescaler
8.6 Programming Example of Watch Prescaler
357
CHAPTER 8 Watch Prescaler
8.1 Overview of Watch Prescaler
The watch prescaler is a 15-bit free-run counter that counts down synchronized with the sub clock oscillation divided by two. The watch prescaler has an interval timer function that can select from four different interval times.The clock prescaler also provides the timer output for the sub clock oscillation stabilization wait time and the operating clock for the watchdog timer.
Interval Timer FunctionThe watch prescaler can generate repeated interrupt requests at a fixed interval by counting the suboscillation clock divided by two.
• The counter of the watch prescaler counts down and sets the watch interrupt request flag bit in the watchprescaler control register (WPCR:WTIF) to "1" each time the selected interval time elapses.
• The interval time can be selected from four different option.
Table 8.1-1 lists the watch prescaler interval time.
Note:
The watch prescaler cannot be used on single-clock models.
Function of Clock SupplyThe clock supply function of the watch prescaler provides the timer output for the sub clock oscillationstabilization wait time (15 available settings) and can supply the clock to the watchdog timer.
Halting the output of the watch prescaler also halts the clocks supplied by the watch prescaler.
Table 8.1-2 lists the cycles of the clocks supplied from the watch prescaler.
Table 8.1-1 Interval time of watch prescaler
Internal count clock cycle Interval Time
2/FCL(61.0 µs)
211 × 2/FCL(125 ms)
212 × 2/FCL(250 ms)
213 × 2/FCL(500 ms)
214 × 2/FCL(1.00 s)
FCL: Sub oscillation clockThe value in parentheses is a value when sub oscillation clock 32.768 kHz operating.
Table 8.1-2 Clock supplied from watch prescaler
Where to supply clock Sub clock cycle Remark
Sub clock oscillation stabilization wait time of sub clock
214 × 2/FCL(1.00 s) to
2/FCL(61.0 µs)Setting by the setting register of oscillation stabilization wait time
Watchdog timer213 × 2/FCL(500 ms)
212 × 2/FCL(250 ms)Watchdog timer count up clock
FCL: Sub oscillation clock
Figures enclosed in () are for 32.768 kHz sub clock operation.
358
8.2 Configuration of Watch Prescaler
The watch prescaler consists of the following four blocks.• Counter for watch prescaler• Counter clear circuit• Interval timer selector• Watch prescaler control register (WPCR)
Block Diagram of Watch Prescaler
Figure 8.2-1 Block Diagram of Watch Prescaler
Reset, sub-oscillation clock stop
Watch prescaler counter To watchdog timer
Two divisionof FCL
Counter clear
Watchdog timer clear
Counter clearcircuit
Interval timer selector
214 × 2/FCH to 2/FCHTo clock control blockoscillation stabilizationwait time selector
Watch interrupt
Watch prescaler control register (WPCR)
FCL: Sub oscillation clock
WTIF WTIE WCLRWTC0WTC1
× 214 × 215× 213× 212× 211× 210× 29× 28× 27× 26× 25× 24× 23× 21 × 22
359
CHAPTER 8 Watch Prescaler
Counter for watch prescaler
A 15-bit down-counter that uses the sub clock divided by two as its count clock.
Counter clear circuit
Controls the clear of watch prescaler
Interval timer selector
This circuit selects one of four bits in the counter of the clock timer to use to generate the interval time.
Watch prescaler control register (WPCR)
Selects a interval time, clears the counter, controls interrupts, and checks the status.
360
8.3 Watch Prescaler Control Register (WPCR)
The watch prescaler control register (WPCR) is used to select the interval time, clear the counter, control interrupts, and check the status.
Watch Prescaler Control Register (WPCR)
Figure 8.3-1 Watch Prescaler Control Register (WPCR)
0
1
0 0 0 11 01 1
Address Bit7 Bit6 Bit0Bit1Bit2Bit3Bit4Bit5
WTIF WTIE WCLRWTC0WTC1R(RM1),W R/W R0,WR/WR/WR0/WXR0/WXR0/WX
000BH
Initial value
00000000B
Watch timer initialization bitRead Write
"0" is always readNo change, No effect to operation
WCLR
WTC0WTC1
Counter of watch prescaleris cleared.
Watch interrupt interval timer time select bit(when sub oscilltaion clock FCL = 32.768 kHz)
211 × 2/FCL (125 ms)212 × 2/FCL (250 ms)213 × 2/FCL (500 ms)214 × 2/FCL (1.00 s)
WTIF
WTIE Interrupt request enable bitInterrupt request output is disabled.Interrupt request output is enabled.
Watch interrupt request flag bit
Read WriteUnpassage of interval timePassage of interval time
Clear the bit.
No change, No effect to operation
R (RM1), W
R/W
R0/WX
R0,W
: Read and write enabled (Reading value is different from writing value. 1-read at read-modify-write instruction.): Read and write enabled (Reading value is writing value.): Undefined bit (Reading value is 0. Writing has no effect to operation.): Write only (Write is enabled. Reading value is 0.): Unused: Initial value
0
1
01
361
CHAPTER 8 Watch Prescaler
Table 8.3-1 Function description of each bit of watch prescaler control register (WPCR)
Bit name Functions
Bit7WTIF: Watch interrupt request flag bit
• Becomes "1" after the interval time set for the watch prescaler elapses. • When this bit and the interruption request enable bit (WTIE) are set to "1", an interrupt
request is outputted. • Writing "0" to this bit sets it to "0".• Writing "1" is ignored and has no effect on the operation.• Always read "1" by read-modify-write instruction.
Bit6WTIE: Interrupt request enable bit
• This bit is used to allow and prohibit interrupt request output to the CPU.• Writing "1" to this bit enables output of watch prescaler interrupt requests.• Writing "0" to this bit disables output of watch prescaler interrupt requests.• An interrupt request is output when this bit and the clock interrupt request flag bit
(WTIF) are both "1".
Bit5to
Bit3Unused bit
• Reading value is always "0". • Writing has no effect to the operation.
Bit2Bit1
WTC1, WTC0: Watch interrupt and interval time select bits
• This bit sets the interval time.
Bit0WCLR: Watch timer initialization bit
• This bit clears the counter for the watch prescaler. • Writing "1" initializes all the counter bits to "1".• Writing "0" is ignored and has no effect on the operation.• Reading value is always "0". Note:
When the output of the watch prescaler is selected as the count clock for the watchdog timer, using this bit to clear the watch prescaler also clears the watchdog timer.
WTC1 WTC0Interval time select bits
(when sub oscillation clock FCL=32.768 kHz)
0 0 211 × 2/FCL(125 ms)
0 1 212 × 2/FCL(250 ms)
1 0 213 × 2/FCL(500 ms)
1 1 214 × 2/FCL(1.00 s)
362
8.4 Operations of Watch Prescaler
The watch prescaler operates as an interval timer function.
Operations of the Interval Timer Function (Watch Prescaler)The counter of the watch prescaler is initialized to "7FFF" after a reset and starts counting synchronized
with the sub clock oscillation divided by two.
The watch prescaler counts down continuously while the sub clock is running. If the sub clock halts, the
count also halts and is initialized to "7FFF".
The settings shown in Figure 8.4-1 are required to use the interval timer function.
Figure 8.4-1 Settings of Interval Timer Function
Writing "1" to the watch timer initialization bit in the watch prescaler control register (WPCR:WCLR)
initializes the clock prescaler counter to "7FFF" and then continues counting down. The watch interrupt
request flag bit in the watch prescaler control register (WPCR: WTIF) is set to "1" when the selected
interval time elapses. In other words, interrupt requests are generated repeatedly at the selected time
intervals based on the time when the counter was last cleared.
Clear of Watch prescalerClearing the watch prescaler causes the length of time that the watch prescaler output is at the "L" level to
become shorter by up to one half period, or for the "H" level to become longer by up to one half period. If
using the output of the watch prescaler in other peripheral functions, this will have effects such as changing
the count time.
Set up the other peripheral functions such that clearing the counter, using the watch prescaler initialization
bit (WTCR:WCLR) does not have any unexpected effects.
When the output of the watch prescaler is selected as the count clock for the watchdog timer, clearing the
watch prescaler also clears the watchdog timer.
In addition to being cleared by the watch prescaler initialization bit (WTCR:WCLR), the clock prescaler is
also cleared when the sub clock is halted and a count for the oscillation stabilization wait time is required.
• On changing to stop mode from sub clock mode or sub PLL clock mode.
• When the sub clock oscillation stabilization halt bit in the system clock control register (SYCC:SUBS)is set to "1" in main clock mode or main PLL clock mode.
The counter of the watch prescaler is also cleared and operation halts if a reset occurs.
WPCRBit7 Bit6 Bit0Bit1Bit2Bit3Bit4Bit5WTIF WTIE WTC1 WCLRWTC0
0 1 0 10
: Using bit: Set 1.: Set 0.
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CHAPTER 8 Watch Prescaler
Example of Watch Prescaler OperationFigure 8.4-2 shows examples of operation in the following states.
1) When power-on reset is generated
2) On changing to sleep mode from sub clock mode or sub PLL clock mode while the interval timer
function is operating.
3) When transferring to stop mode during operating of interval timer in sub clock mode and sub PLL clock
mode
4) A request to clear the counter is issued.
Changing to the watch mode is the same as changing to sleep mode.
Figure 8.4-2 Example of watch prescaler operation
When the interval time selection bit (WPCR:WTC1,0) of the watch prescaler control register is set to "11" (214 x 2/FCL)
Counter value(count down)
Count value detected inWATR: SWT3,2,1,0
Count value detected inWPCR: WTC1,0
Sub clock oscillation stabilization wait time
1) Power on reset
WTIF bit
interval cycle(WPCR: WTC1, 0 = 11B)
Sub clock oscillation stabilization wait time
Clear by transferring to stop mode
4) Counter clear(WPCR: WCLR = 1)
Clear at settinginterval
Clear in interrupt routine
Sleep
StopSleep released by watch interrupt (WIRQ)
Stop released by external interrupt
WTIE bit
2) SLP bit (STBC register)
3) STP bit (STBC register)
7FFFH
0000H
WPCR: WTC1,0: Interval time select bit of watch prescaler control register WPCR: WTC1,0: Watch timer initialization bit of watch prescaler control register WPCR: WTC1,0: Watch interrupt request flag bit of watch prescaler control register
WPCR: WTC1,0: Sub clock oscillation stabilization wait time select bit of oscillation stabilization wait time setting registerWPCR: WTC1,0: Stop bit of standby control register WPCR: WTC1,0: Sleep bit of standby control register WPCR: WTC1,0: Watch interrupt request enable bit of watch prescaler control register
364
8.5 Interrupt of Watch Prescaler
An interrupt resource is generated when the interval time set for the watch prescaler elapses (interval timer function).The interrupt number and interrupt vector are listed in the interrupt resource table in section XX.
Interrupt of Watch Prescaler
Oscillation Stabilization Wait Time and Watch Prescaler InterruptWhen setting the interval time that is shorter than sub clock oscillation stabilization wait time, during sub
clock oscillation stabilization wait time at recovery by external interrupt, interrupt request of watch
prescaler is generated from the stop mode in sub clock mode or sub PLL clock mode. Accordingly, always
set the watch interrupt request enable bit (WPCR:WTIE) in the watch prescaler control register to "0" to
disable watch prescaler interrupts before changing to stop mode in sub clock mode or sub PLL clock mode.
Table 8.5-1 Interrupt of watch prescaler
Interrupt resource Interval passage
Interrupt condition Interval time set in WPCR:WTC1, WTC0 elapsed.
Interrupt flag WPCR:WTIF
Interrupt enable WPCR:WTIE
365
CHAPTER 8 Watch Prescaler
8.6 Programming Example of Watch Prescaler
This section shows an example program for watch prescaler.
Program Example of Watch Prescaler
Processing specification
Generates clock interrupts repeatedly at 214 × 2/FCL (FCL: sub oscillation clock) intervals. The interval time
in this case is 1.0 s (at 32.768 kHz operation).
Coding example
WPCR EQU 000BH ;Address of watch prescaler control registerWTIF EQU WPCR:7 ;Definition of watch interrupt request flag
bitILR5 EQU 007EH ;Interrupt level setting registerINT_V DSEG ABS ;[DATA SEGMENT]ORG 0FFDCHWIRQ DW WARI ;Interrupt vector settingINT_V ENDS;----------Main Program------------------------------------------------------
CSEG ;[CODE SEGMENT]; Stack pointer(SP), etc. shall be initialized.
:CLRI ;ANDCCR, #0BFH; Disables the interrupt.
MOV ILR5,#11111110B ;Interrupt level setting (level 2)MOV WPCR,#01000111B ;Interrupt request flag clear, interrupt
request output enable, 214 × 2/FCL select,
watch prescaler clearSETI ;Interrupt enable :
;--------- Interrupt Program ----------------------------------------------------WARI CLRB WTIF ;Interrupt request flag clear
PUSHW AXCHW A,TPUSHW A :User processing :POPW AXCHW A,TPOPW ARETI
; ------------------------------------------------------------------------------- ENDS
END
366
CHAPTER 9Watch Counter
This chapter describes the function and operation of the clock counter.
9.1 Overview of Watch Counter
9.2 Block Diagram Watch Counter
9.3 Register of Watch counter
9.4 Interrupt of Watch Counter
9.5 Operations of Watch Counter
9.6 Notes on Using Watch Counter
367
CHAPTER 9 Watch Counter
9.1 Overview of Watch Counter
The watch counter counts the selected count clock the number of times set in the register and then generates an interrupt. The count clock can be selected from four clocks generated by the watch prescaler.
Watch CounterThe watch counter counts the selected count clock the number of times set in the register and then
generates an interrupt. Table 9.1-1 lists the four count clocks. The count value can be set in the range from
0 to 63. No interrupt is generated if "0" is set.
If the count clock period is 1 s and the count value is set to 60, interrupts are generated every one minute.
Fcl: Sub clock source oscillation
Table 9.1-1 Kinds of Count Clock
Count Clock Count cycle when Fcl = 32.768 kHz
212/Fcl 125 ms
213/Fcl 250 ms
214/Fcl 500 ms
215/Fcl 1 s
368
9.2 Block Diagram Watch Counter
Figure 9.2-1 shows a block diagram of the watch counter.
Block Diagram of Clock Counter
Figure 9.2-1 Block diagram of watch counter
Inte
rnal b
us
ISEL WCFLG CTR5 CTR4 CTR3 CTR2 CTR1 CTR0
CS1 CS0 RCTR5 RCTR4 RCTR3 RCTR2 RCTR1 RCTR0
Watch counter status register (WCSR)
Watch counter data register (WCDR)
Counter value
2 /Fcl2 /Fcl2 /Fcl2 /Fcl
12
13
14
15
Fcl:
Watch counterinterrupt
Under flow
Counter clear 6 bitcounter
Interruptenable
Interruptof watchprescaler
Countclockselect
Reload value
369
CHAPTER 9 Watch Counter
9.3 Register of Watch counter
Figure 9.3-1 shows the registers of watch counter.
Register of Watch Counter
Figure 9.3-1 Registers of watch counter
CS1 CS0 RCTR5 RCTR4 RCTR3 RCTR2 RCTR1 RCTR0 00111111B
R/W R/W R/W R/W R/W R/W R/W R/W
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
WCDR (Watch counter data register)
CTR0 00000000B
R/W R(RM1)/W R/WX R/WX R/WX R/WX R/WX R/WX
ISEL WCFLG CTR5 CTR4 CTR3 CTR2 CTR1
bit7 bit6 bit5 bit4 bit3 Initial valuebit2 bit1 bit0
WCDR (Watch counter status register)
370
9.3.1 Watch Counter Data Register (WCDR)
The watch counter data register (WCDR) is used to select the count clock and set the counter reload value.
Watch Counter Data Register (WCDR)
Figure 9.3-2 Watch counter data register (WCDR)
R/W
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00111111BCS1 CS0 RCTR4 RCTR2 RCTR1 RCTR0RCTR5
R/W
RCTR3
: Initial valueR/W : Read and Write enabled (The reading value is the writing value) Fcl :
CS1
0
0
1
1
CS0
0
1
0
1
R/W R/W R/W R/W R/W R/W
RCTR5 toRCTR0
2 /Fcl (125ms)
2 /Fcl (250ms)
2 /Fcl (500ms)
2 /Fcl (1s)
12
13
14
15
Initial value
Setting the reload value of counter (Initial value = 3FH)
Select bit of count clock (Fcl = 32.768 kHz)
Table 9.3.1-1 Function description of each bit in watch counter data register (WCDR)
Bit name Functions
Bit7Bit6
CS1, 0:Count clock selection bits
Clock select of the watch counter is executed.
"00"=212/Fcl, "01"=213/Fcl, "10"=214/Fcl, "11"=215/Fcl (Fcl: Sub clock source oscillation) Only modify this bit when the WCSR:ISEL bit is "0".
Bit5Bit4Bit3Bit2Bit1Bit0
RCTR5 to 0:Counter reload value setting bits
Reload value of counter is set.If modified while counting is in progress, the new value is used to reload the counter when the next underflow occurs.No interrupts are generated if this bit is "0".As the correct value is not loaded if the reload value (RCTR5 to 0) is modified at the same time as an interrupt occurs (WCSR:WCFLG= "1"), always modify the reload value before the interrupt occurs such as while the clock prescaler is halted (WCSR:ISEL bit = 0) or
371
CHAPTER 9 Watch Counter
9.3.2 Watch Counter Status Register (WCSR)
The watch counter status register (WCSR) controls the operation and interrupts for the watch counter. It can also be used to read the count value.
Watch Counter Status Register (WCSR)
Figure 9.3-3 Watch Counter Status Register (WCSR)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00000000BISEL WCFLG CTR4 CTR2 CTR1 CTR0CTR5 CTR3
: Initial valueR/W : Read and Write enabled (The reading value is the writing value)R/WX : Read only (The reading is enabled. The writing has no effect to operation.)R(RM1),W : Read and Write enabled (The reading value is different from the writing value. Read "1" at read-modify-write instruction.)
0
1
R/W R(RM1)/W R/WX R/WX R/WX R/WX R/WX R/WX
ISEL
0
1
WCFLG
Initial value
Counter value can be readCTR5 to CTR0
Interrupt request flag bit
Read Weite
Interrupt request is not generated.
Interrupt request is generated.
Clear this bit.
No change, no effect on operation
Activation of watch counter & interrupt enable bit
Stop the watch counter and disables the watch counter interrupt request. (watch prescaler interrupt request enabled).
Activates the watch counter and enables the watch counter interrupt request. (watch prescaler interrupt request disabled).
372
Table 9.3.2-1 Function description of each bit in watch counter status register (WCSR)
Bit name Functions
Bit7ISEL:Interrupt request enable bit
• This bit is used to start the watch counter and to select whether to enable the watch counter interrupt or watch prescaler interrupt.
• Setting this bit to "0" clears and halts the watch counter. This also disables watch counter interrupt requests and enables watch prescaler interrupt requests.
• Setting this bit to "1" enables output of watch counter interrupt requests and starts the counter. This also disables watch prescaler interrupt requests.
• Always disable the watch prescaler interrupt before setting this bit to "1" to select watch counter interrupts.
• As the watch counter counts the asynchronous watch from the watch prescaler, an error of up to one count clock period may occur in the count start time depending on the timing when the ISEL bit is set to "1".
Bit6WCFLG:Interrupt request flag bit
• This bit goes to "1" when the counter underflow.• A watch counter interrupt is generated if this bit and the ISEL bit are both "1".• Writing "0" sets this bit to "0".• Writing "1" to this bit does not change the bit value and has no effect on the operation.• "0" is always read in the Read-modify-write operation
Bit5Bit4Bit3Bit2Bit1Bit0
CTR5 to CTR0:Counter read bits
• The count value can be read during counting. As the read value may be incorrect if read when the count is changing, always read the counter value twice and only use the result if the same value is read both times.
• Writing to these bits has no effect to operation.
373
CHAPTER 9 Watch Counter
9.4 Interrupt of Watch Counter
The watch counter outputs an interrupt request when the counter underflow (counter value = "1").
Interrupt of Watch CounterTable 9.4-1 lists the interrupt control bits and interrupt resources for the watch counter.
The interrupt request flag bit (WCFLG) in the watch counter status register (WCSR) is set to
"1" when an underflow occurs in the watch counter (bits CTR5 to CTR0 of WCSR). If the watch counter
interrupt request enable bit (ISEL) is "1", a clock counter interrupt request is output to the interrupt
controller.
For interrupt request numbers, see Section 3.4 "Interrupts".
Table 9.4-1 Interrupt control bits and interrupt resources for watch timer
Item Description
Interrupt request flag bit WCFLG bit in the WCSR register
Interrupt request enable bit ISEL bit in the WCSR register
Interrupt cause Underflow of counters (bits CTR5 to CTR0 in the WCSR register)
374
9.5 Operations of Watch Counter
Setting the ISEL bit to "1" starts the watch counter down counting from the count value set in bits RCTR5 to RCTR0 using the count clock selected by bits CS1 and CS0. The WCFLG bit becomes "1" and an interrupt is generated when the counter underflow.
Operations of Watch CounterOperations of watch counter is shown below.
(1) Select the count clock (bits CS1 and CS0) and counter reload value (bits RCTR5 to RCTR0).
(2) Set the ISEL bit to "1" to start the count and enable the interrupt. In this case, disable the watch
prescaler interrupt.
As the watch counter counts the (asynchronous) divided clock of the watch prescaler, an error of up to one
count clock period may occur in the count start time depending on the timing of setting the ISEL bit to "1".
(3) The WCFLG bit becomes "1" and an interrupt is generated when the counter underflow.
(4) Writing "0" to the WCFLG bit clears the bit.
(5) If RCTR5 to RCTR0 are modified while the count is in progress, the reload value is updated when the
counter reaches "1".
(6) Clearing the ISEL bit initializes the counter to "0" and halts the count.
Figure 9.5-1 Operations of watch counter
Operation in Sub Stop ModeThe watch counter stops counting on entering sub stop mode. As the watch prescaler is cleared on entering
sub stop mode, the watch counter cannot count the correct value after recovering from sub stop mode.
Always set the ISEL bit to "0" after recovering from sub stop mode before using the watch counter. The
watch counter continues to operate in standby modes other than sub stop mode.
RCTR5 to 0
WCFLG
ISEL
7 9
CS1,0 "1,1"
CTR5 to 0 70 6 5 4 3 2 1 9 8 7 6 5 4 0
Count clock
(1)
(2)
(3) (4)
(5)
(6)
375
CHAPTER 9 Watch Counter
9.6 Notes on Using Watch Counter
The following describes the points to note when using the watch counter.
• As clearing the watch prescaler while the watch counter is running may interfere with watch counteroperation, set the ISEL bit to "0" when clearing the watch prescaler.
376
CHAPTER 10Wild Register
This chapter describes the operation of the wild register function.
10.1 Overview of Wild Register
10.2 Structure of Wild Register
10.3 Wild Register Registers
10.4 Explanation of Wild Register Operation
10.5 Typical Hardware Connection
377
CHAPTER 10 Wild Register
10.1 Overview of Wild Register
The wild register function can be used to patch the program which has the bugs by specifying the addresses and substitute data in internal registers. The primary purpose of this register is to substitute ROM code in the ROM space. The wild register consists of 3-byte data setting registers, 3-byte upper address setting registers, 3-byte lower address setting registers, a 1-byte address compare enable register, and a 1-byte data test register. The wild register function is described below.
Wild Register FunctionThe wild register consists of three data setting registers, three upper address setting registers, three lower
address setting registers, a 1-byte address compare enable register, and a 1-byte data test register. You can
substitute new data at specific addresses by specifying the addresses and data in these registers. Up to three
bytes of data can be set in the three data setting registers. Similarly, up to three different addresses can be
set in the three upper and lower address setting registers.
You can use the wild register function to substitute ROM code anywhere in the ROM space. This can be
used for program debugging after creating the mask or to patch bugs in the program. This is done by setting
up the wild registers from an external device via the communication bus.
Address Range able to be Substituted by Wild Register FunctionThe wild register can substitute data anywhere in the address space except 0078H.
As address 0078H is the mirror address for the register bank pointer and direct bank pointer, accessing
address 0078H always reads the register bank pointer and direct bank pointer.
378
10.2 Structure of Wild Register
Block diagram of wild register is shown. The wild register consists of the following two blocks.• Memory area block: Data setting register (WRDR0 to WRDR2)
Address setting register (WRAR0 to WRAR2)Address comparing enable register (WREN)Data test setting register (WROR)
• Control circuit block
Block Diagram of Wild Register Function
Figure 10.2-1 Block Diagram of Wild Register Function
Wild register function
Inte
rnal
bus
Control circuit block Access control circuit
Decoder and logic control circuit
Address comparing
circuit
Memory area block
Address setting register(WRAR)
Data setting register(WRDR)
Address comparing enableregister (WREN)
Access controlcircuit
Data test setting register(WROR)
Memory space
379
CHAPTER 10 Wild Register
Memory area
The memory area block consists of the data setting registers (WRDR), address setting registers (WRAR),
address compare enable register (WREN), and data test setting register (WROR). These are used to specify
the addresses and data that the wild register is to substitute. The address compare enable register (WREN)
enables the wild register function for each data setting register (WRDR). Also, the data test setting register
(WROR) enables the read function for each data setting register (WRDR).
Control circuit block
This circuit compares the data set in the address setting registers (WRAR) with the actual address data and,
if the values match, outputs the data from the data setting registers (WRDR) to the data bus. The operation
of the control circuit block can control by the address compare enable register (WREN).
380
10.3 Wild Register Registers
The wild register registers consist of the data setting registers (WRDR), address setting registers (WRAR), address compare enable register (WREN), and data test setting register (WROR).
Wild Register Registers
Figure 10.3-1 Wild Register Function Registers
bit7RD7
0F80H,0F81H WRAR0 RA15
EN2
DRR2
Wild register data setting register (WRDR0 to WRDR2)
Wild register address setting register (WRAR0 to WRAR2)
Wild register address comparing enable register (WREN)
Wild register data test setting register (WROR)
Address
Address
Address
Address
Reserved bit Reserved bitReserved bit
Reserved bit Reserved bitReserved bit
bit6 bit0bit3 bit1bit2bit4bit5RD5 RD4 RD2 RD0RD1RD3RD6
bit15 bit0
RA00F83H,0F84H WRAR10F86H,0F87H WRAR2
EN1 EN00076H WREN
0077H WROR DRR1 DRR0
0F82H WRDR00F85H WRDR15F88H WRDR2
bit7 bit6 bit0bit3 bit1bit2bit4bit5
bit7 bit6 bit0bit3 bit1bit2bit4bit5
381
CHAPTER 10 Wild Register
Wild Register NumberSpecifies the address setting register (WRAR) and data setting register (WRDR) corresponding to the wild
register number.
Table 10.3-1 Address Setting Register and Data Setting Register for Each Wild Register Number
Wild register number Address setting register (WRAR) Data setting register (WRDR)
0 WRAR0 WRDR0
1 WRAR1 WRDR1
2 WRAR2 WRDR2
382
10.3.1 Data Setting Register (WRDR0 to WRDR2)
The data setting registers (WRDR0 to WRDR2) specify the substitute data to be used by the wild register function.
Data Setting Register (WRDR0 to WRDR2)
Figure 10.3-2 Data Setting Register (WRDR0 to WRDR2)
RD7R/W
00000000B0F82H
WRDR1
Address Initial value
Address Initial value
Address Initial value
R/W: Read and write enabled (Reading value is writing value.)
bit7 bit6 bit0bit3 bit1bit2bit4bit5
RD5 RD3 RD2 RD1 RD0RD6 RD4R/W R/W R/W R/W R/W R/W R/W
WRDR0
WRDR2
0F85H
0F88H
bit7 bit6 bit0bit3 bit1bit2bit4bit5
bit7 bit6 bit0bit3 bit1bit2bit4bit5
00000000B
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/WRD7 RD5 RD3 RD2 RD1 RD0RD6 RD4
RD7 RD5 RD3 RD2 RD1 RD0RD6 RD4
Table 10.3-2 Explanation of Each Data Setting Register (WRDR) Bit
Bit name Functions
Bit7 to
Bit0
RD7,RD6,RD5,RD4,RD3,RD2,RD1,RD0:Wild register data setting bit
Set the new data to substitute using the wild register function.• These bits specify the new data for the address specified by the address setting
register (WRAR). The data applies to the address set for the corresponding wild register number.
• Reading these bits is only enabled if the corresponding data test setting bit in the data test setting register (WROR) is 1.
383
CHAPTER 10 Wild Register
10.3.2 Address Setting Register (WRAR0 to WRAR2)
The address setting registers (WRAR0 to WRAR2) specify the addresses for which the wild register function is to substitute data.
Address Setting Register (WRAR0 to WRAR2)
Figure 10.3-3 Address Setting Register (WRAR0 to WRAR2)
RA15
WRAR0
Address Initial value
R/W: Read and write enabled (Reading value is writing value.)
Address Initial value
Address Initial value
Address Initial value
Address Initial value
Address Initial value
bit7 bit6 bit0bit3 bit1bit2bit4bit5
00000000B0F80H
bit15 bit14 bit8bit11 bit9bit10bit12bit13
bit7 bit6 bit0bit3 bit1bit2bit4bit5
bit15 bit14 bit8bit11 bit9bit10bit12bit13
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
bit15 bit14 bit8bit11 bit9bit10bit12bit13
bit7 bit6 bit0bit3 bit1bit2bit4bit5
0F81H
0F83H
0F84H
0F86H
0F87H
WRAR1
WRAR2
RA14 RA13 RA12 RA11 RA10 RA9 RA8
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8
00000000B
00000000B
00000000B
00000000B
00000000B
Table 10.3-3 Explanation of Each Address Setting Register (WRAR) Bit
Bit name Functions
Bit15 to
Bit0
RA15,RA14,RA13,RA12,RA11,RA10,RA9,RA8,RA7,RA6,RA5,RA4,RA3,RA2,RA1,RA0: Wild register address Setting bit
Specifies the address that the wild register function is to modify.• Set the assigned address in these bits. This register specifies the address for the
corresponding wild register number.
384
10.3.3 Address Compare Enable Register (WREN)
The address compare enable register (WREN) enables or disables operation of the wild register independently for each wild register number.
Address Compare Enable Register (WREN)
Figure 10.3-4 Address Compare Enable Register (WREN)
EN2
Address Initial value
: Undefined bit (Reading value is 0 and write has no effect to operation.): Reserved bit (Writing value is 0 and reading value is 0.): Read and write enabled (Reading value is writing value.): Unused
R0/WXR0/W0R/W
Reserved bit Reserved bit Reserved bit
bit7 bit6 bit0bit3 bit1bit2bit4bit5
R0/WX R0/WX R0/W0 R0/W0 R0/W0 R/W R/W R/WEN1 EN0 00000000B0076H
Table 10.3-4 Explanation of Address Compare Enable Register (WREN) Functions
Bit name Function
Bit7Bit6
Unused bit• Reading value is "0". • Writing has no effect.
Bit5 to
Bit3Reserved bit
Reserved bit• Reading always returns 0.• Always write 0.
Bit2 to
Bit0
EN2,EN1,EN0: Wild register address comparing enable bit
Enables or disables operation of the wild register function.• EN0 corresponds to wild register number 0.• EN0 corresponds to wild register number 1.• EN0 corresponds to wild register number 2.• Operation of the wild register function is disabled if these bits are 0.• Operation of the wild register function is enabled if these bits are 1.
385
CHAPTER 10 Wild Register
10.3.4 Data Test Setting Register (WROR)
The data test setting register (WROR) enables or disables reading for each data setting register (WRDR0 to WRDR2).
Data Test Setting Register (WROR)
Figure 10.3-5 Data Test Register (WROR)
DRR2
Address Initial value
: Undefined bit (Reading value is 0 and write has no effect to operation.): Reserved bit (Writing value is 0 and reading value is 0.): Read and write enabled (Reading value is writing value.): Unused
R0/WXR0/W0R/W
Reserved bit Reserved bit Reserved bit
bit7 bit6 bit0bit3 bit1bit2bit4bit5
R0/WX R0/WX R0/W0 R0/W0 R0/W0 R/W R/W R/W
00000000B0077H DRR1 DRR0
Table 10.3-5 Explanation of Data Test Setting Register (WROR) Functions
Bit name Function
Bit7Bit6
Unused bit• Reading value is "0".• Writing has no effect.
Bit5 to
Bit3Reserved bit
Reserved bit• Reading always returns 0.• Always write 0.
Bit2 to
Bit0
DRR2,DRR1,DRR0: Wild register data test setting bit
Enables or disables reading from the corresponding data setting register of the wild register function.• DRR0 enables reading of the data setting register (WRDR0).• DRR1 enables reading of the data setting register (WRDR1).• DRR2 enables reading of the data setting register (WRDR2).• Reading is disabled if these bits are 0.• Reading is enabled if these bits are 1.
386
10.4 Explanation of Wild Register Operation
To use the wild register, set the addresses to be patched in the address setting registers (WRAR0 to WRAR2) and set the substitute data in the data setting registers (WRDR0 to WRDR2).The wild register function is enabled independently for each wild register number by setting the corresponding enable bit in the address compare enable register (WREN).This section describes the sequence of operation for the wild register.
Operation of Wild RegisterBefore executing the main program, execute a special program to read the wild register setting values from
external memory (EEPROM, for example). The following describes the procedure for setting the wild
registers. Note that the communication method used to transfer data between external memory and the
device is not specified here.
• Write the addresses of the internal ROM code to be modified to the address setting registers (WRAR0 toWRAR2).
• Write the new code to the corresponding data setting registers (WRDR0 to WRDR2).
• Write to the corresponding bits in the address compare enable register (WREN) to enable the wildregister function.
Table 10.4-1 lists the sequence of steps for setting the wild register registers.
Table 10.4-1 Register Setting Sequence for Wild Register
Order of operation
Operation Operation example
1Read the substitute data from outside the device via any of the communication methods.
Set the address of the internal ROM code to modify at location F011H and set
the modify data at B5H.A maximum of three internal ROM code locations
can be modified.
2Write the substitute addresses to the address setting registers (WRAR0 to WRAR2).
Address setting registerFrame Number is set;WRAR0=F011H,WRAR1=...,WRAR2=...
3Write the new ROM code (the data to substitute for the internal ROM code) to the data setting registers (WRDR0 to WRDR2).
Data setting registerFrame Number is set;WRDR0=B5H,WRDR1=...,WRDR2=...
4
When substituting more than one internal ROM code, repeat this for wild registers 1 to 3. Data can be modified for a maximum of three addresses.
Repeat steps 1 to 3.
5Enable the corresponding bits in the address compare enable register (WREN).
Setting 1 to bit 0 of the address compare enable register (WREN) enables the wild register function. If the address matches an value set in one of the address setting registers (WRAR), the value set in the data setting register (WRDR) is substituted for the internal ROM code. If more than one internal ROM code needs to be substituted, enable the corresponding bits in the address compare enable register (WREN).
387
CHAPTER 10 Wild Register
10.5 Typical Hardware Connection
This shows a typical hardware connection used for the wild register function.
Hardware Connection
Figure 10.5-1 General Connection Between Hardware
E2PROM
SOSI
SCK
(Correcting program storing)
MB95XXX seriesSOSI
SCK
388
CHAPTER 11Prescaler
This chapter describes the function and operation of the prescaler.
11.1 Overview of Prescaler
11.2 Block Diagram of Prescaler
11.3 Operations of Prescaler
11.4 Notes on Using Prescaler
389
CHAPTER 11 Prescaler
11.1 Overview of Prescaler
The prescaler generates the count clock source for various internal resources from the machine clock (MCLK) and the count clock of the time-base timer.
PrescalerThe prescaler generates the count clock source for various internal resources from the machine clock
(MCLK) that drives the CPU and the count clock of the time-base timer (27/FCH or 28/FCH). The count
clock source is used by the following internal resources. The count clock is either the divided or buffered
output of the prescaler. The prescaler does not have a control register and operates continuously driven by
the machine clock (MCLK) and the count clock of the time-base timer (27/FCH or 28/FCH).
• 8/16-bit multifunction timer 0, 1
• 16-bit reload timer 0, 1
• 16-bit PPG timer 0, 1
• 16-bit PPG timer 0, 1, 2
• UART/SIO baud rate generator 0, 1
• 10-bit A/D converter
390
11.2 Block Diagram of Prescaler
Figure 11.2-1 shows a block diagram of the prescaler.
Block Diagram of Prescaler
Figure 11.2-1 Block Diagram of Prescaler
5-bit Counter 1
The machine clock (MCLK) is counted by a 5-bit counter and the count value is output to the outputcontrol circuit.
Output control circuit
Based on the counter count value, this supplies clocks consisting of the machine clock (MCLK) dividedby 2, 4, 8, 16, or 32 to the various resources. The circuit also buffers the clock from the timebase timer
(27/FCH and 28/FCH) and supplies this to the resources.
2/ MCLK2/ MCLK
Prescaler
Outputcontrolcircuit
Counter value4/ MCLK4/ MCLK
8/ MCLK8/ MCLK
16/ MCLK16/ MCLK
32/ MCLK32/ MCLK
27/ Fch/ Fch
28/ Fch/ Fch
To various internalTo various internalresourcesresources
5 bit Counter
27/ Fch/ Fch
28/ Fch/ Fch
Fromtimebase timer
MCLK *
*: MCLK: Machine clock (internal operating frequency)
391
CHAPTER 11 Prescaler
11.3 Operations of Prescaler
The prescaler generates the count clock source supplied to the various resources.
Operations of Prescaler
The prescaler divides the machine clock (MCLK) or generates the time-base timer (27/FCH and 28/FCH)
signal, and supplies these to the internal resources as the count clock sources. The prescaler operates
continuously while the machine clock and timebase timer clocks are running.
The count clock sources generated by the prescaler are listed below.
Table 11.3-1 Count clock sources generated by prescaler
Count Clock Source Cycle Cycle (When FCH=10 MHz, MCLK=10 MHz)
2/MCLK MCLK/2 (5 MHz)
4/MCLK MCLK/4 (2.5 MHz)
8/MCLK MCLK/8 (1.25 MHz)
16/MCLK MCLK/16 (0.625 MHz)
32/MCLK MCLK/32 (0.3125 MHz)
27/ FCH FCH /27 (78 kHz)
28/ FCH FCH /28 (39 kHz)
392
11.4 Notes on Using Prescaler
The following describes points to note when using the prescaler.
The prescaler uses the machine clock and timebase timer clock and operates continuously while these
clocks are running. Accordingly, the operation of various resources immediately after they are first
activated may vary by up to one cycle of the clock used by the resource, depending on the prescaler output
value.
Figure 11.4-1 Clock Capturing Error Immediately after Activating
The following functions are affected by the prescaler count value.
• UART/SIO
• 8/16-bit composite timer
• 8/16-bit PPG
• 16-bit PPG
• 16-bit reload timer
• A/D converter
Output of prescaler
Resource activation
Clock capturing byresource
Clock capturing errorimmediately after activating
393
CHAPTER 11 Prescaler
394
CHAPTER 128/16-bit Composite Timer
This chapter describes the functions and operations of an 8/16-bit composite timer.
12.1 Overview of 8/16-bit Composite Timer
12.2 Configuration of 8/16-bit Composite Timer
12.3 Channels of 8/16-bit Composite Timer
12.4 Pins of 8/16-bit Composite Timer
12.5 Register of 8/16-bit Composite Timer
12.6 Operating Explanation of Interval Timer Function (One-shot Mode)
12.7 Operating Explanation of Interval Timer Function (Continuous Mode)
12.8 Operating Explanation of Interval Timer Function (Free-running Mode)
12.9 Operating Explanation of PWM Timer Function (Fixed-period Mode)
12.10 Operating Explanation of PWM Timer Function (Variable-period Mode)
12.11 Operating Explanation of PWC Timer Function
12.12 Operating Explanation of Input Capture Functions
12.13 Explanation of Noise Filter Operation
12.14 States in Each Mode During Operation
12.15 Interrupt of 8/16-bit Composite Timer
12.16 Note on Using 8/16-bit Composite Timer
395
CHAPTER 12 8/16-bit Composite Timer
12.1 Overview of 8/16-bit Composite Timer
The 8/16-bit composite timer comprises two 8-bit counters. They can either serve as two individual 8-bit timers or be cascaded into a single 16-bit timer. This composite timer can select its function from among 16 different timer functions including interval timer, PWM timer, pulse width count (PWC) timer, and input capture timer by the register setting. When the composite timer is sued as two 8-bit timers, independent timer functions can be selected separately except the PWM timer function (variable-period mode).
Interval Timer Function (One-shot Mode)When the interval timer function (one-shot mode) is selected, the counter starts counting from "00H" as the
timer is started. When the counter value matches the register setting value, the timer output is inverted, the
interrupt flag is set to "1", and the count operation is stopped.
Interval Timer Function (Continuous Mode)When the interval timer function (continuous mode) is selected, the counter starts counting from "00H" as
the timer is started. When the counter value matches the register setting value, the timer output is inverted,
the interrupt flag is set to "1", the count operation is continued from "00H" again. The timer outputs a
square waveform through this repeated operation.
Interval Timer Function (Free-runnig Mode)When the interval timer function (free-running mode) is selected, the counter starts counting from "00H".
When the counter value matches the register setting value, the timer output is inverted and the interrupt flag
is set to "1". When the counter continues to count to reach "FFH", it restarts counting from "00H" again to
continue. The timer outputs a square waveform through this repeated operation.
PWM Timer Functions (Cycle Fixed Mode)When the PWM timer function (fixed-period mode) is selected, a PWM signal variable in "H" pulse width
is generated at fixed intervals. The period is fixed to "FFH" during 8-bit operation or "FFFFH" during 16-bit
operation. The time is determined by the count clock selected. The "H" pulse width is specified by setting a
register.
PWM Timer Functions (Cycle Changeable Mode)When the PWM timer function (variable-period mode) is selected, two 8-bit counters are used to generate
an 8-bit PWM signal at arbitrary intervals and duty depending on the period and L pulse width specified by
registers.
In this operation mode, the composite timer cannot serve as a 16-bit counter.
PWC Timer FunctionsWhen the PWC timer function is selected, the width and period of an external input pulse can be measured.
The edges to start and end counting are selected by timer operation mode setting.
In this operation mode, the counter starts counting from "00H" upon detection of a count start edge of an
external input signal and transfers the count value to a register to generate an interrupt upon detection of a
count end edge.
396
Input Capture FunctionWhen the input capture function is selected, the counter value is stored in a register upon detection of an
edge for an external input signal. The edge to be detected is selected by timer operation mode setting.
This function is available in either free-running mode or clear mode, which can be selected by timer
operation mode setting.
In clear mode, the counter starts counting from "00H" and transfers its value to a register to generate an
interrupt upon detection of an edge. In this case, the counter continues to count from "00H".
In free-running mode, the counter transfers its value to a register to generate an interrupt upon detection of
an edge. In this case, however, the counter continues to count without being cleared.
397
CHAPTER 12 8/16-bit Composite Timer
12.2 Configuration of 8/16-bit Composite Timer
The 8/16-bit composite timer consists of the following blocks. • 8-bit counter x 2 channels• 8-bit comparator (including a temporary latch) x 2 channels• Data register x 2 channels (T00DR/T01DR)• Control status register 0 x 2 channels (T00CR0/T01CR0)• Control status register 1 x 2 channels (T00CR1/T01CR1)• Timer mode control register (TMCR0)• Output controller x 2 channels• Control logic x 2 channels• Count clock selector x 2 channels• Edge detector x 2 channels• Noise filter x 2 channels
Block Diagram of 8/16-bit Composite Timer
398
Figure 12.2-1 Block Diagram of 8/16-bit Composite Timer
8-bit counter
8-bit comparator
8-bit data register
Count
Edge Detector
Pulse
OutputController
Timer
Cont
rol L
ogic
s
IFE
STA
Timer 00
Timer 01
IRQLogics
IRQ0
8-bit counter
8-bit comparator
8-bit data register
Edge Detector
Pulse
OutputController
Timer
Con
trol
Logic
s
IFE C2 C1 C0 F3 F2 F1 F0
Output
Output
16-bit Mode clock
T00CR0
T00CR1
T01CR1
T01CR0
TO00
EC00
TO01
ENO0
ENO1
IRQ116-bit mode
clockselector
::
Countclockselector
NoiseFilter
control signals
CK00
CK06
::
clocks from
prescalar/ TBT
::
CK10
CK16
::
clocks from
prescalar/ TBT
EC01
NoiseFilter
External Input
STA
TO1
CK07
CK17
TMCR*
*: Register shared by timer00 and timer01
TII0
EC0
F0F1F2F3C0C1C2
FE01FE11 FE10 FE00 TO0 MODIIS
SOIFBFIR OEIE HO
IE IRHO OESOIFBF
399
CHAPTER 12 8/16-bit Composite Timer
8-bit counter
The counter serves as the basis for various timer operations. It can be used either as two channels of 8-bitcounters or as a single channel of 16-bit counter.
8-bit comparator
The comparator compares the values in the data register and counter. It incorporates a latch to temporarilystore the data register value.
Data register
The data register is used to write the maximum value counted during interval timer or PWM timeroperation and to read the count value during PWC timer or input capture operation.
Control status register (T00CR0/T01CR0)
This register is used to select the timer operation mode, select the count clock, and to enable or disable IFflag interrupts.
Control status register (T00CR1/T01CR1)
This register is used to control interrupt flags, timer output, and timer operation.
Timer mode control register (TMCR0)
This register is used to select the noise filter function, 8-bit or 16-bit operation mode, and signal input totimer 00 and to indicate the timer output value.
Output controller
The output controller controls timer output. The timer output is supplied to the external pin when the pinoutput has been enabled.
Control logic
The control logic controls timer operation.
Count clock selector
The selector selects the counter operation clock signal from among prescaler outputs (machine clockdivided signal and timebase timer output).
Edge detector
The edge detector selects the edge of an external input signal to be used as an event for PWC timeroperation or input capture operation.
Noise filter
This filter serves as a noise filter for external input signals. H-pulse noise, L-pulse noise, or H/L-pulsenoise elimination can be selected as the filter function.
TII0 internal pin (internally connected to the LIN-UART, available only in channel 0)
The TII0 pin serves as the signal input pin for timer 00; it is connected to the LIN-UART inside the chip.For how to use the pin, see the chapter for the LIN-UART. Note that the TIIO pin in channel 1 is internallyfixed to "0".
400
12.3 Channels of 8/16-bit Composite Timer
This section describes the channels of 8/16-bit composite timer.
Channels of 8/16-bit Composite TimerThis series contains two channels of 8/16-bit composite timer.
The following tables list the external pins and registers corresponding to each channel.
The sections that follow describe only the 8/16-bit composite timer in channel 0.
Table 12.3-1 8/16-bit Composite Timer Channels and Corresponding External Pins
Channel Pin Name Pin Function
0
TO00 Timer 00 output
TO01 Timer 01 output
EC0 Timer 00 input and timer 01 input
1
TO10 Timer 10 output
TO11 Timer 11 output
EC1 Timer 10 input and timer 11 input
Table 12.3-2 8/16-bit Composite Timer Channels and Corresponding Registers
Channel Register Name Registers
0
T00CR0 Timer 00 control status register 0
T01CR0 Timer 01 control status register 0
T00CR1 Timer 00 control status register 1
T01CR1 Timer 01 control status register 1
T00DR Timer 00 data register
T01DR Timer 01 data register
TMCR0 Timer 00/01 timer mode control register
1
T10CR0 Timer 10 control status register 0
T11CR0 Timer 11 control status register 0
T10CR1 Timer 10 control status register 1
T11CR1 Timer 11 control status register 1
T10DR Timer 10 data register
T11DR Timer 11 data register
TMCR1 Timer 10/11 timer mode control register
401
CHAPTER 12 8/16-bit Composite Timer
12.4 Pins of 8/16-bit Composite Timer
This section describes the pins related to the 8/16-bit composite timer.
Pins Related to 8/16-bit Composite TimerThe external pins related to the 8/16-bit composite timer are TO00, TO01, EC00, and EC01 as well as TIIO
for chip internal connection.
TO00 pins
TO00:
This pin serves as the timer output pin for timer 00 during 8-bit operation or for timers 00 and 01 during16-bit operation. When the output is enabled (T00CR1:OE = 1) in interval timer, PWM timer, or PWCtimer function, the pin is set for output automatically regardless of the port x direction register(DDRx:bitx) to serve as the timer output TO00 pin.
The output remains indeterminate when the input capture function has been selected.
TO01 pins
TO01:
This pin serves as the timer output pin for timer 01 during 8-bit operation. When the output is enabled(T00CR1:OE = 1) in interval timer, PWM timer (fixed-period mode), or PWC timer function, the pin isset for output automatically regardless of the port x direction register (DDRx:bitx) to serve as the timeroutput TO01 pin.
The output remains indeterminate during 16-bit operation when the PWM timer function (variable-periodmode) or input capture function has been selected.
EC0 pins
The EC0 pin is connected to the EC00 and EC01 internal pins.
EC00 internal pin:
This pin serves as the external count clock input pin for timer 00 when the interval timer or PWM timerfunction has been selected or the signal input pin for timer 00 when the PWC timer or input capturefunction has been selected. The pin cannot be set as the external count clock input pin when the PWCtimer or input capture function has been selected.
To use this input feature, set the port direction register (DDRx:bitx) to "0" to set the pin as an input port.
EC01 internal pin:
This pin serves as the external count clock input pin for timer 00 when the interval timer or PWM timerfunction has been selected or the signal input pin for timer 01 when the PWC timer or input capturefunction has been selected. The pin cannot be set as the external count clock input pin when the PWCtimer or input capture function has been selected.
This input is not used during 16-bit operation. The input can be used as well when the PWM timerfunction has been selected (variable-period mode).
To use this input feature, set the port direction register (DDRx:bitx) to "0" to set the pin as an input port.
402
12.5 Register of 8/16-bit Composite Timer
This section describes the register related to the 8/16-bit composite timer.
Register Related to 8/16-bit Composite Timer
Figure 12.5-1 Register Related to 8/16-bit Composite Timer
T00CR0/T01CR0 (Control status register 0)bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
IFE C2 C1 C0 F3 F2 F1 F0 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
T00CR1/T01CR1 (Control status register 1)bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
STA HO IE IR BF IF SO OE 00000000B
R/W R/W R/W R/WX R(RM1),W R/W R/W
T00DR/T01DR (Data register)bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
TMCR0 (Timer mode control register)bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
00000000B
R/WX R/WX R/W R/W R/W R/W R/W R/W
R/WR(RM1),W
R/WX
R(RM1),W
TO1 TO0 IIS MOD FE11 FE10 FE01 FE00
: Read and write enabled: Read enabled (RMW read "1") and write enabled (including the case reading value is different from writing value): Read enabled and write disabled
403
CHAPTER 12 8/16-bit Composite Timer
12.5.1 Control Status Register 0 (T00CR0/T01CR0)
The control status register 0 (T00CR0/T01CR0) selects the timer operation mode, selects the count clock, and enables or disables IF flag interrupts. The T00CR0 and T01CR0 registers correspond to timers 00 and 01, respectively.
Control Status Register 0 (T00CR0/T01CR0)
Figure 12.5-2 Control Status Register 0 (T00CR0/T01CR0)
F2 F1 F0 Timer operation mode selection bit
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
IFE IF flag interrupt enable
0 IF flag interrupt disabled
1 IF flag interrupt enabled
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
IFE C2 C1 C0 F3 F2 F1 F0 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
R
F3
0
0
0
0
0
0
0
0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
1
1
1
1
1
1
1
C2 C1 C0 Count clock selection bit
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 External clock
Interval timer (one-shot mode)
Interval timer (continuous mode)
Interval timer (free-running mode)
PWM timer (fixed-cycle mode)
PWM timer (variable cycle mode)
PWC timer (H pulse = rising to falling)
PWC timer (L pulse = falling to rising)
PWC timer (cycle = rising to rising)
PWC timer (cycle = falling to falling)
PWC timer (H pulse = rising to falling and cycle = rising to rising)
Input capture (rising, free-running counter)
Input capture (falling, free-running counter)
Input capture (both edges, free-runnig counter)
Input capture (rising, counter clear)
Input capture (falling, counter clear)
Input capture (both edges, counter clear)
1/27 × Fch
1/32 × MCLK (machine clock)
1/16 × MCLK (machine clock)
1/8 × MCLK (machine clock)
1/4 × MCLK (machine clock)
1/2 × MCLK (machine clock)
1 × MCLK (machine clock)
: Read and write enabled
: Read only
: Initial value
404
Table 12.5-1 Function of Each Bit in Control Status Register 0 (T00CR0/T01CR0)
Bit name Functions
bit7IFE:IF flag interrupt enable
Enables or disables the IF flag interrupt.
• An IF flag interrupt request is output when both of this bit and the IE bit (T00CR1/T01CR1:IE)contain "1" with the IF flag (T00CR1/T01CR1:IF) set to "1".
• Setting this bit to "0" disables IF flag interrupts.
bit6bit5bit4
C2, C1, C0:Count Clockselection bits
Selects the count clock.• The count clock signal is generated by the prescaler. Refer to Chapter 11 "Prescaler". • Write access to these bits is nullified during timer operation (T00CR1/T01CR1:STA = "1").• T01CR0 (timer 01) clock selection is nullified during 16-bit operation. • These bits cannot be set to "111B" when the PWC or input capture function is used. An attempt to
write "111B" with the PWC or input capture function in use resets the bits to "000B". The bits are alsoreset to "000B" if the timer enters the input capture operation mode with the bits set to "111B".
Bit3Bit2Bit1Bit0
F3, F2, F1, F0:Timer operation mode select bits
Selects a timer operation mode.• The PWM timer function (variable-period mode: F3,F2,F1,F0 = "0100B") is set by either the
T00CR0 (timer 00) register or T01CR0 (timer 01) register. In this case, the other register is set toF3,F2,F1,F0 = "0100B" automatically when the timer starts operation (T00CR1/T01CR1:STA = "1").
• The MOD bit is set to "0" automatically when the timer set for 16-bit operation (TMCR0:MOD ="1") starts operation (T00CR1/T01CR1:STA = 1) in the PWM timer function (variable-period mode).
• Write access to these bits is nullified during timer operation (T00CR1/T01CR1:STA = "1").
C2 C1 C0 Count clock selection bit
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 External clock
1/27 × Fch
1/32 × MCLK (machine clock)
1/16 × MCLK (machine clock)
1/8 × MCLK (machine clock)
1/4 × MCLK (machine clock)
1/2 × MCLK (machine clock)
1 × MCLK (machine clock)
F2 F1 F0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
F3
0
0
0
0
0
0
0
0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
1
1
1
1
1
1
1
Timer operation mode selection bit
Interval timer (one-shot mode)
Interval timer (continuous mode)
Interval timer (free-running mode)
PWM timer (fixed-cycle mode)
PWM timer (variable cycle mode)
PWC timer (H pulse = rising to falling)
PWC timer (L pulse = falling to rising)
PWC timer (cycle = rising to rising)
PWC timer (cycle = falling to falling)
PWC timer (H pulse = rising to falling and cycle = rising to rising)
Input capture (rising, free-running counter)
Input capture (falling, free-running counter)
Input capture (both edges, free-runnig counter)
Input capture (rising, counter clear)
Input capture (falling, counter clear)
Input capture (both edges, counter clear)
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CHAPTER 12 8/16-bit Composite Timer
12.5.2 Control Status Register 1 (T00CR1/T01CR1)
Control status register 1 (T00CR1/T01CR1) controls the interrupt flag, timer output, and timer operations. The T00CR1 and T01CR1 registers correspond to timers 00 and 01, respectively.
Control Status Register1 (T00CR1/T01CR1)
Figure 12.5-3 Control Status Register 1 (T00CR1/T01CR1)
IR Pulse width measuring complete and edge detection flag
0 Measuring complete and no edge detection
1 Measuring complete and edge detection
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
STA HO IE IR BF IF SO OE 00000000B
R/W R/W R/W R(RM1),W R/WX R(RM1),W R/W R/W
IE Interrupt enable bit
0 Interrupt disabled
1 Interrupt enabled
HO Timer temporary stop bit
0 Timer operation enabled
1 Timer temporary stop
STA Timer operation enable bit
0 Timer stop
1 Timer operation
Read Write
Flag clear
No effect to operation
R/WR(RM1),W
R/WX
OE Timer output enable bit
0 Timer output disabled
1 Timer output enabled
SO Timer output initial value bit
0 Timer initial value "0"
1 Timer initial value "1"
IF Timer reload and overflow flag
0 No reload and overflow
1 Reload and overflow
Read Write
Flag clear
No effect to operation
BF Data register full flag
0 Measuring data is not in data register.
1 Measuring data is in data register.
: Read and write enabled: Read enabled (RMW read "1") and write enabled (including the case reading value is different from writing value): Read enabled and write disabled: Initial value
406
Table 12.5-2 Function of Each Bit in Control Status Register 1 (T00CR1/T01CR1)
Bit name Functions
bit7STA:Timer operation enable bit
This bit enables or disables timer operation.• Writing "1" to the bit causes the timer to start operation at a count value of "00H". • Be sure to set the count clock selection bit (T00CR0/T01CR0:C2, C1, C0), timer operation mode
select bit (T00CR0/T01CR0:F3, F2, F1, F0), timer output initial value bit (T00CR1/T01CR1:S0),16-bit mode enable bit (TMCR0:MD), and filter function select bit (TMCR0:FE11, FE10, FE01,FE00) before this bit is set to "1".
• Writing "0" to the bit causes the timer to stop operation and resets the count value to "00H". • When the PWM timer function (variable-period mode) has been selected (T00CR0/
T01CR0:F3,F2,F1,F0 = "0100B"), the STA bit can be used to enable or disable timer operationfrom within either the T00CR1 (timer 00) or T01CR1 (timer 01) register. In this case, the STA bit inthe other register is set to the same value automatically.
• During 16-bit operation (TMCR0:MD = 1), use the STA bit in the T00CR1 (timer 00) register toenable or disable timer operation. In this case, the STA bit in the other register is set to the samevalue automatically.
bit6HO:Timer suspend bit
This bit suspends or resumes timer operation.• Writing "1" to the bit during timer operation suspends the operation. • Writing "0" to the bit when timer operation has been enabled (T00CR1/T01CR1:STA = 1) resumes
the timer operation. • When the PWM timer function (variable-period mode) has been selected (T00CR0/
T01CR0:F3,F2,F1,F0 = "0100B"), the HO bit can be used to suspend or resume timer operationfrom within either the T00CR1 (timer 00) or T01CR1 (timer 01) register. In this case, the HO bit inthe other register is set to the same value automatically.
• During 16-bit operation (TMCR0:MD = 1), use the HO bit in the T00CR1 (timer 00) register tosuspend or resume timer operation. In this case, the STA bit in the other register is set to the samevalue automatically.
bit5IE:Interrupt request enable bit
This bit enables or disables interrupt request output. • Writing "1" to the bit outputs an interrupt request when the pulse width measurement completion/
edge detection flag (T00CR1/T01CR1:IR) or timer reload/overflow flag (T00CR1/T01CR1:IF) is"1". Note, however, that an interrupt request from the timer reload/overflow flag (T00CR1/T01CR1:IF) is not outputted unless the IF flag interrupt enable (T00CR0/T01CR0:IFE) bit is set to"1" as well.
bit4
IR:Pulse width measurement completion/edge detection flag
This bit detects the completion of pulse width measurement or an edge.• The bit is set to "1" upon completion of pulse width measurement when the PWC timer function has
been selected. • The bit is set to "1" upon detection of an edge when the input capture function has been selected. • The bit is "0" when any timer function other than the PWC timer and input capture functions has
been selected. • This bit always returns "1" to a read modify write instruction. • The IR bit in T01CR1 (timer 01) register is set to "0" during 16-bit operation. • Writing "0" to the bit sets it to "0". • An attempt to write "1" to the bit is ignored.
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CHAPTER 12 8/16-bit Composite Timer
bit3BF:Data register full flag
• This bit is set to "1" when a count value is stored in the data register (T00DR/T01DR) uponcompletion of pulse width measurement in PWC timer function.
• This bit is set to "0" when the data register (T00DR/T01DR) is read during 8-bit operation. • The data register holds data with this bit containing "1". Even when the next edge is detected with
this bit containing "1", the count value is not transferred to the data register and thus the nextmeasurement result is lost. However, as the exception, when the H-pulse and cycle measurement (T00CR0/T01CR0:F3, F2, F1,F0="1001B") is selected, the H-pulse measurement result is transferred to the data register with thisbit set to "1". The cycle measurement result is not transferred to the data register with the bit set to"1". For period measurement, therefore, the H-pulse measurement result must be read before theperiod is completed. Note also that the result of H-pulse measurement or period measurement is lostunless read before the completion of the next H pulse.
• The BF bit in the T00CR1 (timer 00) register is set to "0" when the T01DR (timer 01) register isread during 16-bit operation.
• The BF bit in T01CR1 (timer 01) register is set to "0" during 16-bit operation. • This bit is "0" when any timer function other than the PWC timer function has been selected. • An attempt to write to this bit is always ignored.
Bit2IF:Timer reload/overflow flag
This bit detects a match with a count value or a counter overflow. • The bit is set to "1" when the data register (T00DR/T01DR) value matches the count value during
interval timer function (both one-shot and continuous mode) or PWM timer function (variable-period mode).
• The bit is set to "1" when a counter overflow occurs during PWC or input capture function. • This bit always returns "1" to a read modify write instruction. • Writing "0" to the bit sets it to "0". • An attempt to write "1" to the bit is ignored.• The bit is "0" when the PWM function (variable-period mode) has been selected. • The IF bit in the T01CR1 (timer 01) register is "0" during 16-bit operation.
Bit1SO:Timer output initial value bit
Writing to this bit sets the timer output (TMCR0:TO1/TO0) initial value. The value in this bit isreflected in the timer output when the timer operation enable bit (T00CR1/T01CR1:STA) changesfrom "0" to "1". • During 16-bit operation (TMCR0:MOD = 1), use the SO bit in the T00CR1 (timer 00) register to set
the timer output initial value. In this case, the value of the SO bit in the other register is meaningless. • An attempt to write to this bit is nullified during timer operation (T00CR1/T01CR1:STA = 1).
During 16-bit operation, however, a value can be written to the SO bit in the T01CR1 (timer 01)register even during timer operation but it has no direct effect on the timer output.
• The value of this bit is meaningless when the PWM timer function (either fixed-period or variable-period mode) or input capture function has been selected.
Bit0OE:Timer output enable bit
This bit enables or disables timer output. • Writing "1" to the bit supplies timer output (TMCR0:T01/TO0) to the external pin. • Writing "0" to the bit prevents the timer output from being supplied to the external pin. In this case,
the external pin serves as a general-purpose port.
Table 12.5-2 Function of Each Bit in Control Status Register 1 (T00CR1/T01CR1)
Bit name Functions
408
12.5.3 Timer Mode Control Register (TMCR0)
The timer mode control register (TMCR0) selects the noise filter function, 8-bit or 16-bit operation mode, and signal input to timer 00 and to indicate the timer output value. This register serves for both of timers 00 and 01.
Timer Mode Control Register (TMCR0)
Figure 12.5-4 Timer Mode Control Register (TMCR0)
MOD 16-bit mode enable bit
0 8-bit operation
1 16-bit operation
TO0 Timer 00 timer output bit
0Timer 00 output value
1
TO1
0Timer 01 output value
1
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
TO1 TO0 IIS MOD FE11 FE10 FE01 FE00 00000000B
R/WX R/WX R/W R/W R/W R/W R/W R/W
R/WR(RM1),W
R/WX
FE01 FE00 Timer 00 filter function selection bit
0 0 No filtering
0 1
1 0
1 1
Removal of H pulse noise
Removal of L pulse noise
Removal H/L pulse noise
FE11 FE10 Timer 01 filter function selection bit
0 0 No filtering
0 1
1 0
1 1
Removal of H pulse noise
Removal of L pulse noise
Removal of H/L pulse noise
IIS Timer 00 internal signal selection bit
0 Select the external signal (EC00) as timer 00 input
1 Select the internal signal (TII0) as timer 00 input
Timer 01 timer output bit
: Read and write enabled: Read enabled (RMW read "1") and write enabled (including the case reading value is different from writing value): Read enabled and write disabled: Initial value
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CHAPTER 12 8/16-bit Composite Timer
Table 12.5-3 Function of Each Bit in Timer Mode Control Register (TMCR0)
Bit name Functions
bit7TO1:Timer 01 output bit
This bit indicates the output value of timer 00. When the timer starts operation (T00CR1/T01CR1:STA = 1), the value in the bit changes depending on the selected timer function. • Writing to this bit has no effect on the operation. • The value in the bit remains indeterminate during 16-bit operation when the PWM timer
function (variable-period mode) or input capture function has been selected. • When the timer stops operation (T00CR1/T01CR1:STA = 0)in interval timer or PWC timer
function, this bit holds the last value. • When the timer stops operation in PWM timer function (fixed-period mode), this bit is set to
"0". • When the timer operation mode select bit (T00CR0/T01CR0:F3,F2,F1,F0) is changed with the
timer being stopped, the bit indicates the last value of timer operation if the same timer operationhas ever been performed or otherwise contains "0".
bit6TO0:Timer 00 output bit
This bit indicates the output value of timer 01. When the timer starts operation (T00CR1/T01CR1:STA = 1), the value in the bit changes depending on the selected timer function. • Writing to this bit has no effect on the operation. • The value in the bit remains indeterminate when the input capture function has been selected. • When the timer stops operation (T00CR1/T01CR1:STA = 0) in interval timer, PWM timer
(variable-period mode), or PWC timer function, this bit holds the last value. • When the timer stops operation in PWM timer function (fixed-period mode), this bit is set to
"0". • When the timer operation mode select bit (T00CR0/T01CR0:F3,F2,F1,F0) is changed with the
timer being stopped, the bit indicates the last value of timer operation if the same timer operationhas ever been performed or otherwise contains "0".
bit5IIS:Timer 00 internal signal select bit
This bit selects the signal input to timer 00 when the PWC timer or input capture function hasbeen selected. • Writing "1" to the bit selects the internal signal (TII0) as the signal input for timer 00. • Writing "0" to the bit selects the external signal (EC00) as the signal input for timer 00.
bit4MOD:16-bit mode enable bit
This bit selects 8-bit or 16-bit operation mode. • Writing "1" to the bit causes timers 00 and 01 to operate as 16-bit timers. • Writing "0" to the bit causes timers 00 and 01 to operate as 8-bit timers. • This bit is set to "0" automatically when the timer starts operation (T00CR1/T01CR1:STA = 1)
in PWM timer mode (variable-period mode). • Write access to this bit is nullified during timer operation (T00CR1:STA = 1 or T01CR1:STA =
1).
bit3bit2
FE11,FE10:Timer 01 filter function select bits
These bits select the filter function for the external signal (EC01) to timer 01 when the PWCtimer or input capture function has been selected.
• An attempt to write to these bits is nullified during timer operation (T01CR1:STA = 1). • The settings of these bits have no effect on operation when the interval timer or PWM timer
function has been selected.
FE11 FE10 Timer 01 filter function selection bit
0 0 No filtering
0 1
1 0
1 1
Removal of H pulse noise
Removal of L pulse noise
Removal of H/L noise
410
bit1bit0
FE01,FE00:Timer 00 filter function select bits
These bits select the filter function for the external signal (EC00) to timer 00 when the PWCtimer or input capture function has been selected.
• An attempt to write to these bits is nullified during timer operation (T00CR1/STA = 1). • The settings of these bits have no effect on operation when the interval timer or PWM timer
function has been selected.
Table 12.5-3 Function of Each Bit in Timer Mode Control Register (TMCR0)
Bit name Functions
FE01 FE00 Timer 00 filter function selection bit
0 0 No filter
0 1
1 0
1 1
Removal H pulse noise
Removal L pulse noise
Removal H/L pulse noise
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CHAPTER 12 8/16-bit Composite Timer
12.5.4 Data Register (T00DR/T01DR)
The data register (T00DR/T01DR) is used to write the maximum value counted during interval timer or PWM timer operation and to read the count value during PWC timer or input capture operation. The T00DR and T01DR registers correspond to timers 00 and 01, respectively.
Data Register (T00DR/T01DR)
Figure 12.5-5 Data Register (T00DR/T01DR)
Interval timer function
The data register (T00DR/T01DR) is used to set the interval time. When the timer starts operation(T00CR1/T01CR1:STA=1), the value of this register is transferred to the latch in the 8-bit comparator andthe counter starts counting. When the count value matches the value held in the latch in the 8-bitcomparator, the value of this register is transferred again to the latch, the count value is reset to "00H" tocontinue to count.
The current count value can be read from this register.
PWM timer functions (fixed-cycle)
The data register (T00DR/T01DR) is used to set "H" pulse width time. When the timer starts operation(T00CR1/T01CR1:STA = 1), the value of this register is transferred to the latch in the 8-bit comparator andthe counter starts counting from timer output "H". When the count value matches the value held in thelatch, the timer output becomes "L" and the count value continues to count until it reaches "FFH". When anoverflow occurs, the value of this register is transferred again to the latch in the 8-bit comparator and thecounter performs the next cycle of counting.
The current count value is read from this register.
PWM timer functions (variable-cycle)
The timer 00 data register (T00DR) and timer 01 data register (T01DR) are used to set "L" pulse width timeand period, respectively. When the timer starts operation (T00CR1/T01CR1:STA = 1), the value of eachregister is transferred to the latch in the 8-bit comparator and two counters starts counting from timer output"L". When the T00DR value held in the latch matches the timer 00 counter value, the timer output becomes"H" and counting continues until the T01DR value held in the latch matches the timer 01 counter value.When the T01DR value held in the latch of the 8-bit comparator matches the timer 01 counter value, thevalues of these registers are transferred again to the latch and the next PWM cycle of counting is performedcontinuously.
The current count value is read from this register.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 00000000B
R,W R,W R,W R,W R,W R,W R,W R,W
R,W : Read and write enabled (including the case writing function is different from reading function)
412
PWC timer function
The data register (T00DR/T01DR) is used to read PWC measurement results. When PWC measurement iscompleted, the BF bit is set to "1" and the counter value is transferred to this register.
When the data register is read, the BF bit is set to "0". Transfer to the data register is not performed with theBF bit containing "1".
As the exception, when the H-pulse and cycle measurement (T00CR0/T01CR0:F3, F2, F1, F0="1001B") is
selected, the H-pulse measurement result is transferred to the data register with the BF bit set to "1", but the
cycle measurement result is not transferred to the data register with the BF bit set to "1". For period
measurement, therefore, the H-pulse measurement result must be read before the period is completed. Note
also that the result of H-pulse measurement or period measurement is lost unless read before the
completion of the next H pulse.
When reading the data register, be careful not to clear the BF bit unintentionally.
Writing a value to the data register updates the measurement data stored there with that value. Therefore,do not write to the data register.
Input capture function
The data register (T00DR/T01DR) is used to read input capture results. When a specified edge is detected,the counter value is transferred to the data register.
Writing a value to the data register updates the measurement data stored there with that value. Therefore,do not write to the data register.
Note:
Pay attention to the following notes when reading or writing the T00DR and T01DR registers during16-bit operation:
• Read from T01DR: Read access from the register involves writing the T00DR value to theinternal read buffer.
• Read from T00DR: Read from the internal read buffer.
• Write to T01DR: Write to the internal write buffer.
• Write to T00DR: Write access to the register involves writing the value of the internal writebuffer to the T01DR register.
The following diagram illustrates how T00DR and T01DR registers are read from and written toduring 16-bit operation.
Reading buffer
T01DR write
T00DR write
T01DR read
T00DR read
Write data
Write buffer
T00DR register
T01DR register
Read data
413
CHAPTER 12 8/16-bit Composite Timer
12.6 Operating Explanation of Interval Timer Function (One-shot Mode)
This section describes the operations of the interval timer function (one-shot mode) for the 8/16-bit composite timer.
Operation of Interval Timer Function (One-shot Mode)The composite timer requires the register settings shown in Figure 12.6-1 to serve as the interval timerfunction.
Figure 12.6-1 Settings of Interval Timer Function
In interval timer function (one-shot mode), enabling timer operation (T00CR0/T00CR1:STA = 1) causesthe counter to start counting from "00H" at the rising edge of a selected count clock signal. When thecounter value matches the value of the data register (T00DR/T01DR), the timer output (TMCR0:T00/T01)is inverted, the interrupt flag (T00CR1/T01CR1:IF) is set to "1" and the start bit (T00CR0/T00CR1:STA)to "0", then the count operation stops.
The value of the data register (T00DR/T01DR) is transferred to the temporary storage latch (comparisondata storage latch) in the comparator when the counter starts counting.
Figure 12.6-2 shows the operation of the interval timer function in 8-bit mode.
Figure 12.6-2 Operation of Interval Timer Function in 8-bit Mode (Timer 0)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
T00/01CR0 IFE C2 C1 C0 F3 F2 F1 F0
0 0 0 0
T00/01CR1 STA HO IE IR BF IF SO OE
1
TMCR TO1 TO0 IIS MOD FE11 FE10 FE01 FE00
T00/01DR Sets interval time (counter compare value)
: Used bit
: Unused bit
1: Set "1"
0: Set "0"
Counter value FF H
80 H
00 H
Timer cycle
Cleared by the program
Time
IF bit
STA bit
T00/01DR value (FF H )
TO bit
Automatically clear Reactivate
Invert Reactivates with the output initial value unchanged (“0”)
For an initial value of “1” on activation
*: If the T00/01DR data register value is modified during operation, the new value is used from the next activate cycle.
Automatically clear Reactivate
T00/01DR value modified (FFH 80 H) *
414
12.7 Operating Explanation of Interval Timer Function (Continuous Mode)
This section describes the operation for the interval timer function (continuous mode) of the 8/16-bit composite timer.
Operation of Interval Timer Function (Continuous Mode)The composite timer requires the register settings shown in Figure 12.7-1 to serve as the interval timerfunction (continuous mode).
Figure 12.7-1 Counter Function (8-bit Mode) Settings
In interval timer function (continuous mode), enabling timer operation (T00CR0/T00CR1:STA = 1) causesthe counter to start counting from "00H" at the rising edge of a selected count clock signal. When thecounter value matches the value in the data register (T00DR/T01DR), the timer output bit (TMCR0:TO0/TO1) is inverted, the interrupt flag (T00CR1/T01CR1:IF) is set to "1", and the counter continues to countby restarting at "00H". The timer outputs a square waveform through this continuous operation.
The value of the data register (T00DR/T01DR) is transferred to the temporary storage latch (comparisondata storage latch) in the comparator either when the counter starts counting or when a counter valuecomparison match is detected.
When the timer stops operation, the timer output bit holds the last value.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
T00/01CR0 IFE C2 C1 C0 F3 F2 F1 F0
0 0 0 1
T00/01CR1 STA HO IE IR BF IF SO OE
1
TMCR TO1 TO0 IIS MOD FE11 FE10 FE01 FE00
T00/01DR Sets interval time (counter compare value)
: Used bit
: Unused bit
1: Set "1"
0: Set "0"
415
CHAPTER 12 8/16-bit Composite Timer
Figure 12.7-2 Operating Diagram of Interval Timer Function (Continuous Mode)
Counter valueCompare value
Compare value (80 H )
FF H
80 H
00 H
T00/01DR value (E0 H )T00/01DR value modified (FFH 80 H)*
Cleared by the program
Time
IF bit
STA bit
Counter clear *2
Timer output pin
*1: If theT00/01DR reload register value is modified during operation, the new value is used from the next cycle.
E0 H
(FF H )Compare value
(E0 H )
Activitate Match Match Match Match Match
*2: At activation, and each time a match is detected, the counter is cleared and the data register setting is loaded into thecomparison data latch.
416
12.8 Operating Explanation of Interval Timer Function (Free-running Mode)
This section describes the operations of the interval timer function (free-running mode) for the 8/16-bit composite timer.
Operation of Interval Timer Function (Free-running Mode)The composite timer requires the settings shown in Figure 12.8-1 to serve as the interval timer function
(free-running mode).
Figure 12.8-1 Setting of Interval Timer Function (Free-running Mode)
In interval timer function (free-running mode), enabling timer operation (T00CR0/T00CR1:STA = 1)
causes the counter to start counting from "00H" at the rising edge of a selected count clock signal. When the
counter value matches the value in the data register (T00DR/T01DR), the timer output bit (TMCR0:TO0/
TO1) is inverted and the interrupt flag (T00CR1/T01CR1:IF) is set to "1". The counter continues to count,
and when the count value reaches "FFH", restarts counting at "00H" to continue. The timer outputs a square
waveform through this continuous operation.
The value of the data register (T00DR/T01DR) is transferred to the temporary storage latch (comparison
data storage latch) in the comparator either when the counter starts counting or when a counter value
comparison match is detected.
When the timer stops operation, the timer output bit holds the last value.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
T00/01CR0 IFE C2 C1 C0 F3 F2 F1 F0
0 0 1 0
T00/01CR1 STA HO IE IR BF IF SO OE
1
TMCR TO1 TO0 IIS MOD FE11 FE10 FE01 FE00
T00/01DR Sets interval time (counter compare value)
: Used bit
: Unused bit
1: Set "1"
0: Set "0"
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CHAPTER 12 8/16-bit Composite Timer
Figure 12.8-2 Operating Diagram of Interval Timer Function (Free-running Mode)
Counter value
FF H
80 H
00 H
T00/01DR value (E0 H )T00/01DR value modified but not updated to comparison latch
Cleared by the program
Time
IF bit
STA bit
Counter value match *2
Timer output pin
*1: If theT00/01DR reload register value is modified during operation, the new value is used from the next T00/01CR1:STA=”0” -> “1“cycle.
E0 H
(E0 H )
Activitate Match Match Match
*2: At activation, and each time a match is detected, the counter is not cleared and the data register setting is not reloaded into the comparison data latch.
Match
418
12.9 Operating Explanation of PWM Timer Function (Fixed-period Mode)
This section describes the operations of the PWM timer function (fixed-period mode) for the 8/16-bit composite timer.
Operationg of PWM Timer Functions (Fixed-period Mode)The composite timer requires the settings shown in Figure 12.9-1 to serve as the PWM timer function (in
fixed-period mode).
Figure 12.9-1 Setting of PWM Timer Functions (Fixed-period Mode)
In PWM timer function (fixed-period mode), the timer output (TMCR0:TO0/TO1) generates a PWM signal
variable in "H" pulse width at fixed intervals. The period is fixed to "FFH" during 8-bit operation or
"FFFFH" during 16-bit operation. The time is determined by the count clock selected. The "H" pulse width
is determined by the value in the data register (T00DR/T01DR).
This function has no effect on the interrupt flag (T00CR1/T01CR1:IF). As each cycle always begins with
"H" pulse output, the timer initial value setting bit (T00CR1/T01CR1:SO) is meaningless.
The value of the data register (T00DR/T01DR) is transferred to the temporary storage latch (comparison
data storage latch) in the comparator either when the counter starts counting or when a counter value
comparison match is detected.
The timer output bit is set to "0" when the timer stops operation.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
T00/01CR0 IFE C2 C1 C0 F3 F2 F1 F0
0 0 1 1
T00/01CR1 STA HO IE IR BF IF SO OE
1
TMCR TO1 TO0 IIS MOD FE11 FE10 FE01 FE00
T00/01DR Sets "H" width of pulse (compare value)
: Used bit
: Unused bit
1: Set "1"
0: Set "0"
419
CHAPTER 12 8/16-bit Composite Timer
Figure 12.9-2 Operating Diagram of PWM Timer Functions (Fixed-period Mode)
Fo r T 00 / 0 1 DR re g is te r v alu e o f “0 0 H” (d u t y ra t io = 0 % )
Co u n te r v a lu e
H
L
H
L
H
L
00 H
Co u n te r v a lu e
Co u nt e r va lu e
PW M w a ve fo rm
PW M w a ve fo rm
P W M wa ve f o rm
Fo r T 00 / 0 1 DR re g is te r v alu e o f “8 0 H” (d u t y ra t io = 5 0 % )
F o r T0 0 /0 1 DR re g ist er va lu e o f “FFH ” (d u ty ra tio = 9 9 .6 % )
FFH 0 0H
F FH0 0 H
8 0 H
o ne co u n t w id th
N o te : W h e n P W M fu n ct ion is se le cte d , th e tim e r o u t pu t p in m a in t ain s its e xis tin g le ve l wh e n th e
co u n te r is st o p pe d (T0 0 /0 1 CR0 : S TA =”0 ”).
F FH0 0 H
0 0 H
00 H
420
12.10 Operating Explanation of PWM Timer Function (Variable-period Mode)
This section describes the operations of the PWM timer function (variable-period mode) for the 8/16-bit composite timer.
Operating of PWM Timer Functions (Variable-period Mode)The composite timer requires the settings shown in Figure 12.10-1 to serve as the PWM timer function (in
variable-period mode).
Figure 12.10-1 Setting of PWM Timer Functions (Variable-period Mode)
In PWM timer function (variable-period mode), both of timer 00 and 01 are used when the period is
specified by the timer 01 data register (T01DR), and the "L" pulse width is specified by the timer 00 data
register (T00DR), any period and duty PWM signal is generated from the timer output bit (TMCR0:T00).
For this function, the composite timer cannot serve as a 16-bit counter.
Enabling timer operation (by setting either T00CR0:STA = 1 or T01CR0:STA = 1) sets the mode bit
(TMCR0:MOD) to "0".
As the first cycle always begins with "L" pulse output, the timer initial value setting bit (T00CR1/
T01CR1:SO) is meaningless.
The interrupt flag (T00CR1/T01CR1:IF) is set when each 8-bit counter matches the value in the
corresponding data register (T00DR/T01DR).
The data register value is transferred to the temporary storage latch (comparison data storage latch) in the
comparator either when the counter starts counting or when a comparison match with each counter value is
detected.
"H" is not outputted when the "L" pulse width setting is greater than the period setting.
The count clock must be selected for both of timers 00 and 01. Different count clocks can be selected at this
time.
When the timer stops operation, the timer output bit holds the last value.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
T00/01CR0 IFE C2 C1 C0 F3 F2 F1 F0
0 1 0 0
T00/01CR1 STA HO IE IR BF IF SO OE
1
TMCR TO1 TO0 IIS MOD FE11 FE10 FE01 FE00
T00DR Sets "L" width of pulse (compare value)
T01DR Sets the cycle of a PWM wave (compare value)
: Used bit
: Unused bit
1: Set "1"
0: Set "0"
421
CHAPTER 12 8/16-bit Composite Timer
Figure 12.10-2 Operating Diagram of PWM Timer Functions (Variable-period Mode)
Counter timer00 value
H
L
H
L
H
L
00H
PWM waveform
PWM waveform
PWM waveform
For T00DR register value of “80H”, and T01DR register value of “80H” (duty ratio = 0%)
FFH00H
*: The minimal length of the “L” width can be reduced by setting timer00 count clock faster than timer01 count.
80H00H00H 80H00H80H00H00H 80H00HCounter timer01 value
Counter timer00 valueCounter timer01 value
00H00H 00H80H00H00H 80H00H
40H 40H
Counter timer00 valueCounter timer01 value
00H 00H
one count width *
(timer00 value >= timer01 timer value)
For T00DR register value of “40H”, and T01DR register value of “80H” (duty ratio = 50%)
For T00DR register value of “00H”, and T01DR register value of “FFH” (duty ratio = 99.6%)
422
12.11 Operating Explanation of PWC Timer Function
This section describes the operations of the PWC timer function for the 8/16-bit composite timer.
Operation of PWC Timer FunctionsThe composite timer requires the settings shown in Figure 12.11-1 to serve as the PWC timer function.
Figure 12.11-1 Settings for PWC Timer Function
When the PWC timer function is selected, the width and period of an external input pulse can be measured.
The edges to start and end counting are selected by timer operation mode setting (T00CR0/
T01CR0:F3,F2,F1,F0).
In this operation mode, the counter starts counting from "00H" upon detection of the specified count start
edge of an external input signal. Upon detection of the specified count end edge, the count value is
transferred to the data register (T00DR/T01DR) and the interrupt flag (T00CR1/T01CR1:IR) and buffer
full flag (T00CR1/T01CR1:BF) are set to "1". The buffer full flag is set to "0" when the data register
(T00DR/T01DR) is read from.
The data register holds data with the buffer full flag set to "1". Even when the next edge is detected at this
time, the next measurement result is lost as the count value is not transferred to the data register.
As the exception, when the H-pulse and cycle measurement (T00CR0/T01CR0:F3, F2, F1, F0="1001B") is
selected, the H-pulse measurement result is transferred to the data register with the BF bit set to "1", but the
cycle measurement result is not transferred to the data register with the BF bit set to "1". For period
measurement, therefore, the H-pulse measurement result must be read before the period is completed. Note
also that the result of H-pulse measurement or period measurement is lost unless read before the
completion of the next H pulse.
To measure the time exceeding the length of the counter, you can use software to count the number of
occurrences of a counter overflow. When the counter causes an overflow, the interrupt flag (T00CR1/
T01CR1:IF) is set to "1". The interrupt service routine can therefore be used to count the number of times
the overflow occurs.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
T00/01CR0 IFE C2 C1 C0 F3 F2 F1 F0
T00/01CR1 STA HO IE IR BF IF SO OE
1
TMCR TO1 TO0 IIS MOD FE11 FE10 FE01 FE00
T00/01DR Holds the pulse width measurement value
: Used bit
: Unused bit
1: Set "1"
0: Set "0"
423
CHAPTER 12 8/16-bit Composite Timer
Note also that an overflow toggles the timer output (TMCR0:TO1/TO0). The timer output initial value can
be set by the timer output initial value bit (T00CR1/T01CR1:SO).
When the timer stops operation, the timer output bit holds the last value.
Figure 12.11-2 PWC Timer Function Operation Diagram (Example of H-pulse Width Measurement)
Input pulse (input waveform to the PWC pin)
Counter value FFH
STA bit
IR bit
BF bit
“H” width
Counter operation
Time
Cleared by the program
Data transferred from counter to T00/01DR T00/01DR data register read
424
12.12 Operating Explanation of Input Capture Functions
This section describes the operations of the input capture function for the 8/16-bit composite timer.
Input Capture Function OperationThe composite timer requires the settings shown in Figure 12.12-1 to serve as the input capture timer.
Figure 12.12-1 Setting of Input Capture Function
When the input capture function is selected, the counter value is stored to the data register (T00DR/T01DR)
upon detection of an edge of the external signal input. The edge to be detected is selected by timer
operation mode setting (T00CR0/T01CR0:F3,F2,F1,F0).
This function is available in either free-running mode or clear mode, which can be selected by timer
operation mode setting.
In clear mode, the counter starts counting from "00H ". When the edge is detected, the counter value is
transferred to the data register (T00DR/T01DR), the interrupt flag (T00CR1/T01CR1:IR) is set to "1", and
the counter continues to count by restarting at "00H".
When the edge is detected in free-running mode, the counter value is transferred to the data register
(T00DR/T01DR) and the interrupt flag (T00CR1/T01CR1:IR) is set to "1". In this case, the counter
continues to count without being cleared.
This function has no effect on the buffer full flag (T00CR1/T01CR1:BF).
To measure the time exceeding the length of the counter, you can use software to count the number of
occurrences of a counter overflow. When the counter causes an overflow, the interrupt flag (T00CR1/
T01CR1:IF) is set to "1". The interrupt service routine can therefore be used to count the number of times
the overflow occurs.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
T00/01CR0 IFE C2 C1 C0 F3 F2 F1 F0
T00/01CR1 STA HO IE IR BF IF SO OE
1
TMCR TO1 TO0 IIS MOD FE11 FE10 FE01 FE00
T00/01DR Holds the pulse width measurement value
: Used bit
: Unused bit
1: Set "1"
0: Set "0"
425
CHAPTER 12 8/16-bit Composite Timer
Figure 12.12-2 Operating Diagram of Input Capture Function
FFH
BFH
7FH9FH
3FH
3FH 9FH
counter free-run modecounter clear mode
BFH 7FHCapture value inT00/01DR
capture falling edge capture falling edge capture rising edgecapture rising edge
External input
426
12.13 Explanation of Noise Filter Operation
This section describes the operations of the noise filter of the 8/16-bit composite timer.
When the input capture or PWC timer function has been selected, a noise filter can be used to eliminate
pulse noise from the signal from the external input pin (EC00/EC01). H-pulse noise, L-pulse noise, or H/L-
pulse noise elimination can be selected depending on the register setting (TMCR0:F11,F10,F01,F00). The
maximum pulse width from which to eliminate noise is three machine clock cycles. When the filter
function is active, the signal input is subject to a delay of four machine clock cycles.
Figure 12.13-1 Noise Filter Operation
Filter sample clock
External input signal
FilteredH noise
Output
FilteredL noise
Output
FilteredH/L noise
Output
427
CHAPTER 12 8/16-bit Composite Timer
12.14 States in Each Mode During Operation
This section describes how the 8/16-bit composite timer behaves when the microcontroller enters watch mode or stop mode or when a suspend (T00CR1/T01CR1:HO = "1") request is issued during operation.
When The Interval Timer, Input Capture, or Pwc Function Has Been SelectedFigure 12.14-1 shows how the counter value changes when transition to watch mode or stop mode or a
suspend request occurs during operation of the 8/16-bit composite timer.
The counter stops operation while holding the value when transition to stop mode or watch mode occurs.
When the stop mode or watch mode is canceled by an interrupt, the counter resumes operation with the last
value held. So the first interval time and external clock count are incorrect. After releasing from stop mode
or watch mode, be sure to initialize the 8/16-bit composite timer.
Also, when suspend the counter (T00CR1/T01CR1:HO = "1"), the counter stops operation with the value
held.
Figure 12.14-1 Operations of Counter in Standby Mode or at Halt (Not Serving as PWM Timer)
Counter valueFF H
80 H
00 H
T00/01DR data register value (FFH)
Timer cycle
Stop request
Oscillation stabilization delay time
Interval time after wake-up from stop mode (indeterminate)
Time
IF bit
Cleared by the program
Operation halts
Operation restarts
Operation halts
STA bit
IE bit
SLP bit (STBC register)
STP bit(STBC register)
Wake-up from stop mode by an external interruptWake-up from sleep mode by interrupt
Stop mode
Sleep mode
HO bit
HO request
HO requestends
Operation resumes
428
Figure 12.14-2 Operations of Counter in Standby Mode or at Halt (Serving as PWM Timer)
Counter valueFF H
00 H
T00/01DR value (FF H )Time
STA bit
PWM Timer output pin
(FF H )
SLP bit (STBC register)
STP bit(STBC register)
Wake-up from stop mode by an external interruptWake-up from sleep mode by interrupt
Sleep mode
*
Oscillation stabilization delay time
maintains the level prior stop
*: The PWM timer output maintains it value prior changing to stop mode.
HO bit
maintains the level prior hold
429
CHAPTER 12 8/16-bit Composite Timer
12.15 Interrupt of 8/16-bit Composite Timer
The 8/16-bit composite timer generates the following types of interrupts, to each of which an interrupt number and interrupt vector are assigned. • Timer 00 interrupt• Timer 01 interruptFor the interrupt numbers and interrupt vector values, see Section "29.2 Interrupt Source Table".
Timer 00 InterruptTable 12.15-1 summarizes the timer 00 interrupt and its cause.
Timer 01 InterruptTable 12.15-2 summarizes the timer 01 interrupt and ist cause.
Table 12.15-1 Timer 00 Interrupt
Interrupt cause Comparison match Overflow Edge detection
Interrupt generating condition
Comparison match in interval timer function or PWM timer function (variable-period mode) has been selected
Overflow in PWC timer function or input capture function
Completion of measurement in PWC timer function or edge detection in input capture function
Interrupt flag T00CR1:IF T00CR1:IF T00CR1:IR
Interrupt enable T00CR1:IE and T00CR0:IFE T00CR1:IE and T00CR0:IFE T00CR1:IE
Table 12.15-2 Timer 01 interrupt
Interrupt cause Comparison match Overflow Edge detection
Interrupt generating condition
Comparison match in interval timer function or PWM timer function (variable-period mode) has been selectedExcluded during 16-bit operation
Overflow in PWC timer function or input capture functionExcluded during 16-bit operation
Completion of measurement in PWC timer function or edge detection in input capture functionExcluded during 16-bit operation
Interrupt flag T01CR1:IF T01CR1:IF T01CR1:IR
Interrupt enable T01CR1:IE and T00CR0:IFE T01CR1:IE and T00CR0:IFE T01CR1:IE
430
12.16 Note on Using 8/16-bit Composite Timer
This section provides notes on using the 8/16-bit composite timer.
Notes on Using 8/16-bit Composite TimerWhen the timer function is changed using the timer operation mode selection bit (T00CR0/
T01CR1:F3,F2,F1,F0), the timer operation has been stopped (T00CR1/T01CR1:STA=0) then the interrupt
flag (T00CR1/T01CR1:IF and IR), interrupt enable bit (T00CR1/T01CR1:IE and T00CR0/T01CR0:IFE),
and buffer full flag (T00CR1/T01CR1:BF) is cleared.
431
CHAPTER 12 8/16-bit Composite Timer
432
CHAPTER 138/16-bit PPG
This chapter describes the functions and operation of the 8/16-bit PPG.
13.1 Overview of 8/16-Bit PPG
13.2 Block Diagram of 8/16-Bit PPG
13.3 Channel of 8/16-Bit PPG
13.4 Register of 8/16-bit PPG
13.5 Interrupt of 8/16-Bit PPG
13.6 Operation of 8/16-BIt PPG
13.7 Precautions for Using 8/16-Bit PPG
13.8 Example Program for 8/16-Bit PPG
433
CHAPTER 13 8/16-bit PPG
13.1 Overview of 8/16-Bit PPG
The 8/16-bit PPG is an 8-bit reload timer module and uses pulse output control based on timer operation to implement a PPG output.The hardware consists of two 8-bit down-counters, period setting registers, duty setting registers, control registers, two external pulse outputs, and two interrupt outputs.
Overview of 8/16-bit PPGThe following summarizes the 8/16-bit PPG functions.
8-bit PPG output independent operation mode
Can operate as 8-bit PPG of two channels (ch0 and ch1).
8-bit prescaler 8-bit PPG output operation mode
The rising and falling edge detection pulses from the ch1 PPG output can be input to the ch0 down-counter
to implement a variable-period 8-bit PPG output.
16-bit PPG output operation mode
The unit can also operate in cascade (ch1 (upper 8 bits + ch0 (lower 8 bits)) as 16-bit PPG output.
PPG output operation
Outputs a pulse waveform with variable period and duty ratio.
Can also be used in conjunction with an external circuit as D/A converter.
Output inverted mode
The PPG output value can be inverted.
434
13.2 Block Diagram of 8/16-Bit PPG
This shows the block diagram of the 8/16-bit PPG.
Block Diagram of 8/16-Bit PPGFigure 13.2-1 shows the block diagram of 8/16-bit PPG.
Figure 13.2-1 Block Diagram of 8/16-Bit PPG
PPG00
CH0 cycle setting register CH0 duty setting register buffer
MCLK PCK0 PCK1 PCK2 PCK3 PCK4 PCK5 PCK6 8-bit
down counter (ch0)
CLK
START
STOP
BORROW
LOA DCOMP
CKS00[2] CKS00[1] CKS00[0]
CH1 cycle setting register
MCLK PCK0 PCK1 PCK2 PCK3 PCK4 PCK5 PCK6
CLK
START
STOP
BORROW
LOA D
CKS01[2] CKS01[1] CKS01[0]
PEN00
PEN01
MD 1[1] MD0[0]
1
0
01
S Q R
REV00
COMP
S Q R
REV01
1
0PPG01
1
0
1
010
PIE 01 PUF 01 POEN01
IRQ01
POEN01
PIE00 PUF00 POEN00
IRQ00
POEN0
01
1
0
001011
1
0
CH0 duty setting register
Edge detection
Using for serect signal for each
CH1 cycle setting register buffer
CH1 duty setting register
CH1 cycle setting register buffer
Edge detection
Edge detection
8-bit down counter (ch1)
435
CHAPTER 13 8/16-bit PPG
13.3 Channel of 8/16-Bit PPG
This describes the 8/16-bit PPG channels.
Channel of 8/16-bit PPGTable 13.3-1 and Table 13.3-2 show the corresponding of channels, pins and registers.
Table 13.3-1 Pin of 8/16-bit PPG
Channel Pin Name Pin Function
0PPG00 PPG0 output ch0 (8-bit PPG (00), 16-bit PPG)
PPG01 PPG0 output ch1 (8-bit PPG (01), 8-bit prescaler)
1PPG10 PPG1 output ch0 (8-bit PPG (10), 16-bit PPG)
PPG11 PPG1 output ch1 (8-bit PPG (11), 8-bit prescaler))
Table 13.3-2 Register of 8/16-bit PPG
Channel Register Name Register correspondence (description used on this manual)
0
PC01 PC1: PPG1 control register ch0
PC00 PC0: PPG0 control register ch0
PPS01 PPS1: PPG1 cycle setting buffer register ch0
PPS00 PPS0: PPG0 cycle setting buffer register ch0
PDS01 PDS1: PPG1 duty setting buffer register ch0
PDS00 PDS0: PPG0 duty setting buffer register ch0
1
PC11 PC1: PPG1 control register ch1
PC10 PC0: PPG0 control register ch1
PPS11 PPS1: PPG1 cycle setting buffer register ch1
PPS10 PPS0: PPG0 cycle setting buffer register ch1
PDS11 PDS1: PPG1 duty setting buffer register ch1
PDS10 PDS0: PPG0 duty setting buffer register ch1
CommonPPGS PPGS: PPG start register
REVC REVC: PPG output inversion register
436
13.4 Register of 8/16-bit PPG
This describes the 8/16-bit PPG registers.
List of registers of 8/16-bit PPGFigure 13.4-1 shows the registers of 8/16-PPG.
Figure 13.4-1 Registers of 8/16-bit PPG
As this series has two 8/16-bit PPG channels, bits 7 to 4 of the PPG start register (PPGS) and PPG output
inversion register (REVC) are unused bit on this model.
- - PIE1 PUF1 POEN1 CKS12 CKS11 CKS10
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PPG ch1 control registerPC1
MD1 MD0 PIE0 PUF0 POEN0 CKS02 CKS01 CKS00
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PPG ch0 control registerPC0
PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PPG ch1 cycle setting buffer registerPPS1
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DH7 DH6 DH5 DH4 DH3 DH2 DH1 DH0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DL7 DL6 DL5 DL4 DL3 DL2 DL1 DL0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PPG ch0 cycle setting buffer registerPPS0
PPG ch1 duty setting buffer registerPDS1
PPG ch0 duty setting buffer registerPDS0
PEN30 PEN30 PEN21 PEN20 PEN11 PEN10 PEN01 PEN00
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PPG start up registerPPGS
REV30 REV30 REV21 REV20 REV11 REV10 REV01 REV00
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PPG output invertion registerREVC
437
CHAPTER 13 8/16-bit PPG
13.4.1 PPG1 Control Register (PC1)
The PPG1 control register (PC1) sets the operating conditions for channel 1.
PPG1 Control Register (PC1)
Figure 13.4-2 PPG1 Control Register (PC1)
0 1/MCLK
PIE1 PUF1 POEN1 CKS12 CKS11 CKS10 00000000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R0/WX R0/WX R/W R(RM1),W R/W R/W R/W R/W
CKS10CKS11CKS1200
2/MCLK1004/MCLK0108/MCLK11016/MCLK00132/MCLK10127/CH01128/FCH111
POEN101
PUF1
01
PIE101
MCLK : Machine clock frequencyFCH : Main oscillation frequencyR/W : Read and write enabled (The reading value is the writing value.)
R(RM1),W : Read and write enabled (The reading value is different from the writing value. "1"read atread-modify-write instruction.)
R0/WX : Undefined bit (The reading value is 0. Writing has no effect to operation.) : Initial value
Initial value
Operating clock select bit
Output enable
Output enable bitOutput disable(general-purpose port)
Counter borrow dataction flagRead Write
Counter borrow undatactionCounter borrow dataction
Flag clearNo effect on operation
Interrupt request enable bitInterrupt enableInterrupt disable
438
Table 13.4-1 PPG1 Control Register (PC1)
Bit name Function
bit7bit6
-:Undefined bits
•
bit5PIE1:Interrupt request enable bit
•
bit4PUF1:Counter borrow detection flag bit
bit3POEN1:Output enable bit
• Enables or disables output for the PPG ch1 pin."0": Sets the PPG ch1 pin as a general-purpose port."1": Sets the PPG ch1 pin as the PPG output pin.
• In 16-bit PPG operation mode, setting this bit to "1" sets the PPG ch1 pin as an output.(Output the setting value of REV01. L output at REV01 = 0.
bit2bit1bit0
CKS12,CKS11,CKS10:Operation clock select bit
• Selects the operating clock for PPG down-counter ch0.• The operating clock is supplied from the prescaler.
Refer to Chapter 11 "Prescaler".• In 16-bit PPG operation mode, the value of this bit has no effect on the operation.
’000’: 1/MCLK’001’: 2/MCLK’010’: 4/MCLK’011’: 8/MCLK’100’: 16/MCLK’101’: 32/MCLK
’110’: 27/FCH
’111’: 28/FCH
Note:As the time-base timer halts when the sub clock is used (in dual clock versions), setting "110" or "111" is prohibited.
439
CHAPTER 13 8/16-bit PPG
13.4.2 PPG0 Control Register (PC0)
The PPG control register (PC0) sets the operating condition for channel 0 and the operation mode.
PPG for channel 0 Control Register (PC0)
Figure 13.4-3 PPG0 Control Register (PC0)
0
0 1/MCLK
MD1 MD0 PIE0 PUF0 POEN0 CKS02 CKS01 CKS00 00000000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R/W R/W R/W R(RM1),W R/W R/W R/W R/W
CKS00CKS01CKS0200
2/MCLK1004/MCLK0108/MCLK11016/MCLK00132/MCLK101
011111
Output disable(general-purpose port)POEN0
01
PUF0
0No effect on operation1
Interrupt request enable bitInterrupt enable
PIE00
Interrupt disable1
8-bit PPG for 2 channels independent modeMD0MD1
0100111
Initial value
Operating clock select bit
27/FCH28/FCH
Output enable bit
Output enable
Counter borrow dataction flagRead Write
Counter borrow undatactionCounter borrow dataction
Flag clear
MCLK : Machine clock frequencyFCH : Main oscillation frequencyR/W : Read and write enabled (The reading value is the writing value.)
R(RM1),W : Read and write enabled (The reading value is different from the writing value. "1"read atread-modify-write instruction.)
R0/WX : Undefined bit (The reading value is 0. Writing has no effect to operation.) : Initial value
Operating mode select bit
8-bit prescaler + 8-bit PPG mode
16-bit PPG mode
440
Table 13.4-2 PPG0 Control Register (PC0)
Bit name Function
bit7bit6
MD1,MD0:Operation mode select bits
• Select the operation mode of PPG.• Do not modify this bit when the count is in progress.
"00": 8-bit PPG for 2 channels independent mode"01": 8-bit prescaler + 8-bit PPG mode"1x ": 16-bit PPG mode
bit5PIE0:Interrupt request enable bit
• Controls interrupt of PPG for channel 0.• Set this bit in 16-bit PPG operation mode.
"0": PPG ch0 disables the interrupt."1": PPG ch0 enables the interrupt.
• An interrupt request (IRQ) is output when the counter borrow detect bit (PUF0) becomes "1" if the PIF0 bit is also "1".
bit4PUF0:Counter borrow detection flag bit
• Counter borrow detection bit for PPG ch0.• Only this bit is meaningful in 16-bit PPG operation mode.
(PC1:PUF is not operated.)
Note: Always enabled at 8 -bit mode.
• Writing "1" to this bit has no effect.• Writing "0" clears the bit to "0".• Read-modify-write instructions always read the bit as "1".
"0": Counter borrow undetection for PPG channel 0."1": Counter borrow detection for PPG channel 0.
bit3POEN0:Output enable bit
• Enables or disables output for the PPG ch1 pin."0": Sets the PPG ch0 pin as a general-purpose port."1": Sets the PPG ch0 pin as the PPG output pin.
• As the output in 16-bit PPG operation mode is from the PPG ch0 pin, use this bit to control output.
bit2bit1bit0
CKS02,CKS01,CKS00:Operation clock select bit
• Selects the operating clock for PPG down-counter ch0.• The operating clock is generated from the prescaler.
Refer to Chapter 11 "Prescaler".• As the rising and falling edge detection pulses from the ch1 PPG output are used as the count clock for
ch0 in 8-bit prescaler + 8-bit PPG mode, the value of this bit has no effect on the operation in this mode.• Set this bit in 16-bit PPG mode.
’000’: 1/MCLK’001’: 2/MCLK’010’: 4/MCLK’011’: 8/MCLK’100’: 16/MCLK’101’: 32/MCLK
’110’: 27/FCH
’111’: 28/FCH
Note:As the timebase timer halts when the sub clock is used (in dual clock versions), setting"110" or "111" is prohibited.
441
CHAPTER 13 8/16-bit PPG
13.4.3 PPG Cycle Set Register 1(PPS1), 0(PPS0)
The PPG period setting registers (PPS1 and PPS0) set the period for the PPG output.
PPG cycle set register 1(PPS1), 0(PPS0)
Figure 13.4-4 PPG cycle set register 1(PPS1), 0(PPS0)
• This register sets the period of the PPG output.
• In 16-bit PPG mode, PPS1 contains the upper 8 bits and PPS0 contains the lower 8 bits.
• When using 16-bit PPG mode, write the lower byte first followed by the upper byte.If you write to the upper byte only, the previous value is still used at the next reload.
• The maximum period is 255 (FFFFH) x the input clock cycle.
• Initialized at reset.
• Do not set the period to "00H" or "01H" if using 8-bit PPG operation mode or 8-bit prescaler + 8-bit PPGmode.
• Do not set the period to "0000H" or "0001H" if using 16-bit PPG mode.
• If the period setting is modified during operation, the new setting applies from the next PPG cycle.
PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 11111111
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
R/W
PPS1
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 11111111
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PPS0
R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : :
Read and Write enabled (The reading value is the writing value.)Initial value
Initial value
442
13.4.4 PPG Duty Setting Register 1(PDS1), 0(PDS0)
The PPG duty setting registers (PDS1 and PDS0) set the duty for the PPG output.
PPG Duty Setting Register 1(PDS1), 0(PDS0)
Figure 13.4-5 PPG Duty Setting Register 1(PDS1), 0(PDS0)
• This register sets the duty (H pulse width for normal polarity setting) of the PPG output.
• In 16-bit PPG mode, PDS1 contains the upper 8 bits and PDS0 contains the lower 8 bits.
• When using 16-bit PPG mode, write the upper byte first followed by the lower byte.If you write to the upper byte only, the previous value is still used at the next reload.
• Initialized at reset.
• Set "00h" for a duty ratio to 0%.
• Set the same value as the PPS register for a duty ratio to 100%.
• If the PDS register is set to a larger value than the PPS register, the PPG output will remain at the "L"level (if normal polarity is set).
• If the duty setting is modified while the PPG is operating, the new setting applies from the next PPGcycle.
DH7 DH6 DH5 DH4 DH3 DH2 DH1 DH0 11111111
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R/W
PDS1
DL7 DL6 DL5 DL4 DL3 DL2 DL1 DL0 11111111
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PDS0
R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : :
Initial value
Initial value
Initial valueRead and Write enabled (The reading value is the writing value.)
443
CHAPTER 13 8/16-bit PPG
13.4.5 PPG Start Register (PPGS)
The PPG start register (PPGS) starts or halts the down-counter.
PPG Start Register (PPGS)
Figure 13.4-6 PPG Start Register (PPGS)
As this series has two 8/16-bit PPG channels, bits 7 to 4 of the PPG start register (PPGS) and PPG output
inversion register (REVC) are unused bit on this model.
PEN31 PEN30 PEN21 PEN20 PEN11 PEN10 PEN01 PEN00 00000000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R/W R/W R/W R/W R/W R/W R/W R/W
PPG0 (ch0) Down-counter operation enable bitoperation stop
PEN000
operation enable1
PPG0 (ch1) Down-counter operation enable bitoperation stop
PEN010
operation enable1
PPG1 (ch0) Down-counter operation enable bitoperation stop
PEN100
operation enable1
PPG1 (ch1) Down-counter operation enable bitoperation stop
PEN110
operation enable1
PPG2 (ch0) Down-counter operation enable bitoperation stop
PEN200
operation enable1
PPG2 (ch1) Down-counter operation enable bitoperation stop
PEN210
operation enable1
PPG3 (ch0) Down-counter operation enable bitoperation stop
PEN300
operation enable1
PPG3 (ch1) Down-counter operation enable bitoperation stop
PEN310
operation enable1
Initial value
R/W : Read and write enabled (The reading value is the writing value.) : Initial value
444
13.4.6 PPG Output Inversion Register (REVC)
The PPG output inversion register (REVC) inverts the PPG output, including the initial level.
PPG Output Inversion Register (REVC)
Figure 13.4-7 PPG Output Inversion Register (REVC)
As this series has two 8/16-bit PPG channels, bits 7 to 4 of the PPG start register (PPGS) and PPG output
inversion register (REVC) are not used on this model.
REV31 REV30 REV21 REV20 REV11 REV10 REV01 REV00 00000000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R/W R/W R/W R/W R/W R/W R/W R/W
PPG0 (ch0) Output level inversion bitNormal
REV000
Inversion1
PPG0 (ch1) Output level inversion bitREV0101
PPG1 (ch0) Output level inversion bitREV1001
PPG1 (ch1) Output level inversion bitREV1101
PPG2 (ch0) Output level inversion bitREV2001
PPG2 (ch1) Output level inversion bitREV2101
PPG3 (ch0) Output level inversion bitREV3001
PPG3 (ch1) Output level inversion bitREV3101
NormalInversion
NormalInversion
NormalInversion
NormalInversion
NormalInversion
NormalInversion
NormalInversion
Initial value
R/W : Read and write enabled (The reading value is the writing value.) : Initial value
445
CHAPTER 13 8/16-bit PPG
13.5 Interrupt of 8/16-Bit PPG
The 8/16-bit PPG outputs an interrupt request when an counter borrow occurs.
Interrupt of 8/16-Bit PPGTable 13.5-1 shows the interrupt control bits and interrupt causes of 8/16-bit PPG.
When a counter borrow occurs on the down-counter, the 8/16-bit PPG sets the counter borrow detection
flag bit (PUF) in the control register (PC) to "1". If the interrupt request enable bit is enabled (PIE=1), an
interrupt request is output to the interrupt controller.
The control register for ch0 (PC0) is available in 16-bit PPG mode.
For the interrupt request number, Chapter X "Table of interrupt causes".
Table 13.5-1 Interrupt control bits and interrupt causes of 8/16-bit PPG
Item
Description
ch1(8-bit PPG, 8-bit prescaler)
ch0(8-bit PPG, 16-bit PPG)
Interrupt request flag bit PUF1 bit in PC1 PUF0 bit in PC0
Interrupt request enable bit PIE1 bit in PC1 PIE0 bit in PC0
Interrupt cause Counter borrow of down counter
446
13.6 Operation of 8/16-BIt PPG
This describes the settings for the 8/16-bit PPG.
Setting for 8/16-bit PPG
Setting for 8-bit independent operation mode
For operating as 8-bit independent mode, set the registers as Figure 13.6-1 .
Figure 13.6-1 8-bit independent Operation Mode
0 : Setting "0": Depend on built-in channel.
PIE1 PUF1 POEN1 CKS12 CKS11 CKS10
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PC1
MD1 MD0 PIE0 PUF0 POEN0 CKS02 CKS01 CKS00
0 0
PC0
PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0PPS1
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0
DH7 DH6 DH5 DH4 DH3 DH2 DH1 DH0
DL7 DL6 DL5 DL4 DL3 DL2 DL1 DL0
PPS0
PDS1
PDS0
PEN30 PEN30 PEN21 PEN20 PEN11 PEN10 PEN01 PEN00PPGS
REV30 REV30 REV21 REV20 REV11 REV10 REV01 REV00REVC
Setting the PPG output cycle of ch1
Setting the PPG output cycle of ch0
Setting the PPG output duty of ch1
Setting the PPG output duty of ch0
: Using
447
CHAPTER 13 8/16-bit PPG
Setting for 8-bit prescaler + 8-bit PPG mode
For operating as 8-bit prescaler + 8-bit PPG mode, set the registers as Figure 13.6-2 .
Figure 13.6-2 Setting for 8-bit prescaler + 8-bit PPG mode
: Using bit 0 : Setting "0" 1 : Setting "1"
: Setting is invalid
PIE1 PUF1 POEN1 CKS12 CKS11 CKS10
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PC1
MD1 MD0 PIE0 PUF0 POEN0 CKS02 CKS01 CKS00
0 1
PC0
PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0PPS1
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0
DH7 DH6 DH5 DH4 DH3 DH2 DH1 DH0
DL7 DL6 DL5 DL4 DL3 DL2 DL1 DL0
PPS0
PDS1
PDS0
PEN30 PEN30 PEN21 PEN20 PEN11 PEN10 PEN01 PEN00PPGS
REV30 REV30 REV21 REV20 REV11 REV10 REV01 REV00REVC
Setting the PPG output cycle of ch1
Setting the PPG output cycle of ch0
Setting the PPG output duty of ch1
Setting the PPG output duty of ch0
: Depend on built-in channel.
448
8-bit PPG Mode Settings
For operating as 16-bit PPG mode, set the registers as Figure 13.6-3 .
Figure 13.6-3 Setting for 16-bit PPG mode
PIE1 PUF1 POEN1 CKS12 CKS11 CKS10
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PC1
MD1 MD0 PIE0 PUF0 POEN0 CKS02 CKS01 CKS00
1 0/1
PC0
PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0PPS1
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0
DH7 DH6 DH5 DH4 DH3 DH2 DH1 DH0
DL7 DL6 DL5 DL4 DL3 DL2 DL1 DL0
PPS0
PDS1
PDS0
PEN30 PEN30 PEN21 PEN20 PEN11 PEN10 PEN01 PEN00PPGS
REV30 REV30 REV21 REV20 REV11 REV10 REV01 REV00REVC
Setting the PPG output cycle of ch1(upper 8 bit)
Setting the PPG output cycle of ch0(lower 8 bit)
Setting the PPG output duty of ch1(upper 8 bit)
Setting the PPG output duty of ch0(lower 8 bit)
: Using bit 0 : Setting "0" 1 : Setting "1"
: Setting is invalid: Depend on built-in channel.
449
CHAPTER 13 8/16-bit PPG
13.6.1 8-bit PPG Independent Operation Mode
This mode operates as two 8-bit PPG channels (ch0 and ch1).
Operation of 8-bit PPG Independent Operation Mode• Setting the operation mode selection bits (MD1, 0) in the PPG ch0 control register (PC0) to "00" selects
this mode.
• Setting the corresponding start bit (PEN) in the PPG start register (PPGS) to "1" loads the value fromthe PPG period setting register (PPS) and starts the down count. When the count reaches "1", the valuefrom the PPG period setting register is reloaded and counter operation is repeated.
• When the down-counter value matches the value set in the PPG duty register (PDS), the PPG output isset to "H". The output is set back to "L" when the down-counter reaches "1".
However, if the PPG output inversion bit is "1", the PPG output is inverted.
Figure 13.6-4 shows operation of 8-bit PPG independent operation mode.
Figure 13.6-4 Operation of 8-bit PPG Independent OPeration Mode
Reference:
Example for duty ratio of 50%
Setting PPS to "04h" and setting PDS to "02h" results in a PPG output with a duty ratio of 50%.(Sets the PPS setting value / 2 to PDS.)
m=5
n=4
5 4 3 2 1 5 4 3 2 1 5 4 3 2
(1) = n x T
(2) = m x T
T : Count clock periodm : PPS registern : PDS register
Counter borrow
(1)
(2)
PEN
ch0 counter value
(PDS)
(PPS)
Normal polarity
PPG
Count clock
(period T)
Counter start
Period setting
Duty setting
Inversion Polarity
Stop
Stop
Matching of down-countervalue and duty setting value
α
α : Depending on the select of count clock or the timing of start.
450
13.6.2 8-Bit Prescaler + 8-Bit PPG Mode
The rising and falling edge detection pulses from the ch1 PPG output can be used as the count clock for the ch0 down-counter to implement a variable-period 8-bit PPG output from ch0.
Operation of 8-Bit Prescaler + 8-Bit PPG Mode• Setting the operation mode selection bits (MD1, 0) in the PPG ch0 control register (PC0) to "01" selects
this mode. This sets ch1 as an 8-bit prescaler and ch0 as an 8-bit PPG.
• When the PPG ch1 operation enable bit (PEN01) is set to "1", the 8-bit prescaler (ch1) loads the periodsetting register (PPS1) value and starts down-counting. When the down-counter value matches the valueset in the duty register (PDS1), the PPG01 output is set to"H". The PPG01 output is set back to "L" when the down-counter reaches "1". If the output inversionsignal (REV01) is "L" or "H", unchanged polarity or inverted polarity is output to PPG pin respectively.
• When "H" is input to the PPG operating enable bit (PEN01), 8-bit PPG00 (ch0) loads the value ofperiod setting register (PPS0) and starts the down-count operation (Count clock is the rising and fallingedge detection pulses of PPG 01 output (ch1) after PPG ch1 is operation enable state. When the countreaches "1", the value from the PPG period setting register is reloaded and counter operation is repeated.When the down-counter value matches the value set in the duty setting register (PDS0), the PPG00output (ch0) is set to "H". The PPG00 (ch0) output is set back to "L" when the down-counter reaches"1". If the output inversion signal (REV00) is "0", the signal is output from the PPG00 pin withunchanged polarity. If REV00 is "1", the PPG00 pin output is inverted.
• The PPG output waveform will be different for each cycle if the output of the 8-bit prescaler has a dutyof other than 50%. Accordingly, always set a duty of 50%.
• Figure 13.6-5 shows operation of 8-bit independent operation mode.
451
CHAPTER 13 8/16-bit PPG
Figure 13.6-5 Operation of 8-bit prescaler + 8-bit PPG Mode
m1=4
n1=2
4 3 2 1 4 3 2 1 4 3 2 1 4 3 2
(1) = n1 x T(2) = m1 x T
T : Count clock reriode m0 : PPS0 register value n0 : PDS0 register value m1 : PPS1 register value n1 : PDS1 register value α : Depending on the select of count clock
clock or the timing of start β : Depending on the setting value of PPS1 and PDS1
Counter borrow
(1)
(2)
Count clock
PEN01
ch1 Counter value
(PDS1)
(PPS1)
PPG01
PEN00
3
m0=3
n0=2 (PDS0)
(PPS0)
2 1 3 2 1
PPG00
3
1 4
2
(3)
(4)
(3) = (1) x n0 (4) = (1) x m0
(period T)
Period setting
Duty setting
Normal polarty
Inversion polarty
Period setting
Duty setting
ch0 Counter value
Normal polarty
Inversion polarty
Matching of down-counter value and duty settingu value
α
β
452
13.6.3 16-bit PPG Mode
This mode operates as a 16-bit PPG with ch1 as the upper byte and ch0 as the lower byte.
Operation of 16-Bit PPG Mode• Setting the operation mode selection bits (MD1, 0) in the PPG ch0 control register (PC0) to "10" or "11"
selects this mode.
• In 16-bit PPG mode, writing "1" to the PPG operation enable bit (PEN00) loads the values of the periodsetting registers (PPS1 for ch1 and PPS0 for ch0) to the 8-bit down-counters for ch0 and ch1 and startsdown-counting. When the count reaches "1", the value from the PPG period setting register is reloadedand counter operation is repeated.
• When the down-counter values match the values set in the duty registers (PDS1 for ch1 and PDS0 forch0), the PPG00 output (ch0) is set to "H". The PPG00 (ch0) output is set back to "L" when the down-counter reaches "1". If the output inversion signal (REV00) is "0", the signal is output from the PPG00pin with unchanged polarity. If REV00 is "1", the PPG00 pin output is inverted. (ch0 only. ch1 is initialvalue. ("L" if REV01 is "0", "H" if REV01 is "1".))
Figure 13.6-6 Operation of 16-Bit PPG Mode
256 255 254 ... 2 1
PEN00
256 255
m=256
n=2
... 2 1 256 255
PPG00
(1)
(1) = n x T
(2) = m x T
T : Count clock period
m : PPS1 & PPS0 n : PDS1 & PDS0 α : Depending on the select of
count clock or the timing of start
α (2)
Count clock(period T)
Normal polarity
Inversion polarity
453
CHAPTER 13 8/16-bit PPG
13.7 Precautions for Using 8/16-Bit PPG
The following describes points to note when using the 8/16-bit PPG.
Precautions for Using 8/16-Bit PPG
Precautions on operating
• An error may occur in the first cycle of the PPG output depending on the start and count clock timing.This error will be different depending on the selected count clock. After the second cycle the operationbecomes normal.
Precautions on interrupts
• Operation cannot recover from interrupt processing if the interrupt request flag bits (PUF1 and PUF0) inthe PPG control registers (PC1 and PC0) are set to "1" when the interrupt request enable bits (PIE1 andPIE0) are "1". Always clear the interrupt request flag bits (PUF1 and PUF0) to "0".
454
13.8 Example Program for 8/16-Bit PPG
This shows an example program for the 8/16-bit PPG.
455
CHAPTER 13 8/16-bit PPG
456
CHAPTER 1416-bit PPG Timer
This chapter describes the function and operation of the 16-bit PPG timer.
14.1 Overview of 16-bit PPG Timer
14.2 16-bit PPG Timer Block Diagram
14.3 Channel and Pin of 16-bit PPG Timer
14.4 Registers of 16-bit PPG Timers
14.5 16-Bit PPG Timer Interrupt
14.6 16-bit PPG timer operation
14.7 Precautions when Using 16-bit PPG Timer
14.8 Program Example for 16-bit PPG Timer
457
CHAPTER 14 16-bit PPG Timer
14.1 Overview of 16-bit PPG Timer
The 16-bit PPG timer can generate a PWM (Pulse Width Modulation) output or one-shot (square wave) output, and cycle and duty of output waveform can be changed by software freely. The timer can generate an interrupt when a start trigger occurs or on the rising or falling edge of the output waveform.
16-bit PPG timerThe 16-bit PPG timer consists of a 16-bit down-counter, prescaler, 16-bit period setting buffer register, 16-
bit duty setting buffer register, control register, and PPG output pin.
Output waveform
PWM waveform
Normal polarity
Inverted polarity
One-shot waveform
Normal polarity
Inverted polarity
• The counter clock can be selected from eight different clock sources (MCLK/1, MCLK/2, MCLK/4,
MCLK/8, MCLK/16, MCLK/32, Fch/27, or Fch/28). (MCLK: Machine clock, Fch: Source oscillationclock)
• Interrupt can be selectively triggered by the following four conditions.
Start trigger of PPG timer occurs
Counter borrow of 16-bit down counter occurs (cycle match).
Duty match occurs
Counter borrow (cycle match) or duty match occurs
L H L L H
H L H H L
L H L
H L H
L H L L H
H L H H L
L H L
H L H
458
14.2 16-bit PPG Timer Block Diagram
This shows the block diagram of the 16-bit PPG timer.
16-bit PPG timer block diagram
Figure 14.2-1 16-bit PPG timer block diagram
MCLK/1MCLK/2MCLK/4MCLK/8MCLK/16MCLK/32MCLK/2
CLK LOAD
START BORROW
COMP
SQ
R
MDSE PGMS OSEL POEN
IRQ
IRS1 IRS0 IRQF IREN
CKS2 CKS1 CKS0
MCLK/2 STOP
STGR CNTE RTRG
POEN
7
8
1 0
PPG
EGS1 EGS0
Inte
rnal d
ata
bus
When the duty setting register for high-order 8-bit is only written and that for low-order 8-bit is not written, it is 1, otherwise it is 0.
Prescaler
Period setting register(high-order 8-bit)
Period setting register(low-order 8-bit)
Period setting buffer register for high-order 8-bit
16-bit down counter
Duty setting register(high-order 8-bit)
Duty setting register(low-order 8-bit)
Duty setting buffer register for high-order 8-bit
Duty setting buffer register for low-order 8-bit
Edge detection
Dow
n c
ou
nte
r re
gis
ter
Low
-ord
er 8
-bit
Interrupt selection
459
CHAPTER 14 16-bit PPG Timer
14.3 Channel and Pin of 16-bit PPG Timer
This section describes the 16-bit PPG timer channels.
Channel of 16-bit PPG timerTable 14.3-1 and Table 14.3-2 show the correspondence among channel, pin, and register.
Table 14.3-2 Registers of 16-bit PPG Timers
Table 14.3-1 Pins of 16-bit PPG Timer
Channel Pin Name Pin Function
0PPG0 PPG0 output
TRG0 Trigger0 input
1PPG1 PPG1 output
TRG1 Trigger1 input
2PPG2 PPG2 output
TRG2 Trigger2 input
Channel Register Name Registers
0
PDCRH0 PDCRH: PPG count down register (Upper)
PDCRL0 PDCRL: PPG count down register (Lower)
PCSRH0 PCSRH: PPG period setting buffer register (Upper)
PCSRL0 PCSRL: PPG period setting buffer register (Lower)
PDUTH0 PDUTH: PPG duty setting register (Upper)
PDUTL0 PDUTL: PPG duty setting register (Lower)
PCNTH0 PCNTH: PPG status control register (Upper)
PCNTL0 PCNTL: PPG status control register (Lower)
1
PDCRH1 PDCRH: PPG count down register (Upper)
PDCRL1 PDCRL: PPG count down register (Lower)
PCSRH1 PCSRH: PPG period setting buffer register (Upper)
PCSRL1 PCSRL: PPG period setting buffer register (Lower)
PDUTH1 PDUTH: PPG duty setting register (Upper)
PDUTL1 PDUTL: PPG duty setting register (Lower)
PCNTH1 PCNTH: PPG status control register (Upper)
PCNTL1 PCNTL: PPG status control register (Lower)
2
PDCRH2 PDCRH: PPG count down register (Upper)
PDCRL2 PDCRL: PPG count down register (Lower)
PCSRH2 PCSRH: PPG period setting buffer register (Upper)
PCSRL2 PCSRL: PPG period setting buffer register (Lower)
PDUTH2 PDUTH: PPG duty setting register (Upper)
PDUTL2 PDUTL: PPG duty setting register (Lower)
PCNTH2 PCNTH: PPG status control register (Upper)
PCNTL2 PCNTL: PPG status control register (Lower)
460
14.4 Registers of 16-bit PPG Timers
This section lists the 16-bit PPG timer registers.
Registers of 16-bit PPG Timers
Figure 14.4-1 Registers of 16-bit PPG Timers
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
PDCRH
R/WX 0
R/WX 0
R/WX 0
R/WX 0
R/WX 0
R/WX0
R/WX0
R/WX 0
R/WX 0
R/WX 0
R/WX 0
R/WX0
R/WX0
R/WX0
R/WX0
R/WX 0
PDCRL
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
PCSRH
R/W 1
R/W 1
R/W1
R/W 1
R/W1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W1
R/W 1
R/W 1
R/W1
PCSRL
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
PDUTH
R/W1
R/W1
R/W 1
R/W 1
R/W 1
R/W 1
R/W1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1R/W 1
R/W 1
R/W 1
R/W1
PDUTL
DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08
DC07 DC06 DC05 DC04 DC03 DC02 DC01 DC00
CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08
CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00
DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08
DU07 DU06 DU05 DU04 DU03 DU02 DU01 DU00
7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8
PCNTL
R/W 0
R,RM1/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W0
R0/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W0
R/W0
PCNTHCNTE STGR MDSE RTRG CKS1 CKS0 PGMSCKS2
IREN IRQF IRS1 IRS0 POEN OSELEGS0EGS1
R/WR/W00
PPG down counter register (Upper)
PPG down counter register (Lower)
Read/writeInitial value
Read/writeInitial value
Read/writeInitial value
Read/writeInitial value
Read/writeInitial value
Read/writeInitial value
Read/writeInitial value
Read/writeInitial value
PPG period setting buffer register (Lower)
PPG period setting buffer register (Upper)
PPG duty setting buffer register (Lower)
PPG duty setting buffer register (Upper)
PPG status control register (Upper)
PPG status control register (Lower)
Bit number
Bit number
Bit number
Bit number
Bit number
Bit number
Bit number
Bit number
461
CHAPTER 14 16-bit PPG Timer
14.4.1 PPG Down Counter Register (PDCRH, PDCRL)
The PPG down counter registers (PDCRH and PDCRL) form a 16-bit register which is used to read the count value from the 16-bit PPG down-counter.
PPG Down Counter Register (PDCRH, PDCRL)
Figure 14.4-2 PPG Down Counter Register (PDCRH, PDCRL)
These registers form a 16-bit register which is used to read the count value from the 16-bit PPG down-
counter. The initial value of the register is "1".
Always use one of the following procedures to read this register.
• Use the "MOVW" instruction (use a 16-bit access instruction to read the PDCRH register address).
• Use the "MOV" instruction and read PDCRH first and PDCRL second (reading PDCRH automaticallycopies the lower 8 bits of the down-counter to PDCRL).
These registers are read-only and writing has no effect.
note:
If you use the "MOV" instruction and read PDCRL before PDCRH, PDCRL will return the value fromthe previous valid read operation.
7 6 5
5
4 3 2 1 0
7 6 5 4 3 2 1 0
PDCRH
R/WX0
R/WX 0
R/WX 0
R/WX 0
R/WX 0
R/WX 0 1
R/WX0
R/WX 0
R/WX0
R/WX 0
R/WX 0
R/WX 0
R/WX0
R/WX0
R/WX 0
R/WX 0
PDCRL
DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08
DC07 DC06 DC05 DC04 DC03 DC02 DC01 DC00
Read/writeInitial value
PPG down counter register (Upper)
Bit number
Read/writeInitial value
PPG down counter register (Lower)
Bit number
462
14.4.2 PPG Period Setting Buffer Register (PCSRH, PCSRL)
The PPG period setting buffer registers set the period for the output pulses generated by the PPG.
PPG Period Setting Buffer Register (PCSRH, PCSRL)
Figure 14.4-3 PPG Period Setting Buffer Register (PCSRH, PCSRL)
These registers form a 16-bit register which sets the period for the output pulses generated by the PPG. The
values set in these registers are loaded to the down-counter.
When writing to these registers, always use one of the following procedures.
• Use the "MOVW" instruction (use a 16-bit access instruction to write to the PCSRH register address).
• Use the "MOV" instruction and write to PCSRH first and PCSRL second. (If a down-counter loadoccurs after writing data to PCSRH (but before writing data to PCSRL), the previous valid PCSRH/PCSRL value will be loaded to the down-counter.)
• Do not set PCSRH= "00H" and PCSRL= "00H", or PCSRH= "00H" and PCSRL= "01H".
note:
If you use the "MOV" instruction and write to PCSRL before PCSRH or if the down-counter loadoccurs after writing data to PCSRL (but before writing data to PCSRH), the previous valid PCSRHvalue or newly written PCSRL value is loaded to the down-counter.
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
PCSRH
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W1
R/W1
R/W 1
R/W1
R/W 1
R/W 1
R/W 1
R/W 1
R/W1
R/W1
R/W 1
PCSRL
CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08
CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00
Read/writeInitial value
PPG period setting buffer register (Upper)
Bit number
Read/writeInitial value
PPG period setting buffer register (Lower)
Bit number
463
CHAPTER 14 16-bit PPG Timer
14.4.3 PPG Duty Setting Buffer Register (PDUTH, PDUTL)
The PPG duty setting buffer registers control the duty ratio for the output pulses generated by the PPG.
PPG Duty Setting Buffer Register (PDUTH, PDUTL)
Figure 14.4-4 PPG Duty Setting Buffer Register (PDUTH, PDUTL)
These registers form a 16-bit register which controls the duty ratio for the output pulses generated by the
PPG. Transfer of the data from the PPG duty setting buffer registers to the duty setting registers is
performed at the same timing as the down-counter load.
When writing to these registers, always use one of the following procedures.
• Use the "MOVW" instruction (use a 16-bit access instruction to write to the PDUTH register address).
• Use the "MOV" instruction and write to PDUTH first and PDUTL second. (If a down-counter loadoccurs after writing data to PDUTH (but before writing data to PDUTL), the value of the duty settingbuffer registers is not transferred to the duty setting registers.)
note:
• If the same value is set in both the PPG period setting registers and duty setting registers, acontinuous "H" level is output if normal polarity is set, or a continuous "L" level is output if invertedpolarity is set.
• If the duty setting registers are set to "00", a continuous "L" level is output if normal polarity is set,or a continuous "H" level is output if inverted polarity is set.
• If the value set in the duty setting registers is greater than the value in the PPG period settingregisters, a continuous "L" level is output if normal polarity is set, and a continuous "H" level isoutput if inverted polarity is set.
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
PDUTH
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W1
R/W1
R/W 1
R/W1
R/W 1
R/W 1
R/W 1
R/W 1
R/W1
R/W1
R/W 1
PDUTL
DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08
DU07 DU06 DU05 DU04 DU03 DU02 DU01 DU00
Read/writeInitial value
PPG duty setting buffer register (Upper)
Bit number
Read/writeInitial value
PPG duty setting buffer register (Lower)
Bit number
464
14.4.4 PPG Status Control Register (PCNTH, PCNTL)
The PPG status control register is used to enable and disable the 16-bit PPG timer, and to set the operating status for the software trigger, re-trigger control interrupt, and output polarity.Also, it is used to check the status.
PPG Status Control Register, Upper Byte (PCNTH)
Figure 14.4-5 PPG Status Control Register, Upper Byte (PCNTH)
PGMS
0
1
CKS2 CKS1 CKS0
0 0 0 MCLK/1
MCLK/2
MCLK/4
MCLK/8
MCLK/16
MCLK/32
Fch/27
Fch/28
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
RTRG
0
1
MDSE
0 PWM mode
1
STGRSoftware trigger bit
No effect on operation
Generate software trigger
Write Read
0Always read "0"
1
CNTE
0
1R/W : Read/write : Initial value
MCLK: Machine clock
Retrigger enable bit
Disable retrigger
Enable retrigger
Mode selection bit
One-shot mode
Timer enable bit
Stop PPG timer
Enable PPG timer
R/W R0/W R/W R/W R/W R/W R/WR/W
CNTE STGR MDSE RTRG CKS1 CKS0 PGMS
Initial value00000000BCKS2
Bit 7 Bit 6 Bit 0Bit 1Bit 2Bit 3Bit 4Bit 5
PPG output mask enable bit
Disable PPG output mask
Enable PPG output mask
Counter clock selection bit
465
CHAPTER 14 16-bit PPG Timer
Table 14.4-1 PPG Status Control Register, Upper Byte (PCNTH)
Bit name Functions
Bit 0PGMS:PPG output mask enable bit
• This bit is used to mask the PPG output to a specific level regardless of the mode setting (MDSE: bit5), period setting (PCSRH, PCSRL), and duty setting (PDUTH, PDUTL).
• When this bit is set to "0": The PPG output mask function is disabled.• When this bit is set to "1": The PPG output mask function is enabled. When the PPG output
polarity setting is set to "normal" (OSEL bit in PCNTL register = "0"), the output is masked to "L". When the polarity setting is set to "inverted" (OSEL bit in PCNTL register = "1"), the output is masked to "H".
Bit 1Bit 2Bit 3
CKS2 to 0:Counter clock selection bits
• These bits select the operating clock for the 16-bit PPG timer.• The count clock signal is generated by the prescaler. See CHAPTER 11 Prescaler.
Note: As the timebase timer (TBT) is halted in sub clock mode, Fch/27 and Fch/28 cannot be selectedin this case.
Bit 4RTRG:Retrigger enable bit
• This bit enables the PPG software re-trigger function to be used during PPG operation.• When this bit is set to "0": The re-trigger function is disabled.• When this bit is set to "1": The re-trigger function is enabled.Note: This bit setting only applies to the software trigger and has no effect on the TRG inputhardware trigger.
Bit 5MDSE:Mode selection bits
• When this bit is set to "0": The PPG operates in PWM mode.• When this bit is set to "1": The PPG operates in one-shot mode.
Bit 6STGR:Software trigger bit
• This bit is used to start the PPG timer by software.• When this bit is set to "1": The PPG timer starts.• Reading this bit always returns "0".
Bit 7CNTE:Timer enable bit
• This bit is used to enable PPG timer operation.• When this bit is set to "0": Operation halts immediately and the PPG output goes to the initial
level ("L" output if OSEL=0, "H" output if OSEL=1).• When this bit is set to "1": PPG operation is enabled and the PPG goes to standby to wait for
a trigger.
466
PPG Status Control Register, Lower Byte (PCNTL)
Figure 14.4-6 PPG Status Control Register, Lower Byte (PCNTL)
OSEL Output inverted bit
Normal polarity
Inverted polarity
0
1
POEN
0
1
IRS1 IRS0
0
0
Rising edge of PPG output at normal polarity or falling edge of PPG output at inverted polarity (Duty match)
1
1
1
0
1
0
IRQFPPG interrupt request flag
PPG interrupt request enable flag
No PPG interrupt
PPG interrupt occurs
Read Write
0
1
IREN
0
1
: Read/write enabled (Reading value is writing value.): Read/write enabled (Reading value is different from writing value. Read "1" at read-modify-write instruction.): Initial value
Output enable bit
general-purpose I/O port
PPG output pin
Type of interrupt
Trigger, software trigger, trigger by TRG input
Disable interrupt request
Enable interrupt request
R/W R(RM1),W R/W R/W R/WR/W
IREN IRQF IRS0 POEN OSELIRS1
Counter borrow
Rising edge of PPG output at counter borrow or normal polarity or falling edge of PPG output at inverted polarity
Clear this bit
No effect on operation
EGS0EGS1
R/WR/W
EGS1 EGS0
0
0
1
1
1
0
1
0
Enable/disable trigger input
Disable to stop PPG operation by falling edge of TRGDisable to start PPG operation by rising edge of TRG
Initial value00000000B
Bit 7 Bit 6 Bit 0Bit 1Bit 2Bit 3Bit 4Bit 5
Disable to stop PPG operation by falling edge of TRGEnable to start PPG operation by rising edge of TRG
Enable to stop PPG operation by falling edge of TRGDisable to start PPG operation by rising edge of TRG
Enable to stop PPG operation by falling edge of TRGEnable to start PPG operation by rising edge of TRG
R/W R(RM1),W
467
CHAPTER 14 16-bit PPG Timer
Table 14.4-2 PPG Status Control Register, Lower Byte (PCNTL)
Bit name Functions
Bit 0OSEL:Output inversion bit
• This bit selects the polarity of PPG output pin.• When this bit is set to "0": Normal polarity is selected. The PPG output goes to "H" when the
16-bit down-counter value matches the duty setting register value, and goes to "L" when a down-counter borrow occurs.
• When this bit is set to "1": The PPG output is inverted.
Bits 1POEN:Output enable bit
• This bit enables or disables output from the PPG output pin.• When this bit is set to "0": The pin is set as a general-purpose port.• When this bit is set to "1": The pin is set as the PPG timer output pin.
Bit 2Bit 3
IRS1, IRS0:Interrupt selection bits
• These bit select the trigger for the PPG timer interrupt.
Bit 4IRQF:PPG interrupt flag bit
• This bit is set to 1 when PPG interrupt occurs.• When this bit is set to "0": Clears the bit.• When this bit is set to "1": No effect on operation.• Always read "1" at read-modify-write operation.
Bit 5IREN:PPG interrupt request enable bit
• This bit enable or disables PPG interrupt request to the CPU.• If this bit and the interrupt flag bit (IRQF) are "1", the PPG outputs an interrupt request.
Bit 6Bit 7
EGS1, EGS0: Hardware trigger enable bit
• These bits set the active edge for the TRG input trigger.• Setting EGS0 to "1" enables PPG operation start to be triggered by a rising edge on TRG.
Conversely, setting EGS0 to "0" disables PPG operation start from being triggered by a rising edge on TRG.
• Setting EGS1 to "1" enables PPG operation halt to be triggered by a falling edge on TRG. Conversely, setting EGS1 to "0" disables PPG operation halt from being triggered by a falling edge on TRG.
IRS1 IRS0
0
0
Rising edge of PPG output at normal polarity or falling edge of PPG output at inverted polarity (Duty match)
1
1
1
0
1
0
Type of interrupt
Trigger, software trigger, trigger by TRG input
Counter borrow
Rising edge of PPG output at counter borrow or normal polarity or falling edge of PPG output at inverted polarity
468
14.5 16-Bit PPG Timer Interrupt
The 16-bit PPG timer can generate interrupt requests in the following cases.• When generating trigger or counter borrow• When generating rising of PPG in normal polarity• When generating falling of PPG in inverted polarity The interrupt operation is controlled by IRS1 (bit 3) and IRS0 (bit 2) in the PCNTL register.
16-Bit PPG Timer InterruptTable 14.5-1 shows interrupt control bits and interrupt causes of the 16-bit PPG timer.
If IRQF (bit 4) of the PPG status control register (PCNTL) is set to "1" and interrupt requests are enabled
(IREN (bit 5) in the PCNTL register = "1"), the 16-bit PPG timer outputs an interrupt request to the
interrupt controller.
Table 14.5-1 Interrupt control bits and interrupt causes of the 16-bit PPG timer
16-bit PPG timer
Interrupt flag bit PCNTL0:IRQF (bit 4)
Interrupt request enable bit PCNTL0:IREN (bit 5)
Interrupt type selection bits PCNTL0:IRS1, 0 (bit 3, 2)
Interrupt cause
PCNTL0:IRS1, 0="00"Gate trigger, software trigger and retrigger of 16-bit down-counter (ch0)
PCNTL0:IRS1, 0="01"counter borrow of 16-bit down counter (ch0
PCNTL0:IRS1, 0="10"PPG0 output rising in normal polarity or PPG0 output falling in inverted polarity
PCNTL0:IRS1, 0="11"Counter borrow on the 16-bit down-counter (ch0), or a rising edge (normal polarity) or falling edge (inverted polarity) on the PPG0 output
469
CHAPTER 14 16-bit PPG Timer
14.6 16-bit PPG timer operation
The 16-bit PPG timer can operate in PWM mode or one-shot mode. The 16-bit PPG timer can also use a re-trigger function.
PWM mode (MDSE of PCNTH register: Bit 5=0) • In PWM operation mode, the period setting register (PCSRH and PCSRL) values are loaded and the 16-
bit down counter starts down counting when a valid software trigger or a hardware trigger from the TRGinput is detected. The period setting register (PCSRH and PCSRL) values are reloaded and the down-count operation repeats when the count reaches "1".
• The initial state of the PPG output is "L". When the 16-bit down-counter value matches the value set inthe duty setting registers, the output changes to "H". The output changes back to "L" when the counterreaches "1". (The output levels are reversed if setting in OSEL=1.)
• When re-triggering is disabled (RTRG=0), software triggers (STRG=1) are ignored if they occur whenthe down-counter is already running.
• If the down-counter is not running, the maximum time between a valid trigger input occurring and thedown-counter starting is as follows.
- Software trigger:
1 count clock cycle + 2 machine clock cycles
- Hardware trigger by TRG input:
1 count clock cycle + 3 machine clock cycles
• If the down-counter is running, the maximum time between a valid re-trigger input occurring and thedown-counter re-starting is as follows.
- Software trigger:
1 count clock cycle + 2 machine clock cycles
- Hardware trigger by TRG input:
1 count clock cycle + 3 machine clock cycles
470
The retrigger is invalidated. (RTRG of PCNTH register: bit 4=0)
Figure 14.6-1 In the PWM mode in case of the retrigger invalid
The retrigger is made effective. (RTRG of PCNTH register: bit4=1)
Figure 14.6-2 In the PWM mode in case of the retrigger valid
m
n
0Detecting rising edge
Trigger is ignored.
(1)=n x T ns(2)=m x T ns
PPG
(1)
(2)
(Normal polarity)
(Reverse polarity)
Time
16-bit down counter value
Software trigger
n: PDUTH,L register valuem: PCSRH,L register value
T: Count clock cycle
m
n
0Detecting rising edge
Restart by trigger
(1)=n x T ns(2)=m x T ns
PPG
PPG
(1)(2)
(Normal porality)
(Reverse porality)
Time
Counter value
Software trigger
n: PDUTH,L register valuem: PCSRH,L register valueT: Count clock cycle
471
CHAPTER 14 16-bit PPG Timer
One-shot Mode (MDSE of PCNTH register:bit5=1) • One-shot operation mode can be used to output a single pulse with a specified width when a valid
trigger input occurs. If re-triggering is enabled, the down-counter value is reloaded if a valid trigger isdetected while the counter is running.
• The initial state of the PPG output is "L". When the 16-bit down-counter value matches the value set inthe duty setting registers, the output changes to "H". The output changes back to "L" when the counterreaches "1". (The output levels are reversed if OSEL is set to 1.)
Invalid retrigger (RTRG of PCNTH register:bit4=0)
Figure 14.6-3 When Retrigger is invalid at One-shot mode
Valid retrigger (RTRG of PCNTH register:bit4=1)
Figure 14.6-4 When Retrigger is Valid at One-shot Mode
m
n
0
(1)
(2)
Detecting rising edge
Trigger ignored
(1)=n x T ns(2)=m x T ns
PPG
PPG(Normal porality)
(Reverse porality)
Time
Counter value
Software trigger
n: PDUTH,L register valuem: PCSRH,L register valueT: Count clock cycle
m
n
0
(1)
(2)
Detecting rising edge
Restart trigger
(1)=n x T ns(2)=m x T ns
PPG
PPG(Normal porality)
(Reverse porality)
Time
Counter value
Software trigger
n: PDUTH,L register valuem: PCSRH,L register valueT: Count clock cycle
472
Hardware Trigger• If the hardware trigger, which uses the TRG input, is used (EGS1 and EGS0 set to "1"), the PPG starts
on a rising edge and halts when a falling edge is detected. Also, the PPG timer starts again on the nextrising edge.
• The RTRG bit re-trigger setting is ignored if the TRG input hardware trigger is used. In this case,operation is only re-triggered by the hardware trigger (when a valid TRG input occurs).
Figure 14.6-5 Hardware Trigger at PWM Mode
m
n
0Detecting rising edge Detecting falling edge
PPG
(1)
(2)
(Normal porality)
(Reverse porality)
Time
Counter value
Counter value
(1)=n x T ns(2)=m x T ns
n: PDUTH,L register valuem: PCSRH,L register value
T: Count clock cycle
473
CHAPTER 14 16-bit PPG Timer
14.7 Precautions when Using 16-bit PPG Timer
This section describes points to note when using the 16-bit PPG timer.
Precautions when Using 16-bit PPG Timer
Notes on programing
• Do not use the re-trigger if the same values are set for the period and duty. If used, the PPG output willgo to the "L" level for one count clock cycle after the re-trigger, and then go back to the "H" level (forthe case when normal polarity is set).
• When changing to a standby mode, disable the timer enable bit (PCNTH:CNTE="0") or disable thehardware trigger enable bit (PCNTL:EGS1,EGS0="00") to prevent misoperation due to changes in theTRG pin level.
474
14.8 Program Example for 16-bit PPG Timer
This section describes program examples of an 16-bit PPG timer.
Program Example for 16-bit PPG Timer
475
CHAPTER 14 16-bit PPG Timer
476
CHAPTER 1516-bit Reload Timer
The chapter describes the functions and operation of the 16-bit reload timer.
15.1 Overview of 16-bit Reload Timer
15.2 Block Diagram of 16-bit Reload Timer
15.3 Channel of 16-Bit Reload Timer
15.4 Registers of 16-Bit Reload Timer
15.5 Interrupts of 16-Bit Reload Timer
15.6 Operation of 16-bit reload timer
15.7 16-Bit Reload Timer Notes on Use
15.8 Program Example of 16-Bit Reload Timer
477
CHAPTER 15 16-bit Reload Timer
15.1 Overview of 16-bit Reload Timer
The 16-bit reload timer can select the following two clock modes and counter operation modes. Clock Mode
1) Internal clock mode: Counts down synchronized with the clock selected from the seven available internal clocks.
2) Event count mode (external clock mode): Counts down on detection of the available edge at the input pin.
Counter operating mode1) Reload mode: Reload the count setting value and continue counting.2) One-shot mode: Halt the count when an underflow occurs.
Operation Modes of 16-bit Reload TimerTable 15.1-1 shows the operation modes of 16-bit reload timer.
Internal clock modeInternal clock mode is selected if a value other than "111B" is set in the count clock setting bits (CLS2-0) of
the upper timer control status register (TMCSRH).
In internal clock mode, the following three operation modes are available.
Software trigger operation
The count starts if the count enable bit (CNTE) in the lower timer control status register (TMCSRL) is "1"
and "1" is set to the software trigger bit (TRG).
External trigger input operation
If the count enable bit (CNTE) in the lower timer control status register (TMCSRL) is set to "1", the count
starts when the active edge (rising, falling, or both edge) specified by the operation mode setting bits
(MOD2 to 0) is input to the TI pin.
External gate input operation
If the count enable bit (CNTE) in the lower timer control status register (TMCSRL) is set to "1", the count
starts when the level ("L" or "H") specified by the operation mode setting bits (MOD2 to 0) is input to the
TI pin.
Table 15.1-1 Operation Modes of 16-bit Reload Timer
Clock Mode Counter operating mode Trigger operating mode
Internal clock modeReload mode Software trigger operation
External trigger input operationExternal gate input operationOne-shot mode
Event count mode(External clock mode)
Reload modeExternal event clock operation
One-shot mode
478
Event count mode (external clock mode) If the count clock setting bits (CSL2 to 0) in the upper timer control status register (TMCSRH) are set to
"111B", the count starts when the active edge (rising, falling, or both edge) specified by the operation mode
setting bits (MOD2-0) is input to the TI pin. When a constant frequency external clock is input, the reload
timer can also be used as an interval timer.
Counter operation
Reload mode
The value of the 16-bit reload register (TMRLRH/L) is loaded to the 16-bit down-counter and the count
continues when an underflow ("0000H" -> "FFFFH") occurs on the 16-bit down-counter. As an underflow
also triggers output of an interrupt request, the 16-bit reload timer can also be used as an interval timer.
One-shot mode
An interrupt is generated when an underflow occurs on the 16-bit down-counter.
A rectangular waveform indicating when the count is in progress can be output from the TO pin when the
counter is operating.
479
CHAPTER 15 16-bit Reload Timer
15.2 Block Diagram of 16-bit Reload Timer
The 16-bit reload timer consists of the following blocks.• Count clock generation circuit• Reload control circuit• Output control circuit• Operation control circuit• 16-bit timer register (TMRH, TMRL) • 16-bit reload register (TMRLRH, TMRLRL) • Timer control status register (TMCSRH, TMCSRL)
Block Diagram of 16-Bit Reload TimerFigure 15.2-1 shows the block diagram of 16-bit reload timer.
Figure 15.2-1 Block Diagram of 16-Bit Reload Timer
16 bit reload register (TMRLRH/L)
16 bit timer register (TMRH/L)
Input control circuit
Valid clock judgement circuit
CSL2 CSL1 CSL0 MOD2 MOD1 MOD0
Clock selection
OUTE OUTL RELD INTE UF CNTE TRG
Operation control circuit
Reload control circuit
Output signal generationcircuit
PinReve-rse
Enable
SelectFunction selection
Count clock generation circuit
Pin
Internal clock
Output control circuit
Timer control status register (TMCSR)
Internal bus
Wait
CLK
CLK
Reload
Internal bus
Interrupt request signal
TI TO
480
Count clock generation circuit
The count clock for the 16-bit reload timer is generated from the internal clock or the TI input.
Reload control circuit
Controls reload operation when the timer is started or an underflow occurs.
Output control circuit
Controls the reverse operation of the TO pin output by an underflow of the 16-bit down-counter and the
enable/disable of the TO pin output.
Operation control circuit
Starting/stopping of 16 bit down counter is controlled.
16-bit timer register (TMRH, TMRL)
These registers operate as a 16-bit down-counter. Reading returns the current count value.
This register is to be a reading dedicated register.
16-bit reload register (TMRLRH, TMRLRL)
These register is for setting 16-bit down counter load value. The value set in the 16-bit reload registers is
loaded to the 16-bit down-counter when down-counting starts.
These registers are to be a writing dedicated register.
Timer control status register (TMCSRH, TMCSRL)
These registers control the count clock operation mode, clock selection, interrupts, and other aspects of the
16-bit reload timer operation, and store the current status.
481
CHAPTER 15 16-bit Reload Timer
15.3 Channel of 16-Bit Reload Timer
This section describes the channels of the 16-bit reload timer.
Channel of 16-Bit Reload TimerTable 15.3-1 and Table 15.3-2 show the correspondence of the channel, the pin and the register.
Table 15.3-1 Pins of 16-bit Reload Timer
Channel Pin Name Pin Function
0TO0 Timer output
TI0 Timer input
1TO1 Timer output
TI1 Timer input
Table 15.3-2 Registers of 16-bit reload timer
Channel Register Name Corresponding Register (Name in Specifications)
0
TMCSRH0 TMCSRH: Timer control status register (upper)
TMCSRL0 TMCSRL: Timer control status register (lower)
TMRH0 TMRH: 16-bit timer register (upper)
TMRL0 TMRL: 16-bit timer register (lower)
TMRLRH0 TMRLRH: 16-bit reload register (upper)
TMRLRL0 TMRLRL: 16-bit reload register (lower)
1
TMCSRH1 TMCSRH: Timer control status register (upper)
TMCSRL1 TMCSRL: Timer control status register (lower)
TMRH1 TMRH: 16-bit timer register (upper)
TMRL1 TMRL: 16-bit timer register (lower)
TMRLRH1 TMRLRH: 16-bit reload register (upper)
TMRLRL1 TMRLRL: 16-bit reload register (lower)
482
15.4 Registers of 16-Bit Reload Timer
This section describes the registers of the 16-bit reload timer.
List of Register of 16-Bit Reload TimerFigure 15.4-1 shows the registers of 16-bit reload timer.
Figure 15.4-1 Registers of 16-bit reload timer
- - CSL2 CSL1 CSL0 MOD2 MOD1 MOD0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Timer control status register (upper)TMCSRH
- OUTE OUTL RELD INTE UF CNTE TRG
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Timer control status register (lower)TMCSRL
D15 D14 D13 D12 D11 D10 D9 D8
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
16 bit timer register (upper)TMRH
D7 D6 D5 D4 D3 D2 D1 D0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
16 bit timer register (lower)TMRL
D15 D14 D13 D12 D11 D10 D9 D8
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
16 bit reload register (upper)TMRLRH
D7 D6 D5 D4 D3 D2 D1 D0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
16 bit reload register (lower)TMRLRL
Notes: - Same address is assigned to TMRH and TMRLRH.- Same address is assigned to TMRL and TMRLRL.
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CHAPTER 15 16-bit Reload Timer
15.4.1 Upper Timer Control Status Register (TMCSRH)
The timer control status register (TMCSRH) sets the operation mode and operating conditions of the 16-bit reload timer.
Upper Timer Control Status Register (TMCSRH)
Figure 15.4-2 Upper Timer Control Status Register (TMCSRH)
- - CSL2 CSL1 CSL0 MOD2 MOD1 MOD0 00000000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
R0/WX R0/WX R/W R/W R/W R/W R/W R/W
Operation mode selection bit(at internal clocl mode, without CSL2,1,0="111")
Input pin function Valid edge, levelExternal input invalid
MOD0MOD1MOD2
-000
Trigger inputRising edge100Falling edge010Both edge110
Gate input"L" level0X1"H" level1X1
Operation mode selection bit(at event count mode, CSL2,1,0="111")
Input pin function Valid edge-
MOD0MOD1MOD2
-00X
Trigger inputRising edge10XFalling edge01XBoth edge11X
Count clock selection bitOperation mode Count clock
Internal clock
CSL0CSL1CSL2
1/MCLK0002/MCLK1004/MCLK0108/MCLK11016/MCLK001
Event count
32/MCLK10127/F CH011TIx pin111
R/W :R0/WX :MCLK : FCH :
:
Read/write enabled (read value = write value)Undefined bit (read value = "0", No effent on writing opeartion)Machine clockMain oscillasion frequencyInitial value
Note: X : 0 or 1
484
Table 15.4-1 Upper Timer Control Status Register (TMCSRH)
Bit name Function
Bit7Bit6
-:Unused bits
• These bits are invalid at writing.• Reading always returns "0".
Bit5Bit4Bit3
CSL2,CSL1,CSL0:Count clock selection bits
• These bits select the count clock of the 16-bit reload timer.• If set to other than "111": Counts an internal clock. (Internal clock mode) The internal clock is generated
by the prescaler. See "CHAPTER 11 Prescaler".• If set to "111": Counts the edges of the external event clock. (event count mode)
Bit2Bit1Bit0
MOD2,MOD1,MOD0:Operation mode select bits
• These bits set the operation conditions of the 16-bit reload timer.• When internal clock mode (without CSL2 to 0="111")
MOD2 bit selects the input pin functionWhen MOD2 sets to 0:- The TI pin functions as a trigger input.- The MOD1 and MOD0 bits are used to select the edge to be detected.- When the edge is detected, the value set in the 16-bit reload register is reloaded in the 16-bit timer
register (TMR), starting the count operation of the TMR.When MOD2 sets to 1:- The TI pin functions as a gate input.- MOD1 bit setting is invalid.- The MOD0 bit selects the active signal level (H or L). The 16-bit timer register only counts while the
active signal level is being input. Note: External input is disabled if MOD2 to 0 are "000". In this case, operation is controlled by software
using the TRG bit.• When event count mode (CSL2 to 0="111")
- The MOD2 bit is always fixed to "0".- Input the external event clock from the TI pin.- The MOD1 and MOD0 bits are used to select the edge to be detected.
485
CHAPTER 15 16-bit Reload Timer
15.4.2 Lower Timer Control Status Register (TMCSRL)
The timer control status register (TMCSRL) sets the operating conditions of the 16-bitreload timer, enables or disables counting, controls interrupts, and stores the interruptrequest status.
Lower Timer Control Status Register (TMCSRL)
Figure 15.4-3 Lower Timer Control Status Register (TMCSRL)
- OUTE OUTL RELD INTE UF CNTE TRG 00000000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
R0/WX R/W R/W R/W R/W R(RM1),W R/W R0,W
Software trigger bitat read at write
Always read "0".
TRG
No effent on operation0Start count after reload1
Count enable bitCount stop
CNTE0
Count enable (wait for start trigger)1
Underflow interrupt request flag bitat read at write
No underflow
UF
Clear the interrupt request0Underflow1 No effent on operation
Underflow interrupt request enable bitUnderflow interrupt disabled
INTE0
Underflow interrupt enabled1
Reload selection bitOne-shot mode
RELD0
Reload mode1
Pin output level selection bitOne-shot mode Reload mode
Output "H" rectangular waveform during count
OUTL
Output "L" toggleat count start
0
Output "L" rectangular waveform during count
1 Output "H" toggleat count start
Timer output enabled bitTimer output disabled (general purpose I/Oport)
OUTE0
Timer output enabled1
R/W :R0,W :
R(RM1),W :R0/WX :
:
Read, write enabled (read value = write value)Write only (waritable, read value = "0")Read, write enabled (read value = write value, At read modify write, read "1".)Undefine bit (read value = "0", Writing has no effect on operation.)Initial value
486
Table 15.4-2 Lower Timer Control Status Register (TMCSRL)
Bit name Function
Bit7-:Undefined bits
• This bit is invalid at writing.• Reading always returns "0".
Bit6OUTE:Timer output enable bit
• The TO terminal function of the 16-bit reload timer is set."0": Functions as a general-purpose I/O port."1": Functions as the TO pin of the 16-bit reload timer.
Bit5OUTL:Pin output level selection bit
• This bit sets the output level of the output pin of the 16-bit reload timer.• When selecting one-shot mode (RELD=0)
"0": Outputs an "H" level rectangular waveform while the 16-bit timer is counting."1": Outputs an "L" level rectangular waveform while the 16-bit timer is counting.
• When selecting reload mode (RELD=1)"0": Outputs an "L" when the 16-bit timer is started and then toggles each time an underflow occurs."1": Outputs an "H" when the 16-bit timer is started and then toggles each time an underflow occurs.
Bit4RELD:Reload select bit
• Reload operation is set when underflow is generated."1": When underflow is generated, the value that has been set to the 16-bit reload register is loaded to
the 16-bit timer register, and counting will continue. (Reload mode) "0": When underflow is generated, counting is suspended. (One-shot mode)
Bit3
INTE:Underflow interrupt request enable bit
• Underflow interrupt can be enabled or disabled. An interrupt request is generated if this bit is "1" when the underflow interrupt request flag bit (UF) goes to "1".
Bit2
UF:Underflow interrupt request flag bit
• Indicates that an underflow has occurred on the 16-bit reload timer.When set to "1": Writing has no meaning.When set to "0": Clears the UF bit.
• The bit is always read as "1" by read-modify-write instructions.
Bit1CNTE:Count enable bit
• This bit enables/disables the operation of 16-bit reload timer"1": Goes to standby to wait for a start trigger. When the activation trigger is input, the 16-bit timer
register starts counting."0": Halts the count.
Bit0TRG:Software trigger bit
• 16-bit reload timer can be activated by the software.• The TRG bit is only meaningful when timer operation is enabled (CNTE=1).
"1": The value of the 16-bit reload register is reloaded to the 16-bit timer register and the 16-bit timer register starts counting from the next count clock input.
"0": No effectNote: This bit can be set to "1" at the same time as the CNTE bit.• When reading: "0" is always read.
However, reading returns "1" during the time between writing "1" to start the timer and the timer count actually starting.
487
CHAPTER 15 16-bit Reload Timer
15.4.3 Upper, Lower 16-bit Timer Register (TMRH, TMRL)
The upper and lower 16-bit timer registers (TMRH and TMRL) can be used to read thecurrent value of the 16-bit down-counter.
Upper, Lower 16-bit Timer Register (TMRH, TMRL)
Figure 15.4-4 Upper, Lower 16-bit Timer Register (TMRH, TMRL)
The 16-bit timer register can read the count value of the 16-bit down-counter.
If counting is enabled (CNTE=1 in TMCSRL) when a count start occurs, the value written in the 16-bit
reload register is reloaded to these registers and down-counting starts.
Note:
• The count can be read from these registers even while counting is in progress. When reading,use a word move instruction or read the upper byte first and the lower byte second. (The circuit isimplemented so that the lower byte is saved when the upper byte is read.)
• The registers are read-only and are located at the same address as the 16-bit reload register.Accordingly, writing to these registers writes to the 16-bit reload register.
D15 D14 D13 D12 D11 D10 D9 D8 00000000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
R,W
TMRH
D7 D6 D5 D4 D3 D2 D1 D0 00000000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
TMRL
R,W R,W R,W R,W R,W R,W R,W
R,W R,W R,W R,W R,W R,W R,W R,W
R,W :: Initial value
Read, write enabled (read value = write value)
488
15.4.4 Upper, Lower 16-bit Reload Register (TMRLRH, TMRLRL)
The upper (TMRLRH) and lower (TMRLRL) 16-bit reload registers set the reload value forthe 16-bit down-counter. The value set in the 16-bit reload registers is reloaded to the16-bit down-counter and down-counting starts.
Upper, Lower 16-bit Reload Register (TMRLRH, TMRLRL)
Figure 15.4-5 Upper, Lower 16-bit Reload Register (TMRLRH, TMRLRL)
These registers set the reload value to the 16-bit down-counter.
The value set in the 16-bit reload registers is reloaded to the 16-bit down-counter and down-counting starts
at the timing of start or underflow.
(Rewritable on counter operation)
Note:
• The registers can be written to while the counter is running. Write using a word move instructionor write the upper byte first and lower byte second. (The circuit is implemented so that the upperbyte is not used until the lower byte is written.)
• The registers are write-only and are located at the same address as the 16-bit timer register.Accordingly, reading these registers returns the 16-bit reload register value.
D15 D14 D13 D12 D11 D10 D9 D8 00000000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TMRLRH
D7 D6 D5 D4 D3 D2 D1 D0 00000000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TMRLRL
R,W R,W R,W R,W R,W R,W R,W R,W
R,W R,W R,W R,W R,W R,W R,W R,W
R,W ::
Initial value
Initial value
Initial valueRead, write enabled (read value = write value)
489
CHAPTER 15 16-bit Reload Timer
15.5 Interrupts of 16-Bit Reload Timer
The 16-bit reload timer outputs an interrupt request when an underflow occurs on the16 down-counter.
Interrupts of 16-bit Reload TimerTable 15.5-1 shows the interrupt control bits and interrupt causes of the 16-bit reload timer
The 16-bit reload timer sets the underflow interrupt request flag bit (UF) in the lower timer control status
register (TMCSRL) to "1" when an underflow ("0000H" → "FFFFH") occurs in the 16-bit down-counter. If
the underflow interrupt request enable bit is enabled (INTE=1), the interrupt request is output to the
interrupt controller.
For interrupt request number, see "CHAPTER x Interrupt Source Table".
Table 15.5-1 Interrupt control bits and interrupt causes of the 16-bit reload timer
Item Description
Interrupt request flag bit UF bit in the TMCSRL register
Interrupt request enable bit INTE bit in the TMCSRL register
Interrupt cause Underflow of down counter (TMRH/L)
490
15.6 Operation of 16-bit reload timer
This section explains the setting of the 16-bit reload timer and the operation state of thecounter.
Setting of 16-bit Reload Timer
Setting of internal clock mode
For operating as interval timer, the register should be set as Figure 15.6-1 .
Figure 15.6-1 Setting of internal clock mode
- - CSL2 CSL1 CSL0 MOD2 MOD1 MOD0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
other than "111"
TMCSRH
- OUTE OUTL RELD INTE UF CNTE TRG
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
1
TMCSRL
D15 D14 D13 D12 D11 D10 D9 D8
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TMRLRH
D7 D6 D5 D4 D3 D2 D1 D0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TMRLRL
: Using bit1 : Set "1"
Set the counter initial value (reload value) (upper)
Set the counter initial value (reload value) (lower)
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CHAPTER 15 16-bit Reload Timer
Setting of Event Count Mode
For operating as event counter, the register should be set as Figure 15.6-2 .
Figure 15.6-2 Setting of Event Count Mode
- - CSL2 CSL1 CSL0 MOD2 MOD1 MOD0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TMCSRH
- OUTE OUTL RELD INTE UF CNTE TRG
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
1
TMCSRL
D15 D14 D13 D12 D11 D10 D9 D8
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TMRLRH
D7 D6 D5 D4 D3 D2 D1 D0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TMRLRL
Set the counter initial value (reload value) (upper)
Set the counter initial value (reload value) (lower)
111
: Using bit1 : Set "1"
492
Operation State of CounterThe counter status is determined by the value of the count enable bit (CNTE) in the timer control status
register (TMCSLR) and the internal signal start trigger wait signal (WAIT). In the STOP state (halted),
WAIT state (waiting for a start trigger) and RUN state (operating state) can be set.
Figure 15.6-3 shows status transition of these counters.
Figure 15.6-3 State Transition Diagram of counter
Reset STOP status CNTE=0,WAIT=1
TI pin: input disable
TO pin: genaral purpose I/O port
16-bit timer register: keep the value at stopValue immediately after reset = 16'h0000
WAIT status CNTE=1,WAIT=1
TI pin: only trigger input is valid
TO pin: 16-bit reload register output
16-bit timer register: keep the value at stopValue immediately after reset = 16'h0000
RUN status CNTE=1,WAIT=0
TI pin: 16-bit reload timer input
TO pin: 16-bit reload register output
16-bit timer register: count operation
LOAD CNTE=1,WAIT=0
16bit reload register setting value →load 16bit timer register
: Status transision by hardware: Status transision by register access: WAIT signal (internal signal): Software trigger bit (TMCSRL): Timer operation enabled bit (TMCSRL): Underflow generation flag bit (TMCSRL): Reload selection bit (TMCSRL)
WAITTRGCNTEUFRELD
CNTE=0
CNTE=1
TRG=0
CNTE=1
TRG=1
CNTE=0
External trigger from TI pin
TRG=1(software trigger)
Load end
TRG=1(software trigger)
UF=1 &RELD=0(one-shot mode)
UF=1 &RELD=1(reload mode)
External trigger from TI pin
CNTE=0
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CHAPTER 15 16-bit Reload Timer
15.6.1 Internal Clock Mode (Reload Mode)
The 16-bit down-counter counts down synchronized with the internal count clock, andoutputs an interrupt request to the CPU when the count underflow ("0000H" →"FFFFH"). Also can output toggle waveforms from the timer output pin.
Operation of Internal Clock Mode (Reload Mode)When "1" is set to the count enable bit (CNTE) to enable counting, and the timer is started by setting "1" to
the software trigger (TRG) or by an external trigger, the value set in the 16-bit reload register (TMRLR) is
reloaded to the 16-bit down-counter and down-counting starts. If counting is enabled when the count enable
bit (CNTE) and software trigger bit (TRG) are set to "1" at the same time, the count is started at the same
time.
If the reload selection bit (RELD) is "1", the value of the 16-bit reload register (TMRLR) is reloaded to the
16-bit down-counter and the count continues when the 16-bit counter underflow ("0000H" → "FFFFH"). If
the underflow interrupt request flag bit (UF) is "1" when the underflow interrupt request enable bit (INTE)
is set to "1", an interrupt request is output.
A toggle waveform that inverts each time an underflow occurs can be output from the TO pin.
Software trigger operation
The count starts if the count enable bit (CNTE) is "1" when the software trigger bit (TRG) is set to "1".
Figure 15.6-4 shows the software trigger operation in reload mode.
Figure 15.6-4 Count operation in reload mode (software trigger operation)
Count clock
Counter -1 0000 -1 0000 -1 0000 -1
Data load signal
UF bit
CNTE bit
TRG bit
TO pin
Reload data Reload data Reload data Reload data
494
External trigger input operation
The count starts if the count enable bit (CNTE) is "1" when the trigger input active edge (rising, falling, or
both edge) specified by the operation mode selection bits (MOD2 to 0) is input to the TI pin.
Figure 15.6-5 shows the external retrigger input operation in reload mode.
Figure 15.6-5 Count operation in reload mode (external retrigger input operation)
Gate input operation
The count starts if the count enable bit (CNTE) is "1" when the software trigger bit (TRG) is set to "1".
The count is counting while the gate input active level ("L" or "H") specified by the operation mode
selection bits (MOD2 to 0) is input to the TI pin.
Figure 15.6-6 shows the external gate input operation in reload mode.
Figure 15.6-6 Count operation in reload mode (external gate input operation)
Count clock
Counter -1 0000 -1 0000 -1 0000 -1
Data load signal
UF bit
CNTE bit
TI pin
TO pin
Reload data Reload data Reload data Reload data
-1 0000 -1Reload data
Reload data
TRG bit
-1-1 -1
Count clock
Counter
Data load signal
UF bit
CNTE bit
TI pin
TO pin
495
CHAPTER 15 16-bit Reload Timer
15.6.2 Internal Clock Mode (One Shot Mode)
The 16-bit down-counter counts down synchronized with the internal count clock, andoutputs an interrupt request to the CPU when the count underflows ("0000H" →"FFFFH"). A rectangular waveform can be output from the timer output pin to indicate
when the count is in progress.
Operation of Internal Clock Mode (One Shot Mode)If the count enable bit (CNTE) is set to "1", the value set in the 16-bit reload register is reloaded to the 16-
bit down-counter and down-counting starts when the software trigger bit (TRG) is set to "1" or the active
edge (rising, falling, or both edge) specified by the operation mode selecting bits (MOD2 to 0) is input to
the TI pin. If counting is enabled when the count enable bit (CNTE) and software trigger bit (TRG) are set
to "1" at the same time, the count is started at the same time.
If the reload selection bit (RELD) is "0", the 16-bit counter halts at "FFFFH" when the 16-bit counter
underflows ("0000H" → "FFFFH"). In this case, the underflow interrupt request flag bit (UF) is set to "1"
and, if the underflow interrupt request enable bit (INTE) is "1", an interrupt request is output.
A rectangular waveform can be output from the TO pin to indicate when the count is in progress.
Software trigger operation
The count starts if the count enable bit (CNTE) is "1" when the software trigger bit (TRG) is set to "1".
Figure 15.6-7 shows the software trigger operation in one-shot mode.
Figure 15.6-7 Count operation in one-shot mode (software trigger operation)
-1 0000 -1 0000
Reload data Reload data
FFFF FFFF
Wait for inptu start trigger
Count clock
Counter
Data load signal
UF bit
CNTE bit
TRG bit
TO pin
496
External trigger input
The count starts if the count enable bit (CNTE) is "1" when the trigger input active edge (rising, falling, or
both edge) specified by the operation mode selection bits (MOD2 to 0) is input to the TI pin.
Figure 15.6-8 shows the external trigger input operation in one-shot mode.
Figure 15.6-8 Count operation in one-shot mode (external trigger input operation)
Gate input operation
The count starts if the count enable bit (CNTE) is "1" when the software trigger bit (TRG) is set to "1".
The count starts if the trigger input enable level ("L" or "H") specified by the operation mode selection bits
(MOD2 to 0) is input to the TI pin.
Figure 15.6-9 shows the external gate input operation in one-shot mode.
Figure 15.6-9 Count operation in one-shot mode (external gate input operation)
-1 0000 -1 0000
Reload data Reload data
FFFF FFFF
Wait for inptu start trigger
Count clock
Counter
Data load signal
UF bit
CNTE bit
TI pin
TO pin
Reload data
Reload data
-1 0000 FFFF -1 -1
Wait for input start trigger
Count clock
Counter
Data load signal
UF bit
CNTE bit
TRG bit
TI pin
TO pin
497
CHAPTER 15 16-bit Reload Timer
15.6.3 Event Count Mode
The 16-bit down-counter counts down each time the active edge is detected on thepulses input to the TI pin, and an interrupt request is output to the CPU when anunderflow ("0000H" → "FFFFH") occurs. In addition, the toggle waveform or the
rectangular waveform can be output from the TO terminal.
Event Count ModeThe value of the 16-bit reload register (TMRLRH/L) is reloaded to the 16-bit counter when the software
trigger bit (TRG) is set to "1" if the count enable bit (CNTE) is "1". The counter counts each time the active
edge (rising, falling, or both edge) is detected on the pulses input to the TI pin (external count clock).
Operation of reload mode
If the reload selection bit (RELD) is "1", the value of the 16-bit reload register (TMRLRH/L) is reloaded to
the 16-bit counter and the count continues when the 16-bit counter underflows ("0000H" → "FFFFH").
The underflow interrupt request flag bit (UF) in the lower timer control status register (TMCSRL) is set to
"1" when an underflow ("0000H" -> "FFFFH") occurs in the 16-bit counter, and an interrupt request is
output if the underflow interrupt enable bit (INTE) is "1".
A toggle waveform that inverts each time an underflow occurs can be output from the TO pin. Figure 15.6-
10 shows the count operation in reload mode.
Figure 15.6-10 Count operation in reload mode (event count mode)
TI pin
Counter -1 0000 -1 0000 -1 0000 -1
Data load signal
UF bit
CNTE bit
TRG bit
TO pin
Reload data Reload data Reload data Reload data
498
Operation of One-shot mode
If the reload selection bit (RELD) is "0", the value of 16-bit counter halts at "FFFFH" when the 16-bit
counter underflows ("0000H" → "FFFFH").
The underflow request flag bit (UF) in the lower timer control status register (TMCSRL) is set to "1" and
an interrupt request is output if the underflow interrupt request enable bit (INTE) is "1".
A rectangular waveform can be output from the TO pin to indicate when the count is in progress. Figure
15.6-11 shows the count operation in one-shot mode.
Figure 15.6-11 Count operation in one-shot mode (event count mode)
TI pin
Counter -1 0000 -1 0000
Data load signal
UF bit
CNTE bit
TI pin
TO pin
Reload data Reload data
FFFF FFFF
Wait for start trigger input
499
CHAPTER 15 16-bit Reload Timer
15.7 16-Bit Reload Timer Notes on Use
This section explains precaution on using the 16 bit reload timer.
16 bit reload timer notes on use
Note on programming
• The 16-bit timer register can be read even if counting is in progress. When reading, use a word moveinstruction or read the upper byte first and the lower byte second.
• A value can be written to the 16-bit reload register even if counting is in progress. Write using a wordmove instruction or write the upper byte first and lower byte second.
Precautions on interrupts
• Operation cannot recover from interrupt processing if the underflow interrupt request flag bit (UF) in thelower timer control status register (TMCSRL) is set to "1" and the underflow interrupt request enable bit(INTE) is "1". Always clear the underflow interrupt request flag bit (UF) to "0".
500
15.8 Program Example of 16-Bit Reload Timer
This section shows the program example of 16-bit reload timer.
501
CHAPTER 15 16-bit Reload Timer
502
CHAPTER 16External Interrupt Circuit
This chapter explains the function and the operation of external interrupt circuit.
16.1 Overview of External Interrupt Circuit
16.2 Block Diagram of the External Interrupt Circuit
16.3 External Interrupt Circuit Channels
16.4 Register for External Interrupt Circuit
16.5 Interrupt of External Interrupt Circuit
16.6 Operation of External Interrupt Circuit
16.7 Notes of Using External Interrupt Circuit
16.8 Sample Program for External Interrupt Circuit
503
CHAPTER 16 External Interrupt Circuit
16.1 Overview of External Interrupt Circuit
The external interrupt circuit detects edges on the signal input to the external interrupt circuit pin and generates interrupt requests to the CPU.
Functions of External Interrupt CircuitThe external interrupt circuit functions to detect an optionally selected edge or edges of a signal input to
any of the external interrupt pins and then generates and issues an interrupt request to the CPU. These
interrupts can be used to recover from standby modes and return to normal operation.
504
16.2 Block Diagram of the External Interrupt Circuit
The external interrupt circuit consists of the following two blocks.• Edge detection circuit• External interrupt control register
Block Diagram of the External Interrupt CircuitFigure 16.2-1 shows the block diagram of the external interrupt circuit.
Figure 16.2-1 Block diagram of the external interrupt circuit
Edge detection circuit
If the polarity of the edge detected on a signal input to an external interrupt circuit pin (INT) is the same as
the polarity of the edge selected in the interrupt control register (EIC), the corresponding external interrupt
request flag bit (EIR) is set to "1".
External interrupt control register (EIC)
This register is used to select the active edge, enable or disable interrupt requests, check for interrupt
requests, etc.
EIR1 SL11 SL10 EIE1 EIR0 SL01 SL00 EIE0
INT0 Pin
INT1 Pin
10 01 11
Selector
10 01 11
Selector
Interrupt request 0
Interrupt request 1
Internal data bus
External interruptcontrol register (EIC)
Edge detection circuit 1 Edge detection circuit 0
505
CHAPTER 16 External Interrupt Circuit
16.3 External Interrupt Circuit Channels
This section describes the external interrupt circuit channels.
External Interrupt Circuit ChannelsThis series has eight external interrupt circuits.
Table 16.3-1 and Table 16.3-2 show the correspondence among the channel, the pin, and register.
Note:
As the external interrupts share pins with the I/O ports, set the corresponding bit in the port directionregister (DDR) to "0" (input) when using a pin as an external interrupt input.
Table 16.3-1 Pins of external interrupt circuit
Channel Pin Name Pin Function
0INT00
External interrupt input
INT01
1INT02
INT03
2INT04
INT05
3INT06
INT07
4INT10
INT11
5INT12
INT13
6INT14
INT15
7INT16
INT17
Table 16.3-2 Register for external interrupt circuit
Channel Register Name Corresponding Register (Notation in Specifications)
0 EIC00
EIC: External interrupt control register
1 EIC10
2 EIC20
3 EIC30
4 EIC01
5 EIC11
6 EIC21
7 EIC31
506
16.4 Register for External Interrupt Circuit
This section describes register for external interrupt circuit.
Register for External Interrupt CircuitFigure 16.4-1 shows the register for external interrupt circuit.
Figure 16.4-1 Register for external interrupt circuit
EIR1 SL11 SL10 EIE1 EIR0 SL01 SL00 EIE0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
External interrupt control register EIC
507
CHAPTER 16 External Interrupt Circuit
16.4.1 External Interrupt Control Register (EIC)
The external interrupt control register (EIC) is used to select the edge polarity for the external interrupt input and for interrupt control.
External interrupt control register (EIC)
Figure 16.4-2 External interrupt control registers (EIC)
0
0
EIR1 SL11 SL10 EIE1 EIR0 SL01 SL00 EIE0 00000000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
R(RM1),W R/W R/W R/W R/W R/W R/W
Interrupt request enabled bit 0Interrupt request output disabled.Interrupt request output enabled.
EIE001
Edge polarity selection bit 0No edge detection
SL010
Rising edge0
Both edges
External interrupt request flag bit 0at reading at writing
Not input specified edge
EIR0
Clear this bit0Input specified edge1 There is no change.
There is no influence on another.
Falling edge1011
1
SL00
Interrupt request enabled bit 1Interrupt request output disabledInterrupt request output enabled
EIE101
Edge polarity selection bit 1No edge detection
SL110
Rising edge0
Both edges
External interrupt request flag bit 1at reading at writing
Not input specified edge
EIR1
Clear this bit0Input specified edge1 There is no change.
There is no influence on another.
Falling edge1011
1
SL10
R(RM1),W
R/W :R(RM1),W :
:
Read, write enabled (The value of read is the value of write.)Read, write enabled (Differ between read value and write value. Read "1" at read modify write instruction.Initial value
508
Table 16.4-1 Explanation of external interrupt control register (EIC) bits
Bit name Functions
Bit7EIR1: External interrupt request flag bit 1
• When the edge selected by edge polarity selection bits (SL11, SL10) is input to the external interrupt pin INT1, this bit is set to "1".
• When this bit and the interruption request enable bit 1 (EIE1) are set to "1", an interruption request is output.
• Writing "0" clears the bit. Writing "1" has no effect and does not change.• The bit becomes 1 when reading a read modify write instruction.
Bit6Bit5
SL11, SL10: Edge polarity selection bit 1
• These bits are used to select the polarity of the interrupt triggering edge of the pulse input to the external interrupt pin INT1.
• Edge detection is not performed and no interrupt request is generated when these bits are "00B".
• Rising edges are detected when these bits are "01B", falling edges when "10B", and both edges when
"11B".
Bit4EIE1: Interrupt request enable bit 1
• This bit is used to allow and prohibit interrupt request output to the CPU. An interrupt request is output when this bit and external interrupt request flag bit 1 (EIR1) are "1".
Reference:• When using an external interrupt pin, write "0" to the corresponding bit in the port direction register
(DDR) and set the pin as an input.• Regardless of the interrupt request enable bit state, the state of the external interrupt pin can be read
directly from the port data register.
Bit3EIR0: External interrupt request flag bit 0
• When an edge selected by edge polarity selection bits (SL01, SL00) is input to the external interrupt pin INT0, this bit is set to 1.
• When this bit and the interruption request enable bit 0(EIE0) are set to "1", an interruption request is output.
• Writing "0" clears the bit. Writing "1" has no effect and does not change.• The bit returns 1 when reading a read modify write instruction.
Bit2Bit1
SL01, SL00: Edge polarity selection bit 0
• These bits are used to select the polarity of the interrupt triggering edge of the pulse input to the external interrupt pin INT0.
• Edge detection is not performed and no interrupt request is generated when these bits are "00B".
• Rising edges are detected when these bits are "01B", falling edges when "10B", and both edges when
"11B".
Bit0EIE0: Interrupt request enable bit 0
• This bit is used to allow and prohibit interrupt request output to the CPU. An interrupt request is output when this bit and external interrupt request flag bit 0 (EIR0) are "1".
Reference:• When using an external interrupt pin, write "0" to the corresponding bit in the port direction register and
set the pin as an input.• Regardless of the interrupt request enable bit state, the state of the external interrupt pin can be read
directly from the port data register.
509
CHAPTER 16 External Interrupt Circuit
16.5 Interrupt of External Interrupt Circuit
This section describes the detection for the specified edge or edges of signal input to any of the external interrupt pin as the interrupt trigger of the external interrupt circuit.
Interrupt During the Operation of External Interrupt CircuitWhen external interrupt circuit detects the specified edge or edges of external interrupt input at a pin, an
external interrupt request flag bit (EIC: EIR0, EIR1) corresponding to the pin is set to 1. At this time, if the
interrupt request enable bit corresponding to the pin contains the value indicating the enabled state (EIC:
EIE0, EIE1=1), the external interrupt circuit issues the appropriate interrupt request to CPU.
Writing "0" to the corresponding external interrupt request flag bit clears the interrupt request.
Always set the interrupt enable bit to "0" when not using an external interrupt to recover from stop mode.
Set the interrupt request enable bit (EIE) to "0" when setting the edge polarity selection bit (SL) to avoid
inadvertently setting the interrupt flag. Also, always clear the interrupt request flag bit (EIR) to "0" after
changing the edge polarity.
See "29.2 Interrupt Cause Table" for interrupt request numbers.
510
16.6 Operation of External Interrupt Circuit
The section describes the operation of external interrupt circuit.
Operation of External Interrupt CircuitWhen the polarity of an edge or edges of a signal input from one of the external interrupt pins (INT0, 1)
matches the selected edge polarity (EIC: SL00 to SL01) for the pin stored in the appropriate external
interrupt control register, one of the external interrupt request flag bits (EIC: EIR0, EIR1) corresponding to
the pin is set to 1.
Figure 16.6-1 shows the operation for setting the INT0 pin to the external interrupt input.
Figure 16.6-1 Operation of external interrupt
Input waveform to INT0 pin
IRQ
Rising edge Falling edge Both edges
Clear the interrupt request flag bit by program
EIR0 bit
EIE0 bit
SL01 bit
SL00 bit
No edge detection
Clearby program
511
CHAPTER 16 External Interrupt Circuit
16.7 Notes of Using External Interrupt Circuit
This section describes points to note when using the external interrupt circuit.
Notes of Using External Interrupt Circuit• Always clear the interrupt request enable bit (EIE) to "0" when setting the edge polarity selection bit
(SL).
Also, always clear the external interrupt request flag bit (EIR) to "0" after setting the edge polarity.
• Operation cannot return from interrupt processing if the external interrupt request flag bit is "1" and theinterrupt request enable bit is enabled. Always clear the external interrupt request flag bit in the interrupthandler routine.
512
16.8 Sample Program for External Interrupt Circuit
An example of programming external interrupt circuit is given below.
Sample Program for External Interrupt Circuit
513
CHAPTER 16 External Interrupt Circuit
514
CHAPTER 17Interrupt Pin Selecting
Circuit
This chapter describes the functions and operation of the interrupt pin selection circuit.
17.1 Overview of Interrupt Pin Selecting Circuit
17.2 Block Diagram of Interrupt Pin Selecting Circuit
17.3 Pin Description of Interrupt Pin Selecting Circuit
17.4 Register for Interrupt Pin Selecting Circuit
17.5 Operation of Interrupt Pin Selecting Circuit
17.6 Note on Using Interrupt Pin Selecting Circuit
515
CHAPTER 17 Interrupt Pin Selecting Circuit
17.1 Overview of Interrupt Pin Selecting Circuit
The interrupt pin selecting circuit selects which pins to use as interrupt inputs from amongst various resource input pins.
Interrupt Pin Selecting CircuitThis circuit is used to select the interrupt input pins from amongst various resource inputs (TRG0/ADTG,
UCK0, UI0, EC0, SCK, SI, and INT00). The input signals from each resource input are selected by this
circuit to be used as the INT0 (channel 0) of external interrupt input. This enables the input signals to the
resource input pins to also function as external interrupt pins.
516
17.2 Block Diagram of Interrupt Pin Selecting Circuit
Figure 17.2-1 shows a block diagram of the interrupt pin selecting circuit.
Block Diagram of Interrupt Pin Selecting Circuit
Figure 17.2-1 Block diagram of interrupt pin selection circuit
• WICR register (interrupt pin control register)
This register selects which of the inputs from the resource input pins is output to the interrupt circuit asthe interrupt pin.
• Selection circuit
This circuit outputs the input from the pin selected by the WICR register to the INT0 input of theexternal interrupt circuit (channel 0).
INT01
INT00
SI
SCK
EC0
UI0
UCK0
TRG0/ADTG
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
Selection circuit
Interrupt pin selection circuit
WICR register
Externalinterruptcircuit
INT1
INT0
(Channel 0)
Inte
rna
l da
ta b
us
517
CHAPTER 17 Interrupt Pin Selecting Circuit
17.3 Pin Description of Interrupt Pin Selecting Circuit
This section explains the pin of the interrupt pin selecting circuit.
Pin Related to Interrupt Pin Selecting CircuitThe resource pins managed by the interrupt pin selection circuit are the TRG0/ADTG, UCK0, UI0, EC0,
SCK, SI, and INT00 pins. These inputs (except INT00) are also connected to their respective resources in
parallel and can be used for both functions simultaneously. Table 17.3-1 lists the relationship between the
resources and resource input pins.
Table 17.3-1 Relation between Resource and Resource Input Pin
Resource input pin name Resource name
INT00 Interrupt pin selecting circuit
TRG0/ ADTGInterrupt pin selecting circuit16-bit PPG timer (trigger input) A/D converter (trigger input)
UCK0Interrupt pin selecting circuitUART/SIO (clock I/O)
UI0Interrupt pin selecting circuitUART/SIO (data input)
EC0Interrupt pin selecting circuit8/16-bit multi-function timer (event input)
SCKInterrupt pin selecting circuitLIN UART (clock I/O)
SIInterrupt pin selecting circuitLIN UART (data input)
518
17.4 Register for Interrupt Pin Selecting Circuit
Figure 17.4-1 shows the register for the interrupt pin selecting circuit.
Register for Interrupt Pin Selecting Circuit
Figure 17.4-1 Register for Interrupt Pin Selecting Circuit
WICR (interrupt pin control register)
-
Initial value 01000000B
R0/WX R/W R/WR/WR/WR/WR/WR/WTRG0UCK0UI0EC0SCKSIINT00
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
519
CHAPTER 17 Interrupt Pin Selecting Circuit
17.4.1 Interrupt Pin Control Register (WICR)
This register selects which of the inputs from the resource input pins is output to the interrupt circuit as the interrupt pin.
Interrupt Pin Control Data Register (WICR)
Figure 17.4-2 Interrupt Pin Control Register (WICR)
-
Initial value
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Read/ write enabled
: Initial value
WICR (Interrupt pin control register)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
R0/WX R/W R/W R/W R/W R/W R/W R/W01000000BTRG0UCK0UI0EC0SCKSIINT00
TRG0 interrupt pin selection bit
No selecting TRG0 as the interrupt input pinSelecting TRG0 as the interrupt input pin
UCK0 interrupt pin selection bitNo selecting UCK0 as the interrupt input pinSelecting UCK0 as the interrupt input pin
UI0 interrupt pin selection bitNo selecting UI0 as the interrupt input pinSelecting UI0 as the interrupt input pin
EC0 interrupt pin selection bitNo selecting EC0 as the interrupt input pinSelecting EC0 as the interrupt input pin
SCK interrupt pin selection bitNo selecting SCK as the interrupt input pinSelecting SCK as the interrupt input pin
SI interrupt pin selection bitNo selecting SI as the interrupt input pinSelecting SI as the interrupt input pin
INT00 interrupt pin selection bitNo selecting INT00 as the interrupt input pinSelecting INT00 as the interrupt input pin
TRG0
UCK0
UI0
EC0
SCK
SI
INT00
Undefined bit (read value = 0, No effect on writing operation)
R/W:
R0/WX:
520
Table 17.4-1 Functional Description of Each Bit in Interrupt Pin Control Register (WICR)
Bit name Functions
Bit7 Unused bit• Read value is always "0".• Writing has no effect on the operation.
Bit6INT00: INT00 interrupt pin selection bit
• This bit specifies whether the INT00 pin functions as an interrupt input pin.• Writing "0" to this bit deselects the INT00 pin as an interrupt input pin and the circuit treats the INT00
pin input as being fixed at "0".• Writing "1" to this bit selects the INT00 pin as an interrupt input pin and the circuit passes the INT00
pin input to INT0 (channel 0) of the external interrupt circuit. In this case, the input signal to the INT00 pin can trigger an external interrupt if INT0 (channel 0) operation is enabled in the external interrupt circuit.
Bit5SI: SI interrupt pin selection bit
• This bit specifies whether the SI pin functions as an interrupt input pin.• Writing "0" to this bit deselects the SI pin as an interrupt input pin and the circuit treats the SI pin
input as being fixed at "0".• Writing "1" to this bit selects the SI pin as an interrupt input pin and the circuit passes the SI pin input
to INT0 (channel 0) of the external interrupt circuit. In this case, the input signal to the SI pin can trigger an external interrupt if INT0 (channel 0) operation is enabled in the external interrupt circuit.
Bit4SCK: SCK interrupt pin selection bit
• This bit specifies whether the SCK pin functions as an interrupt input pin.• Writing "0" to this bit deselects the SCK pin as an interrupt input pin and the circuit treats the SCK pin
input as being fixed at "0".• Writing "1" to this bit selects the SCK pin as an interrupt input pin and the circuit passes the SCK pin
input to INT0 (channel 0) of the external interrupt circuit. In this case, the input signal to the SCK pin can trigger an external interrupt if INT0 (channel 0) operation is enabled in the external interrupt circuit.
Bit3EC0: EC0 interrupt pin selection bit
• This bit specifies whether the EC0 pin functions as an interrupt input pin.• Writing "0" to this bit deselects the EC0 pin as an interrupt input pin and the circuit treats the EC0 pin
input as being fixed at "0".• Writing "1" to this bit selects the EC0 pin as an interrupt input pin and the circuit passes the EC0 pin
input to INT0 (channel 0) of the external interrupt circuit. In this case, the input signal to the EC0 pin can trigger an external interrupt if INT0 (channel 0) operation is enabled in the external interrupt circuit.
Bit2UI0: UI0 interrupt pin selection bit
• This bit specifies whether the UI0 pin functions as an interrupt input pin.• Writing "0" to this bit deselects the UI0 pin as an interrupt input pin and the circuit treats the UI0 pin
input as being fixed at "0".• Writing "1" to this bit selects the UI0 pin as an interrupt input pin and the circuit passes the UI0 pin
input to INT0 (channel 0) of the external interrupt circuit. In this case, the input signal to the UI0 pin can trigger an external interrupt if INT0 (channel 0) operation is enabled in the external interrupt circuit.
Bit1UCK0: UCK0 interrupt pin selection bit
• This bit specifies whether the UCK0 pin functions as an interrupt input pin.• Writing "0" to this bit deselects the UCK0 pin as an interrupt input pin and the circuit treats the UCK0
pin input as being fixed at "0".• Writing "1" to this bit selects the UCK0 pin as an interrupt input pin and the circuit passes the UCK0
pin input to INT0 (channel 0) of the external interrupt circuit. In this case, the input signal to the UCK0 pin can trigger an external interrupt if INT0 (channel 0) operation is enabled in the external interrupt circuit.
Bit0TRG0: TRG0 interrupt pin selection bit
• This bit specifies whether the TRG0 pin functions as an interrupt input pin.• Writing "0" to this bit deselects the TRG0 pin as an interrupt input pin and the circuit treats the TRG0
pin input as being fixed at "0".• Writing "1" to this bit selects the TRG0 pin as an interrupt input pin and the circuit passes the TRG0
pin input to INT0 (channel 0) of the external interrupt circuit. In this case, the input signal to the TRG0 pin can trigger an external interrupt if INT0 (channel 0) operation is enabled in the external interrupt circuit.
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CHAPTER 17 Interrupt Pin Selecting Circuit
Reference:
If these bits are "1" and the INT0 (channel 0) of the external interrupt circuit is enabled when theMCU goes to standby mode, the MCU wakes up from standby mode if a pulse with the specifiededge is input to a selected pin for which input has been enabled.See "3.7 Standby Modes (Low Power Consumption Mode)" for details of the standby modes.
note:
The input signals to the resource pins do not generate an external interrupt even when "1" is written tothese bits if the INT0 (channel 0) of the external interrupt circuit is disabled.
note:
Do not modify the values of these bits while the INT0 (channel 0) of the external interrupt circuit isenabled. If modified, the external interrupt circuit may detect an active edge, depending on the pininput level. This is because, as the circuit treats the input to the pin as being "0" when these bits are"0", the internal circuit will detect the input level as having changed if the input level at the externalpin is "H".
522
17.5 Operation of Interrupt Pin Selecting Circuit
The WICR (interrupt pin control register) setting selects the interrupt pins.
Operation of Interrupt Pin Selecting CircuitThe WICR (interrupt pin control register) setting selects the input pins to input to INT0 of the external
interrupt circuit (channel 0). The explanation below describes the procedure for setting up the interrupt pin
selection circuit and external interrupt circuit (channel 0) to select the TRG0 pin as an interrupt pin.
1) Write "0" to the corresponding bit in the port direction register (DDR) to set the pin as an input.
2) Select the TRG0 pin as an interrupt input pin in WICR (interrupt pin control register). (Write "01H" to
the WICR register. At this time, the operation of the external interrupt circuit is disabled.)
3) Enable INT0 of the external interrupt circuit (channel 0). (Set the SL01 and SL00 bits of the EIC00
register in the external interrupt circuit to other than "00B" to select the active edge, and write "1" to the
EIE0 bit to enable the interrupt.)
4) The subsequent interrupt operation is the same as for the external interrupt circuit.
523
CHAPTER 17 Interrupt Pin Selecting Circuit
17.6 Note on Using Interrupt Pin Selecting Circuit
This section describes points to note when using the interrupt pin selection circuit.
• WICR (interrupt pin control register) is initialized to "40H" after a reset. This selects the INT00 bit onlyas an interrupt pin. If using pins other than the INT00 pin as external interrupt pins, update the value ofthis register before enabling the operation of the external interrupt circuit.
• If multiple interrupt pins are selected in WICR (interrupt pin control register) simultaneously, an input tothe INT0 (channel 0) of the external interrupt circuit is treated as "H" if any of the selected input signalsis "H". (The signals input from the selected pins are "OR".)
• If multiple interrupt pins are selected in WICR (interrupt pin control register) simultaneously and INT0(channel 0) of the external interrupt circuit is enabled, the selected pins will continue to be enabled forreceiving interrupts in standby mode also.
524
CHAPTER 18UART/SIO
This chapter explains the function and operation of the UART/SIO.
18.1 Overview of UART/SIO
18.2 Configuration of UART/SIO
18.3 UART/SIO Channel
18.4 UART/SIO Pin
18.5 Register of UART/SIO
18.6 UART/SIO Interrupt
18.7 Explanation of Operation Mode 0
18.8 Explanation of Operation Mode 1
525
CHAPTER 18 UART/SIO
18.1 Overview of UART/SIO
The UART/SIO is a general-purpose serial data communications interface. Serial transfers of variable-length data can be made with a synchronous or asynchronous clock. The transfer format is NRZ. The transfer rate can be set with the dedicated baud rate generator or external clock (in clock synchronous mode).
Functions of UART/SIOThe UART/SIO is capable of serial data transmission/reception (serial input/output) to/from another CPU
or peripheral device.
• Equipped with a full-duplex double buffer that allows 2-way full-duplex communication.
• The synchronous or asynchronous transfer mode can be selected.
• The optimum baud rate can be selected with the dedicated baud rate generator.
• The data length is variable; it can be set to 5 to 8 bits when no parity is used or to 6 to 9 bits when parityis used. (See Table 18.1-1 .)
• The data transfer format is NRZ (Non-Return-to-Zero).
• Two operation modes (0 and 1) are available.Operation mode 0 operates in the asynchronous clock mode (UART).Operation mode 1 operates in clock synchronous mode (SIO).
Table 18.1-1 UART/SIO Operation Modes
Operating ModeData Length
Synchronization Mode Length of Stop BitNo Parity With Parity
0
5 6
Asynchronous 1 bit or 2 bits6 7
7 8
8 9
1
5 -
Synchronous -6 -
7 -
8 -
526
18.2 Configuration of UART/SIO
The UART/SIO consists of the following five blocks.• Serial mode control register 1 (SMC1)• Serial mode control register 2 (SMC2)• Serial status register (SSR)• Serial input data register (RDR)• Serial output data register (TDR)
UART/SIO Block Diagram
Figure 18.2-1 UART/SIO Block Diagram
Dedicated baud rate generator (BRCLK)
1/4 Clock selector
External serial clock input(SCKI)
Serial data input(SI)
Start bit
detection
Reception bit
count
Parity Operation
Shift register
for reception
Serial input data register
Serial status
register
Serial mode control register
1,2
Serial output data
register
Shift register
for trans-
missionTrans- mission bit count
Parity operation
Serial data output(SO)
Serial clock output(SCKO)
Port control(TXOE, SCKE)
Set to each block
Inte
rnal
bus
Reception state decision sircuit
PER
OVE
FER
RDRF
Trans- mission state decision circuit
TDRE
RIE
TEIE
RXIRQ
TXIRQ
State from each block
State from each block
TCPL
TCIE
Data sample clock input(DSCLK)
527
CHAPTER 18 UART/SIO
Serial mode control register 1 (SMC1)
Used for UART/SIO operation mode control. The register is used to set the serial data direction (endian),
parity and its polarity, stop bit length, operation mode (synchronous/asynchronous), data length, and serial
clock.
Serial mode control register 2 (SMC2)
Used for UART/SIO operation mode control. The register is used to enable/disable serial clock output,
serial data output, transmission/reception, and interrupts and to clear the reception error flag.
Serial status register (SSR)
Indicates the UART/SIO transmission/reception and error statuses.
Serial input data register (RDR)
The register retains the receive data. The serial input is converted and then stored in this register.
Serial output data register (TDR)
The register sets the transmit data. Data written to this register is serial-converted and then output.
528
18.3 UART/SIO Channel
This section describes the UART/SIO channels.
UART/SIO ChannelThe following tables list the channels and associated pins and registers.
Table 18.3-1 UART/SIO Pins
Channel Pin Name Pin Function
0
UCK0 Clock I/O
UO0 Data output
UI0 Data input
1
UCK1 Clock I/O
UO1 Data output
UI1 Data input
Table 18.3-2 Register of UART/SIO
Channel Register Name Register Association (Designation in Specifications)
0
SMC10 Serial Mode Control Register 1 (SMC1)
SMC20 Serial Mode Control Register 2 (SMC2)
SSR0 SSR: Serial Status Register
TDR0 TDR: Serial output data register
RDR0 RDR: Serial input data register
1
SMC11 Serial Mode Control Register 1 (SMC1)
SMC21 Serial Mode Control Register 2 (SMC2)
SSR1 SSR: Serial Status Register
TDR1 TDR: Serial output data register
RDR1 RDR: Serial input data register
529
CHAPTER 18 UART/SIO
18.4 UART/SIO Pin
This section describes the pins related to the UART/SIO.
Pin Related to UART/SIOThe pins associated with UART/SIO are the clock input and output pin (UCK), serial data output pin (UO)
and serial data input pin (UI). These are switched by the output enable bits (SMC2:SCKE,TXOE).
UCK:
Clock input/output pin at UART/SIO. When the clock output is enabled (SMC2:SCKE=1), it serves as aUART/SIO clock output pin (UCK) regardless of the value of the corresponding port direction register.At this time, do not select the external clock (set SMC1:CKS = 0). When it is to be used as a UART/SIOclock input pin, disable the clock output (SMC2:SCKE=0) and make sure that it is set as input port bycorresponding port direction register. At this time, be sure to select the external clock (set SMC1:CKS =0).
UO:
Serial data output pin for UART/SIO. When the serial data output is enabled (SMC2:TXOE=1), it servesas a UART/SIO serial data output pin (UO) regardless of the value of the corresponding port directionregister.
UI:
Serial data input pin for UART/SIO. When it is to be used as a UART/SIO serial data input pin, makesure that it is set as input port by corresponding port direction register.
530
18.5 Register of UART/SIO
The UART/SIO related registers are: serial mode control register 1 (SMC1), serial mode control register 2 (SMC2), serial status register (SSR), serial output data register (TDR), and serial input data register (RDR).
Register Related to UART/SIO
Figure 18.5-1 Register Related to UART/SIO
BDS PEN TDP SBL CBL0 MD
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00000000B
Serial mode control register 1(SMC1)
SCKE TXOE RERC RXE TXE RIE TEIE
R/W R/W R1/W R/W R/W R/W R/W R/W
Initial value
W0 : Be sure to write "0" at writing.
- - PER OVE FER RDRF TDRE
R0/WX R0/WX R/WX R/WX R/WX R/WX R/W0 R/WX
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0
R/W R/W R/W R/W R/W R/W R/W R/W
CKS
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
R/WX R/WX R/WX R/WX R/WX R/WX R/WX R/WX
CBL1
TCIE
TCPL
Initial value
00100000B
00000001B
Initial value
Initial value
00000000B
Initial value
00000000B
Serial mode control register 2(SMC2)
Serial status register (SSR)
Serial output data register (TDR)
Serial input data register (RDR)
R0 : Be sure to read "0" at reading.R1 : Be sure to read "1" at reading.
WX : Writing has no effect on the operation.R/W: Read and write enabled.
531
CHAPTER 18 UART/SIO
18.5.1 Serial Mode Control Register 1 (SMC1)
Serial mode control register 1 (SMC1) controls the UART/SIO operation mode. The register is used to set the serial data direction (endian), parity and its polarity, stop bit length, operation mode (synchronous/asynchronous), data length, and serial clock.
Serial Mode Control Register 1 (SMC1)
Figure 18.5-2 Serial Mode Control Register 1 (SMC1)
5 bits
6 bits
7 bits
8 bits
BDS
0
1
Transmit/receive from LSB side sequentially
Transmit/receive from MSB side sequentially
Serial data direction control bit
SBL
0
1
1-bit length
2-bit length
Stop bit length control bit
PEN
0
1
No parity
parity
Parity control bit
R/W : Read and write enabled : Initial value
BDS TDP SBL
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00000000B
Initial value
R/W
PEN CBL1 CKS MDCBL0
R/W R/W R/W R/W R/WR/WR/W
CBL10
0
1
1
Character bit length control bitCBL00
1
0
1
TDP
0
1
Even parity
Odd parity
parity polarity bit
CKS
0
1
Dedicated baud rate generator
External clock(cannot use in clock asynchronous mode)
Clock control bit
MD
0
1
Clock asynchronous mode(UART)
Clock synchronous mode (SIO)
Operation mode control bit
532
Note:
• Do not update a control bit to belong to serial mode control register 1 (SMC1) during transmissionor reception.
• Before updating a control bit to belong to serial mode control register 1(SMC1), set both of TXEand RXE to "disable" ("0").
Table 18.5-1 Functions for Individual Bits of Serial Mode Control Register 1 (SMC1)
Bit Name Function
Bit7BDS:Serial data direction control
This bit sets the serial data direction (endian).• When set to "0", the bit specifies transmission or reception to be performed sequentially starting from
the LSB in the serial data register.• When set to "1", the bit specifies transmission or reception to be performed sequentially starting from
the MSB in the serial data register.
Bit6PEN:Parity control
This bit enables or disables parity in clock asynchronous mode.• No Parity when set to "0".• With Parity when set to "1".
Bit5TDP:Parity polarity
This bit controls odd/even parity.• Specifies even parity when set to "0". • Specifies odd parity when set to "1".
Bit4SBL:Length of stop bit control
This bit controls the stop bit length in clock asynchronous mode.• Specifies a stop bit length of 1 when set to "0".• Specifies a stop bit length of 2 when set to "1".
Bit3,2CBL1,0:Character bit length control
These bits select the character bit length as follows:
CBL1 CBL0 Character bit length
0 0 5
0 1 6
1 0 7
1 1 8
• This setting is valid commonly in both of asynchronous and synchronous modes.
Bit1CKS:Clock selection
This bit selects the external clock or dedicated baud rate generator.• Selects the dedicated baud rate generator when set to "0".• Selects the external clock when set to "1".Note:Setting this bit to "1" forcibly disables the output of the SCK port. The external clock cannot be used in clock asynchronous mode (UART).
Bit0MD:Operation mode selection
This bit selects clock asynchronous mode (UART) or clock synchronous mode (SIO).• Selects clock asynchronous mode (UART) when set to "0".• Selects clock synchronous mode (SIO) when set to "1".
533
CHAPTER 18 UART/SIO
18.5.2 Serial Mode Control Register 2 (SMC2)
Serial mode control register 2 (SMC2) controls the UART/SIO operation mode. The register is used to enable/disable serial clock output, serial data output, transmission/reception, and interrupts and to clear the reception error flag.
Serial Mode Control Register 2 (SMC2)
Figure 18.5-3 Serial Mode Control Register 2 (SMC2)
TXOE
0
1
Disable serial data output(usable as port)
Enable sirial data output
Serial data output enable bit
R/W : Read and write enabledR1 : "1" is always read at reading : Initial value
RIE
0
1
Disable reception interrupt
Enable reception interrupt
Reception interrupt enable bit
RERC
0
1
Each error flag is cleared
No change and no effect on others
Reception error flag clear bit
RXE
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00100000B
Initial value
TXE TCIE TEIERIE
R/WR/W
SCKE TOEX RERC
R/WR/WR/WR1/WR/WR/W
TEIE
0
1
Disable transmission data register empty interrupt
Enable transmission data register empty interrupt
Transmission data register empty interrupt enable bit
TCIE
0
1
Disable transmisson completion interrupt
Enable transmisson completion interrupt
Trensmisson completion interrupt enable bit
TXE
0
1
Disable transmission operation
Enable transmission operation
Transmission operation enable bit
RXE
0
1
Disaable reception operation
Enable reception operation
Reception operation enable bit
SCKE
0
1
Disable serial clock output(usable as port)
Enable serial clock output
Serial clock output enable bit
534
Table 18.5-2 Functions of Individual Bits of Serial Mode Control Register 2 (SMC2)
Bit Name Function
Bit7SCKE:Serial clock output enable bit
This bit controls the input/output of the serial clock (UCK pin) in clock synchronous mode.• Allows the pin to be used as a general-purpose port when set to "0".• Enables the pin for serial clock output when set to "1".Note:When the CKS bit contains "1", the internal clock signal is not outputted even with this bit set to "1".If this bit is set to "1" with SCM1:MD set to 0 (asynchronous mode), the output from the port is always "H".
Bit6TXOE:Serial-data output enable bit
This bit controls the output of the serial data (UO pin).• Allows the pin to be used as a general-purpose port when set to "0".• Enables the pin for serial data output when set to "1".
Bit5RERC:Receive error flag clear bit
This bit clears the reception error flag.• Entering "0" for this bit clears the SSR register error flag (PER, OVE, FER).• The bit always returns "1" when read.
Bit4RXE:Reception operation enable bit
This bit enables the reception of the serial data.• If this bit is set to "0" during reception, the reception is immediately disabled and initialization is
performed. The data received so far is not transferred to the serial input data register.
Bit3TXE:Transmit operation enable bit
This bit enables the transmission of the serial data.• If this bit is set to "0" during transmission, the transmission is immediately disabled and
initialization is performed. The transmission completion flag (TCPL) is set to "1" and the transmit data register empty (TDRE) bit is set to "1" as well.
Bit2RIE:Receive interrupt enable bit
Reception interrupt is enabled.• A reception interrupt occurs the moment either the receive data register full (RDRF) bit or an error
flag (PER, OVE, FER, or RDRF) is set to "1" when this bit contains "1" (enable).
Bit1TCIE:Interrupt enable bits of transmission completion
This bit enables interrupts by the transmission completion flag.• A transmission interrupt occurs the moment the transmission completion flag (TCPL) bit is set to "1"
when this bit contains "1" (enable).
Bit0
TEIE:Transmission data register empty interrupt enable bit
This bit enables interrupts by the transmit data register empty.• A transmission interrupt occurs the moment the transmit data register empty (TDRE) bit is set to "1"
when this bit contains "1" (enable).
535
CHAPTER 18 UART/SIO
18.5.3 Serial Status Register (SSR)
The serial status register (SSR) indicates a transmission/reception or error status of the UART/SIO.
Serial Status and Data Register (SSR)
Figure 18.5-4 Serial Status and Data Register (SSR)
R/W : Read and write enabledR0 : "0" is always read at readingW0 : "0" is always writen at writingWX : Writing has no effect on the operation : Initial value
- - PER OVE FER RDRF TCPL
R/WXR/WX
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00000001B
Initial value
R/WXR/WX R/W0
OVE
0
1
No overran error
Overran error
Overran error flag
FER
0
1
No framing error
Framing error
Framing error flag
TCPL
0
1
Cleaaar by writing "0"
Complete serial transmission
Transmission completion flag
PER
0
1
No parity error
Parity error flag
Parity error flag
RDRF
0
1
Empty
Receive data present
Reception data register full
TDRE
0
1
Transmission data present
Empty
Transmission data register empty
R/WX
TDRE
R0/WXR0/WX
536
Table 18.5-3 Functions of Bits in Serial Status and Data Register (SSR)
Bit Name Function
Bit7, 6 Unused• The read value of this bit is always 0.• Writing to this bit has no effect on operation.
Bit5PER:PE: Parity error flag
Detect an parity error in receiving.• The bit is set when a parity error occurs during reception. Writing "0" to the RERC bit clears this
flag.• If error detection and clearing by RERC occur at the same time, the error flag is set preferentially.
Bit4OVE:Overrun error flag
This bit detects a receive data overrun error.• The bit is set when an overrun error occurs during reception. Writing "0" to the RERC bit clears this
flag.• If error detection and clearing by RERC occur at the same time, the error flag is set preferentially.
Bit3FER:Framing error flag
Detect a framing error in receive data.• The bit is set when a framing error occurs during reception. Writing "0" to the RERC bit clears this
flag.• If error detection and clearing by RERC occur at the same time, the error flag is set preferentially.
Bit2RDRF:Reception data register full
This flag indicates the status of the serial input data register.• The bit is set to "1" when received data is loaded to the serial input data register.• The bit is cleared to "0" when data is read from the serial input data register.
Bit1TCPL:Transmission completion flag
This bit is the flag indicating the data transmission status.• The bit is set to "1" upon completion of serial transmission. Note, however, that the bit is not set to
"1" even upon completion of transmission when the serial output data register contains data to be transmitted in succession.
• Writing "0" to this bit clears its flag.• If events to set and clear the flag occur at the same time, it is set preferentially.• Operation is not influenced when 1 is written to this bit.
Bit0TDRE:Transmission data register empty
This flag indicates the status of the serial output data register.• The bit is set to "0" when transmit data is written to the serial output register.• The bit is set to "1" upon transmission is started with the transmission shift register loaded.
537
CHAPTER 18 UART/SIO
18.5.4 Serial Input Data Register (RDR)
The serial input data register (RDR) is used to input (receive) serial data.
Serial Input Data Register (RDR)Figure 18.5-5 shows the bit structure of the serial input data register.
Figure 18.5-5 Serial Input Data Register (RDR)
This register stores received data. The serial data signals sent to the serial data input pin (UI pin) is
converted by the shift register and stored in this register.
When received data is set correctly in this register, the receive data register full (RDRF) bit is set to "1". At
this time, an interrupt occurs if reception interrupt requests have been enabled. If an RDRF bit check by the
program or using an interruption shows that received data is stored in this register, the reading of the
content for this register clears the RDRF flag.
When the character bit length (CBL1,0) is set to less than 8 bits, the excess upper bits (beyond the set bit
length) are set to "0".
R/WX:Read only(writing has no effect on the operation)
R/WXR/WX R/WX R/WXR/WX R/WX R/WXR/WX
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00000000B
Initial valueRD6RD7 RD5 RD3 RD2 RD1 RD0RD4
538
18.5.5 Serial Output Data Register (TDR)
The serial output data register (TDR) is used to output (transmit) serial data.
Serial Output Data Register (TDR)Figure 18.5-6 shows the bit structure of the serial output data register.
Figure 18.5-6 Serial Output Data Register (TDR)
This register holds data to be transmitted. The register accepts a write when the transmit data register empty
(TDRE) bit contains "1". An attempt to write to the bit is ignored when the bit contains "0".
If transmit data is written to this register when transmission is enabled, the transmit data is transferred to
the transmission shift register, converted to serial data, and output from the serial data output pin.
When transmit data is written to the serial output data register (TDR), the transmit data register empty bit
(TDRE) is set to "0". Upon completion of transfer of transmit data to the transmission shift register, the
transmit data register empty bit (TDRE) is set to "1", allowing the next piece of transmit data to be written.
At this time, an interrupt occurs if transmit data register empty interrupts have been enabled. Write the next
piece of transmit data either when a transmit data register empty interrupt occurs or when the transmit data
empty (TDRE) bit is set to "1".
When the character bit length (CBL1,0) is set to less than 8 bits, the excess upper bits (beyond the set bit
length) are ignored.
Note:
The data in this register cannot be updated when TDRE is "0".
Write data before enabling transmission (setting TXE = "1"). Before updating data, write TXE= "0"first to set TDRE to "1".
R/W : Read and write enableX : Undetermined
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
XXXXXXXXB
Initial value
R/WR/W R/W R/WR/W R/W R/WR/W
TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0
539
CHAPTER 18 UART/SIO
18.6 UART/SIO Interrupt
The UART/SIO has six interrupt-related bits: error flag bits (PER, OVE, FER), receive data register full bit (RDRF), transmit data register empty bit (TDRE), and transmission completion flag (TCPL).
UART/SIO InterruptTable 18.6-1 lists the UART/SIO interrupt control bits and interrupt sources.
Transmission InterruptWhen transmit data is written to the serial output data register (TDR), the data is transferred to the internal
transmission shift register. When the next piece of data can be written, the TDRE bit is set to "1". At this
time, an interrupt request to the CPU occurs when transmit data empty interrupts have been enabled
(SMC2:TEIE = 1).
The TCPL bit is set to "1" upon completion of transmission of all pieces for transmit data. At this time, an
interrupt request to the CPU occurs when transmission completion interrupts have been enabled
(SMC2:TCIE = 1).
Reception InterruptIf the data is input successfully up to the stop bit, the RDRF bit is set to 1. If an overrun, parity, framing
error occurs, the individual error flags bits (PER, OVE, FER) are set to "1".
These bits are set when a stop bit is detected. If the setting to permit reception interruptions (SMC2:RIE=1)
has been made by this point, an interruption request to the CPU will occur.
For interrupt request numbers, see Section "3.4 Interrupt".
Table 18.6-1 UART/SIO Interrupt Control Bits and Interrupt Sources
ItemTransmission Data
Register EmptyTransmit
CompletionReceive Data
FullParity Error Overrun Error Framing Error
Interrupt request flag bit
SSR: TDRE SSR: TCPL SSR: RDRF SSR: PER SSR: OVE SSR: FER
Interrupt request enable bit
SMC2: TEIE SMC2: TCIE SMC2: RIE SMC2: RIE SMC2: RIE SMC2: RIE
Interrupt causeTransmission data
register emptyTransmit
completionReceive data
fullParity error Overrun error Framing error
540
18.7 Explanation of Operation Mode 0
The operation mode 0 operates as the clock asynchronous mode.
Explanation of UART/SIO Operating Mode 0Setting the MD bit in serial mode control register 1 (SCM1) to 0 selects clock asynchronous mode
(UART).
The serial clock is selected by the CKS bit in the SMC1 register. Be sure to select the dedicated baud rate
generator at this time.
In CLK asynchronous mode (UART), the baud rate is equivalent to the CKS-bit selected shift clock signal
frequency-divided by four. The UART can perform communication within the range from -2% to + 2% of
the selected baud rate.
The baud rate generated by the dedicated baud rate generator is obtained from the equation illustrated
below. (For the dedicated baud rate generator, see "CHAPTER 19 Dedicated Baud Rate Generator" as
well.)
Figure 18.7-1 Baud Rate Calculation for Using Dedicated Baud Rate Generator
Boud rate value =
4 ×2:
255
1248
Prescaler selection (PSS1,PSS2) of UART prescaler selection register(PSSR)
×
Machine clock(MCLK)[bps]
Baud rate setting(BRS7 to 0) of UART baud rate setting registetr(BRSR)
Table 18.7-1 Example of Asynchronous Transfer Rate Based on Dedicated Baud Rate Generator (Clock Gear 4/Fch, Machine Clock 10 MHz)
Setting of Dedicated Baud Rate GeneratorUART Internal
DivisionTotal Divide Ratio(PSS x BRS x 4)
Baud Rate(10MHz / Total Division
Ratio)Prescaler Selection
PSS[1:0]Baud Rate Counter Setting
BRS[7:0]
1 (Set value:0,0) 20 4 80 125000
1 (Set value:0,0) 22 4 88 113636
1 (Set value:0,0) 44 4 176 56818
1 (Set value:0,0) 87 4 348 28736
1 (Set value:0,0) 130 4 520 19231
2 (Set value:0,1) 130 4 1040 9615
4 (Set value:1,0) 130 4 2080 4808
8 (Set value:1,1) 130 4 4160 2404
541
CHAPTER 18 UART/SIO
The baud rate in the UART mode can be set in the following range.
Transfer Data FormatUART can treat data only in NRZ (Non-return to Zero) format. Figure 18.7-2 shows the data format.
The character bit length can be selected from among 5 to 8 bits depending on the CBL1 and CBL0 settings.
The stop bit length can be set to 1 or 2 bits depending on the SBL setting.
PEN and TDP can be used to enable/disable parity and to select a parity poarity.
As shown in Figure 18.7-2 , the transfer data always starts from the start bit (’L’ level) and ends with the
stop bit (’H’ level) by performing the specified data bit length transfer with LSB first (Selectable LSB/
MSB first by BDS bit). If becomes ’H’ livel at the idle state.
Figure 18.7-2 Transfer Data Format
Table 18.7-2 Baud Rate Setting Range in UART Mode
PSS[1:0] BRS[7:0]
“0,0” to “1,1” 02h (2) to FFh(255)
ST D0 D1 D2 D3 D4
ST D0 D1 D2 D3 D4
ST D0 D1 D2 D3 D4
ST D0 D1 D2 D3 D4
SP
P SP
SP SP
P SP SP
ST D0 D1 D2 D3 D4 D5 D6 D7
ST D0 D1 D2 D3 D4 D5 D6 D7
ST D0 D1 D2 D3 D4 D5 D6 D7
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
P SP
SP SP
P SP SP
Without P
With P
Without P
With P
Data 5-bit
Data 8-bit
ST : Start bit SP : Stop bitP : Parity bit D0 to 7 : Data. The sequence can be selected LSB/MSB first
by direction control register(BDS bit)
...data 6-bit and data 8-bit are also same
542
Receiving Operation in CLK Asynchronous Mode (UART)Use serial mode control register 1 (SMC1) to select a serial data direction (endian), parity/non-parity, parity
polarity, stop bit length, character bit length, and clock.
Reception remains performed as long as the reception enable bit (RXE) contains "1".
Upon detection of a start bit in receiving data with the reception enable bit (RXE) set to "1", one frame of
data is received according to the data format set in serial control register 1 (SMC1).
When the reception of one frame of data has been completed, the received data is transferred to the serial
input data register (RDR) and the next frame of serial data can be received.
When the serial input data register (RDR) stores data, the receive data register full (RDRF) bit is set to "1".
A reception interrupt occurs the moment the receive data register full (RDRF) bit is set to "1" when the
reception interrupt enable bit (RIE) contains "1".
Received data is read from the serial input data register (RDR) after each error flag (PER, OVE, FER) in
the serial status register is checked.
When received data is read from the serial input data register (RDR), the receive data register full (RDRF)
bit is cleared to "0".
Note that updating serial mode control register 1 (SMC1) during reception may result in unpredictable
operation. If the RXE bit is set to "0" during reception, the reception is immediately disabled without
transferring the data received so far to the serial input data register.
Figure 18.7-3 Receiving Operation in Asynchronous Clock Mode
SI St D0 D1 D2 D3 D4 D5 D6 Sp SpD7 St D0 D1 D2
RXE
Reading of RDR
RDRF
543
CHAPTER 18 UART/SIO
Reception Error at CLK Asynchronous Mode (UART)If any of the following three error flags (PER, FER, OVE) has been set, received data is not transferred to
the serial input data register (RDR) and the receive data register full (RDRF) bit is not set to "1" either.
1. Parity error (PER)
The parity error (PER) bit is set to "1" if the parity bit in received serial data does not match the paritypolarity bit (TDP) when the parity control bit (PEN) contains "1".
2. Framing error (FER)
The framing error (FER) bit is set to "1" if "1" is not detected at the position of the first stop bit in serialdata received in the set character bit length (CBL) under parity control (PEN). Note that the stop bit is notchecked if it appears at the second bit or later.
3. Overrun error (OVE)
Upon completion for reception of serial data, the overrun error (OVE) bit is set to "1" if the receive dataregister full (RDRF) bit has been set to "1" by the reception of the preceding piece of data, or if that datahas not been read from the RDR register.
Each flag is set at the position of the first stop bit.
Figure 18.7-4 Setting Timing for Receiving Errors
SI D5 D6 D7 P SP SP
PEROVEFER
RDRF
Reception interrupt
544
Start Bit Detection during Reception and Data ReceptionThe start bit is detected by a fall of the serial input followed by a succession of three "L" levels after the
serial data input is sampled according to the clock (BRCLK) signal provided by the dedicated baud rate
generator with the reception operation enable bit (RXE). When the first "H,L,L,L" train is detected in a
BRCLK sample, therefore, the current bit is regarded as the start bit.
The frequency-quartered circuit is activated upon detection of the start bit and serial data is input to the
reception shift register at intervals of four periods of BRCLK.
When data is received, sampling is performed at three points of the baud rate clock (BRCLK) and data
sampling clock (DSCLK) and received data is asserted on a majority basis when two bits out of three
match.
Figure 18.7-5 Start Bit Detection and Serial Data Input
Baud rate clock
(BRCLK)
RXE
Counter divided - by 4 0
H
D0
Sample three point and determine '0' or '1' by the majority basis when two bits out of three match
X
Reception shift register
L L L L
D1
1 2 3
Data sampling clock(DSCLK)
Serial data input
(SI)
Start bit detection
0 1 2 3
D0 D1X
Start bit
545
CHAPTER 18 UART/SIO
CLK Asynchronous Mode TransmissionUse serial mode control register 1 (SMC1) to select a serial data direction (endian), parity/non-parity, parity
polarity, stop bit length, character bit length, and clock.
The following two procedures can be used to initiate the transmission process:
• Set the transmission operation enable bit (TXE) to "1", then write transmit data to the serial output data registerto start transmission.
• Write transmit data to the serial output data register, then set the transmission operation enable bit (TXE) to "1"to start transmission.
Transmit data is written to the serial output data register (TDR) with the transmit data register empty (TDRE) bit
set to "1".
When the transmit data is written to the serial output data register (TDR), the transmit data register empty (TDRE)
bit is cleared to "0".
The transmit data is transferred from the serial output data register (TDR) to the transmission shift register, and the
transmit data register empty (TDRE) is set to "1".
When the transmission interrupt enable bit (TIE) contains "1", a transmission interrupt occurs if the transmit data
register empty (TDRE) bit is set to "1". This allows the next piece of transmit data to be written to the serial output
data register (TDR) by interrupt handling. Serial transmission can be continued with the transmission operation
enable bit (TXE) set to "1".
A transmission interrupt can also be used to detect the completion of serial transmission. For this usage, set
the transmission interrupt output enable bits this way: TEIE=0, TCIE=1. Upon completion of transmission,
the transmission completion flag (TCPL) is set to 1 and a transmission interrupt occurs.
Also, the transmission completion flag(TCPL) and the transmisson data register empty flag(TDRE) when
transmitting consecutively is set at the position which the transmission of last bit was completed (it differs by
setting data length, parity enable, or stou bit length).
Note that updating serial mode control register 1 (SMC1) during transmission may result in unpredictable
operation.
Figure 18.7-6 CLK Asynchronous Mode (UART) Transmission
The TDRE flag is set at the point indicated in the following diagram if the preceding piece of transmit data
does not exist in the transmission shift register (when frames of data are transmitted in a discontinuous
manner).
SO D5 D6 D7 P SP SP
TCPLTDRE
Transmission interrupt
If set the STOP bit length to two bits.If set the STOP bit length to one bit.
546
Figure 18.7-7 Transmit Data Register Empty Flag (TDRE) Set Timing 1
Figure 18.7-8 Transmit Data Register Empty Flag (TDRE) Set Timing 2
Concurrent Transmission and ReceptionIn clock asynchronous mode (UART), transmission and reception can be performed independently.
Transmission and reception can therefore be performed at the same time or even with transmitting and
receiving frames overlapping each other in shifted phases.
SO D0 D1
TDRE
Transmission interrupt
TXE “1”
Writing of transmission data
D2 D3
Transfer from serial output data tregister(TDR) to transmit shift register is performed by one machine clock (MCLK).
SO D0 D1
TDRE
Transmission interrupt
TXE
Writing of transmission data
D2 D3
547
CHAPTER 18 UART/SIO
18.8 Explanation of Operation Mode 1
Operation mode 1 operates in clock synchronous mode.
Explanation of UART/SIO Operating ModeSetting the MD bit in serial mode control register 1 (SCM1) to 1 selects clock synchronous mode (SIO).
The character length in clock synchronous mode (SIO) is variable between 5 and 8 bits. Note, however,
that parity is disabled and no stop bit is used.
The serial clock is selects by the CKS bit in the SMC1 register. Select the dedicated baud rate generator or
external clock. The SIO performs shift operation using the selected serial clock as a shift clock. To input
the external clock signal, set the SCKE bit to "0".
To output the dedicated baud rate generator output as a shift clock signal, set the SCKE bit to "1". The
serial clock signal is obtained by frequency-dividing BRCLK supplied by the dedicated baud rate
generator. The baud rate in the SIO mode can be set in the following range. (For the dedicated baud rate
generator, see "CHAPTER 19 Dedicated Baud Rate Generator" as well.)
The baud rate applied when the external clock or dedicated baud rate generator is used obtained from the
corresponding equation illustrated below.
Figure 18.8-1 Calculating Baud Rate Based on External Clock
Table 18.8-1 Baud Rate Setting Range in SIO Mode
PSS[1:0] BRS[7:0]
0,0 to 1,101h(1) to FFh(255),00h(256)
(The setting for the highest baud rate is 01h; that for the lowest is 00h.)
Baud rate value =
External clock
1[bps]
548
Figure 18.8-2 Baud Rate Calculation Formula for Using Dedicated Baud Rate Generator
The serial clock signal is outputted under control of the output for transmit data. When only reception is
performed, therefore, set transmission control (TXE=1) to write dummy transmit data to the serial output
register.
Boud rate value =
4 ×2:
255
1248
Prescaler selection (PSS1,PSS2) of UART prescaler selection register(PSSR)
×
Machine clock(MCLK)[bps]
Baud rate setting(BRS7 to 0) of UART baud rate setting registetr(BRSR)
549
CHAPTER 18 UART/SIO
8-bit ReceptionFor reception in operation mode 1, each register is used as follows.
Figure 18.8-3 Registers Used for Reception in Operation Mode 1
The reception startup procedure depends on whether the serial clock has been set to external or internal.
<External Serial Clock enable>
When the reception operation enable bit (RXE) contains "1", serial data is received always at the risingedge of the external serial clock signal.
<Internal Serial Clock enable>
The serial clock signal is outputted to meet transmission. The following two procedures can therefore beused.
• Set the transmission operation enable bit (TXE) to "1", then write transmit data to the serial output dataregister to generate the serial clock signal and start reception.
• Write transmit data to the serial output data register, then set the transmission operation enable bit(TXE) to "1" to generate the serial clock signal and start reception.
When 8-bit serial data is received by the reception shift register, the received data is transferred to the serial
input data register (RDR) and the next piece of serial data can be received.
When the serial input data register stores data, the receive data register full (RDRF) bit is set to "1".
A reception interrupt occurs the moment the receive data register full (RDRF) bit is set to "1" when the
reception interrupt enable bit (RIE) contains "1".
To take received data, read it from the serial input data register after checking the error flag (OVE) in the
serial status register.
When received data is read from the serial input data register (RDR), the receive data register full (RDRF)
BDS PEN TDP SBL CBL1 MD
× × ×
SMC1
SCM1(Serial mode control register 1)
SCKE TXOE RERC RXE TXE RIE TEIE
0 ×
SMC2
SCM2(Serial mode control register 2)
: Used bit × : Unused bit 1 : Set to 1
- - PER OVE FER RDRF TDRE
× × × ×
SSR
SSR(Serial status register)
TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0
× × × × × × × ×
TDR
TDR(Serial output data register)
CKS
1
×
×
SDR
RDR(serial input data register)
CBL0
TCIE
×
TCPL
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
550
bit is cleared to "0".
Operation at receive error
When an overrun error (OVE) exists, received data is not transferred to the serial input data register(RDR).
Overrun error (OVE)
Upon completion of reception for serial data, the overrun error (OVE) bit is set to "1" if the receive dataregister full (RDRF) bit has been set to "1" by the reception for the preceding piece of data.
Figure 18.8-4 8-bit Reception of CLK Synchronous Mode
SI D0 D1 D2 D3 D4 D5 D6 D7
SCK
Reading to RDR
RDRF
Writing to RDR
Interrupt to CPU
551
CHAPTER 18 UART/SIO
8-bit TransmissionFor transmission in operation mode 1, each register is used as follows.
Figure 18.8-5 Registers Used for Transmission in Operation Mode 1
The following two procedures can be used to initiate the transmission process:
• Setting the transmission operation enable bit (TXE) to "1", then write transmit data to the serial output dataregister to start transmission.
• Write transmit data to the serial output data register, then set the transmission operation enable bit (TXE) to "1"to start transmission.
Transmit data is written to the serial output data register (TDR) with the transmit data register empty (TDRE) bit
set to "1".
When the transmit data is written to the serial output data register (TDR), the transmit data register empty (TDRE)
bit is cleared to "0".
When serial transmission is started after transmit data is transferred from the serial output data register (TDR) to
the transmission shift register, the transmit data register empty (TDRE) bit is set to "1".
When the use of the external clock signal has been set, serial data transmission starts at the fall of the first
serial clock signal after the transmission process is started.
A transmission interrupt occurs the moment the transmit data register empty (TDRE) bit is set to "1" when the
transmission interrupt enable bit (TIE) contains "1". At this time, the next piece of transmit data can be written to
the serial output data register (TDR). Serial transmission can be continued with the transmission operation enable
bit (TXE) set to "1".
To use a transmission interrupt to detect the completion of serial transmission, enable transmission interrupt
output this way: TEIE=0, TCIE=1. Upon completion of transmission, the transmission completion flag
(TCPL) is set to 1 and a transmission interrupt occurs.
BDS PEN TDP SBL CBL0 MD
× × ×
SMC1
SCM1(Serial mode control register 1)
SCKE TXOE RERC RXE TXE RIE TEIE
1 ×
SMC2
SCM2(Serial mode control register 2)
: Used bit× : Unused bit1 : Set to 1
- - PER OVE FER RDRF TDRE
× × × × × ×
SSR
SSR(Serial status register)
TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0
TDR
TDR(Serial output data register)
CKS
1
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
× × × × × × × ×
SDR
RDR(Serial input data register)
CBL1
´
TCIE
TCPL
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
552
Figure 18.8-6 8-bit Transmission under CLK Synchronous Mode
Concurrent Transmission and Reception<External Serial Clock enable>
Transmission and reception can be performed independently of each other. Transmission and receptioncan therefore be performed at the same time or even when their phases are shifted from each other andoverlapping.
<Internal Serial Clock enable>
As the transmitting side has a serial clock generation feature, reception is subordinate to transmission. Iftransmission stops during reception, the receiving side is suspended. It resumes reception when thetransmitting side is restarted.
SI D0 D1 D2 D3 D4 D5 D6 D7
SCK
TCPL
Writing to TDR
Interrupt to CPU
TDRE
Interrupt to CPU
553
CHAPTER 18 UART/SIO
554
CHAPTER 19Dedicated Baud Rate
Generator
This chapter describes the function and operation of the dedicated baud rate generator.
19.1 Dedicated Baud Rate Generator
19.2 Channels of Dedicated Baud Rate Generator
19.3 Registers of Dedicated Baud Rate Generator
19.4 Dedicated Baud Rate Generator
555
CHAPTER 19 Dedicated Baud Rate Generator
19.1 Dedicated Baud Rate Generator
The dedicated baud rate generator generates the baud rate for the UART/SIO. The dedicated baud rate generator consists of the UART/SIO prescaler selection register (PSSR) and UART/SIO baud rate setting register (BRSR).
Block Diagram of Dedicated Baud Rate Generator
Figure 19.1-1 UART/SIO Block Diagram
Pre Scaler
Baud rate generator
CLK
PCK[0] 8-bit
UART
1/4
PSS1,0 BSR7~0
BRCLK
MCLK
Down counterPCK[1]
PCK[2]
556
19.2 Channels of Dedicated Baud Rate Generator
Channels of dedicated baud rate generator is explained.
Channels of Dedicated Baud Rate GeneratorThe following shows the correspondence between channels and registers.
Table 19.2-1 Registers of Dedicated Baud Rate Generator
Channel Register Name Corresponding Register (Name in Specifications)
0PSSR0 PSSR: UART/SIO prescaler selection register.
BRSR0 BRSR: UART/SIO baud rate setting register.
1PSSR1 PSSR: UART/SIO prescaler selection register.
BRSR1 BRSR: UART/SIO baud rate setting register.
557
CHAPTER 19 Dedicated Baud Rate Generator
19.3 Registers of Dedicated Baud Rate Generator
The registers used by the dedicated baud rate generator are the UART/SIO prescaler selection register (PSSR) and UART/SIO baud rate setting register (BRSR).
Registers of Dedicated Baud Rate Generator
Figure 19.3-1 Registers Concerning Dedicated Baud Rate Generator
BRS7
bit7 bit6 bit0bit3 bit1bit2bit4bit5 Initial value00000000B
Initial value00000000B
bit7 bit6 bit0bit3 bit1bit2bit4bit5
R0/WX R0/WX R0/WX R0/WX R0/WX R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
BRS6 BRS5 BRS4 BRS3 BRS2 BRS1 BRS0
BRGE PSS1 PSS0
R0 : Read always returns 0.WX : Write has no effect to operations.
R/W : Read and write are enabled.
UART/SIO prescaler select register (PSSR)
UART/SIO baud rate setting register (BRSR)
558
19.3.1 UART/SIO Prescaler Selection Register (PSSR)
The UART/SIO prescaler selection register (PSSR) controls the baud rate clock output and prescaler.
UART/SIO Prescaler Selection Register (PSSR)
Figure 19.3-2 UART/SIO Prescaler Selection Register (PSSR)
- - - - - BRGE PSS1
TCPL
0
1
PSS1 PSS2
0
0
1
1
0
1
0
1
1/1
1/2
1/4
1/8
PSS0
Initial value00000000B
bit7 bit6 bit0bit3 bit1bit2bit4bit5
R0/WX R0/WX R0/WX R0/WX R0/WX R/W R/W R/W
R0 : Read always returns 0.WX : Write has no effect to operations.
R/W : Read and write are enabled.
: Initial value
Prescaler selection bit
Baud rate output enable control bit
Baud rate output disabled
Baud rate output enabled
559
CHAPTER 19 Dedicated Baud Rate Generator
Table 19.3-1 UART/SIO Prescaler Selection Register (PSSR)
Bit name Function
Bit7 to Bit3 Unused Reading these bits always returns 0.
Bit2BRGE:Baud rate clock output enabled
• Enable output of the baud rate clock BRCLK.• Setting this bit to 1 loads BRS(7:0) to the 8-bit down-counter and outputs BRCLK
which is supplied to the UART/SIO. • Setting this bit to 0 stops BRCLK output.
Bit1, Bit0PSS1,0:Prescaler pulse selection
PSS1 PSS0 Prescaler selection
0 0 1/1
0 1 1/2
1 0 1/4
1 1 1/8
560
19.3.2 UART/SIO Baud Rate Setting Register (BRSR)
The UART/SIO baud rate setting register (BRSR) controls the baud rate setting.
UART/SIO Baud Rate Setting Register (BRSR)
Figure 19.3-3 UART/SIO Baud Rate Setting Register (BRSR)
Sets the period of the 8-bit down-counter. This register allows any desired baud rate clock to be specified.
Only write to this register when the UART is stopped.
Do not set BRSR(7:0) to 00 or 01 during UART mode.
R/WR/W R/W R/WR/W R/W R/W R/W
BRS7 BRS6 BRS5 BRS4 BRS3 BRS2 BRS1 BRS0
bit7 bit6 bit0bit3 bit1bit2bit4bit5 Initial value00000000B
R/W : Read and write are enabled.
561
CHAPTER 19 Dedicated Baud Rate Generator
19.4 Dedicated Baud Rate Generator
The dedicated baud rate generator acts as the baud rate generator in clock asynchronous mode.
Baud Rate SettingSMC1 register (CKS bit) in the UART/SIO selects the serial clock. This selects the dedicated baud rate
generator.
In the CLK asynchronous mode, the 1/4 clock of the shift clock selected by the CKS bits is used and
transfers can be performed within the range between -2% to +2% of the selected baud rate. The baud rate
calculated formula by dedicated baud rate generator is shown as following.
Figure 19.4-1 Baud Rate Calculation at Using of Dedicated Baud Rate Generator
The permitted range for the baud rate setting in UART mode is as follows.
Machine clock (MCLK)[bps]
41248
2
255
Baudrate value
Prescaler selection (PSS1 and PSS2) of UART prescaler selectionregister (PSSR)
Baud rate setting(BRS7 to 0) of UART baud rate setting register (BRSR)
Table 19.4-1 Example Asynchronous Transmission Rates Generated by Baud Rate Generator (Clock Gear = 4/Fch, Machine Clock = 10MHz)
Setting of dedicated baud rate generator UART internal division
Total divide ratio(PSS x BRS x 4)
Baud rate(10MHz / Total divide ratio)Prescaler selection
PSS[1:0]Baud rate counter setting
BRS[7:0]
1 (Set value:0,0) 20 4 80 125000
1 (Set value:0,0) 22 4 88 113636
1 (Set value:0,0) 44 4 176 56818
1 (Set value:0,0) 87 4 348 28736
1 (Set value:0,0) 130 4 520 19231
2 (Set value:0,1) 130 4 1040 9615
4 (Set value:1,0) 130 4 2080 4808
8 (Set value:1,1) 130 4 4160 2404
Table 19.4-2 Permitted Setting Range for UART Mode
PSS[1:0] BRS[7:0]
“0,0” to “1,1” 02h(2) to FFh(255)
562
CHAPTER 20LIN-UART
This chapter describes the function and operation of the LIN-UART.
20.1 Overview of LIN-UART
20.2 Configuration of LIN-UART
20.3 LIN-UART Pins
20.4 Register of LIN-UART
20.5 LIN-UART Interrupt
20.6 LIN-UART Baud Rate
20.7 Operation of LIN-UART
20.8 Notes on Using LIN-UART
563
CHAPTER 20 LIN-UART
20.1 Overview of LIN-UART
LIN (Local Interconnect Network)-UART is a general-purpose serial data communication interface for synchronous or asynchronous (start-stop synchronization) communications with external devices. In addition to a bi-directional communication function (normal mode) and master/slave communication function (multiprocessor mode: supports both master and slave operation), the LIN-UART also supports the special functions used by the LIN bus.
Functions of LIN-UARTThe LIN-UART is a general-purpose serial data communications interface for exchanging serial data with
other CPUs and peripheral devices. Table 20.1-1 lists the functions of the LIN-UART.
Table 20.1-1 Functions of LIN-UART
Functions
Data buffer Full-duplicate double-buffer
Serial inputThe LIN-UART oversamples received data for five times to determine the received value by majority decision (only asynchronous mode).
Transfer mode• Clock synchronization (Select start/stop synchronization or the start/stop bit.)• Clock asynchronous (Start/stop bits available)
Baud rate• Dedicated baud rate generator provided (made of a 15-bit reload counter)• The external clock can be inputted. The reload counter can also be used to adjust the external
clock.
Data length• 7 bits (not in synchronous or LIN mode)• 8 bits
Signal type NRZ (Non Return to Zero)
Start bit timing Synchronization with the start bit falling edge in asynchronous mode.
Detection of receive error• Framing error• Overrun error• Parity error (Not supported in operation mode 1)
Interrupt request
• Receive interrupt (receive complete, receive error detected, LIN synch break detected)• Send interrupt (send data empty)• Interrupt request to TII0 (LIN synch field detected: LSYN)
• Both sending and receiving support the extended intelligent I/O service (EI2OS) and DMA function.
Master/slave mode communication function (Multiprocessor mode)
Capable of 1 (master) to n (slaves) communication(Both of the master and slave systems are supported.)
Synchronization mode Master or slave function
Pin access The status of the serial I/O pins can be read directly.
LIN bus option
• Master device operation• Slave device operation• LIN Synch break detection• LIN Synch break generation• Detection of LIN synch field start and stop edges connected to the 8/16-bit multifunction timer
Synchronous serial clockContinuous output to the SCK pin is possible for synchronous communication using the start/stop bits
Clock delay option Special synchronous clock mode for delaying the clock (used for SPI)
564
The LIN-UART can operate in four different modes. The operation mode is set in the MD0 and MD1 bits of
the LIN-UART serial mode register (SMR). Modes 0 and 2 are used for bidirectional serial communication,
mode 1 for master/slave communication, and mode 3 for LIN master/slave communication.
The MD0 and MD1 bits of the LIN-UART serial mode register (SMR) are used to select the following
LIN-UART operation modes.
Note:
• Mode 1 is used for master/slave connections and supports both master and slave operation.
• Mode 3 uses a fixed LSB-first 8N-1 communication format (8 data bits, no parity, one stop bit).
• If the mode is changed during communications, the current send or receive operation is haltedand the LIN-UART goes to standby (waits for the next communication operation to start).
Table 20.1-2 LIN-UART Operation Modes
Operating ModeData Length Synchronization
MethodsLength of Stop
BitData Bit Format
No Parity With Parity
0 Normal mode 7 bits or 8 bits Asynchronous1 bit or 2 bits
LSB firstMSB first
1 Multiprocessor mode 7 bits or 8 bits +1* - Asynchronous
2 Normal mode 8 SynchronousNon, 1 bit, 2 bits
3 LIN mode 8 - Asynchronous 1 bit LSB first
- : Un available*: "+ 1" is the address/data selection bit (A/D) used for communications control in multiprocessor mode.
Table 20.1-3 LIN-UART Operation Modes
MD1 MD0 Mode Type
0 0 0 Asynchronous (Normal mode)
0 1 1 Asynchronous (Multiprocessor mode)
1 0 2 Synchronous (Normal mode)
1 1 3 Asynchronous (LIN mode)
565
CHAPTER 20 LIN-UART
20.2 Configuration of LIN-UART
The blocks making up the LIN-UART are outlined below.
LIN-UART Blocks• Reload counter
• Reception control circuit
• Receive shift register
• Receive data register (RDR)
• Transmission control circuit
• Transmission shift register
• Transmit data register (TDR)
• Error detection circuit
• Oversampling circuit
• Interruption generation circuit
• LIN synch break/Synch Field detection circuit
• Bus idle detection circuit
• Serial control register (SCR)
• LIN-UART serial mode register (SMR)
• Serial status register (SSR)
• Extended status control register (ESCR)
• Extended communication control register (ECCR)
566
LIN-UART Block Diagram
Figure 20.2-1 LIN-UART Block Diagram
RDR TDR
PENP
SBLCL
A/DCRERXETXE
MD1MD0OTOEXT
REST
USCKEUSOE
PEOREFRE
RDRFTDRE
BDSRIETIE
LBIELBD
SOPESIOPCCO
SCES
LBIELBD
RBI
RIETIE
IRQ
IRQ
LBD
SIN
PE ORE FRE
CLK
SIN
SOT
MS
SSM SCDE
TDRE
RDRF
RBITBI
UPCL
OTO,EXT,REST
PEOREFRE
TBI
RBI TBI
SIN
SCK
SOT
SSR SMR SCR ESCR ECCR
LBR
LBRLBL1LBL0
LBL1LBL0
Pin
Pin
Pin
Reload counter
Restart receptionreload counter
Over- sampling circuit
Internal signal to 8/16-bit compound timer
LIN break/SynchField detection circuit
Reception shift register
Error detection
Transmission shift register
Transfer start
Bus idle detection circuit
LIN break generating circuit
Reception
Transfer
Write generating circuit
Transfer control circuit
Internal data bus
Register RegisterRegisterRegisterRegister
Transfer clock
Reception clock
Reception control circuit
Start bit detection circuit
Reception bitcounter
Reception parity counter
Transmission start circuit
Transmission bit counter
Transmission parity counter
567
CHAPTER 20 LIN-UART
Explanation of Different Blocks
Reload counter
This block is a 15-bit reload counter serving as a dedicated baud rate generator. The block consists of a 15-bit register for reload values; it generates the transmission/reception clock signal from the external orinternal clock. The count value in the send reload counter is read from the baud rate generator (BGR1 andBGR0).
Reception control circuit
This block consists of a receive bit counter, a start bit detection circuit, and a receive parity counter. Thereceive bit counter counts the received data bits and sets a flag in the LIN-UART receive data register whenreception of the specified number of data bits has completed. If the receive interrupt is enabled when thisoccurs, a receive interrupt request is generated. The start bit detection circuit detects a start bit in a serialinput signal. When a start bit is detected, the circuit sends a signal to the reload counter in synchronizationwith the falling edge of the start bit. The received parity counter calculates the parity of the received data.
Receive shift register
The circuit inputs received data from the UI pin while bit-shifting and transfers it to the RDR register uponcompletion of reception.
Receive data register (RDR)
The receive data register retains the receive data. Serial input data is converted and stored in the receivedata register.
Transmission control circuit
This block consists of a transmit bit counter, a transmission start circuit, and a transmit parity counter. Thesend bit counter counts the sent data bits and sets a flag in the send data register when the specified numberof data bits have been sent. If the send interrupt is enabled when this occurs, a send interrupt request isgenerated. The transmission start circuit starts transmission when data is written to the TDR. The transmitparity counter generates a parity bit for data to be transmitted if the data is parity-checked.
Transmission shift register
The data written to the send data register (TDR) is transferred to the send shift register and bit-shifted outvia the SOT pin.
Transmit data register (TDR)
The transmit data register sets the transmit data. The data written to the register is converted to serial dataand outputted.
Error detection circuit
Upon completion of reception, an error is detected, if any. If an error occurs, the corresponding error flag isset.
Oversampling circuit
When operating in asynchronous mode, over-sampling is performed five times and the majority value isused as the receive value. The LIN-UART stops during operation in synchronous mode.
Interruption generation circuit
All interrupt sources are controlled. An interrupt occurs immediately if the corresponding interrupt enablebit has been set.
568
LIN synch break/synch field detection circuit
A LIN synch break is detected upon transmission of a message header from the LIN master node. The LBDflag bit is set upon detection of the LIN synch break. Outputs an internal signal to the combined 8/16-bittimer to measure the actual serial clock synchronization being transmitted by the master node by detectingthe first and fifth falling edge on the LIN synch field.
LIN synch break generation circuit
Generates a LIN synch break with the specified length.
Bus idle detection circuit
Detects that no sending or receiving is in progress and sets the TBI and RBI flag bits.
Serial control register (SCR)
Operating functions are as follows:
• Setting of parity bit existence
• Parity bit selection
• Sets stop bit length
• Sets data length
• Selecting the frame data format in mode 1
• Clears error flag
• Transmit enable/disable
• Reception enable/disable
LIN-UART serial mode register (SMR)
Operating functions are as follows:
• Selecting the LIN-UART operation mode
• Selecting a clock input source
• It is selected whether the external clock is of one-to-one connection or of reload counter connection.
• Resets the dedicated reload timer.
• LIN-UART software reset (maintains register settings)
• Enabling/disabling output to the serial data pin
• Enable/disable output to the clock pin.
Serial status register (SSR)
Operating functions are as follows:
• Checks send/receive, error, and other status information.
• Selects the transfer direction (LSB-first or MSB-first).
• Enable/disable receive interrupt
• Enable/disable send interrupt
Extended status control register (ESCR)
• Enable/disable LIN synch break interrupt
• LIN synch break detection
• Select LIN synch break length
• Direct access to SIN and SOT pins
• Sets continuous clock output in LIN-UART synchronous clock mode.
569
CHAPTER 20 LIN-UART
• Sampling clock edge selection
Extended communication control register (ECCR)
• Bus idle detection
• Synchronous clock setting
• LIN synch break generated
570
20.3 LIN-UART Pins
Pins of LIN-UART are shown.
LIN-UART PinsThe LIN-UART pins also serve as general-purpose ports. Table 20.3-1 lists the pin functions and settings
for using the LIN-UART.
Refer to "3. DC Ratings" in "Electrical Characteristics" in the Data Sheet for ratings.
Table 20.3-1 LIN-UART Pins
Pin Name Pin Function Setting Required for Using The Pin
SIN Serial data inputSet to the input port.
(DDR: Corresponding bit = 0)
SOT Serial data outputSet to output enable.
(SMR:SOE = 1)
SCK Serial clock input/output
Set as an input port when used as clock input. (DDR: Corresponding bit = 0)
Enable output when used as clock output.(SMR:SCKE = 1)
571
CHAPTER 20 LIN-UART
20.4 Register of LIN-UART
The list of the register for LIN-UART is shown.
List of LIN-UART Register
Figure 20.4-1 List of LIN-UART Register
bit 7 bit0
SCR PENS P SBL CL A/D CRE RXE TXE 00000000B
R/W R/W R/W R/W R,W R0,W R/W R/W
bit7 bit0
SMR MD1 MD0 OTO EXT REST UPCL SCKE SOE 00000000B
R/W R/W R/W R/W R0,W R0,W R/W R/W
bit7 bit0
SSR PE ORE FRE RDRF TDRE BDS RIE TIE 00001000B
R/WX R/WX R/WX R/WX R/WX R/W R/W R/W
bit7 bit0
RDR/TDR 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit7 bit0
ESCR LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES 00000100B
R/W R(RM1),W R/W R/W R/W R(RM1),W R/W R/W
bit7 bit0
ECCR - LBR MS SCDE SSM BIE RBI TBI 000000XXB
R0/W0 R0,W R/W R/W R/W R/W R/WX R/WX
bit7 bit0
BGR1 - 00000000B
R0/WX R/W R/W R/W R/W R/W R/W R/W
bit7 bit0
BGR0 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
Serial control register
LIN-UART serial mode register
Serial status register
Reception data register/transmission data register
Extended status control register
Extended communication control register
Baud rate generator register 1
Baud rate generator register 0
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
572
20.4.1 Serial Control Register (SCR)
The serial control register (SCR) is used to specify whether to use parity, select the number of stop bits and data, select the frame data format in mode 1, clear the receive error flag, and enable or disable send and receive operation.
Serial Control Register (SCR)
Figure 20.4-2 Serial Control Register (SCR)
PEN P SBL CL A/D CRE RXE TXE
bit7
R/W
00000000B
bit6 bit5 bit4 bit3 bit0bit1bit2
R/WR/WR/WR/W R/WR0,WR,W
TXE
0
1
RXE
0
1
CRE
0
1
A/D
0
1
CL
0
1
SBL
0
1
P
0
1
PEN
0
1
R/WR0,W
:::
Initial value
Transmission enable bit
Transmission disabled
Transmission enabled
Reception enable bit
Reception disabledReception enabled
Reception error flag clear bit
Write Read
No effect
Clear reception error flag (PE, FRE, ORE)
0 is always read.
Address/data format selection bit
Data frame
Address frame
Data length selection bit
7-bit8-bit
Stop bit length selection bit
1-bit
2-bit
Parity selection bit
Even parity
Odd parity
Parity enable bitWith parityWithout parity
Read/write enabledWrite is only enabled. Reading value is always "0".Initial value
573
CHAPTER 20 LIN-UART
Table 20.4-1 Functional Description of Each Bit in Serial Control Register (SCR)
No. Bit Name Functions
bit7PEN: Parity enable bit
Specify whether to add (at sending) and detect (at receiving) a parity bit.Notes: • The parity bit is only added in operation mode 0 and when use of start and stop is set
(ECCR:SSM=1) in operation mode 2.• Always "0" in mode 3 (LIN).
bit6P: Parity selection bit
Select either (1) odd or even parity (0) when the use of the parity bit has been selected (SCR: PEN = 1).
bit5SBL: Stop-bit length select bit
Specifies the number of stop bits (frame end mark for send data) for operation modes 0 and 1 (asynchronous) and when use of start and stop bits is set (ECCR:SSM=1) in operation mode 2 (synchronous). This bit is fixed as "0" in modes 3 (LIN).Note: During receiving data, only the first bit of the stop bit is detected in all cases.
bit4CL: Data length selection bit
Specify the data length of data to be transmitted and received. This bit is fixed as "1" in modes 2 and 3.
bit3A/D: Address/data type selection bit
Specifies the data format for send and receive frames in multi-processor mode (mode 1). Write to this bit when in master mode and read the bit when in slave mode. The operation in master mode is as follows.• When the bit is set to "0": The frame format is set to data frame. • When the bit is set to "1": The frame format is set to address data frame. The value of the last data type received is read.Note: See "20.8 Notes on Using LIN-UART" for further information about using this bit.
bit2CRE: Receive error flag clear bit
Bits to clear FRE, ORE and PE flags in serial status register (SSR)• Writing "1" clears the error flag.• Writing "0" has no effect.Reading this bit always returns "0".Note: Clear the receive error flag after halting receive operation.
bit1RXE: Reception enable bit
The bit enables or disables the LIN-UART for reception.• When set to "0": Data frame reception is disabled.• When set to "1": Data frame reception is enabled.The detection of a LIN synch break in mode 3 is not affected.Note: If receive operation is disabled (RXE=0) during reception, the receive operation halts immediately. In that case, received data is not guaranteed.
bit0TXE: Transmit enable bit
The bit enables or disables the LIN-UART for transmission. • When set to "0": Data frame sending is disabled. • When set to "1": Data frame sending is enabled. Note: If send operation is disabled (TXE=0) during sending, the send operation halts immediately. In that case, received data is not guaranteed.
574
20.4.2 LIN-UART Serial Mode Register (SMR)
The LIN-UART serial mode register (SMR) is used to select the operation mode, select the baud rate clock, and enable or disable output to the serial data and clock pins.
LIN-UART Serial Mode Register (SMR)
Figure 20.4-3 Serial Mode Register (SMR)
MD1 MD0 OTO EXT REST UPCL SCKE SOE
bit7
R/W R/W R/W R/W R0,W R0,W R/W R/W
00000000B
bit0bit1bit2bit3bit4bit6 bit5
SOE
0
1
SCKE
0
1
UPCL
0
1
REST
0
1
EXT
0
1
OTO
0
1
MD1 MD0
0 0
0 1
1 0
1 1
R/W
R0,W
::
:
Initial value
LIN-UART serial data output enable bit
General-purpose I/O port
LIN-UART serial data output pin
LIN-UART serial clock output enable bit
General-purpose I/O port or LIN-UART clock input pin
Serial clock output pin of LIN-UART
LIN-UART programmable clear bit
Write Read
0 is always read.
No effect
LIN-UART reset
Reload counter restart bit
Write Read
0 is always read.
No effect
LIN Restart reload counter
External serial clock source select bit
Use of baud rate generator (reload counter)
Use of external serial clock source
One-to-one clock input enable bit
Use of baud rate generator (reload counter)
Direct use of external clock
Operation mode setting bit
Mode 0 : asynchronous normal
Mode 1 : asynchronous multiprocessor
Mode 2 : synchronous
Mode 3 : asynchronous LIN
Read and write are enabled.
Only write is enabled. Reading value is always "0".
Initial value
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CHAPTER 20 LIN-UART
Table 20.4-2 Functional Description of Each Bit in Serial Mode Register (SMR)
No. Bit Name Functions
bit7, bit6
MD1, MD0: Operation mode select bits
Set operating mode
bit5OTO: One-to-one external clock enable bit
Writing "1" enables the external clock to be used directly as the LIN-UART serial clock.Used for slave operation (ECCR:MS=1) in operation mode 2 (synchronous).When EXT = 0, the OTO bit is fixed at 0.
bit4EXT: External clock selection bit
Selecting clock inputSetting the bit to "0" selects the clock of the internal baud rate generator (reload counter); setting it to "1" selects the external serial clock source.
bit3REST: Reload counter restart bit
Restart reload counter.Writing "1" restarts the reload counter.Writing "0" has no effect.The bit always returns 0 when read.
bit2UPCL: LIN-UART programmable clear bit (LIN-UART software reset)
Reset the LIN-UART. Writing "1" resets the LIN-UART immediately (LIN-UART software reset). Note that the register settings are maintained. In this case, sending and receiving is halted. All of the transmission/reception interrupt sources (TDRE, RDRF, LBD, PE, ORE, FRE) are reset. Reset the LIN-UART after disabling the interrupt and disabling sending. The receive data register is cleared (RDR=00H) and the reload counter is restarted.Writing "0" has no effect. Reading this bit always returns "0".
bit1SCKE: LIN-UART serial clock output enable bit
Controls the serial clock I/O port.When "0", the SCK pin becomes a general-purpose I/O port or the serial clock input pin. When "1", the SCK pin becomes the serial clock output pin and outputs the clock in operation mode 2 (synchronous). Note: When the SCK pin is used as the serial clock input (SCKE=0), always set the
general-purpose I/O port as an input port in the corresponding DDR bit. Also, use the clock select bit to select the external clock (EXT=1).
Reference: When the SCK pin is set as a serial clock output (SCKE=1), the pin serves as a serial clock output pin regardless of the state for the general-purpose I/O port.
bit0SOE: LIN-UART serial-data output enable bit
Enable or disable output of serial data.When "0", the SOT pin becomes a general-purpose I/O port. When "1", the SOT pin becomes the serial data output pin (SOT). Reference: For serial data output (SOE=1), the SOT pin works as SOT pin regardless of
the state for the general-purpose I/O port.
576
20.4.3 Serial Status Register (SSR)
The serial status register (SSR) is used to check send/receive, error, and other status information and to enable or disable interrupts.
Serial Status Register (SSR)
Figure 20.4-4 Serial Status Register (SSR)
PE ORE FRE RDRF TDRE BDS RIE TIE
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R/WX R/WX R/WX R/WX R/WX R/W R/W R/W
00001000B
R/W :
R/WX :
:
TIE
0
1
9
RIE
0
1
BDS
0
1
TDRE
0
1
RDRF
0
1
FRE
0
1
ORE
0
1
PE
0
1
Initial value
Transmission interrupt enable bit
Transmission interrupt is disabled.Transmission interrupt is enabled.
Reception interrupt enable bit
Reception interrupt is disabled.
Reception interrupt is enabled.
Transmission direction select bit
LSB first (transmission from lowest bit)
MSB first (transmission from highest bit)
Transmission data empty flag bit
Data is existent in transmission data register TDR.
Transmission data register TDR is empty.
Reception data full flag bit
Reception data register RDR is empty.
Data is existent in reception data register RDR.
Framing error flag bit
Without framing error
With framing error
Overrun error flag bit
Without overrun errorWith overrun error
Parity error flag bit
Without parity error
With parity error
Read and write are enabled.
Only read is enabled. Write has no effect.
Initial value
577
5
CHAPTER 20 LIN-UART
78
Table 20.4-3 Functional Description Functions of Each Bit in Serial Status Registers (SSR)
No. Bit Name Functions
bit7PE: Parity error flag bit
Detect an parity error in received data.• Set to "1" when a parity error occurs during receiving with PE=1. Cleared by
writing "1" to the CRE bit in the LIN-UART serial mode register (SMR).• When the PE and RIE bits are both "1", a reception interrupt request is outputted.• The data in the receive data register (RDR) is not valid when this bit is set.
bit6ORE: Overrun error flag bit
Detect an overrun error for the received data.• Set to "1" when an overrun error occurs during receiving. Cleared by writing "1" to
the CRE bit in the LIN-UART serial mode register (SMR).• When the ORE and RIE bits are both "1", a reception interrupt request is outputted.• The data in the receive data register (RDR) is not valid when this bit is set.
bit5FRE: Framing error flag bit
Detect a framing error in receive data. • Set to "1" when a framing error occurs during receiving. Cleared by writing "1" to
the CRE bit in the LIN-UART serial mode register (SMR). • When the FRE and RIE bits are both "1", a reception interrupt request is outputted. • The data in the receive data register (RDR) is not valid when this bit is set.
bit4RDRF: Receive data full flag bit
The flag shows the state of the receive data register (RDR). • The bit is set to "1" when the RDR loads received data. The bit is cleared to "0"
when the receive data register (RDR) is read.• When the RDRF and RIE bits are both "1", a reception interrupt request is
outputted.
bit3TDRE: Transmission data empty flag bit
The flag shows the state of the transmission data register (TDR). • Goes to "0" when send data written to TDR to indicate that TDR contains valid
data. Changes to "1" when the data is loaded into the send shift register and sendingstarts. This indicates that the TDR does not contain valid data.
• When the TDRE and TIE bits are both "1", a transmission interrupt request isoutputted.
• Setting the LBR bit of the extended communication control register (ECCR) to "1"when the TDRE bit is "1" changes the TDRE bit to "0". The TDRE bit then goes to"1" after a LIN sync break occurs.
Note: The initial state is TDRE= "1".
bit2BDS: Transfer direction selection bit
Specifies whether the serial transmission data is sent starting from the least significant bit (LSB-first, BDS=0) or from the most significant bit (MSB-first, BDS=1).
Note: As the upper and lower data values are swapped when reading or writing the serial data register, changing the BDS bit after writing data to the RDR register invalidates that data. The BDS bit is fixed at "0" in mode 3 (LIN).
bit1RIE: Reception interrupt request enable bit
Enables or disables output of receive interrupt requests to the CPU. • A receive interrupt request is outputted when the RIE bit and receive data flag bit
(RDRF) are "1", or when one or more error flag bits (PE, ORE, FRE) are "1".
bit0TIE: Transmission interrupt request enable bit
This bit enables/disables transmission interrupt request output to the CPU.• When the TDRE and TIE bits are both "1", a transmission interrupt request is
outputted.
20.4.4 Receive Data Register, Transmit Data Register (RDR/TDR)
The receive data and send data registers are located at the same address. The register address functions as the read data register when reading and the send data register when writing.
Receive Data Register (RDR) Figure 20.4-5 shows the bit layout of the receive register.
Figure 20.4-5 Receive Data Register, Transmit Data Register (RDR/TDR)
The receive data register (RDR) acts as a data buffer register for the received serial data.
The serial data signal sent to the serial input pin (SIN pin) is converted via a shift register and saved in the
receive data register (RDR).
If the data length is 7 bits, the upper 1 bit (RDR:D7) goes to "0".
The receive data full flag bit (SSR:RDRF) is set to "1" when the receive data is stored in the receive data
register (RDR). When receiving interrupts are enabled (SSR: RIE=1), receiving interrupt requests are
generated.
Read the receive data register (RDR) contents when the receive data full flag bit (SSR:RDRF) is "1". The
receive data full flag bit (SSR:RDRF) is automatically cleared to "0" when the receive data register (RDR)
is read.
The receive interrupt is also cleared if enabled and if no error has occurred.
The data in the receive data register (RDR) is invalid if a receive error has occurred (any of SSR:PE, ORE,
or FRE is "1").
0 0 0 0 0 0 0 0 Bbit 7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
R/W : Read and write are enabled.
Initial value
Data register
Read
Write
Read from reception data register
Write to transmission data register
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CHAPTER 20 LIN-UART
Transmit Data Register (TDR)
The send data register (TDR) is a data buffer register for the serial send data.
If sending is enabled (SCR:TXE=1), writing data to the send data register (TDR) causes the data to be
transferred to the send shift register, converted to serial data, and outputted from the serial data output pin
(SOT pin).
When the data length is 7 bits, the data in upper one bit (TDR: D7) is invalid.
The send data empty flag (SSR:TDRE) is cleared to "0" when send data is written to the send data register
(TDR).
The send data empty flag (SSR:TDRE) is set to "1" after the data is transferred to the send shift register and
sending starts.
The next send data can be written once the send data empty flag (SSR:TDRE) goes to "1". When sending
interrupts are enabled, a sending interrupt is generated. You can use the send interrupt to write the next
send data. Only write the next data when the send data empty flag (SSR:TDRE) is "1".
Note:
The send data register is a write-only register, and the receive data register is a read-only register.Both of the registers are located in the same address, so the writing values and reading values aredifferent. Therefore, instructions, such as the INC/DEC instruction, which provide the read modifywrite (RMW) operation cannot be used.
580
20.4.5 Extended Status Control Register (ESCR)
The extended status control resister (ESCR) contains the setting for enabling/disabling LIN synch break interrupts, LIN synch break length selection, LIN synch break detection, direct access to the SIN and SOT pins, continuous clock output in LIN-UART synchronous clock mode, and sampling clock edge.
Bit Configuration of Extended Status Control Register (ESCR)Figure 20.4-6 shows the bit configuration of the extended status control register (ESCR) bits and Table
20.4-4 describes the function of each bit.
Figure 20.4-6 Bit Configuration of Extended Status Control Register (ESCR)
LBIE LBD LBL1 LBL0 SIOP CCO SCES 00000100BSOPE
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R/W R(RM1),W R(RM1),WR/W R/W R/W R/W R/W
SCES01
CCO01
SIOP
01
SOPE01
LBL0 LBL1
0 0
1 00 1
1 1
LBD
0
1
LBIE
0
1
R/W :
x :
:
Initial value
Sampling clock edge selection bit (mode 2)Sampling with rising clock edge (normal)Sampling with falling clock edge (invertion clock)
Continuous clock output enable bit (mode 2)Disable continuous clock outputEnable continuous clock output
Serial I/O pin direct access setting bitWrite (SOPE = "1") Read
Fixed SOT pin to "0"Fixed SOT pin to "1"
Read the value of SIN pin
Serial output pin direct access enable bitDisable serial output pin direct accessEnable serial output pin direct access
LIN Synch break length selection bit13 bits14 bits
16 bits
15 bits
LIN Synch break detection flag bitWrite Read
LIN synch break detection flag clear
No effect
Without LIN synch break detectionWith LIN synch break detection
LIN synch break detection interrupt enable bitDisable LIN synch break detection interrupt
Enable LIN synch break detection interrupt
Read and write are enabled
Undefined
Initial value
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CHAPTER 20 LIN-UART
Table 20.4-4 Functional Description of Each Bit in Extended Status Control Register (ESCR)
NO. Bit Name Functions
bit7LBIE: LIN synch break detection interrupt enable bit
This bit enables/disables LIN synch break detection interrupts. An interrupt is generated when the LIN synch break detected flag (LBD) is "1" and the interrupt is enabled (LBIE=1). The bit is fixed at 0 in mode 1 or 2.
bit6LBD: LIN synch break detection flag bit
LIN synch break detected.Set to "1" when a LIN synch break is detected in operation mode 3 (goes to "0" when length of serial input is 11 bits or longer). Also, writing "0" clears the LBD bit and the interrupt. The bit is always read as "1" by RMW instructions but this does not indicate that a LIN synch break was detected. Note: If you intend to detect LIN synch breaks, enable the LIN synch break detection
interrupt (LBIE=1) and then disable reception (SCR:RXE=0).
bit5, bit4LBL1/0: LIN synch break length selection bits
These bits specify the number of bits that generates a LIN synch break. The LIN synch break length for reception is always 11 bits.
bit3SOPE: Serial output pin direct access
enabled bit*
Enable or disable direct writing to the SOT pin. Setting this bit to "1" when serial data output is enabled (SMR:SOE=1) enables direct
writing to the SOT pin.*
bit2SIOP:
Serial I/O pin direct access bit *
Controls direct access to the serial I/O pin. Standard read instructions always read the SIN pin value. When direct access to the serial output pin is enabled (SOPE=1), the value of this bit is output to the SOT pin when a write is performed. Note: In the case of a bit manipulation instruction, the instruction reads the value of
the SOT pin at the time of the read cycle.
bit1CCO: Continuous clock output enable bit
Enables or disables continuous serial clock output from the SCK pin. Setting this bit to "1" when set as master in operation mode 2 (synchronous) enables output of the continuous serial clock from the SCK pin provided the SCK pin is set as the clock output. Note: When the CCO bit is "1", set the SSM bit in ECCR to "1".
bit0SCES: Sampling clock edge selection bit
Select the sampling edge. When set as a slave in operation mode 2 (synchronous), setting SCES to "1" changes the sampling edge from the rising edge to the falling edge. When set as master in operation mode 2 (ECCR:MS=0) with SCK pin set as the clock output, this inverts the internal serial clock and output clock signal. Set to "0" for operation modes 0, 1, and 3.
*:Table 20.4-5 Mutual Relationships between SOPE and SIOP
SOPE SIOP Writing into SIOP Reading from SIOP
0 R/W No effect (However, retains the value written) The SIN value is returned.
1 R/W Writes "0" or "1" to SOT. The SIN value is returned.
1 RMW Reads the SOT value. Writes "0" or "1".
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20.4.6 Extended Communication Control Register (ECCR)
The extended communication control register (ECCR) is used to detect the bus idle state, set the synchronous clock, and generate LIN synch break.
Bit Configuration of Extended Communication Control Register (ECCR)Figure 20.4-7 shows the bit configuration of the extended communication control register (ESCR) bits andTable 20.4-6 describes the function of each bit.
Figure 20.4-7 Bit Configuration of Extended Communication Control Register (ECCR)
MS SCDE SSM RBI TBI 000000XXBLBR
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R0,W R/W R/W R/W R/WX R/WXR0/W0 RX,W0
TBI*01
RBI*01
SSM0
1
SCDE01
MS01
LBR
01
R/W :
R/WX :
R0,W
:RX,W0
:
X:
:
Initial value
Transmission bus idle detection flag bitIn transmissionWithout transmission operation
Reception bus idle detection flag bitIn receptionWithout reception operation
Reserved bitReading value is undefined. "0" is always set.
Start/stop enable bit (mode 2)
Without start/stop bit
With start/stop bit
Serial clock delay enable bit (mode 2)
Clock delay is disabled.Clock delay is enabled.
Master/slave function selection bit (mode 2)Master mode (serial clock generation)Slave mode (external serial clock reception)
LIN Synch break generating bit
Write ReadNo effectLIN Synch break generation "0" is always read.
Reserved bitReading value is undefined. "0" is always set.
Read and write are enabled.Only read is enabled. Write has no effect to operation. Only write is enabled. Reading value is always "0". Read is undefined. Writing value is always "0". UndefinedInitial value
*: Unused at SSM = 0 in operating mode 2
Reserved Reserved
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CHAPTER 20 LIN-UART
Table 20.4-6 Functional Description of Each Bit in Extended Communication Control Register (ECCR)
NO. Bit Name Functions
bit7 Reserved bitThe read value is indeterminate.Be sure to always set it to "0".
bit6LBR:LIN synch break generating bit
Setting "1" to this bit in operation mode 3 generates a LIN synch break for the number of bits specified by LBL0 and 1 in ESCR. Set to "0" in operation mode 0.
bit5MS: Master/Slave mode selection bit
Selects master or slave mode in mode 2.When the master mode (0) is selected, a synchronous clock signal is generated.When the slave mode (1) is selected, the external serial clock signal is received. Set to "0" in operation modes 0, 1, and 3.Only modify this bit when the SCR:TXE bit is "0".Note: When slave mode is selected, the clock source must be set to external clock and
external clock input enabled (SMR:SCKE=0, EXT=1, OTO=1).
bit4SCDE: Serial clock delay enable bits
When set as master in operation mode 2, setting the SCDE bit to "1" outputs a delayed serial clock as shown in Figure 20.7-5 . This bit is used for SPI.Set to "0" in operation modes 0, 1, and 3.
bit3SSM: Start/stop bit mode enable bits
If this bit is set to "1" in mode 2, start and stop bits are added to the synchronous data format.Set to "0" in operation modes 0, 1, and 3.
bit2 Reserved bitThe read value is indeterminate.Be sure to always set it to "0".
bit1RBI: Reception bus idle flag bit
Goes to "1" when the SIN pin is at the "H" level and when receive operation is not in progress. Do not use this bit when SSM=0 in operation mode 2.
bit0TBI: Transmission bus idle flag bit
The bit is set to "1" when the SOT pin has no operation for transmission. Do not use this bit when SSM=0 in operation mode 2.
584
20.4.7 Baud Rate Generator Registers 0 and 1 (BGR0/1)
The baud rate generator registers 0 and 1 (BGR0/1) set the serial clock divide ratio. The registers can also be used to read the count value from the transmission reload counter.
Bit Configuration of Baud Rate Generator Registers (BGR0/1)Figure 20.4-8 shows bit configuration of baud rate generator registers (BGR0/1).
Figure 20.4-8 Bit Configuration of Baud Rate Generator Registers (BGR0/1)
The baud rate generator registers set the serial clock divide ratio.
BGR1 contains the upper bits and BGR0 contains the lower bits. Use the registers to write the reload value
for the counter and read the send reload counter value. Byte word access is also possible.
Writing a reload value to the baud rate generator registers causes the reload counter to start counting.
00000000B
R0/WX
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00000000B
R/W R/W R/W R/W R/W R/W R/W
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R/W R/W R/W R/W R/W R/W R/W R/W
BGR0
BGR1
R/W
R/W :R0/WX :
R/W
Initial value
Baud rate generator register 1
WriteRead
Write to reload counter bits 8 to 14.Read transmission reload counter bits 8 to 14.
Undefined bit
Read
Initial value
"0" is enable to read.
Baud rate generator register 0
WriteRead
Write to reload counter bits 0 to 7.Read transmission reload counter bits 0 to 7.
Read and write are enabled. Reading value is always "0". Write has no effect to operations.
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CHAPTER 20 LIN-UART
20.5 LIN-UART Interrupt
The LIN-UART has send and receive interrupts which are triggered by the following events. The two interrupts are allocated to separate interrupt numbers and interrupt vectors. Also, it has the LIN synch field edge detection interrupt function using the combined 8/16-bit timer interrupt.• Reception Interrupt
When received data is set in the receive data register (RDR) or a reception error occurs. Also, when LIN synch break is detected.
• Transmission Interrupt When the send data is transferred from the send data register (TDR) to the send shift register and sending starts.
See "3.4 Interrupts" for details of interrupt numbers and interrupt vectors.
Reception Interrupt Table 20.5-1 lists the control bits and interrupt triggers for the receive interrupt.
Reception interrupt
Each flag bit in the serial status register (SSR) is set to "1" if any of the following events takes place in
reception mode:
Data receive completed
When receive data is transferred from the serial input shift register to the receive data register (RDR)(RDRF=1)
Overrun error
When the next serial data is received with RDRF= "1" before RDR has been read by the CPU (ORE=1)
Framing error
When a stop bit receive error occurs (FRE=1)
Parity error flag bit
When a parity detect error occurs (PE=1)
Table 20.5-1 Interrupt Control Bits and Interrupt Triggers for Receive Interrupt
Interrupt Request Flag Bit
Flag Register
Operating ModeInterrupt Cause
Interrupt Causes Enable Bit
Interrupt Request Flag Clear0 1 2 3
RDRF SSR RDR writing of received data
SSR:RIE
Reading receive data
ORE SSR Overrun errorWrite "1" to receive error flag clear bit (SCR:CRE)
FRE SSR ∆ Framing error
PE SSR ∆ Parity error
LBD ESCR LIN synch break detection ESCR:LBIE ESCR: Writing "0" to LBD
: Using bit : Unused bit∆ : Only ECCR:SSM=1 available
586
A receive interrupt request generates if any of the above bits goes to "1" and receive interrupts are enabled
(SSR:RIE=1).
The RDRF flag is automatically cleared to "0" when you read the receive data register (RDR). All of the
error flags are cleared to "0" when "1" is written to the reception error flag clear bit (CRE) in the serial
control register (SCR).
Note:
The CRE flag is write only. When "1" is written to the bit, it retains the value "1" for one clock cycle.
LIN synch break interrupt
Used when operating as a LIN slave in operation mode 3.
If the bus (serial input) goes to "0" for 11 bits or longer, the LIN synch break detected flag bit (LBD) in the
extended status control register (ESCR) is set to "1". The LIN synch break interrupt and LBD flag are
cleared by writing "0" to the LBD flag. Clear the LBD flag before the combined 8/16-bit timer interrupt is
generated for the LIN synch field.
If you intend to detect LIN synch break, you must disable reception (SCR:RXE=0).
Transmission Interrupt Table 20.5-2 lists the control bits and interrupt triggers for the send interrupt.
Transmission interrupt
The send data register empty flag bit (TDRE) in the serial status register (SSR) is set to "1" after the send
data is transferred from the send data register (TDR) to the send shift register and sending starts. In this
case, a transmission interrupt request issues if transmission interrupts have been enabled (SSR:TIE=1).
Note:
As the initial value of TDRE after a hardware or software reset is "1", setting the TIE bit to "1" willtrigger an interrupt immediately. Also, TDRE can only be cleared by writing data to the send dataregister (TDR).
Table 20.5-2 Interrupt Control Bits and Interrupt Triggers for Send Interrupt
Interrupt Request Flag Bit
Flag Register
Operating ModeInterrupt Cause
Interrupt Causes Enable Bit
Interrupt Request Flag Clear0 1 2 3
TDRE SSR Transmit registers are empty.
SSR:TIE Writing transmit data
: Using bit
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CHAPTER 20 LIN-UART
LIN Synch Field Edge Detect Interrupt (Combined 8/16-Bit Timer Interrupt)Table 20.5-3 lists the control bits and interrupt triggers for the LIN synch field edge detect interrupt.
LIN synch field edge detect interrupt (combined 8/16-bit timer interrupt)
Used when operating as a LIN slave in operation mode 3.
After a LIN synch break is detected, the internal signal (LSYN) is set to "1" at the first falling edge of the
LIN synch field and set to "0" at the fifth falling edge. If the combined 8/16-bit timer is setup so that the
internal signal is input to the combined 8/16-bit timer, and detection of either edge is specified, a combined
8/16-bit timer interrupt generates if the combined 8/16-bit timer interrupt is enabled.
The difference in the count values detected by the combined 8/16-bit timer (see Figure 20.5-1 ) corresponds
to the 8 bits in the master serial clock, and the new baud rate can be calculated from this value. When a new
baud rate is set, the new baud rate is used from the next start bit falling edge detection.
Figure 20.5-1 Baud Rate Calculation for 8/16-Bit Multi-Function Timer
Table 20.5-3 Interrupt Control Bits and Interrupt Triggers for LIN Synch Field Edge Detect Interrupt
Interrupt Request Flag Bit
Flag Register
Operating ModeInterrupt Cause
Interrupt Causes Enable Bit
Interrupt Request Flag Clear0 1 2 3
IR TOOCR1 First falling edge of the LIN synch field
TOOCR1:IETOOCR1: Writing 0 to IR
IR TOOCR1 Fifth falling edge of the LIN synch field
: Using bit : Unused bit
LIN synch field
Received data
Internal signal (LSYN)
8/16-bit combined timer
Start
Data = 0x55
Stop
Capture value 1 Capture value 2
Difference in count value = (capture value 2) - capture value 1
0 1 2 3 4 5 6 7
588
20.5.1 Reception Interrupt Generation and Flag Set Timing
Interrupts during reception are one generated upon completion of reception (SSR:RDRF) and one generated upon occurrence of a reception error (SSR:PE, ORE, FRE).
Reception Interrupt Generation and Flag Set TimingThe received data is saved in the receive data register (RDR) when the first stop bit is detected in modes 0,
1, 2 (SSM=1), and 3, or when the final data bit is detected in mode 2 (SSM=0). The flags are set when
reception completes (SSR:RDRF=1), or a receive error occurs (SSR:PE, ORE, FRE=1). A receive interrupt
also generates if the receive interrupt is enabled (SSR:RIE=1).
Note:
If a reception error occurs in each mode, the data in the receive data register (RDR) is made invalid.
Figure 20.5-2 shows the receive operation and flag set timing.
Figure 20.5-2 Reception Operation and Flag Set Timing
Note:
Figure 20.5-2 does not show all receive operations for mode 0. Examples are shown for the "7P1"and "8N1" (P= "even parity" or "odd parity") cases only.
RDRF
PE*1, FRE
ORE*2
(RDRF = "1")
ST D0 D1 D2 D5 D6 D7/P SP ST
ST D0 D1 D2 D6 D7 A/D SP ST
D0 D1 D2 D4 D5 D6 D7 D0
Receive data (Mode 0/3)
Receive data (Mode 1)
Receive data (Mode 2)
Reception interrupt generated
*1: The PE flag is always "0" in mode 1 or 3.*2: An overrun error occurs if the next data is transferred before received data is read (RDRF = 1). ST: Start bit, SP: Stop bit, A/D: Mode 1 (multiprocessor) address/data select bit
...
...
...
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CHAPTER 20 LIN-UART
Figure 20.5-3 ORE Flag Set Timing
RDRF
ORE
ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3 4 5 6 7 SPReceive Data
590
20.5.2 Transmit Interrupt Generation and Flag Set Timing
The send interrupt is generated after the send data is transferred from the send data register (TDR) to the send shift register and sending starts.
Transmit Interrupt Generation and Flag Set Timing Writing the next data becomes available (SSR:TDRE=1) once the data written to the send data register
(TDR) has been transferred to the send shift register and sending has started. A send interrupt generates at
this time if the send interrupt is enabled (SSR:TIE=1).
Because the TDRE bit is read-only, it can only be cleared to "0" by writing data to the send data register
(TDR).
Figure 20.5-4 shows the send operation and flag set timing for each LIN-UART mode setting.
Figure 20.5-4 Transmission Operation and Flag Set Timing
Note:
Figure 20.5-4 does not show all send operations for mode 0. The figure only shows the "8P1" (P="even parity" or "odd parity") case.
No parity bit is sent in mode 3 or when SSM=0 in mode 2.
TDRE
TDRE
ST D0 D1 D2 D3 D4 D5 D6 D7 PAD
SP ST D0 D1 D2 D3 D4 D5 D6 D7 PAD
SP
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4
Send interrupt occurred Send interrupt occurred
Mode 0, 1, 3: TDR write
Serial output
Mode 2(SSM=0): TDR write
Serial output
ST: Start bit, D0 to D7: Data bits, P: Parity, SP: Stop bit, AD: Address data select bit (mode 1)
Send interrupt occurred Send interrupt occurred
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CHAPTER 20 LIN-UART
Transmission Interrupt Request Generation Timing
A send interrupt is generated when the TDRE flag is set to "1" if the send interrupt is enabled (SSR:TIE=1).
Note:
As the initial value of the TDRE bit is "1", enabling the send interrupt (SSR:TIE=1) triggers aninterrupt immediately. As the TDRE bit can only be cleared by writing new data to the send dataregister (TDR), care is required in relation to the timing for enabling the send interrupt.
592
20.6 LIN-UART Baud Rate
The transmission/reception clock source for the LIN-UART can be selected from among the following. Dedicated baud rate generator (reload counter) Input external clock to the baud rate generator (reload counter) External clock (use the clock input from the SCK pin directly)
LIN-UART Baud Rate SelectionYou can select one of the following three different baud rates. Figure 20.6-1 shows the baud rate selection
circuit.
Baud rate obtained by dividing the internal clock in the dedicated baud rate generator (reload counter)
Two internal reload counters are provided and are used for the send and receive serial clocks respectively.
You can select a baud rate by setting a 15-bit reload value in the baud rate generator registers 1 and 0
(BGR1 and BGR0).
The reload counter divides the internal clock frequency by the set value.
The baud rate is used in asynchronous mode and in synchronous mode (master).
To set the clock source, select the internal clock and the use of the baud rate generator clock (SMR:EXT=0,
OTO=0).
Baud rate obtained by dividing the external clock in the dedicated baud rate generator (reload counter)
The external clock is used as the clock source for the reload counter.
You can select a baud rate by setting a 15-bit reload value in the baud rate generator registers 1 and 0
(BGR1, BGR0).
The reload counter divides the external clock frequency by the set value.
The baud rate is used in asynchronous mode.
To set the clock source, select the external clock and the use of the baud rate generator clock
(SMR:EXT=1, OTO=0).
Baud rate of the external clock (one-to-one mode)
The clock signal input to the clock input pin (SCK) of the LIN-UART is directly used as the baud rate
(slave operation (ECCR:MS=1) in synchronous mode 2).
The baud rate is used in synchronous mode (slave).
To set the clock source, select the external clock and its direct use (SMR:EXT=1, OTO=1).
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CHAPTER 20 LIN-UART
Figure 20.6-1 LIN-UART Baud Rate Selection Circuit
EXTREST
BGR7
BGR10BGR9BGR8
BGR6BGR5
BGR4BGR3BGR2BGR1BGR0
Txc = 0?
Txc = v/2?
OTO
1
01
0
BGR13BGR12BGR11
BGR14
FF
Rxc = 0?
Rxc = v/2?
FF
EXT
OTO
1
0
MCLK
MCLK
SCK
Reload Value: v
Reception 15-bit reload counter
Transmission 15-bit reload counter
Reload Value: v
Counter value: TXC
Reload
Reload
ResetStart bit falling edge detection
Receptionclock
Transmission clock
(External clock input)
Reset
Reset
Set
Set
Internal data bus
SMRregister
BGR1register
BGR0register
(Machine clock)
594
20.6.1 Baud Rate Setting
Baud rate settings are shown. The calculation result for the serial clock frequency is also shown.
Calculation of Baud RateThe two 15-bit reload counters are set by baud rate generator registers 1 and 0 (BGR1 and BGR0).
The baud rate is calculated by the following equation.
Reload Value:
v=(MCLK/b)-1
v: Reload value, b: Baud rate, MCLK: Machine clock or external clock frequency
Calculation example
Use the following settings to set 19200 bps baud rate when using the internal clock with 10 MHz machine
clock.
Reload value:
Therefore, the actual baud rate can be calculated as follows.
Note:
Setting a reload value of "0" stops the reload counter. The smallest divide ratio is therefore 2.
For transmission/reception in asynchronous mode, the reload value must be at least 4 as thereceived value is determined by oversampling received data for five times.
v= (10 106
) - 1 = 52019200
b =MCLK
=10 106
= 19193.8579(v + 1) 521
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CHAPTER 20 LIN-UART
Reload Value and Baud Rate of Each Clock SpeedTable 20.6-1 lists the reload values and baud rates for each clock speed.
Table 20.6-1 Reload Values and Baud Rates
The units for frequency deviation value (dev.) is %. MCLK is the machine clock.
The maximum baud rate in synchronous mode is 1/5th of the machine clock.
External ClockWriting "1" to the EXT bit in the LIN-UART serial mode register (SMR) selects the external clock. The
baud rate generator allows the external clock to be used in the same way as the internal clock.
For slave operation in synchronous mode 2, select the one-to-one external clock input mode
(SMR:OTO=1). In this mode, the external clock input to SCK is directly inputted as the LIN-UART serial
clock.
Note:
The external clock signal is synchronized with the internal clock (MCLK: machine clock) by the LIN-UART. Accordingly, the signal will be unstable if the external clock is faster than one half the internalclock cycle (if the external clock cannot be divided).
Baud Rate8 MHz (MCLK) 10 MHz (MCLK)
Value Dev. Value Dev.
2 M - - 4 0
1 M 7 0 9 0
500000 15 0 19 0
460800 - - - -
250000 31 0 39 0
230400 - - - -
153600 51 - 0.16 64 - 0.16
125000 63 0 79 0
115200 68 - 0.64 86 0.22
76800 103 - 0.16 129 - 0.16
57600 138 0.08 173 0.22
38400 207 - 0.16 259 - 0.16
28800 277 0.08 346 < 0.01
19200 416 0.08 520 0.03
10417 767 < 0.01 959 < 0.01
9600 832 0.04 1041 0.03
7200 1110 < 0.01 1388 < 0.01
4800 1666 0.02 2082 - 0.02
2400 3332 < 0.01 4166 < 0.01
1200 6666 < 0.01 8334 0.02
600 13332 < 0.01 16666 < 0.01
300 26666 < 0.01 - -
596
597
Operation of Dedicated Baud Rate Generator (Reload Counter)
Figure 20.6-2 shows the operation of the two reload counters when the reload value is 832.
Figure 20.6-2 Operation of Dedicated Baud Rate Generator (Reload Counter)
Note:
The falling edge of the serial clock signal is generated after the value half the reload value((v+1)/2) is counted.
Transmission/reception clock
Reload Counter
Reload counter value
001 001 832 831 830 829 828 417 416 415 414 413 412 413
Fall at (V + 1)/2
CHAPTER 20 LIN-UART
20.6.2 Reload Counter
The 15-bit reload counter serves as the dedicated baud rate generator. The transmission/reception clock signal is generated from the external or internal clock. Also, the count value of the send reload counter can be read from the baud rate generator registers (BGR1 and BGR0).
Function of Reload CounterA pair of the transmission and reception reload counters serves as the dedicated baud rate generator. The
block consists of a 15-bit register for reload values; it generates the transmission/reception clock signal
from the external or internal clock. Also, the count value of the send reload counter can be read from the
baud rate generator registers (BGR1 and BGR0).
Start counting
Writing a reload value to the baud rate generator registers (BGR1 and BGR0) causes the reload counter to
start counting.
Restart
The reload counters restart in the following cases.
Both send and receive reload counters
• LIN-UART programmable reset (SMR:UPCL bit)
• Programmable restart (SMR:REST bit)
Reception Reload Counter:
• Falling edge of start bit detected in asynchronous mode
Setting "1" to the REST bit in the serial mode register (SMR) causes both reload counters to restart at thenext clock cycle. This function enables the send reload counter to be used as a simple timer.Figure 20.6-3 shows an example of how to use this function (for a reload value of 100).
Figure 20.6-3 Example of Using the Reload Timer Restart to Implement a Simple Timer
90
: don’t care
37 36 35 100 99 98 97 96 95 94 93 92 91 90 89 88 87
Write
Reload
MCLK(machine clock)
SMR registerREST bit
write signal
Reload counter
BGR0/1 registerreading signal
Register reading value
598
The number of machine cycles after the restart (cyc) for this example is obtained as follows.
cyc = v-c + 1 = 100 - 90 + 1 = 11
v: Reload value, c: Reload counter value
Note:
The reload counters also restart when the LIN-UART is reset by writing "1" to the SMR:UPCL bit.
• Automatic start (receive reload counter only)
The receive reload counter is restarted when the falling edge on the start bit is detected in asynchronousmode. This function is used to synchronize the reception shift register with received data.
Counter clear
When a reset occurs, the reload value of the baud rate generator registers (BGR1, BGR0) and the reload
counters are cleared to 00H, and the reload counters stops operation.
A LIN-UART reset (writing 1 to SMR:UPCL) clears the counter value temporarily to 00H. The reload
counters restart operation as the reload value is maintained. Setting the restart bit (writing "1" to
SMR:REST) restarts the counter value without clearing it to "00H".
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CHAPTER 20 LIN-UART
20.7 Operation of LIN-UART
The LIN-UART operates in mode 0 for bidirectional serial communication, in mode 1 for master/slave multiprocessor communication, or in mode 2 or 3 for master/slave bidirectional communication.
Operation of LIN-UART
Operating mode
The LIN-UART has four operation modes (0 to 3), allowing different combinations of inter-CPU
connection and data transfer methods to be selected as listed in Table 20.7-1 .
Note:
Mode 1 supports the operations for both of the master and slave in a system arranged in a master/slave configuration. Mode 3 uses a fixed communications format of 8N1, LSB-first.
Switching the mode cancels all the operations for transmission/reception, causing the device to waitfor the next operation.
Inter-CPU Connection MethodYou can select either external clock one-to-one connection (normal mode) and master/slave connection
(multiprocessor mode). For either mode, the data length, parity setting, and synchronization type must be
the same between all CPUs and thus the operation mode must be selected as follows.
• Peer-to-peer connection: 2 CPUs should adopt the same method either in the mode 0 or in the mode 2. Select operation mode 0 for asynchronous communication or operation mode 2 for synchronous communication. For operation mode 2, set one CPU as the master and the other as the slave.
• For master/slave connection: Select operation mode 1. Use the system as a master/slave system.
Table 20.7-1 UART Operation Modes
Operating ModeData Length Synchronization
MethodsLength of Stop
BitData Bit Format
No Parity With Parity
0 Normal mode 7 bits or 8 bits Asynchronous1 bit or 2 bits LSB first
MSB first1
Multiprocessor mode 7 bits or 8 bits + 1* - Asynchronous
2 Normal mode 8 bits Synchronous None, 1 bit, 2 bits
3 LIN mode 8 bits - Asynchronous 1 bit LSB first
-: Setting disabled* : "+ 1" is the address/data selection bit (A/D) used for communications control in multiprocessor mode.
600
Synchronization Methods
In asynchronous mode, the reception clock is synchronized with the falling edge of the reception start bit.
In synchronous mode, synchronization is assured by the clock signal of the master or the clock signal of the
node serving as the master.
Signal TypeNRZ (Non Return to Zero) method.
Transmission and Reception EnabledThe LIN-UART uses the SCR:TXE and SCR:RXE bits to control transmission and reception, respectively.
To disable transmission or reception, follow the instruction below:
• If reception is in progress, wait until the reception is completed, read the receive data register (RDR),then disable reception.
• If transmission is in progress, wait until the transmission is completed, then disable transmission.
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CHAPTER 20 LIN-UART
20.7.1 Operation of Asynchronous Mode (Operation Mode 0, 1)
The LIN-UART uses asynchronous transfer when used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode).
Asynchronous Mode Operating
Format of transmit/receive data
Transmit/receive data always begins with a start bit ("L" level) followed by a specified length of data bits
and ends up with at least one stop bit ("H" level).
The bit transfer direction (LSB-first or MSB-first) is determined by the BDS bit in the serial status register
(SSR). When parity is used, the parity bit is always placed between the last data bit and the first stop bit.
For use in operation mode 0, select a data length of seven or eight bits. You can select whether to use
parity. The stop bit length (1 or 2) can be selected.
Operation mode 1 uses a data length of seven or eight bits and adds the address/data bit without the parity
bit. The stop bit length (1 or 2) can be selected.
The bit length of transmit/receive frames is calculated as follows:
Length=1 + d + p + s
(d = Number of data bits [7 or 8], p = parity [0 or 1],
s = Number of stop bits [1 or 2])
Figure 20.7-1 shows the data formats used in asynchronous modes.
602
Figure 20.7-1 Format of Transmit/Receive Data (Operation Mode 0 or 1)
Note:
When the BDS bit in the serial status register (SSR) is set to "1" (MSB-first), bits are manipulated inthe order of: D7, D6,... D1, D0 (P).
Transmission operation
When the transmit data register empty flag bit (TDRE) in the serial status register (SSR) is "1", transmit
data can be written in the transmit data register (TDR). Writing data sets the TDRE flag to "0". At this time,
if transmission has been enabled (serial control register (SCR) TXE bit = "1"), data is written to the
transmission shift register and its transmission is started sequentially from the start bit in the next serial
clock cycle.
An interrupt occurs when the TDRE flag is set with transmission interrupts enabled (TIE = "1"). Note that,
as the TDRE initial value is "1", an interrupt occurs as soon as "1" is written to TIE when the TDRE bit
ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 SP
SPST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 SP SP
ST D0 D1 D2 D3 D4 D5 D6 P SP
ST D0 D1 D2 D3 D4 D5 D6 SP
SPST D0 D1 D2 D3 D4 D5 D6 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 A/D SP
ST D0 D1 D2 D3 D4 D5 D6 A/D SP
ST D0 D1 D2 D3 D4 D5 D6 D7 A/D
ST D0 D1 D2 D3 D4 D5 D6 A/D SP SP
SP
SP
[Operation modes 0]
[Operation modes1]
ST: Start bitSP: Stop modeP: Parity bitA/D: Address/data bit
P: None
Data 8 bits
Data 7 bits
P: Yes
P: None
P: Yes
Data 8 bits
Data 7 bits
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CHAPTER 20 LIN-UART
holds that value.
When the data length has been set to 7 bits (CL = "0"), bit 7 in the TDR register becomes an unused bit
regardless of the transfer direction select bit (BDS) setting (LSB-first or MSB-first).
Note:
As the initial value of the transmit data empty flag bit (SSR:TDRE) is "1", an interrupt occurs as soonas transmission interrupts are enabled (SSR:TIE = "1").
Reception operation
The receiving operation is performed if reception has been enabled (SCR:RXE=1). Upon detection of the
start bit, one frame of data is received according to the data format set in the serial control register (SCR).
When an error occurs, the error flag (SSR:PE, ORE, FRE) is set. Upon completion of reception for one
frame of data, the received data is transferred from the reception shift register to the receive data register
(RDR) and the receive data register full flag bit (SSR:RDRF) is set to "1". At this time, a reception
interrupt request is outputted if reception interrupt requests have been enabled (SSR: RIE = 1).
To read received data, check the error flag status after receiving one frame of data and, if it has been
received normally, read the received data from the receive data register (RDR). When a reception error
occurs, perform error handling.
When received data is read, the receive data register full flag bit (SSR:RDRD) is cleared to "0".
When the data length has been set to 7 bits (CL = "0"), the TDR MSB becomes an unused bit regardless of
the transfer direction select bit (BDS) setting (LSB-first or MSB-first).
Note:
The data in the receive data register (RDR) is made valid when the receive data register full flag bit(SSR:RDRF) is set to "1" without causing any error (SSR:PE, ORE, FRE="0").
Used clock
The internal or external clock is used. For the baud rate, select the baud rate generator (SMR:EXT = "0" or
"1", OTO = "0").
Stop bit
You can select one or two stop bits for transmission. When two stop bits are selected, both of the stop bits
are detected upon reception.
Upon detection of the first stop bit, the receive data register full flag (SSR:RDRF) is set to "1". If the next
start bit is not detected, the reception bus idle flag (ECCR:RBI) is set to "1", indicating no reception.
Error detection
In mode 0, parity, overrun, and frame errors can be detected.
In mode 1, overrun and frame errors can be detected. Parity errors cannot be detected.
604
Parity
You can specify that the parity bit be added (during transmission) and detected (during reception).
Use the parity enable bit (SCR:PEN) to select whether to use parity and the parity select bit (SCR:P) to
select the odd or event parity.
Parity cannot be used in operation mode 1.
Figure 20.7-2 Transmission Data to Which Parity is Effective
Data signal type
NRZ data format.
Data transfer method
You can select the LSB-or MSB-first data bit transfer method.
SIN
1 0 1 1 0 0 0
SOT
1 0 1 1 0 0 1
SOT
1 0 1 1 0 0 0
ST SP
ST SP
ST SP
0
0
0
0
0
0
At reception with even paritygenerating parity error (SCR:P = 0)
Transmission of even parity(SCR:P = 0)
Transmission of odd parity (SCR:P = 1)
ST: Start bit, SP: Stop bit, Parity used (PEN=1)Note: No parity can be used in operation mode 1.
ParityData
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CHAPTER 20 LIN-UART
20.7.2 Operation of Synchronous Mode (Operation Mode 2)
When the LIN-UART is used in operation mode 2 (normal mode), the transfer method is clock-synchronous.
Operation of Synchronous Mode (Operation Mode 2)
Format of transmit/receive data
Synchronous mode transmits and receives 8-bit data and allows you to select whether to include the start
and stop bits (ECCR:SSM). When you select the use of the start and stop bits (ECCR:SSM = 1), you can
also select whether to include a parity bit (SCR:PEN).
Figure 20.7-3 shows the data format for use in synchronous mode.
Figure 20.7-3 Format of Transmit/Receive Data (Operation Mode 2)
Clock inversion
The serial clock signal is inverted when the SCES bit in the extended status control register (ESCR)
contains "1". In slave mode, the LIN-UART samples data at the falling edge of a received serial clock.
Note that, in master mode, the mark level becomes "0" with the SCES bit set to "1".
Figure 20.7-4 Transmit Data Format during Clock Inversion
Start/stop bits
When the SSM bit in the extended communication control register (ECCR) contains "1", the start and stop
bits are added to in the data format as in asynchronous mode.
*
*
(ECCR:SSM=0,SCR:PEN=0)
(ECCR:SSM=1,SCR:PEN=0)
(ECCR:SSM=1,SCR:PEN=1)
D0 D1 D2 D3 D4 D5 D6 D7
ST D0 D1 D2 D3 D4 D5 D6 D7
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP SP
SP SP
Transmit/receive data
Transmit/receive data
Transmit/receive data
*: When two stop bits are set (SCR:SBL = 1).
ST: Start bit, SP: Stop bit, P: Parity bit, LSB-first
Data frame
Reception or transmission clock
Data stream (SSM = 1)(here: no parity, 1 stop bit)
ST SP
(SCES = 0, CCO = 0):
Reception or transmission clock(SCES = 1, CCO = 0):
mark level
mark level
606
Clock supply
In clock synchronous mode (normal mode), the number of transmitted/received bits must be equal to the
number of clock cycles. When the start and stop bits are enabled, they must match including the added start
and stop bits.
If clock output is enabled (SMR:SCKE = 1) in master mode (ECCR:MS = 0), a synchronous clock signal is
outputted automatically during transmission/reception. Either in slave (ECCR:MS = 1) or when serial clock
output is disabled (SMR:SCKE = 0), an external clock signal for each bit of transmitted/received data must
be supplied.
The clock signal must remain at the mark level ("H") as long as it is irrelevant to transmission/reception.
When the ECCR SCDE bit is set to "1", a transmission clock signal delayed as shown in Figure 20.7-5 is
outputted. This function is required when the receiving device samples data at the rising or falling edge of
the clock signal.
Figure 20.7-5 Transmission Clock Signal Delayed (SCDE = 1)
When the SCES bit in the extended status register (ESCR) contains "1", the clock signal for the LIN-UART
is inverted, so that it samples receiving data at the falling edge of the clock signal. At this time, serial data
must have a valid value at the falling edge of the clock signal.
When the ESCR CCO bit contains "1", the serial clock output from the SCK pin is supplied continuously in
master mode. In this mode, add the start and stop bits to the data format (SSM = 1) to identify the
beginning and end of the data frame. Figure 20.7-6 illustrates how this function works.
Figure 20.7-6 Continuous Clock Supply (Mode 2)
Error detection
When the start/stop bits are disabled (ECCR:SSM = 0), only overrun errors are detected.
Transmission datawriting
Transmitting orreceiving clock
Transmission andreception data 1
DataLSB MSB
Mark level
(normal)
Transmittingclock (SCDE = 1)
Mark level
Mark level
Reception data sample edge (SCES = 0)
0 1 1 0 1 0 0
Data frame
Reception or transmission clock
Data stream (SSM = 1)(here: no parity, 1 stop bit)
ST SP
(SCES = 0, CCO = 1):
Reception or transmission clock(SCES = 1, CCO = 1):
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CHAPTER 20 LIN-UART
Communication settings for synchronous mode
The following settings are required for communication in synchronous mode.
• Baud Rate Generator Registers (BGR0/1):
Set the dedicated baud rate reload counter to a desired value.
• Serial mode register (SMR)
MD1, MD0: "10B" (mode 2)
SCKE: "1": Use of dedicated baud rate reload counter.
"0": Input external clock.
SOE: "1": Transmission/reception enabled.
"0": Only reception enabled.
• Serial control register (SCR)
RXE,TXE: Set either bit to "1".
A/D: The value of this bit is invalid because the address/data select function is not used.
CL: The value of this bit is invalid as a length of 8 bits is set automatically.
CRE: "1": Error flag is cleared and transmission/reception is stopped.
For DES--- When SSM="0"
PEN, P, SBL: Parity bit and stop bit are not used, so they are invalid.
For DES--- When SSM="1"
PEN: "1": Parity bit added/detected, "0": Parity bit unused
P: "1": Even parity, "0": Odd parity
SBL: "1": Stop bit length 2, "0": Stop bit length 1
• Serial status register (SSR)
BDS: "0": LSB first, "1": MSB first
RIE: "1": Reception interrupt enabled, "0": Reception interrupt disabled
TIE: "1": Transmission interrupt enabled, "0": Transmission interrupt disabled
• Extended communication control register (ECCR)
SSM: "0": Start bit/stop bit unused (normal),
"1": Start bit/stop bit used (extended function)
MS: "0": Master mode (serial clock output),
"1": Slave mode (Input serial clock from master device.)
Note:
To start communication, write data to the transmit data register (TDR).
To receive data, disable the serial output (SMR:SOE = "0") and write dummy data to the TDRregister.
Enabling continuous clock supply and the start/stop bits enables bidirectional communication as inasynchronous mode.
608
20.7.3 Operation of LIN Function (Operation Mode 3)
In operation mode 3, the LIN-UART operates as the LIN master and LIN slave. In operation mode 3, the data format is set to 8N1 (8-bit data, no parity, 1 stop bit), LSB-first.
Asynchronous LIN Mode Operation
Operation as LIN master
In LIN master mode, the master determines the baud rate for the entire bus and the slave is synchronized
with the master. The baud rate is fixed at the required value as the master operates after initialization.
When "1" is written to the LBR bit in the extended communication control register (ECCR), 13 to 16 bits
are outputted at the "L" level from the SOT pin. The bits serve as a LIN synch break signifying the
beginning of a LIN message.
The TDRE flag bit in the serial status register (SSR) is set to "0" and, after the break, it is set to "1" (initial
value). If the SSR TIE bit contains "1" at this time, a transmission interrupt is outputted.
The length of the LIN break transmitted is set by the LBL0/1 bits as in the following table.
A Synch field is transmitted as byte data 0x55 that follows the LIN break. To prevent a transmission
interrupt from occurring, 0x55 can be written to the TDR register after setting the LBR bit to "1" even with
the TDRE holding "0".
Operation as LIN slave
In LIN slave mode, the LIN-UART must be synchronized with the baud rate for the master. The LIN-
UART generates a reception interrupt when LIN break interrupts are enabled (LBIE = 1) even though
reception is disabled (RXE = 0). The ESCR LBD bit is set to "1" at this time.
Writing "0" to the LBD bit clears the reception interrupt request flag.
For calculation of the baud rate, the following describes an example of operations for the LIN-UART.
Upon detection of the first falling edge of Synch field, the LIN-UART starts the 8/16-bit composite timer
with its internal input signal set to "H". The internal signal goes "L" at the fifth falling edge. The 8/16-bit
composite timer must be set to the input capture mode. Also, 8/16-bit composite timer interrupts must be
enabled and set for detection at both edges. The time for which the input signal to the 8/16-bit composite
timer remains "1" is the value obtained by multiplying the baud rate by 8.
The baud rate setting value is calculated as follows:
Table 20.7-2 LIN Break Length
LBL0 LBL1 Break Length
0 0 13 bits
1 0 14 bits
0 1 15 bits
1 1 16 bits
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CHAPTER 20 LIN-UART
When the 8/16-bit composite timer has not causes a counter overflow: BGR value = (b-a) / 8 -1
When the 8/16-bit composite timer has caused a counter overflow: BGR value = (max + b-a) / 8 -1
max: Free-running timer maximum value
a: TII0 data register value after the first interrupt
b: TII0 data register value after the second interrupt
Note:
Do not set the baud rate if the new BGR value calculated based on Synch field as above in LIN slavemode involves an error over + /-15%.
For the operations of the input capture function of the 8/16-bit composite timer, see Section 12.12
"Operations of the Input Capture Function".
Interrupt and flag upon detection of LIN Synch Break
If a LIN synch break is detected in slave mode, the ESCR LIN break detection flag (LBD) is set to "1". An
interrupt occurs if LIN break interrupts have been enabled (LBIE = 1).
Figure 20.7-7 LIN Synch Break Detection and Flag Setting Timing
The above diagram shows the LIN synch break detection and flag timing.
The data framing error (FRE) flag bit in the SSR register generates a reception interrupt two bits earlier
than a LIN break interrupt (in the 8N1 format). When a LIN break is used, therefore, set RXE = "0".
LIN synch break detection works only in operation mode 3.
Figure 20.7-8 illustrates the beginning of a typical LIN message and the operation of the LIN-UART.
FRE(RXE=1)
LBD(RXE=0)
0 1 2 3 4 5 6 7 8 9 10 1112 13 14 15
Serial clock cycle #
Serial clock
Serial input(LIN bus)
Reception interrupt occurred with RXE = 1 Reception interrupt occurred with RXE = 0
610
Figure 20.7-8 LIN-UART Operation in LIN Slave Mode
LIN bus timing
Figure 20.7-9 LIN Bus Timing and LIN-UART Signals
LBD
Synch field
Serial clock
Serial input(LIN bus)
TII0 input(LSYN)
LBR cleared by the CPU
Synch break (when 14 bits are set)
bus
RXE
LBD(IRQ0)
RDRF
(SIN)
(IRQ0)
IRQ(TII0)
LIN
LBIE
RIE
No clock(Calculation frame)Previous serial clock Newly calculated serial clock
8/16-bit composite timer count
Reception Interrupt enable
LIN break startedLIN break detected, interrupt generated
IRQ cleared by the CPU (LBD → 0)
IRQ clear: 8/16-bit composite timer input capture started
IRQ clear: Baud rate calculated and setLBIE disabledReception enabled
Falling edge of start bit1 bit of receive data saved to RDR
RDR read by the CPU
RDR read by the CPU
TII0 input(LSYN)
IRQ (8/16-bit composite timer)
IRQ (8/16-bit composite timer)
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CHAPTER 20 LIN-UART
20.7.4 Serial Pins Direct Access
The transmission pin (SOT) or reception pin (SIN) can be directly accessed.
LIN-UART Pin Direct AccessThe LIN-UART allows the programmer to directly access the serial I/O pins.
The state of the serial input pin (SIN) can be read from the serial I/O pin direct access bit (ESCR:SIOP).
You can set the value of the serial output pin (SOT) arbitrarily by enabling direct write (ESCR:SOPE=1) to
the serial output pin (SOT), writing "0" or "1" to the serial I/O pin direct access bit (ESCR:SIOP), and then
enabling the serial output (SMR:SOE=1).
In LIN mode, this feature can be used for reading transmitted data or for error handling when a LIN bus
line signal is physically incorrect.
Note:
Direct access is allowed only when transmission is not in progress (with transmission shift registerempty).
Before enabling transmission (SMR:SOE = 1), write a value to the serial output pin direct access bit(ESCR:SIOP). This prevents a signal of an unexpected level from being outputted as the SIOP bitholds a previous value.
While normal read access reads the value of the SIN pin, RMW instructions reads the value of theSOT pin for the SIOP bit.
612
20.7.5 Bidirectional Communication Function (Normal Mode)
Standard serial bidirectional communication can be performed in operation mode 0 or 2. Asynchronous communication and synchronous communication can be selected in operation modes 0 and 2, respectively.
Bidirectional Communication FunctionThe settings shown in Figure 20.7-10 are required for the LIN-UART to operate in normal mode (operation
mode 0 or 2).
Figure 20.7-10 Settings for LIN-UART in Operation Mode 0 or 2
Inter-CPU connection
For bidirectional communication, interconnect two CPUs as shown in Figure 20.7-11 .
Figure 20.7-11 Connection Example for LIN-UART Mode 2 Bidirectional Communications
Sample communication procedure
The transmitting side starts communication at arbitrary timing when data to transmit becomes ready. The
receiving side returns ANS at regular intervals (for every one byte in the example) while receiving
transmitted data. Figure 20.7-12 is an example of bidirectional communication flowchart.
LBL1
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PEN P SBL CL A/D CRE RXE TXE MD1 MD0 OTO EXT REST UPCLSCKE SOE
TDREPE ORE FRE RDRF BDS RIE TIE Set conversion data (during writing)Retain reception data (during reading)
LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES LBR SCDEMS SSM RBI TBI
SCR, SMR
SSR, TDR/RDR
ESCR, ECCR
Mode 0Mode 2
Mode 0Mode 2
Mode 0Mode 2
: Using bit: Unused bit: Set "1".: Set "0".: Used when SSM = 1 (Synchronous start/stop bit mode): Bit correctly set automatically
SOT
SIN
SCK
SOT
SIN
SCKOutput Input
CPU-1 (master) CPU-2 (slave)
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CHAPTER 20 LIN-UART
Figure 20.7-12 Example of Two-way Communication Flowchart
(ANS)
NO
NO
YES
YES
Start Start
(Transmitting side) (Receiving side)
Operation mode setting(Either 0 or 2)
Communicate with 1-byte data set in TDR.
Data received
Read and process received data.
Operation mode setting(Follow transmitting side.)
Read and process received data.
Data received
Send 1-byte data.Data transmission
Data transmission
614
20.7.6 Master/Slave Type Communication Function (Multi-processor Mode)
Operation mode 1 allows communication between multiple CPUs connected in master/slave mode. It can be used as the master or slave.
Master/slave Type Communication FunctionThe settings shown in Figure 20.7-13 are required for the LIN-UART to operate in multiprocessor mode
(operation mode 1).
Figure 20.7-13 Setting of LIN-UART Operation Mode 1
Inter-CPU connection
For master/slave communication, connect one master CPU and two or more slave CPUs to two common
communication lines to make up a communication system as shown in Figure 20.7-14 . The LIN-UART
can be used with either the master or slave.
Figure 20.7-14 Connection Example for LIN-UART Master-slave Communications
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PEN P SBL CL A/D CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
PE ORE FRE RDRF TDRE BDS RIE TIE
LBIE LBD LBL1 SOPE SIOP CCO SCES LBR MS SCDE SSM RBI TBILBL0
Set conversion data (during writing)Retain reception data (during reading)
SCR, SMR
SSR, TDR/RDR
ESCR, ECCR
: Using bit: Unused bit: Set "1".: Set "0".: Bit correctly set automatically
Mode 1
Mode 1
Mode 1
SOT
SIN
SOT SIN SOT SIN
Master CPU
Slave CPU #0 Slave CPU #1
615
CHAPTER 20 LIN-UART
Function selection
For master/slave communication, select the operation mode and data transfer method as shown in Table
20.7-3 .
Communication procedure
Master/slave communication is started by the master CPU by transmitting address data. The address data,
having an A/D bit as "1", locates the slave CPU as the destination. Each slave CPU checks address data
using a program and communicates with the master CPU when the data matches an assigned address.
Figure 20.7-15 is a flowchart for master/slave communication (multiprocessor mode).
Table 20.7-3 Select of Master/Slave Communication Function
Operating modeData Parity
Synchronization Methods
Stop Bit Bit directionMaster CPU Slave CPU
Address transmit/receive Mode 1
(Send/receive A/D bit)
Mode 1 (Send/receive
A/D bit)
A/D="1" +7-or 8-bit address Not
providedAsynchronous
1 bit or 2 bits
LSB or MSB firstData transmit/
receiveA/D="0" +
7-or 8-bit data
616
Figure 20.7-15 Flowchart for Master/Slave Communications
NO
YES
YES
NO
NO
NO
YES
YES
YES
NO
(Master CPU) (Slave CPU)
Start Start
Set to operation mode 1. Set to operation mode 1.
Set SIN pin for serial data input.
Set SOT pin for serial data output.
Set SIN pin for serial data input.
Set SOT pin for serial data output.
Set 7 or 8 data bits.Set 1 or 2 stop bits.
Set 7 or 8 data bits.Set 1 or 2 stop bits.
Set "1" to A/D bit. Enable transmission/reception.
Enable transmission/reception.
Send address to slave.
Receive byte.
A/D bit = 1
Set "0" to A/D bit.
Communicate with slave CPU
Terminating communications?
Communicate with another slave CPU
Disable transmission/reception.
End
Slave address matched?
Communicate with master CPU.
Terminating communications
617
CHAPTER 20 LIN-UART
20.7.7 LIN Communication Function
For LIN-UART communication, the LIN device can be used in the LIN master system or LIN slave system.
LIN Master/Slave Mode Communication FunctionThe settings shown in Figure 20.7-16 are required for the LIN-UART to operate in LIN communication
mode (operation mode 3).
Figure 20.7-16 Setting of LIN-UART Operation Mode 3 (LIN)
LIN device connection
Figure 20.7-17 illustrates a communication system comprising one LIN master and one LIN slave.
The LIN-UART can serve as the LIN master or LIN slave.
Figure 20.7-17 Example of LIN Bus System Communication
LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES LBR MS SCDE SSM RBI TBI
PEN P SBL CL A/D CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
PE ORE FRE RDRF TDRE BDS RIE TIE Set conversion data (during writing)Retain reception data (during reading)
Mode 3
Mode 3
Mode 3
: Using bit: Unused bit: Set "1". : Set "0". : Bit correctly set automatically
SOT
SIN
SOT
SIN
LIN master Transceiver Transceiver LIN slave
LIN bus
618
20.7.8 Example LIN Communications Flowchart for LIN-UART (Operating Mode 3)
Given below is an example of a LIN-UART LIN communication flowchart.
LIN Master Device
Figure 20.7-18 LIN Master Flowchart
Y
N
N
Y
Y
N
Y N
Start
Initialization: Set operation mode to 3.Enable serial data output and set baud rate.Set Synch break length.TXE = 1, TIE = 0, RXE = 1, RIE = 1
Message?
RXE = 0Synch break interruption permissionSync break transmission: ECCR: LBR = 1Synch field transmission: TDR = 0x55
LBD = 1Synch Break interrupt
ID Field reception *1
Enable reception.LBD = 0Synch Break disables interrupt.
There is no error? Error handling*2
Data fieldreception?
Set transmit data 1.TDR = Data 1Transmission Interruptenable
Wake up?(0x80 reception)
Synch field reception *1
Set Identify Field: TDR = lD
RDRF = 1Reception Interrupt
RDRF = 1Reception Interrupt
(Reception) (Transmission)
RDRF = 1Reception Interrupt
Data 1 reception *1
Data N reception *1
RDRF = 1Reception Interrupt
Set transmit data N.TDR = Data NDisable transmission interrupts.
Data 1 reception *1
Data 1 read
Data N reception *1
Data N read
TDRE = 1Transmission Interrupt
RDRF = 1Reception Interrupt
RDRF = 1Reception Interrupt
* 1: Handle an error if it occurs. * 2:-If the FRE or ORE flag becomes "1", write "1" to the SCR:CRE bit to clear the error flag. -If the ESCR:LBD bit becomes "1", execute a LIN-UART reset. (Note) Perform error detection in each process and take appropriate action.
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CHAPTER 20 LIN-UART
LIN Slave Device
Figure 20.7-19 LIN Slave Flowchart (1/2)
Y
N
N
Y
Y
N
Y N
Y
N
Start
Initialization: Set operation mode to 3.Enable serial data output.TXE = 1, TIE = 0, RXE = 0, RIE = 1Connect LIN-UART with 8/16-bit composite timer.
Read 8/16-bit composite timer data.Adjust baud rate.Enable reception.Clear 8/16-bit composite timer interrupt flag.Disable 8/16-bit composite timer interrupts.
LBD = 1Synch Break interrupt
Identify Field reception *1
Disable reception.Enable 8/16-bit composite timer interrupts.Synch Break interruption permission
There is no error? Error handling*2
Data Fieldreception?
Set transmit data 1.TDR = Data 1Transmission Interruptenable
Read 8/16-bit composite timer data.Clear8/16-bit composite timer interrupt flag.
TII0 interrupt
TII0 interrupt
(Reception) (Transmission)
RDRF = 1Reception interrupt
Data 1 reception *1
Data N reception *1
RDRF = 1Reception interrupt
Set transmit data N.TDR = Data NDisable transmission interrupts
Data 1 reception*1
Data 1 read
Data N reception*1
Data N readDisable reception.
TDRE = 1Transmission Interrupt
RDRF = 1Reception Interrupt
RDRF = 1Reception Interrupt
* 1: Handle an error if it occurs.* 2:-If the fre or ore flag becomes "1", write "1" to the SCR:CRE bit to clear the error flag.
-If the ESCR:LBD bit becomes "1", execute a LIN-UART reset. Note: Perform error detection in each process and take appropriate action.
Clear Synch Break detectionECCR: LBD = 0Synch Break interrupt disabled
RDRF = 1Reception Interrupt
Sleep mode?
Wakeup received?
Wakeup sent?
Disable reception.
Send wakeup code
620
20.8 Notes on Using LIN-UART
Given below are notes on using the LIN-UART.
Notes on Using LIN-UART
Enabling operations
The LIN-UART has the TXE (transmission) and RXE (reception) enable bits in the serial control register
(SCR). Transmission and reception are both disabled by default. You have to enable the operations before
transfer can be performed. You can disable the operations to stop transfer as required.
Communication mode setting
Set the communication mode while the LIN-UART is not operating. If you set the mode during
transmission/reception, the currently transmitted/received data is not guaranteed.
Transmission interrupt enable timing
As the transmit data empty flag bit (SSR:TDRE) has a default (initial) value of "1" (no transmit data,
transmit data write enabled), a transmission interrupt request occurs as soon as transmission interrupt
requests are enabled (SSR:TIE = 1). To prevent this, be sure to set transmit data before setting the TIE flag
to "1".
Changing operation settings
Reset the LIN-UART after changing its settings such as the addition of the start/stop bits and change of the
data format.
Correct operation settings are not guaranteed if you reset the LIN-UART (SMR:UPCL=1) while setting the
LIN-UART serial mode register (SMR). After setting the bit in the LIN-UART serial mode register (SMR),
reset the LIN-UART (SMR:UPCL = 1) again.
Use of LIN function
Although the LIN features are available in mode 3, the LIN format is automatically set in mode 3 (8-bit
length, no parity, 1 stop bit, LSB-first).
While the LIN break transmit bit length is variable, the detection bit length is fixed at 11 bits.
LIN slave settings
To start LIN slave mode, be sure to set the baud rate before receiving the first LIN synch break to detect the
minimum length of 13 bits for LIN synch breaks without fail.
Bus idle function
The bus idle function is not available in synchronous mode 2.
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CHAPTER 20 LIN-UART
A/D bit (serial control register (SCR): address/data format select bit)
When using the A/D bit, pay attention to the following points:
The A/D bit is used to select the address/data for transmission when written and to read the A/D bit value
received last when read. Internally, the A/D bit values for transmission and reception are stored in different
registers.
The transmission A/D bit value is read when RMW instructions are used. When any other bit in the SCR
register is bit-accessed, therefore, a wrong value may be written to the A/D bit.
That is why the A/D bit must be set at the last access to the SCR register before transmission. Otherwise,
byte access to write to the SCR can work around the above problem.
LIN-UART software reset
When the TXE bit in the serial control register (SCR) contains "0", execute a LIN-UART software reset
(SMR:UPCL = 1).
Synch break detection
If serial input becomes "0" in 11 bits or more in length in mode 3 (LIN mode), the LBR bit in the extended
status control register (ESCR) is set to "1" (Synch Break detected) and the LIN-UART waits for Synch
Field. If serial input becomes "0" in 11 bits or more except at a Synch Break, the LIN-UART recognizes
that the Synch Break has been inputted (LBD = 1) and waits for Synch Field.
In this case, execute a LIN-UART reset (SMR:UPCL = 1).
622
CHAPTER 21
I2C
This chapter describes the I2C functions and operation.
21.1 Overview of I2C
21.2 I2C Block Diagram
21.3 I2C Channel
21.4 I2C Register
21.5 I2C Interrupt
21.6 Explanation of Operation of I2C
21.7 Notes on Using I2C
623
CHAPTER 21 I2C
21.1 Overview of I2C
The I2C interface supports the I2C bus specification published by Philips. The interface supports send and receive in master and slave mode, detection of arbitration lost, detection of slave address and general call address, generation and detection of start and stop conditions, bus error detection, and an MCU standby wakeup function.
Functions of I2C
The I2C interface is a two-wire, bi-directional bus consisting of a serial data line (SDA) and serial clock
line (SCL). The devices connected to the bus via these two wires can exchange data, and each device can
operate as a sender or receiver in accordance with their respective functions based on the unique address of
each device. Furthermore, the interface establishes a master/slave relationship between devices.
Also, the I2C interface can connect multiple devices provided the bus capacitance does not exceed the
upper limit of 400pF. The I2C interface is a true multi-master bus with collision detection and a
communication control protocol that prevent loss of data even if more than one master attempts to start a
data transfer at the same time.
The communication control protocol ensures that only one master is able to take control of the bus at a
time, even if multiple masters attempt to take control of the bus simultaneously, without messages being
lost or data being altered. Multi-master means that more than one master can attempt to take control of the
bus at the same time without causing messages to be lost.
Also, the I2C interface includes a function to wakeup the MCU from standby mode.
Figure 21.1-1 I2C Interface Configuration
SDA
SCL
Microcontroller A LCD driverStaticRAM/E2PROM
Note:External pull-up is required
Microcontroller BGate array A/D converter
624
21.2 I2C Block Diagram
I2C consists of the following block.• Clock selector• Clock divider• Shift clock generator• Start stop condition generation circuit• Start/stop condition detector• Arbitration lost detection circuit• Slave address comparison circuit• IBSR register• IBCR register (IBCR0, IBCR1)• ICCR register• IAAR register• IDDR register
625
CHAPTER 21 I2C
I2C Block Diagram
Figure 21.2-1 I2C Block Diagram
F2
MC
8F
X
inte
rna
l bu
s
SCC
BEIE
MSS
DACKE
GACKE
INTE
INT
BER
IBSR
Sync
I2C enable
ICCR
EN
CS2CS1CS0
RSC
LRB
TRX
FBT
BB
IBCR1
8
5DMBP
CS4CS3
6 7 8
224
AAS
GCA
IBSR
IBCR0
38 98 128 256 512
ALF
ALE
SPF
SPE
AACKX
INTS
WUF
WUE
Machine clock
Clock driver 2
Clock driver 1
Clock selecter 2
Clock selecter 1
Shift clock generator
Shift clockedge
Start/stop condition
detection circuit
Bus busy
Repeat start
Last bitTransmission/Reception
Error
First byte
Arbitration lost detection circuit
Transfer interrupt
EndStart
MasterACK enabledGC-ACK enabledAddress ACK enabled
INI timing selection
Start/stop condition
generation circuit
SlaveGeneral call
IDDR register
Slave address comparison circuit
IAAR register
SCL I Line
SDA Line
Stop interrupt
626
Clock selector, clock divider, and shift clock generator
This circuit uses the machine clock to generate the shift clock for the I2C bus.
Start stop condition generation circuit
When the bus is idle (SCL and SDA are at the "H" level), a master starts communications by transmitting a
start condition. When SCL = "H", a start condition is generated by changing the SDA from "H" to "L".
Communication can be ended by the master generating a stop condition. When SCL = "H", a stop condition
is generated by changing the SDA from "L" to "H".
Start/stop condition detector
This circuit detects start/stop condition for data transfer.
Arbitration lost detection circuit
The interface circuit supports multi-master systems. If more than one master and this I2C interface attempt
to start transmitting at the same time, the arbitration lost condition occurs. When the SDA line goes to the
"L" level to send logic level "1", this is treated as arbitration lost. In this case, IBCR0:ALF goes to "1" and
the master changes to a slave.
Slave address comparison circuit
The slave address is received after the start condition and compared with the own slave address. The
address is a 7-bit value followed by a data direction (R/W) bit in the eighth bit. If the received address
matches the own slave address, and acknowledge is sent.
IBSR register
The IBSR register shows the status of the I2C interface.
IBCR registers (IBCR0, IBCR1)
The IBCR register selects the operating mode, enables or disables the interrupts, enables or disables
acknowledge, enables or disables acknowledge for a general call, and enables or disables the function to
wakeup the MCU from standby.
ICCR register
The ICCR register is used to enable I2C interface operations and select the shift clock frequency.
IAAR register
The IAAR register is used to set the slave address.
IDDR register
The IDDR register stores the send or receive shift data or address. When sending, the data or address
written to this register is transmitted over the bus MSB-first.
627
CHAPTER 21 I2C
I2C interface interrupt source
Transfer Interrupt:
The I2C interface generates interrupt requests in the following two cases.
• When a bus error occurs and the bus error interrupt enable bit is enabled (IBCR1:BEIE= "1").
• When a data transfer completes and the transfer completion interrupt enable bit is enabled(IBCR1:INTE= "1").
Stop Interrupt:
The I2C interface generates interrupt requests in the following three cases.
• When a start condition is detected and the standby mode wakeup enable bit is enabled (IBCR0:WUE="1").
• When a stop condition is detected and the stop detection interrupt is enabled (IBCR0:SPE= "1").
• When arbitration lost is detected and the arbitration lost interrupt is enabled (IBCR0:ALE= "1").
628
21.3 I2C Channel
This section describes the I2C channels.
I2C Channel
Table 21.3-1 and Table 21.3-2 list the correspondence among the I2C channels, the pins and registers.
Note:
As the pins used by the I2C interface are shared with general-purpose I/O ports, enable I2Coperation (ICCR:EN= "1") and set the corresponding port direction register (DDR) bits to "1" (input)
to use these pins for the I2C.
Table 21.3-1 I2C Pin
Channel Pin Name Pin Function
0SCL0SDA0
I2C-Bus I/O1
SCL1SDA1
Table 21.3-2 I2C Register
Channel Register Name Corresponding Register (Name in Specifications)
0
IBCR00 IBCR0: I2C bus control register 0
IBCR10 IBCR1: I2C bus control register 1
IBSR0 IBSR: I2C bus status register
IDDR0 IDDR: I2C data register
IAAR0 IAAR: I2C address register
ICCR0 ICCR: I2C clock control register
1
IBCR01 IBCR0: I2C bus control register 0
IBCR11 IBCR1: I2C bus control register 1
IBSR1 IBSR: I2C bus status register
IDDR1 IDDR: I2C data register
IAAR1 IAAR: I2C address register
ICCR1 ICCR: I2C clock control register
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CHAPTER 21 I2C
21.4 I2C Register
This section describes the I2C registers.
I2C Register
Figure 21.4-1 I2C Register
IBSR
IBCR1
R(RM1),W0
R/W0
R/W0
R/W0
R(RM1),W0
R/W0
Bit number
BER MSSD ACK EGACKE INTE INT
A6 A5 A4 A3 A2 A1 A0
IDDR
Bit number
D7 D6 D5 D4 D3 D2 D1 D0
R/W0
BEIE
IAAR
R/WX0
BB
R/WX0
RSC
R/WX0
LRB
R/WX0
TRX
R/WX0
AAS
R/WX0
GCA
R/WX0
FBT
R0,W0
SCC
R0/WX 0
ICCR
Bit number
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
DMBP EN CS4 CS3 CS2 CS1 CS0
R0/WX0
IBCR0
Initial valueRead/write
Initial valueRead/write
Initial valueRead/write
Initial valueRead/write
Initial valueRead/write
Initial valueRead/write
Bit number
R/W0
SPE
R(RM1),W0
WUF
R/W0
WUESPF
Bit number
Bit number
ALEALF
R/W0
AACKX
R/W 0
INTS
R/W0
R0/WX0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
I2C bus control register 0
R(RM1),W00
R(RM1),W
R/ W: Read and write enabled (Reading value is writing value.)R(RM1),W: Read and write enabled (Reading and writing values are different and 1 is read at read-modify-write instruction.)
R0,W: Write only (Writing is enabled and reading value is 0.)
R/WX: Read only (Reading is enabled and writing has no effect to operation.)
R0/WX: Undefined bit (Reading value is 0 and writing has no effect to operation.)
7 5 3 16 4 2 0
7 5 3 16 4 2 0
7 5 3 16 4 2 0
7 5 3 16 4 2 0
7 5 3 16 4 2 0
7 5 3 16 4 2 0
I2C bus control register 1
I2C bus status register
I2C data register
I2C address register
I2C clock control register
630
21.4.1 I2C Bus Control Register (IBCR0, IBCR1)
The I2C bus control register selects the operating mode, enables or disables the interrupts, enables or disables acknowledge, enables or disables acknowledge for a general call, and enables or disables the function to wakeup the MCU from standby.
I2C Bus Control Register 0 (IBCR0)
Figure 21.4-2 I2C Bus Control Register 0 (IBCR0)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
AACKX INTS ALF ALE SPF SPE WUF WUE 00000000B
R/W R/W R(RM1),W R/W R(RM1),W R/W R(RM1),W R/W
SPE
0
1
R/W : R(RM1),W :
WUE
0
1
WUF
0
1
SPF
0
1
ALE
0
1
ALF
0
1
INTS
0
1
AACKX
0
1
Initial value
Enable bit for function to wakeup MCU from standby mode
Disable function to wakeup MCU from standby mode in stop/watch mode
Enable function to wakeup MCU from standby mode in stop/watch mode
Request flag bit for interrupt to wakeup MCU from standby mode
Read Write
Start condition undetected
Start condition detected
Clear
No change
Enable bit for stop detection interrupt
Disable stop detection interrupt
Enable bit for stop detection interrupt
Request flag bit for stop detection interrupt
Read Write
Clear
No change
Stop condition undetected
Stop condition detected
Enable bit for arbitration lost interrupt
Disable arbitration lost interrupt
Enable arbitration lost interrupt
Read Write
Clear
No change
Request flag bit for arbitration lost interrupt
arbitration lost undetected
arbitration lost detected
Timing selection for transfer completion flag (INT) when data received
Set INI by ninth SCL cycle
Set INI by eighth SCL cycle
Address acknowledge disable bit
Enable address ACK
Disable address ACK
Read and write enabled(1 is read at RMW instruction)
Initial value
Read and write enabled
:
631
CHAPTER 21 I2C
Table 21.4.1-1 I2C Bus Control Register 0 (IBCR0)
Bit Name Function
Bit7AACKX:Address acknowledge disable bit
This bit controls the address ACK when the first byte is sent.• Writing "0" to this bit causes the address ACK to be output automatically. (The address ACK is
returned automatically if the slave address matches.)• Writing "1" to this bit disables address ACK output.
Bit6
INTS:Timing selection for transfer completion flag (INT) when data received
This bit selects the timing of the transfer completion interrupt (IBCR1:INT) when data is received. (Only when IBSR:TRX=0 and IBCR1:FBT=0)• Writing "0" to this bit causes the transfer completion interrupt (IBCR1:INT) to be generated on the
eighth SCL cycle.• Writing "0" to this bit causes the transfer completion interrupt (IBCR1:INT) to be generated on the
ninth SCL cycle.Note: The transfer completion interrupt (IBCR1:INT) is always generated on the ninth SCL cycle for
cases other than data reception (IBCR1:TRX=1 or IBCR1:FBT=1).• If the data ACK depends on the content of the received data (such as packet error checking
used by SM bus), the data ACK is controlled by setting the data ACK enable bit (IBCR 1: DACKE) after 1 is written to this bit (for example, by previous transfer completion interrupt) to read latest received data.
The latest data ACK (IBSR:LRB) can be read after the ACK has been received (IBSR:LRB must be read during the transfer completion interrupt triggered by the ninth SCL cycle.)Accordingly, if ACK is read when this bit is "1", you must write "0" to this bit in the transfer completion interrupt triggered by the eighth SCL cycle so that another transfer completion interrupt will be triggered by the ninth SCL cycle.
Bit5
ALF:Request flag bit for the arbitration lost interrupt
This bit is used to detect when arbitration is lost.• An arbitration lost interrupt request is generated if this bit and the IBCR0:ALE bit are both "1".• This bit goes to "1" in the following cases:
- When arbitration lost is detected during sending of data or address as master- When the bus is in use by another system when "1" is written to the IBCR1:MSS bit. However, the bit
is not set when "1" is written to the MSS bit after AACK or GCAK is returned when operating as a slave.
• This bit goes to "0" in the following cases:- If IBSR:BB=0 when "0" is written to the IBCR0:ALF bit.- When "0" is written to the IBCR1:INT bit to clear the transmission complete flag.
• Writing "1" to this bit does not change the value and has no effect on the operation.• Read as "1" by read-modify-write operations.
Bit4
ALE:Enable bit for the arbitration lost interrupt
This bit enables or disables the arbitration lost interrupt.• An arbitration lost interrupt request is generated if this bit and the IBCR0:ALF bit are both "1".• Writing "0" to this bit disables the arbitration lost interrupt.• Writing "1" to this bit enables the arbitration lost interrupt.
Bit3SPF:Request flag bit for the stop detection interrupt
This bit is used to detect a stop condition.• A stop detection interrupt request is generated if this bit and the IBCR0:SPE bit are both "1".• This bit goes to "1" if a valid stop condition occurs when the bus is busy.• Writing "0" clears the bit (changes the value to "0").• Writing "1" to this bit does not change the value and has no effect on the operation.• Read as "1" by read-modify-write operations.
Bit2SPE:Enable bit for the stop detection interrupt
This bit enables or disables the stop detection interrupt.• A stop detection interrupt request is generated if this bit and the IBCR0:SPE bit are both "1".• Writing "0" to this bit disables the stop detection interrupt.• Writing "1" to this bit enables the stop detection interrupt.
632
Note: The AACKX, INTS, and WUE bits of the IBCR0 register go to "0" and cannot be written to when the I2C is disabled (ICCR:EN=0) or a bus error occurs (IBSR:BER=1).
Bit1
WUF:Request flag bit for interrupt used to wakeup the MCU from standby mode
This bit is used to detect when waking up the MCU from a standby mode (stop or watch mode).• A wakeup interrupt request is generated if this bit and the IBCR0:WUE bit are both "1".• This bit goes to "1" if a start condition is detected while the wakeup function is enabled
(IBCR0:WUE=1).• Writing "0" clears the bit (changes the value to "0").• Writing "1" to this bit does not change the value and has no effect on the operation.• Read as "1" by read-modify-write operations.
Bit0
WUE:Enable bit for the function to wakeup the MCU from standby mode
This bit enables or disables the function to wakeup the MCU from standby mode (stop or watch mode).• Writing "0" to this bit disables the wakeup function.• Writing "1" to this bit enables the wakeup function.• If a start condition is detected during stop or watch mode when this bit is "1", a wakeup interrupt
request is generated to start I2C operation.Note: Write "1" to this bit immediately prior to changing the MCU to stop or watch mode. To ensure
that I2C operation can restart immediately after the MCU wakes up from stop or watch mode, clear (write "0") this bit as soon as possible.When a wakeup interrupt occurs, the MCU wakes up after the oscillation stabilization delay time elapses.Therefore, to prevent the data loss immediately after wakeup, the SCL is generated as first cycle and the first bit must be received as a data after 100 µs (when minimum oscillation stabilization
wait time is assumed 100 µs) from the wakeup due to start of I2C transmission (detection for falling edge of SDA).
During MCU standby modes, the status flags, state machine, and I2C bus outputs for the I2C function retain the states they had prior to entering standby mode. To prevent a hang-up on the
overall I2C bus system, confirm that IBSR:BB=0 before entering standby mode.The wakeup function does not support the case when the MCU goes to stop or watch mode when IBSR:BB=1. If the MCU does go to stop or watch mode when IBSR:BB=1, a bus error will occur when the start condition is detected.The wakeup function is valid only in stop/watch mode in MCU. (For example, in addition to the oscillation stabilization wait time, the PLL oscillation stabilization wait time adds in the PLL stop mode, the time after wakeup to start communication becomes longer than stop/watch mode.)
Table 21.4.1-1 I2C Bus Control Register 0 (IBCR0)
Bit Name Function
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CHAPTER 21 I2C
I2C Bus Control Register 1 (IBCR1)
Figure 21.4-3 I2C Bus Control Register 1 (IBCR1)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
BER BEIE SCC MSS DACKE GACKE INTE INT
R(RM1),W R/W R0,W R/W R/W R/W R/W R(RM1),W
GACKE
0
1
BEIE
0
1
BER
0
1
DACKE
0
1
MSS
0
1
SCC
0
1
INTE
0
1
INT
0
1
Initial value
00000000B
Transfer termination interrupt request flag bit
Read Write
Clear
No change
Does not terminate data transfer
Terminate 1-byte data transfer (including acknowledge)
Enable bit for transfer complete interrupt
Disable data transfer complete interrupt request
Enable data transfer complete interrupt request
Enable bit for general call address acknowledge
Disable general call address ACK
Enable general call address ACK
Data acknowledge enable bit
Disable data ACK
Enable data ACK
Master/Slave selection bit
Select slave mode
Select master mode
Start condition generation bit
Read Write
No changeAllways "0"
Generate repeated start condition of master mode
Bus error interrupt request enable bit
Disable bus error interrupt request
Enable bus error interrupt request
Bus error interrupt request flag bit
Write
No change
Read
ClearNo bus error
Detect invalid start/stop condition
R/W : R(RM1),W : Read and write enabled
(1 is read at RMW instruction)
Initial value
Read and write enabled
:
R0, W : Write only (Reading is always 0.)
634
Table 21.4.1-1 I2C Bus Control Register1 (IBCR1)
Bit Name Function
Bit7BER:Bus error interrupt request flag bit
This bit is used to detect bus errors.• A bus error interrupt request is generated if this bit and the IBCR1:BEIE bit are both "1".• This bit goes to "1" when an invalid start or stop condition is detected.• Writing "0" clears the bit (changes the value to "0").• Writing "1" to this bit does not change the value and has no effect on the operation.• Read as "1" by read-modify-write operations.
• When this bit goes to "1", ICCR:EN goes to "0", I2C goes to halt mode, and data transfer ends.
Bit6BEIE:Bus error interrupt request enable bit
This bit enables or disables the bus error interrupt• A bus error interrupt request is generated if this bit and the IBCR1:BER bit are both "1".• Writing "0" to this bit disables the bus error interrupt.• Writing "1" to this bit enables the bus error interrupt.
Bit5SCC:Start condition generation bit
When operating in master mode, this bit triggers a repeated start condition to restart communications.• Writing "1" to this bit when operating in master mode generates a repeated start condition.• Writing "0" to this bit has no effect on the operation.• Reading always returns "0".Note: Do not set IBCR1:SCC=1 and IBCR1:MSS=0 simultaneously. Writing "1" to this bit is
ignored (no start condition is generated) if IBCR1:INT=0. Also, when IBCR1:INT=1, this bit has priority and the start condition is generated if you write "1" to this bit and "0" to the IBCR1:INT bit at the same time.
Bit4MSS:Master/slave selection bit
This bit selects master mode or slave mode.
• Writing "1" to this bit while the I2C bus is in the idle state (IBSR:BB=0) selects master mode, generates a start condition, and then starts address transfer.
• Writing "0" to this bit while the I2C bus is in the busy state (IBSR:BB=1) selects slave mode, generates a stop condition, and then ends data transfer.
• If arbitration lost occurs during data or address transfer in master mode, this bit is cleared to "0" and the mode changes to slave mode.
Note: Do not set IBCR1:SCC=1 and IBCR1:MSS=0 simultaneously. Writing "0" to this bit is ignored if IBCR1:INT=0. Also, when IBCR1:INT=1, this bit has priority and the stop condition is generated if you write "0" to this bit and "0" to the IBCR1:INT bit at the same time.The IBCR0:ALF bit is not set if you write "1" to the MSS bit during slave mode sending or receiving. Do not write "1" to the MSS bit during slave mode sending or receiving.
Bit3DACKE:Data acknowledge enable bit
This bit controls data acknowledge for data reception.• Writing "0" to this bit disables data acknowledge output.• Writing "1" to this bit enables data acknowledge output. In this case, data acknowledge is
outputted on the ninth SCL cycle during data reception when operating in master mode. In slave mode, data acknowledge is outputted on the ninth SCL cycle only if address acknowledge is already outputted.
Bit2GACKE:Enable bit for general call address acknowledge
This bit controls general call address acknowledge.• Writing "1" to this bit causes a general call address acknowledge to be outputted if a general call
address (00H) is received during master or slave mode.
• Writing "0" to this bit disables output of the general call address acknowledge.
Bit1INTE:Enable bit for the transfer complete interrupt
This bit enables or disables the transfer complete interrupt.• Writing "0" to this bit disables the transfer complete interrupt.• Writing "1" to this bit enables the transfer complete interrupt.• A transfer complete interrupt request is generated if this bit and the IBCR1:INT bit are both "1".
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CHAPTER 21 I2C
Note: Do not modify the value of the interrupt request enable bit (IBCR1:BEIE) at the same time as writing "0" to clear the interrupt request flag (IBCR1:BER).All bits in IBCR1 except the BER and BEIE bits are cleared to "0" when operation is disabled (ICCR:EN=0) or a bus error occurs (IBSR:BER=1).
Bit0INT:Transfer termination interrupt request flag bit
This bit is used to detect transfer completion.• A transfer complete interrupt request is generated if this bit and the IBCR1:INTE bit are both
"1".• This bit goes to "1" when transfer of an address or data byte completes (whether or not this
includes the acknowledge is controlled by the IBCR0:INTS setting) if any of the following four conditions are satisfied.- Bus master mode- MCU is addressed when in slave mode- General call address received- Arbitration lost detected
• This bit goes to "0" in the following cases:- "0" written to bit.- Repeated start condition (IBCR1:SCC=1) or stop condition (IBCR1:MSS=0) occurred in
master mode.• Writing "1" to this bit does not change the value and has no effect on the operation.• Read as "1" by read-modify-write operations.• The SCL line remains at "L" while this bit is "1".• Writing "0" to clear the bit (change the value to "0") releases the SCL line to enable transmission
for the next byte of data.Note: If "1" is written to IBCR1:SCC when this bit is "0", the IBCR1:SCC bit has priority and the
start condition is generated.If "0" is written to IBCR1:MSS when this bit is "0", the IBCR1:MSS bit has priority and the stop condition is generated.If IBCR0:INTS=1 when data is received, this bit goes to "1" after transfer of one byte of data completes (not including acknowledge). In other cases, this bit goes to "1" after sending or receiving one byte of data/address completes including the acknowledge.
Table 21.4.1-1 I2C Bus Control Register1 (IBCR1)
Bit Name Function
636
21.4.2 I2C Bus Status (IBSR)
The IBSR register contains the status of the I2C interface.
I2C Bus Status Register (IBSR)
Figure 21.4-4 I2C Bus Status Register (IBSR)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
BB RSC --- LRB TRX AAS GCA FBT
R/WX R/WX R0/WX R/WX R/WX R/WX R/WX R/WX
AAS
0
1
RSC
0
1
BB
0
1
TRX
0
1
LRB
0
1
GCA
0
1
FBT
0
1
Initial value00000000B
First byte detection bit
The received data is other than first byte at data reception
The received data is first byte at data reception (address data)
General call address detection bit
Does not receive general call address (00H) at slave
Receive general call address (00H) at slave
Addressing detection bit
No addressing at slave
Addressing at slave
Data transfer start bit
Reception mode
Transmission mode
Acknowledge stored bit
Detect acknowledge by ninth shift clock
Does not detect acknowledge by ninth shift clock
Repeated start condition detection bit
Does not detect repeated start condition
Detect repeated start condition in the bus use
Bus busy bit
Bus is idle state
Bus is busy state
- :
Initial value
Unused
:
R/WX : Read only (Writing has no effect on the operation.)R0/WX : Undefined bit (Reading is always 0.)
(Writing has no effect on the operation.)
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CHAPTER 21 I2C
Table 21.4.2-1 I2C Bus Status Register (IBSR)
Bit Name Function
Bit7BB:Bus busy bit
This bit indicates the bus status.• This bit goes to "1" when a start condition is detected.• This bit goes to "0" when a stop condition is detected.
Bit6RSC:Start condition detection repeatedly bit
This bit is used to detect repeated start conditions.• This bit goes to "1" when a repeated start condition is detected.• This bit goes to "0" in the following cases:
- When "0" is written to IBCR1:INT.- When operating as a slave, the slave address does not match the address set in IAAR.- When operating as a slave, the slave address matches the address set in IAAR but
IBCR0:AACKX=1.- When operating as a slave, the general call address is received but IBCR1:GACKE=0.- When a stop condition is detected.
Bit5 Unused bitRead value is always "0".Writing has no effect on the operation.
Bit4LRB:Acknowledge stored bit
This bit saves the value of the SDA line at the ninth shift clock when transferring a data byte.• This bit goes to "1" when no acknowledge is detected (SDA=H).• This bit goes to "0" in the following cases:
- When acknowledge is detected (SDA=L)- When a start or stop condition is detected.
Note: It follows from the above that this bit must be read after the ACK. (Read in the transfer complete interrupt for the ninth SCL cycle.) Accordingly, if ACK is read when the IBCR0:INTS bit is "1", you must write "0" to the IBCR0:INTS bit in the transfer completion interrupt triggered by the eighth SCL cycle so that another transfer completion interrupt will be triggered by the ninth SCL cycle.
Bit3TRX:State bit of data transfer
This bit indicates the data transfer mode.• This bit goes to "1" when data transfer is performed during transfer mode.• This bit goes to "0" in the following cases:
- Data transfer occurs during receive mode- NACK is received during slave send mode
Bit2AAS:Addressing detection bit
This bit indicates that the MCU has been addressed during slave mode.• This bit goes to "1" if the MCU is addressed during slave mode.• This bit goes to "0" when a start or stop condition is detected.
Bit1GCA:General call address detection bit
This bit is used to detect the general call address.• This bit goes to "1" in the following cases:
- When the general call address (00H) is received during slave mode.
- When the general call address (00H) is received during master mode and IBCR1:GACKE=1.
- Arbitration lost is detected while sending the second byte of the general call address in master mode.
• This bit goes to "0" in the following cases:- When a start or stop condition is detected.- Arbitration lost is not detected while sending the second byte of the general call address in
master mode.
Bit0FBT:First byte detection bit
This bit is used to detect the first byte.• This bit goes to "1" when a start condition is detected.• This bit goes to "0" in the following cases;
- When "0" is written to the IBCR1:INT bit.- When operating as a slave, the slave address does not match the address set in IAAR.- When operating as a slave, the slave address matches the address set in IAAR but
IBCR0:AACKX=1.- When operating as a slave, the general call address is received but IBCR1:GACKE=0.
638
21.4.3 I2C Data Register (IDDR)
The IDDR register is used to set the data or address to send and to store the received data or address.
I2C Data Register (IDDR)
Figure 21.4-5 I2C Data Register (IDDR)
In send mode, each bit of the data or address value written to the register is shifted to the SDA line, starting
with the MSB. Writing side of this register consists of double buffer if the bus is in use (IBSR:BB=1), the
write data is loaded to the 8-bit shift register when the current data transfer complete interrupt is cleared
(Writing "0" to IBCR:INT bit) or when repeated start condition is generated (Writing "1" to IBCR:SCC
bit). Each bit of the shift register data is outputted (shifted) to the SDA line. Note that writing to this
register has no effect on the current data transfer. However, in slave mode, the operation is performed after
confirming the address.
The received data or address can be read from this register during the transfer complete interrupt
(IBCR:INT=1). However, as reading reads the value of the serial transfer register directly, the receive data
is only valid while IBCR1:INT=1.
7 6 5 4 3 2 1 0
IDDR
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
D7 D6 D5 D4 D3 D2 D1 D0
R/W: Read and write enabled
I2C data register
Initial value
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CHAPTER 21 I2C
21.4.4 I2C Address Register (IAAR)
The IAAR register is used to set the slave address.
I2C Address Register (IAAR)
Figure 21.4-6 I2C Address Register (IAAR)
The I2C address register (IAAR) is used to set the slave address. An address acknowledge is sent to the
master on the ninth shift clock in the following cases.
• The slave address matches the address in IAAR and IBCR0:AACKX=0.
• The general call address (00H) is received and IBCR1:GACKE=1.
IAAR
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
A6 A5 A4 A3 A2 A1 A0
R0/WX 0
7 6 5 4 3 2 1 0I2C address register
Initial value
R/W: Read and write enabledR0/WX : Undefined bit (Reading is always 0.)
(Writing has no effect on the operation.)
- : Unused
640
21.4.5 I2C Clock Control Register (ICCR)
The ICCR register is used to enable I2C operation and select the shift clock frequency.
I2C Clock Control Register (ICCR)
Figure 21.4-7 I2C Clock Control Register (ICCR)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DMBP EN CS3 CS2 CS1 CS0
R/W R0/WX R/W R/W R/W R/W R/W R/W
CS4 CS3
0 0 5
6
7
8
EN
0
1
DMBP
0
1
CS2 CS1 CS0
0 0 0 4
8
22
38
98
128
256
512
Initial value00000000BCS4---
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
Clock 2 selection bit (divider n)
1
1
0
0
1
1
Clock 1 selection bit (divider m)
I2C operation enable bit
Enable I2C operation
Disable I2C operation
Divider m bypass bit
Disable bypass
Bypass divider mR/W: Read and write enabledR0/WX : Undefined bit (Reading is always 0.)
(Writing has no effect on the operation.)
- : Unused
Initial value:
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CHAPTER 21 I2C
Note: If not using the standby mode wakeup function, disable I2C operation before changing to stop or watch mode.
Table 21.4.5-1 I2C Clock Control Register (ICCR)
Bit Name Function
Bit7DMBP:Divider m bypass bit
This bit is used to bypass the m divider to raise the shift clock frequency.• Writing "1" to this bit bypasses the m divider.• Writing "0" to this bit sets the value set in CS3 and CS4 as the m divider value.Note: Do not set this bit to "1" when divider n = 4 (ICCR:CS2 to 0 = 000B).
Bit6 Unused bitRead value is always "0".Writing has no effect on the operation.
Bit5EN:
I2C operation enable bit
• This bit enables I2C interface operation.
• Writing "1" to this bit enables operation of the I2C interface.• This bit goes to "0" in the following cases:
- When "0" is written to this bit- When IBCR1:BER is "1".
• Clearing this bit to "0" disables operation of the I2C interface and clears the following bits to "0".- AACKX, INTS, and WUE bits in the IBCR0 register- All bits in the IBCR1 register except BER and BEIE bits- All bits in the IBSR register
Bit4Bit3
CS4, CS3:Clock 1 selection bit (divider m)
These bits set the shift clock frequency.• Shift clock frequency (Fsck) is set as shown by the following formula.
Fsck =
φ is the machine clock frequency (MCLK)
Bit2Bit1Bit0
CS2, CS1, CS0:Clock 2 selection bit (divider n)
φ
(m x n + 2)
642
21.5 I2C Interrupt
The I2C interface has a transfer interrupt and stop interrupt which are triggered by the following events. A separate interrupt number and interrupt vector is used in each case.• Transfer interrupt
When the data transfer ended, or when bus error occurred• Stop interupt
When the stop condition is detected, when the arbitration lost is detected, or when
the access is performed for this I2C in the stop/watch mode.See "3.4 Interrupt" for details of the interrupt numbers and interrupt vectors.
Transfer Interrupt
Table 21.5-1 shows the transfer interrupt control bits and I2C Interrupt" shows the transfer interrupt control
bits and I2C interrupt.
• Interrupt when transfer completes
An interrupt request is outputted to the CPU if the enable bit for the transfer complete interrupt request isenabled (IBCR1:INTE=1) when data transfer completes. In the interrupt handler routine, write "0" to theIBCR1:INT bit to clear the interrupt request. The IBCR1:INT bit is set to "1" when data transfercompletes regardless of the value for the IBCR1:INTE bit.
• Interrupt at bus error
When the following conditions are met, a bus error is deemed to have occurred, and the I2C interface willbe stopped.
- When a stop condition is detected in master mode.
- When a start or stop condition is detected while the first byte is being sent or received.
- When a start or stop condition is detected during sending or receiving data (excluding start, first data
bit, and stop).
In these cases, an interrupt request is outputted to the CPU if the enable bit for the bus error interrupt
request is enabled (IBCR1:BEIE=1). In the interrupt handler routine, write "0" to the IBCR1:BER bit to
clear the interrupt request. The IBCR1:BER bit is set to "1" when a bus error occurs regardless of the value
for the IBCR1:BEIE bit.
Table 21.5-1 Transfer Interrupt Control Bits and I2C Interrupts
The End of Transfer Bus Error
Interrupt request flag bit IBCR1:INT = "1" IBCR1:BER = "1"
Interrupt request enable bit IBCR1:INTE = "1" IBCR1:BEIE = "1"
Interrupt cause Data transfer complete Bus error occurred
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CHAPTER 21 I2C
Stop Interrupt
Table 21.5-2 shows the stop interrupt control bits and I2C interrupts.
• Interrupt when a stop condition detected
A stop condition is considered to be valid if all of the following conditions are satisfied when the stopcondition is detected.
- Bus is busy
- IBCR1:MSS=0
- After transfer of one byte of data completes, including the acknowledge.
In this case, an interrupt request is outputted to the CPU if the enable bit for the stop condition detected
interrupt request is enabled (IBCR0:SPE=1). In the interrupt handler routine, write "0" to the IBCR0:SPF
bit to clear the interrupt request.
The IBCR0:SPF bit is set to "1" when a valid stop condition occurs regardless of the value for the
IBCR0:SPE bit.
• Interrupt when arbitration lost detected
An interrupt request is outputted to the CPU if the enable bit for the arbitration lost detected interruptrequest is enabled (IBCR0:ALE=1) when arbitration lost is detected. Writing "0" to the IBCR0:ALF bitwhile the bus is idle or writing "0" to the IBCR1:INT bit from the interrupt handler routine when the busis busy, clears the interrupt request.
The IBCR0:ALF bit is set to "1" when arbitration lost occurs regardless of the value for the IBCR0:ALEbit.
• Interrupt used by the wakeup function when the MCU is in stop or watch mode.
An interrupt request is outputted to the CPU when a start condition is detected if the function to wakeupthe MCU from stop or watch mode is enabled (IBCR0:WUE=1).
In the interrupt handler routine, write "0" to the IBCR0:WUF bit to clear the interrupt request.
Table 21.5-2 Stop Interrupt Control Bits and I2C Interrupts
Detection of Stop Condition Arbitration Lost DetectedFunction for Waking Up the MCU
from Stop or Watch Mode.
Interrupt request flag bit IBCR0:SPF = "1" IBCR0:ALF = "1" IBCH0:WUF = "1"
Interrupt request enable bit IBCR0:SPE = "1" IBCR0:ALE = "1" IBCR0:WUE = "1"
Interrupt cause Detection of stop condition Arbitration lost detected Start condition detected
644
21.6 Explanation of Operation of I2C
This section describes the operation of the I2C.
Operation of I2C
I2C interface
The I2C interface is a serial interface of 8-bit data synchronized with a shift clock.
Function to wakeup the MCU from standby mode
The wakeup function is waken up the MCU from stop or watch mode when a start condition is detected.
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CHAPTER 21 I2C
21.6.1 I2C Interface
The I2C interface is a serial interface of 8-bit data synchronized with a shift clock.
I2C System
Operating mode
The I2C bus system uses the serial data line (SDA) and serial clock line (SCL) for data transfers. All
connected devices require open drain or open collector outputs which must be connected with a pull-up
resistor.
Each device connected to the bus has a unique address and can be set up using software. The bus always
operates in a simple master/slave relationship, where the master functions as the master transmitter or
master receiver. I2C is a true multi-master bus with a collision detection function and arbitration function to
prevent data from being lost if more than one master attempts to start data transfer at the same time.
I2C ProtocolFigure 21.6-1 shows the required format for the data transfer.
Figure 21.6-1 Data Transfer Example
The slave address is sent after a start condition (S) is generated. For this address, the 8th bit data direction
bit (R/W) is added to the 7-bit length one. Data transfer is always ended in the master stop condition (P).
However, the repeated start condition (Sr) can be used to address a different slave without generating a stop
condition.
Start ConditionWhile the bus is idle and the master is not connected to the bus (SCL and SDA are both at the logical "H"
level), the master generates a start condition. As shown in Figure 21.6-1 , a start condition is triggered
when the SDA line is changed from "H" to "L" while SCL= "H". This starts a new data transfer and
commences master/slave operation. A start condition can be generated in either of the following two ways.
• By writing "1" to the IBCR1:MSS bit while the I2C bus is not in use (IBCR1:MSS=0, IBSR:BB=0,IBCR1:INT=0, and IBCR0:ALF=0). (Next, IBSR:BB is set to "1" to indicate bus busy.)
• By writing "1" to the IBCR1:SCC bit during an interrupt while in bus master mode (IBCR1:MSS=1,IBSR:BB=1, IBCR1:INT=1, and IBCR0:ALF=0). (This generates a repeated start condition.)
Writing "1" to the IBCR1:MSS or IBCR1:SCC bit is ignored in other than the above cases. If another
system is using the bus when "1" is written to the IBCR1:MSS bit, the IBCR0:ALF bit is set to "1".
SDA
SCL
R/W
LSBMSBMSB LSB
Startcondition(s)
7-bit address
Acknowledge bit
8-bit data Stopcondition(ps)
No acknowledge
646
AddressingIn master mode, IBSR:BB and IBSR:TRX are set to "1" after the start condition is generated and the upper
bit of the slave address set in the IDDR register is outputted to the bus starting with the MSB. The address
data consists of eight bits: the 7-bit slave address and the data transfer direction R/W bit (bit 0 of IDDR).
The acknowledge from the slave is received after the address data is sent. SDA goes to "L" on the ninth
clock and the acknowledge bit from the receiving device is received (see Figure 21.6-1 ). In this case, the
R/W bit (IDDR:bit0) is inverted and stored in the IBSR:TRX bit as "1" if the SDA level is "L".
In slave mode, after the start condition is detected, IBSR:BB is set to "1" and IBSR:TRX is set to "0", and
the data received from the master is stored in the IDDR register. After the address data is received, the
IDDR and IAAR registers are compared. If the addresses match, IBSR:AAS is set to "1" and an
acknowledge is sent to the master. Next, bit 0 of the receive data (bit 0 of the IDDR register) is saved in the
IBSR:TRX bit.
Data TransferIf the MCU is addressed as a slave, data is sent or received byte by byte with the direction determined by
the R/W bit sent by the master.
Each byte to be outputted on the SDA line is fixed at 8 bits. As shown in Figure 21.6-1 , The receiver sends
an acknowledge to the sender by forcing the SDA line to the "L" level while the acknowledge clock pulse
is "H". Data is transferred at 1 clock pulse per bit with MSB at the head. Sending and receiving an
acknowledge is required after each byte is transferred. Accordingly, nine clock pulses are required to
transfer one complete data byte.
AcknowledgeThe acknowledge is sent by the receiver on the ninth clock of the data byte sent by the sender based on the
following conditions.
An address acknowledge generates in the following cases.
• The received address matches the address set in IAAR, and IBCR0:AACKX=0.
• A general call address (00H) is received and IBCR1:GACKE=1.
A data acknowledge bit used when data is received can be enabled or disabled by the IBCR1:DACKE bit.
In master mode, a data acknowledge is generated if IBCR1:DACKE=1. In slave mode, a data acknowledge
is generated if an address acknowledge has already been generated and IBCR1:DACKE=1. The received
acknowledge is saved in IBSR:LRB on the ninth SCL cycle.
• If the data ACK depends on the content of received data (such as packet error checking used by SMbus), the data ACK is controlled by setting the data ACK enable bit (IBCR1:DACKE) after "1" iswritten to IBCR0:INTS bit (for example, by previous transfer completion interrupt) to read currentreceived data.
• The latest data ACK (IBSR:LRB) can be read after the ACK has been received (IBSR:LRB must beread during the transfer completion interrupt triggered by the ninth SCL cycle.) Accordingly, if ACK isread when the IBCR0:INTS bit is "1", you must write "0" to this bit in the transfer completion interrupttriggered by the eighth SCL cycle so that another transfer completion interrupt will be triggered by theninth SCL cycle.
General Call TransferA general call transfer consists of the start address byte (00H) and the following second address byte. To
use a general call, you must set IBCR1:GACKE=1 before the acknowledge for the first byte of the general
call address. Also, the acknowledge for the second address byte can be controlled as shown below.
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CHAPTER 21 I2C
Figure 21.6-2 General Call Operation
If this module sends a general call address at the same time as another device, you can determine whether
the module successfully seized control of the bus by checking whether arbitration lost was detected when
the second address byte is transferred. If arbitration lost was detected, the module goes to slave mode and
continues to receive data from the master.
ACK ACK/NACKSlave mode
(a) General call operation at slave mode
(b) General call operation at slave mode (No AL, start from GACKE = 1)
(c) General call operation at slave mode (AL by second address, start from GACKE = 1)
(d)(b) General call operation at slave mode (No AL, start from GACKE = 0)
(e) General call operation at slave mode (AL by second address, start from GACKE = 0)
GACKE=1
ACK : AcknowledgeNACK : No acknowledgeGCA : General call addressAL : Arbitration lost
First byte general call Second byte general call
ACK ACK/NACKFirst byte general call Second byte general call
ACK ACK/NACKFirst byte general call Second byte general call
NACK ACK/NACKFirst byte general call Second byte general call
NACK ACK/NACKFirst byte general call Second byte general call
Master mode
GACKE=1Master mode
GACKE=0Master mode
GACKE=0Master mode
When IBCR1:GACKE=1, ACK is given and IBSR:GCA is set.
IBCR1:INT is set by 9th SCL↓.Set IBCR0:INITS=1.
IBCR1:INT is set by 9th SCL↓.Read IBSR:LRB.
IBCR1:INT is set by 8th SCL↓.Read IDDR and control ACK/NACK by IBCR1:DACKE. When IBSR1:LRB is required to read, set INTS=0.
ACK is given and IBSR:GCA is set.
IBCR1:INT is set by 9th SCL↓.Set IBCR0:INITS=1/GACKE=0.
IBCR1:INT is set by 9th SCL↓.Read IBSR:LRB.
GCA is cleared. IBCR1:INT is set by 8th SCL↓.To read IBSR1:LRB sets INTS=0.
ACK is given and IBSR:GCA is set.
AL generates by second address and switches to slave mode.
IBCR1:INT is set by 9th SCL↓.Set IBCR0:INITS=1/GACKE=0.
IBCR1:INT is set by 9th SCL↓.Read IBSR:LRB.
IBCR1:INT is set by 8th SCL↓.Read IDDR and control ACK/NACK by IBCR1:DACKE.When IBCR1:LRB is required to read, set INTS=0.
ACK is not given and IBSR:GCA is not set.
IBCR1:INT is set by 9th SCL↓.Set IBCR0:INITS=1.
IBCR1:INT is set by 9th SCL↓.Read IBSR:LRB.
IBCR1:INT is set by 8th SCL↓.To read IBSR1:LRB sets INTS=0.
ACK is not given and IBSR:GCA is not set.
IBCR1:INT is set by 9th SCL↓.Set IBCR0:INITS=1.
IBCR1:INT is set by 8th SCL↓.Read IDDR and control ACK/NACK by IBCR1:DACKE.When IBCR1:LRB is required to read, set INTS=0.
IBCR1:INT is set by 9th SCL↓.Read IBSR:LRB.
AL generates by second address,IBSR:GCA is set and switches to slave mode.
648
Stop ConditionThe master can release the bus and end communications by generating a stop condition. Changing the SDA
line from "L" to "H" while SCL is "H" generates a stop condition. This signals to the other devices on the
bus that the master has finished communications (referred to below as "bus free"). However, the master can
continue to generate start conditions without generating a stop condition. This is called a repeated start
condition.
Writing "0" to the IBCR1:MSS bit during an interrupt while in bus master mode (IBCR1:MSS=1,
IBSR:BB=1, IBCR1:INT=1, and IBSR:AL=0) generates a stop condition and changes to slave mode. In
other cases, writing "0" to the IBCR1:MSS bit is ignored.
ArbitrationThe interface circuit is a true multi-master bus able to connect multiple master devices. Arbitration occurs
when another master within the system simultaneously transfers data during a master transfer.
Arbitration generates on the SDA line while the SCL line is at the "H" level. When the send data is "1" and
the data on the SDA line is "L" at the master, this is treated as arbitration lost. In this case, data output is
halted and IBCR0:ALF is set to "1". If this occurs, an interrupt generates if the arbitration lost interrupt is
enabled (IBCR0:ALE=1). If IBCR0:ALF is set to "1", the module sets IBCR1:MSS=0 and IBSR:TRX=0,
clears TRX, and goes to slave receive mode.
If IBCR0:ALF is set to "1" when IBSR:BB=0, IBCR0:ALF is only cleared by writing "0". If IBCR0:ALF
is set to "1" when IBSR:BB=1, IBCR0:ALF is only cleared by clearing IBCR1:INT to "0".
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CHAPTER 21 I2C
Conditions for Generating an Arbitration Lost Interrupt when IBSR:BB= "0"When start condition is generated by the program ("1" is set to IBCR1:MSS bit) at the timing shown in
Figure 21.6-3 and Figure 21.6-4 , the interrupt generated (IBCR1:INT bit=1) is prohibited by arbitration
lost detection (IBCR:ALF=1).
• Conditions in which no interrupt is generated due to arbitration lost
If the program triggers a start condition (by setting the IBCR1:MSS bit to "1") when no start condition has
been detected (IBSR:BB bit=0) and the SDA and SCL line pins are at the "L" level.
Figure 21.6-3 Timing Diagram Showing When No Interrupt Generated for IBCR0:ALF=1
"L"
"L"
1
0
0
SCL or SDA pin is at Low level.
SCL pin
SDA pin
I2C operation enable state (ICCR:EN bit = 1)
Master mode setting (IBCR1:MSS bit = 1)
Arbitration lost detection bit (IBCR0:ALF bit= 1)
Bus busy (IBSR:BB bit)
Interrupt (IBCR1:INT bit)
650
• Conditions in which no interrupt is generated due to arbitration lost 2
If the program enables I2C operation (by setting the ICCR:EN bit to "1") and triggers a start condition (by
setting the IBCR1:MSS bit to "1") when the I2C bus is in use by another master.
This is because, as shown in Figure 21.6-4 , this I2C module cannot detect the start condition (IBSR:BB=0)
if another master starts communications on the I2C bus when operation is disabled (ICCR:EN=0) for this
I2C operation.
Figure 21.6-4 Timing Diagram Showing When No Interrupt Generated for IBCR0:ALF=1
If this situation can occur, use the following procedure to setup the module from the software.
1) Trigger a start condition from the program (by setting the IBCR1:MSS bit to "1").
2) Check the IBCR0:ALF and IBSR:BB bits in the arbitration lost interrupt.
If IBCR0:ALF=1 and IBSR:BB=0, clear the IBCR0:ALF bit to "0".
If IBCR0:ALF=1 and IBSR:BB=1, clear the IBCR0:ALE bit to "0" and perform control as normal.(Normal control means writing "0" to the IBCR0:INT bit in the interrupt to clear IBCR0:ALF.)
In other cases, perform control as normal (Normal control means writing "0" to the IBCR0:INT bit in theINT interrupt to clear IBCR0:ALF.)
0
0
ACKACK
Start condition
SCL pin
SDA pin
ICCR:EN bit
IBCR1:MSS bit
IBCR0:ALF bit
IBSR:BB bit
IBCR1:INT bit
IBCR1:INT bit interrupt does notgenerate by ninth clock cycle. Stop condition
DataSlave address
651
CHAPTER 21 I2C
The figure below shows an example flowchart of this procedure.
no
Enable AL interrupt (IBCR0:ALE="1")
IBCR0:ALF=1
IBSR:BB=0
yes
yes
no
Write "0" to IBCR0:ALF andclear AL flag and interrupt.
Set to master mode
Set the MSS bit of I2C bus control register 1 (IBCR1) to "1".
Write "0" to IBCR0:ALEand clear AL interrupt.
Normal control
652
Example of Generating Interrupt (IBCR1:INT bit = 1) when IBCR0:ALF = 1 is DetectedIf the bus busy (IBSR:BB bit = 1) and arbitration lost is detected when the start condition is generated by
the program ("1" is set to IBCR1:MSS bit), interrupt of BCR1:INT bit generates due to detection of
"ICSR0:ALF bit = 1".
Figure 21.6-5 Timing Diagram Showing When Interrupt Generated for IBCR0:ALF bit = 1
ACK
Start condition Interrupt by ninth clock cycle
Slave address Data
SCL pin
SDA pin
ICCR:EN bit
IBCR1:MSS bit
IBCR0:ALF bit
IBSR:BB bit
IBCR1:INT bit
Clear IBCR0:ALF bit by software
Clear IBCR1:INT bit by software and release the SCL line
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CHAPTER 21 I2C
21.6.2 Function to Wakeup MCU from Standby Mode
The wakeup function enables the I2C macro to be accessed while the MCU is in stop or watch mode.
Function to Wakeup MCU from Standby Mode
The I2C macro includes a function to wakeup the MCU from standby mode. The function is enabled by
writing "1" to the IBCR0:WUE bit.
When the MCU is in stop/watch mode and IBCR0:WUE bit is "1" if the start condition is detected on the
I2C bus, the wakeup interrupt request flag bit (IBCR0:WUF) is set to "1" and the wakeup interrupt request
is generated to wakeup the MCU from stop/watch mode.
Note:
Set IBCR0:WUE to "1" immediately prior to setting the MCU to stop or watch mode. Similarly, clear
IBCR0:WUE (by writing "0") after the MCU wakes up from stop or watch mode so that I2C operationcan restart as soon as possible.The wakeup function only applies to the MCU stop and clock modes. In PLL stop mode, for example,a PLL oscillation stabilization wait time is required in addition to the oscillation stabilization delay.This causes a very long delay between the MCU waking up and communications restarting.
Figure 21.6.2-1 Comparison of Normal I2C Operation and Wakeup Operation
The figure below shows an example flowchart of the wakeup function.
SDA
SCL
IRQ byIBCR0:WUF
MachineClock
1 2 3 4
1
2
3
4
5
5
: IBCR0:WUE bit is set to "1" immediately prior to entering the stop/watch mode and confirm IBSR:BB = 0.
: Set MCU to stop/watch mode and the machine clock stops.
After oscillation stabilization wait time, MCU wakes up and becomes to main clock mode.: Detect start condition in the stop/watch mode. When IBCR0:WUF = 1, wakeup IRQ generates.
: IBCR0:WUE bit is cleared to "0", IBCR0:WUF bit to "0", and wakeup interrupt is cleared so that I2C canrestart the normal operation.
: To receive the data byte correctly, after I2C transmission starts (falling edge detection of SDA) from 100µs(minimum oscillation stabilization wait time is assumed 100µs), SCL must open as first cycle.
654
no
Transmit to stop/watch made
yes
IBCR0:WUE=0
Wakeup function enable IBCR0:WUE = "1"
IBSR:BB=0
IBSR:BB=0
yes
no
Procedure to transfer tostop/watch mode
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CHAPTER 21 I2C
21.7 Notes on Using I2C
Instructions for use of the I2C interface are described.
Notes on Using I2C
Points to note when setting I2C interface registers
• Operation of the I2C interface must be enabled (ICCR:EN) before setting the I2C bus control registers(IBCR0 and IBCR1).
• Setting the master/slave selection bit (IBCR1:MSS) (by writing "1") starts data transfer.
Notes on setting the shift clock frequency
• The shift clock frequency can be calculated by setting m, n, and DMBP values using Fsck formula inTable 21.4.5-1 .
• "DMBP=1" may not be selected if the value of n is 4 (ICCR:CS2=CS1=CS=0). Other settingcombinations are OK.
Points to note when writing settings simultaneously
• Next byte transfer and conflict of stop condition "0" is written to IBCR1:MSS with state IBCR1:INTcleared, the MSS bit is prioritized and the stop condition generates.
• Next byte transfer and conflict of start condition. When "1" is written to IBCR1:SCC with stateIBCR1:INT cleared, the SCC bit is prioritized and the start condition generates.
Instruction for set up using software
• Do not select a repeated start condition (IBCR1:SCC=1) and slave mode (IBCR1:MSS=0)simultaneously.
• Execution cannot return from interrupt processing if interrupt request enable bits are enabled(IBCR1:BEIE=1/IBCR1:INTE=1) and the interrupt request flag bit (IBCR1:BER/IBCR1:INT) is 1. TheIBCR1:BER/IBCR1:INT bit must be cleared.
• The following bits are cleared to "0" when I2C operation is disabled (ICCR:EN=0).
- AACKX, INTS, and WUE bits in the IBCR0 register
- All bits in the IBCR1 register except BER and BEIE
- All bits in the IBSR register
Points to note about data acknowledge
In slave mode, a data acknowledge is generated in the following cases:
- When the received address matches the value in the address register (IAAR) and IBCR0:AACKX=0.
- When a general call address (00H) is received and IBCR1:GACKE=1.
Points to note when selecting the transfer complete timing
• The transfer complete timing selection (IBCR0:INTS) only applies when receiving data (IBCR1:TRX=0and IBCR1:FBT=0).
• In cases other than data reception (IBCR1:TRX=1 or IBCR1:FBT=1), the transfer complete interrupt is
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always generated on the ninth SCL cycle.
• If the data ACK depends on the content of received data (such as packet error checking used by SMbus), the data ACK is controlled by setting the data ACK enable bit (IBCR1:DACKE) after "1" iswritten to IBCR0:INTS bit (for example, by previous transfer completion interrupt) to read currentreceived data.
• The latest data ACK (IBSR:LRB) can be read after the ACK has been received (IBSR:LRB must beread during the transfer completion interrupt triggered by the ninth SCL cycle.) Accordingly, if ACK isread when the IBCR0:INTS bit is "1", you must write "0" to the IBCR0:INTS bit in the transfercompletion interrupt triggered by the eighth SCL cycle so that another transfer completion interrupt willbe triggered by the ninth SCL cycle.
Points to note when using the function to wakeup the MCU from standby mode
• Set IBCR0:WUE to "1" immediately prior to setting the MCU to stop or watch mode. Similarly, clear
IBCR0:WUE (by writing "0") after the MCU wakes up from stop or watch mode so that I2C operationcan restart as soon as possible.
• When a wakeup interrupt request occurs, the MCU wakes up after the oscillation stabilization delaytime elapses. Therefore, to prevent the data loss immediately after wakeup, the SCL is generated as first cycle andthe first bit must be received as a data after 100 µs (when minimum oscillation stabilization wait time is assumed
100 µs) from the wakeup due to start of I2C transmission (detection for falling edge of SDA).
• During MCU standby modes, the status flags, state machine, and I2C bus outputs for the I2C function
retain the states they had prior to entering standby mode. To prevent a hang-up on the overall I2C bussystem, confirm that IBSR:BB=0 before entering standby mode.
• The wakeup function does not support the case when the MCU goes to stop or watch mode whenIBSR:BB=1. If the MCU does go to stop or watch mode when IBSR0:BB=1, a bus error will occurwhen the start condition is detected.
• The wakeup function is valid only in stop/watch mode in MCU. (For example, in addition to the oscillationstabilization wait time, the PLL oscillation stabilization wait time adds in the PLL stop mode, the time after wakeupto start communication becomes longer than stop/watch mode.)
• To ensure correct operation of the I2C interface, always clear IBCR0:WUE to "0" after the MCU wakes
up from stop or watch mode, regardless of whether this occurs due to the I2C wakeup function or thewakeup function for some other resource (such as an external interrupt).
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CHAPTER 21 I2C
658
CHAPTER 22A/D Converter
This chapter describes the functionality and behavior of the A/D converter.
22.1 Overview of A/D Converter
22.2 Block Diagram of A/D Converter
22.3 Pin of A/D Converter
22.4 Registers of A/D Converter
22.5 Interrupt of A/D Converter
22.6 Operation of A/D Converter
22.7 Notes on Using A/D Converter
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CHAPTER 22 A/D Converter
22.1 Overview of A/D Converter
An A/D converter, which is of a 10-bit successive approximation type. It can be started via software, external trigger, and internal clock, selecting one input signal from among multiple analog input pins.
A/D Conversion FunctionsThese functions convert the analog voltage (input voltage) input from an analog input pin to 10-bit digital
values.
• One of multiple analog input pins can be selected.
• The conversion speed is programmable and can be configured (Selected in accordance with voltage andfrequency in use).
• An interrupt is generated when A/D conversion completes.
• It is also possible to determine if conversion has ended by the ADI bit of the ADC1 register.
• To activate A/D conversion functions, follow one of the methods given below.
• Started via the AD bit of the ADC1 register
• Continually started via external pin (ADTG)
• Continually started via 8/16-bit combined timer output TO00
660
22.2 Block Diagram of A/D Converter
The A/D converter is made up of the following blocks. • Clock selector (input clock selector for activation of A/D conversion)• Analog channel selector• Sample hold circuit• Control circuit• A/D data register (ADDH and ADDL)• A/D control register 1 (ADC1)• A/D control register 2 (ADC2)
Block Diagram of A/D ConverterFigure 22.2-1 shows a block diagram of the A/D converter.
Figure 22.2-1 Block Diagram of A/D Converter
AD8 TIM1 TIM0 ADCK ADIE EXT CKDIV1 CKDIV0
ANS3 ANS2 ANS1 ANS0 ADI ADMV ADMVX AD
( ADDH,ADDL)
AVcc
IRQ
AN0 to AN15
AVR
AVss
ADTG pin
8/16 bits compound timer (TO00) output
Startupsignal selector
Analog channelselector
Sample hold circuit
A/D control register 2 (ADC2)
Internal data bus
Control circuit
A/D data register
A/D control register 1 (ADC1)
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CHAPTER 22 A/D Converter
Clock selector
Selects the A/D conversion clock when continual startup enabled (ADC2:EXT = 1).
Analog channel selector
This circuit selects one of multiple analog input pins.
Sample hold circuit
This circuit holds the input voltage selected by the analog channel selector. By performing the sample hold
of the voltage input immediately after the activation of A/D conversion, A/D conversion can be performed
without the variance of the input voltage affecting it during A/D conversion (during comparison).
Control circuit
The A/D conversion function determines the values to set in each successive bit of the 10-bit A/D data
register starting with the MSB based on the voltage compare signal from the comparator. When conversion
is complete, the A/D conversion function sets the interrupt request flag bit (ADC1:AD1).
A/D data register (ADDH/ADDL)
The high-order 2 bits of 10-bit A/D data are stored in the ADDH register. The low-order 8 bits of 10-bit A/
D data are stored in the ADDL register.
Set the A/D conversion precision bit (ADC2:AD8) to "1" for 8-bit precision. The upper 8 bits of the 10-bit
A/D data are stored in the ADDL register.
A/D control register 1 (ADC1)
This register is used to enable and disable functions, select an analog input pin, check statuses, and control
interrupts.
A/D control register 2 (ADC2)
This register is used to select an input clock, enable and disable interrupts, select functions, and perform
other activities.
Interrupt of A/D ConverterIRQ: When A/D conversion is finished, an interrupt request is issued if interrupt request output is enabled
(ADC2:ADIE = 1).
Power Voltage of A/D Converter
AVcc
A/D converter power supply pin. Use this at the same potential as Vcc. If A/D conversion precision is
demanded, you should take measures to ensure that Vcc noise does not enter AVcc, or use a separate power
source. You should connect this pin to a power source even when the A/D converter is not being used.
AVss
This is a ground pin of the A/D converter. Use this at the same potential as Vss. When A/D conversion
precision is required, take action to ensure that the Vss noise does not interfere with AVss. You should
connect this pin to a ground (GND) even when the A/D converter is not being used.
662
AVR
This pin inputs the reference voltage of the A/D converter. 10-bit A/D conversion is performed between the
AVR and AVss. Some series do not have AVR pins, and are internally connected to AVcc.
You should connect to AVss when the A/D converter is not being used.
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CHAPTER 22 A/D Converter
22.3 Pin of A/D Converter
This section describes the pins of the A/D converter.
Pin of A/D ConverterAnalog input pins are jointly used as general-purpose I/O ports.
AN15 to AN0: When using the A/D conversion function, input the analog voltage you wish to convert to
this pin. When the bit corresponding to the port direction register (DDR) is set to "0" and the output
transistor is set to "OFF", selecting these bits via the analog input channel select bits (ADC1:ANS0 to
ANS3) makes them function as analog input pins. Even when the A/D converter is used, pins not used as
analog inputs can be used as general-purpose I/O ports.
Note that the number of analog input pins differs depending on the series.
664
22.4 Registers of A/D Converter
The A/D converter has the following registers: A/D control register 1 (ADC1), A/D control register 2 (ADC2), A/D data register H (ADDH), and A/D data register L (ADDL).
List of A/D Converter RegistersFigure 22.4-1 shows the registers of the A/D converter.
Figure 22.4-1 Registers of A/D Converter
ANS3 ANS2 ANS1 ANS0 ADI ADMV ADMVX AD
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ADC1
AD8 TIM1 TIM0 ADCK ADIE EXT CKDIV1 CKDIV0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ADC2
- - - - - - SAR9 SAR8
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ADDH
SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 SAR1 SAR0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ADDL
A/D control register 1
A/D control register 2
A/D data register H
A/D data register L
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CHAPTER 22 A/D Converter
22.4.1 A/D Control Register 1 (ADC1)
A/D control register 1 (ADC1) is used to set the enabling and disabling functions of the A/D converter, select an analog input pin, and check the states.
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A/D Control Register 1 (ADC1)
Figure 22.4-2 A/D Control Register 1 (ADC1)
00
00000000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R/W R/W R/W R/W R(RM1),W R/WX R/W R0,W
AD01
AN0 pinANS3
0AN1 pin0
AN3 pin
ADI
01
AN2 pin0000
0
ANS2
ANS3 ANS2 ANS1 ANS0 ADI ADMV ADMVX AD
ADMVX
01
ADMV01
00 1
011
1
110
0 010
0
110
0 011
1
011 0
001
1
000 1
011
1
111
1 010
0
111
1 011
1
ANS1 ANS0
AN4 pinAN5 pin
AN7 pinAN6 pin
AN8 pinAN9 pin
AN11 pinAN10 pin
AN12 pinAN13 pin
AN15 pinAN14 pin
R/W :R/WX :R0,W :
R(RM1),W ::
Initial value
A/D conversion start bitA/D conversion start is not operated.A/D conversion start is operated.
Analog switch control bit for current shut outAnalog switch is ON during conversion only.Analog switch is always ON.
Flag bit in convertingNot in converingIn converting
Interrupt request flag bitRead Write
Conversion is not completed.Conversion is completed.
Clear of this bit.No change and no effect to others.
Analog input channel selection
Read and write are enabled. (Reading value is writing value.)Read only (Read is enabled and write has no effect to operations.)Write only (Write is enabled and reading value is 0.)
Initial valueRead and write are enabled. (Reading value is different from writing value. 1 is read at read-modify-write instruction.)
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CHAPTER 22 A/D Converter
ï 22.4.1-1 Functional Description of Each Bit in A/D Control Register 1 (ADC1)
Bit Name Functions
Bit7Bit6Bit5Bit4
ANS3,ANS2,ANS1,ANS0: Analog input channel select bit
Select whether to use the analog input pins in AN0 to AN15. Note that the number of analog input pins differs depending on the series. The number of analog input pin is different in the series. • When A/D conversion is activated (AD=1) via software (ADC2:EXT=0), updating can be performed at the
same time.Note:When the ADMV bit is "1", do not rewrite these bits. Reference:You can use pins not used as analog input pins as general-purpose ports.
Bit3ADI: Interrupt request flag bit
Detects termination of A/D conversion. • During A/D conversion function, set to "1" upon termination of A/D conversion. • When this bit and the interrupt request enable bit (ADC2:ADIE) are "1", interrupt requests are outputted. • When writing, a "0" clears this bit, and with "1" no conversion is made, and there are no other effects.
Bit2ADMV: During conversion flag bit
Indicates that conversion is ongoing during A/D conversion function operation. • During conversion (comparison), this bit is set to "1".Reference:This bit is read-only. The written value carries no significance, and does not affect operation.
Bit1ADMVX: Analog switch control bit]
Controls the internal reference power cutoff analog switch. • When the external impedance of the AVR pin is high, rush current flows immediately after A/D startup. For
this reason, there may be impact on A/D conversion precision. In this kind of situation, this can be avoided by setting this bit to "1" before A/D startup. Set this to "0" before switching to standby mode, in order to reduce current consumption.
• Note that some series do not have AVR pins, and are internally connected to AVcc. In this case, this bit has no significance.
Bit0A/D: Activating A/D conversion bit
Start the A/D conversion function via software. • Write "1" to start the A/D conversion function. Note:Writing "0" to this bit will not stop operation of the A/D conversion function. The read value is always "0".
668
22.4.2 A/D Control Register 2 (ADC2)
The A/D control register 2 (ADC2) selects the A/D converter, selects the input clock, and performs interrupt and status checking.
A/D Control Register 2 (ADC2)
Figure 22.4-3 A/D Control Register 2 (ADC2)
0
00000000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R/W R/W R/W R/W R/W R/W R/W R/W
ADIE01
1 MCLK
CKDIV1
02 MCLK0
8 MCLK4 MCLK
1011
1
CKDIV0
AD8
01
AD8 TIM1 TIM0 ADCK ADIE EXT CKDIV1 CKDIV0
EXT01
ADCK01
0 CKIN x 4TIM1
0CKIN x 70
CKIN x 16CKIN x 10
1011
1
TIM0
MCLK :R/W :
:
Initial value
Clock (CKIN) select bit
Continuous conversion enable bitActivation at AD bit of ADC1 registerContinuous activation at clock selected by ADCK bit of ADC2 register
Interrupt request enable bitProhibition of interrupt request outputEnable of interrupt request output
External activation signal select bitActivation by ADTG input pinActivation by 8/16-bit compound timer (TO00) output
Sampling time select bit
AD conversion accuracy bit10-bit accuracy8-bit accuracy
Machine clockRead and write are enabled. (Reading value is writing value.)Initial value
669
CHAPTER 22 A/D Converter
ï 22.4.2-1 Functional Description of Each Bit in A/D Control Register 2 (ADC2)
Bit Name Functions
Bit7AD8: Precision selection bit
This bit selects the A/D conversion resolution.• When this bit is "0", 10-bit precision is used.• When this bit is "1", 8-bit precision is used, enabling 8-bit partitioned reading by reading the ADDL. Note:The data bit used are different depends on the resolution.Make sure to only rewrite to this bit before conversion, when A/D operation is stopped.
Bit6bit5
TIM1, TIM0: Sampling time select bits
Sets the sampling time. • Changes the sampling-time selection, depending on the operating conditions in use (voltage/frequency). • The value of CKIN is determined by the clock selection bits (ADC2:CKDIV1/CKDIV0).
Bit4ADCK: External start signal selection bit
Selects the start signal during external start (ADC2:EXT = 1).
Bit3ADIE: Interrupt request enable bit
Enables/disables output of interrupts to CPU. • When this bit and interruption request flag bit (ADC1: ADI) are set to "1", an interruption request is
outputted.
Bit2
EXT: Enabling continuous activation bit
• Selects whether to start the A/D conversion function via software, or continually in synchronization with input clock startup.
Bit1Bit0
CKDIV1,CKDIV0: Clock select bit
Selects the clock to use for A/D conversion. The clock is generated via prescaler. See Chapter 11, Prescaler for details. • The sampling time can also be changed via this clock selection. • Changes the value, depending on the operating conditions in use (voltage/frequency). Note:Make sure to only rewrite to these bits before conversion, when A/D operation is stopped.
670
22.4.3 A/D Data Register (ADDH and ADDL)
The A/D data registers (ADDH/ADDL) store the results of 10-bit A/D conversion. The high-order 2 bits of 10-bit data correspond to the ADDH register. The low-order 8 bits correspond to the ADDL register.
A/D Data Register (ADDH and ADDL)
Figure 22.4-4 A/D Data Register (ADDH and ADDL)
The upper 2 bits of the 10-bit A/D data correspond to bits 1 and 0 of the ADDH register. The lower 8 bits
correspond to bits 7 to 0 of the ADDL register.
Set the AD8 bit of the ADC2 register to "1" to set 8-bit precision mode, and read 8-bit data by reading the
ADDL.
This register is read-only. Writing has no significance.
A/D conversion functions
When A/D conversion is started, the results of conversion are finalized and stored in this register after the
conversion time according to the register setting has passed. For this reason, after A/D conversion finishes,
write "0" to the ADI bit (bit 3) of the ADC1 register and read register (conversion results) until the next A/
D conversion terminates, then after A/D conversion finishes, clear this flag. During A/D conversion, the
value of the register is the last conversion performed.
- - - - - - SAR9 SAR8
SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 SAR1 SAR0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00000000
00000000
R0/WX R/WX
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R0/WX R0/WX R0/WX R0/WX R0/WX R/WX
R/WXR/WXR/WXR/WXR/WXR/WXR/WXR/WX
R/WX :R0/WX :
:
Initial value
Initial value
Read only (Reading value is enabled and write has no effect to operations.)Undefined bit (Reading value is 0 and write has no effect to operations.)Initial value
ADDH
ADDL
671
CHAPTER 22 A/D Converter
22.5 Interrupt of A/D Converter
A factor for an interrupt of the A/D converter is the following.• Completion of conversion when A/D conversion functions are operating.
Interrupts when A/D Converter is Operating When A/D conversion is completed, the interrupt request flag bit (ADC1: ADI) is set to "1". Then if the
interrupt request enable bit is enabled (ADC2: ADIE = 1), an interrupt request is sent to the CPU. Write "0"
to the ADI bit using the routine for interrupt handling to clear the interrupt request.
The ADI bit is set when A/D conversion is completed, irrespective of the value for the ADIE bit.
See 29.2 Interrupt Cause Table for interrupt request numbers.
672
22.6 Operation of A/D Converter
Software startup or continuous startup can be selected for the A/D converter, via the EXT bit of the ADC1 register.
Behavior of A/D Converter Conversion Function
Software activation
The settings shown in Figure 22.6-1 are required for software activation of the A/D conversion function.
Figure 22.6-1 A/D Conversion Function (Software Activated) Settings
When A/D conversion is activated, the operations of A/D conversion functions are started. In addition,
even during conversion, A/D conversion functions can be reactivated.
ANS3 ANS2 ANS1 ANS0 ADI ADMV ADMVX AD
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ADC1
AD8 TIM1 TIM0 ADCK ADIE EXT CKDIV1 CKDIV0ADC2
- - - - - -ADDH
ADDL
1
0
1 :0 :
Retaining of A/D converting value
A/D converting value is retained.
Used bitUnused bitSet 1.Set 0.
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CHAPTER 22 A/D Converter
Continuous activation
The settings shown in Figure 22.6-2 are required for continuous activation of the A/D conversion function.
Figure 22.6-2 A/D Conversion Function (Continuous Activation) Settings
When continuous activation is enabled, A/D conversion is activated on a rising edge of the selected input
clock, and the operations of A/D conversion functions are started. Continual startup is stopped by
prohibiting continual startup (ADC2:EXT = 2).
Operations of A/D Conversion FunctionsThis section describes the operation of the A/D converter.
1) The conversion-in-progress bit is set (ADC1:ADMV=1) when an A/D conversion starts, and the selected
analog input pin is connected to the sample & hold circuit.
2) The voltage of the analog input pin is loaded into the internal sample hold capacitor during the sampling
cycle. This voltage is held until A/D conversion has been completed.
3) The voltage loaded into the sample-hold capacitor is compared with the A/D conversion reference
voltage, from the most significant bit (MSB) to the least significant bit (LSB), and the results then sent
to the ADDH and ADDL registers sequentially. After the results have been completely sent, the
"conversion in progress" flag is cleared (ADC1:ADMV = 0), and the interrupt request flag bit is set
(ADC1:ADI = 1).
ANS3 ANS2 ANS1 ANS0 ADI ADMV ADMVX AD
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ADC1
AD8 TIM1 TIM0 ADCK ADIE EXT CKDIV1 CKDIV0ADC2
- - - - - -ADDH
1
1 :0 :
Retaining of A/D converting value
Used bitUnused bitSet 1.Set 0.
674
22.7 Notes on Using A/D Converter
This section describes cautions for using the A/D converter.
Notes on Using A/D Converter
Notes on setting on programs
• When the A/D conversion function is running, the contents of the ADDH and ADDL registers areretained after termination of A/D conversion. Consequently, during A/D conversion, the previouslyconverted value is read.
• Do not change the analog input channel selection (ADC1:ANS3 to ANS0) while the A/D conversionfunction is in use. During continuous startup in particular, you should do so after prohibiting continuousstartup (ADC2:EXT = 0).
• A reset, stop, or watch-mode startup will stop the A/D converter and initialize each register.
• Execution cannot return from interrupt processing if interrupt requests are enabled (ADC2:ADIE=1) andthe interrupt request flag bit (ADC1:ADI) is "1". Be sure to clear the ADI bit.
Notes on interrupt requests
If A/D conversion is reactivated (ADC1: AD = 1) and terminated at the same time, the interrupt request
flag bit (ADC1: ADI) is not set.
Margin of error
As |AVR-AVss| decreases, the size for the margin of error increases correspondingly.
A/D converter power, analog-input order, and cutoff order
Power on the A/D converter (AVcc, AVss) and apply an analog input (AN0 to AN7) at the same time as, or
after turning on the digital power supply (Vcc).
To turn off the power, turn off the digital power supply (Vcc) concurrently with or after turning off the
power supply of the A/D converter (AVcc, AVss) and the analog input (AN0 to AN15).
Make sure that the AVcc, AVss, and analog input do not exceed the voltage of the digital power supply
when turning A/D converter power on and off.
Conversion time
The conversion speed of the A/D conversion function is affected by the clock mode, base oscillation
frequency of the main clock, and the main clock speed switching (gear function).
Example: Machine clock (MCLK) = 10 MHz (100 ns)
Clock select bit (ADC2:CKDIV1/0) = "01" (MCLK x 2) = 200ns (CKIN)
Sampling time select bit (ADC2:TIM1/0) = "10" (CKIN x 10) = 2000ns (SAMP)
Comparing time = CKIN x 13 (fixed value) = 2600ns (COMP)
Conversion time = sampling time (SAMP) + Comparing time (COMP) = 4600ns
675
CHAPTER 22 A/D Converter
676
CHAPTER 23D/A Converter
This chapter explains function and operation of the D/A converter
23.1 Overview of D/A Converter
23.2 Block Diagram of D/A Converter
23.3 D/A Converter Pin
23.4 Registers of D/A Converter
23.5 Explanation of Operations of D/A Converter
23.6 Notes on Using D/A Converter
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CHAPTER 23 D/A Converter
23.1 Overview of D/A Converter
The D/A converter is a R-2R type with 10-bit resolution.
D/A converterThe circuit converts a 10-bit digital input value to analog and outputs the analog level. The output voltage
range of the D/A converter is 0V to 1023/1024 × AVCC. Although the output voltage range can be changed
by adjusting the AVCC voltage externally, take care as this AVCC is also used as the power supply for the
A/D converter. The theoretical value of the D/A converter output voltage is shown in Table 23.1-1 .
Table 23.1-1 Theoretical values of output voltage of the D/A converter
Theoretical value of output voltage Setting value of [DA09 to DA00] bits
0/1024 × AVCC (=0V) 000H
1/1024 × AVCC 001H
2/1024 × AVCC 002H
•••
•••
1021/1024 × AVCC 3FDH
1022/1024 × AVCC 3FEH
1023/1024 × AVCC 3FFH
678
23.2 Block Diagram of D/A Converter
Figure 23.2-1 shows a block diagram of the D/A converter.
Block Diagram of the D/A Converter
Figure 23.2-1 Block Diagram of the D/A Converter
Internal bus
AVCC
DA09
2RR
DA08
2RR
DA07
DA01
2RR
DA00
2R2R
DAE
DA DA DA DA DA DA DA DA08 07 06 05 04 03 02 01
DA output
DA00
DA09
0809
D/A converter control data register (DACR)
D/A converter data register (DAT)
679
CHAPTER 23 D/A Converter
23.3 D/A Converter Pin
This section describes the D/A converter pins and shows the pin block diagram.
Pins Related to the D/A ConverterThe D/A converter pins are DA, AVCC, and AVSS.
AVCC and AVSS pins are the analog power supply for the D/A converter. They also supply the analog
power to the A/D converter. The DA pin is the dedicated D/A converter output pin.
Block Diagram of D/A Converter Pins (DA)
Figure 23.3-1 Block Diagram of D/A converter pins (DA)
Pin
D/A output enabled bit (DAE)
Analog output
680
23.4 Registers of D/A Converter
Figure 23.4-1 shows registers related to D/A converter.
Registers Related to the D/A Converter
Figure 23.4-1 Registers Related to the D/A Converter
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
DAT (D/A converter data register)
DACR (D/A converter control data register)
DA08 00000000B
R/W R/W R0/WX R0/WX R0/WX R0/WX R/W R/W
DAE PIE - - - DA09
bit7 bit6
-
bit5 bit4 bit3 bit2 bit1 bit0 Initial value
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
681
CHAPTER 23 D/A Converter
23.4.1 D/A Converter Data Register (DAT)
The D/A converter data register (DAT) sets the lower byte of the 10-bit output voltage setting. D/A conversion uses this register together with the upper two bits set in the DACR register.
D/A Control Data Register (DAT)
Figure 23.4-2 D/A converter data register (DAT)
The D/A converter data register (DAT) sets the lower 8 bits of the 10-bit output voltage.
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 00000000B
bit7
R/W R/W R/W R/W R/W R/W R/W R/W
bit6 bit0bit2 bit1
R/W:Read/write enabled (read value = write value)
Initial valuebit5 bit4 bit3
682
23.4.2 D/A Converter Control Data Register (DACR)
The D/A converter control data register (DACR) is used to enable and disable the output of the D/A converter. The register also sets the upper two bits of the 10-bit data.
D/A Converter Control Data Register (DACR)
Figure 23.4-3 D/A Converter Control Data Register (DACR)
Table 23.4-1 Functional Description of Each Bit in D/A Converter Control Data Register (DACR)
Bit name Functions
Bit7DAE:D/A converter output control bit
• This bit controls the output of the D/A converter.• Writing "1" to this bit enables D/A output.• Writing "0" to this bit disables D/A output.• Initialized to "0" by reset.• The read/write is possible.• Disabling D/A output turns off an analog switch located in series with the D/A converter output. This
also clears the output state of the D/A converter to "0" and disconnects the DC current path.
Bit6PIE:Port input enabled bit
• If the D/A converter output shares a pin with a general-purpose port, this bit controls the port input. This eliminates the DC path that would result when an intermediate potential is applied to the port input buffer during D/A output.
• Writing "1" to this bit enables operation as a general-purpose port input.• Writing "0" to this bit disables operation as a general-purpose port input.
Bit5Bit4Bit3Bit2
Undefined bits• Writing has no effect on the operation.• These bits indicate "0" when read.
Bit1Bit0
DA08, DA09:D/A input data
Sets the upper two bits of the 10-bit input data. D/A conversion is performed on the combined value of these two bits and the DAT register content.
R/W
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00000000B
Initial value
DAE PIE - - DA09 DA08-
R/W
-
: Initial valueR/W: Read/write enable (read value = write value)R0/WX: Undefined bit (read value = "0", No effect on write operation)
DAE
0
1
D/A converter output control bit
Output disabled
Output enabled
R/W
DA08
DA09Set the upper 2 bis of the 10-bit data
PIE
0
1
Port input enabled bit
General-purpose port input disable
General-purpose port input enable
R0/WXR0/WXR0/WXR0/WXR/W
683
CHAPTER 23 D/A Converter
23.5 Explanation of Operations of D/A Converter
Set the desired D/A output value in the DA09 to DA00 bits and then set the DAE bit to "1" to start D/A output. When setting the output value, set the upper data first followed by the lower data.
Startup of D/A ConverterEnable the D/A converter output after setting the initial 10-bit digital value. If the output is enabled first,
the analog output will go to 0V. The following shows the setting procedure.
1. Set the upper data. (DA09 and DA08 bits of DACR register, DAE bit = "0")
2. Set the lower data. (DA07 to DA00 bits of DAT register)
3. Enable D/A output (Set DAE bit of DACR register to "1". Hold DA09 and DA08 bits.)
4. Update the digital data as required.
5. Disable D/A output. (Set DAE bit of DACR register to "0".)
Reference:
The upper data setting becomes active when the lower data is set.
Updating Method of Upper DataWhen updating the upper data, the lower data must also be updated. If you do not update the lower data
after the upper data, the input setting value of the upper data will be ignored. In this case, the DA09 and
DA08 bits will maintain their previous values and the analog output will remain unchanged. The following
shows an example of how to update the upper data.
1. Set the upper data. (DA09, DA08 bits of DACR register)
2. Set the lower data. (DA07 to DA00 bits of DAT register)
3. Set the upper data. (DA09, DA08 bits of DACR register)
4. Set the lower data. (DA07 to DA00 bits of DAT register)
:
:
Updating Method of Lower DataNo special considerations apply when modifying the lower data.
The lower data can be always updated.
Operation in Standby ModeProvided the DAE bit is "1", the DA output remains unchanged when the MCU goes to standby mode
(stop, sleep. sub, or watch mode). Set the DAE bit to "0" to minimize current consumption.
684
23.6 Notes on Using D/A Converter
The following describes points to note when using the D/A converter.
• No buffer amplifier is included in the output of this D/A converter. However, an analog switch (=100(Ω)) is inserted in series with the output. Remember to take note of the required settling time for theexternal output load.
685
CHAPTER 23 D/A Converter
686
CHAPTER 24LCD Controller
This chapter describes the function and operation of the LCD controller.
24.1 Overview of LCD Controller
24.2 Block Diagram of LCD Controller
24.3 Pins of LCD Controller
24.4 LCD Controller Registers
24.5 LCD Controller Display RAM
24.6 Operation of LCD Controller
24.7 Notes when Using LCD Controller
24.8 Program Example of LCD Controller
687
CHAPTER 24 LCD Controller
24.1 Overview of LCD Controller
The LCD controller has an internal 20-byte display data memory and controls an LCD display via 4 common outputs and 40 segment outputs. 3 duty outputs can be selected to directly drive the LCD panel (liquid crystal display).
Function of LCD controller.The LCD controller displays the contents of the display data memory (display RAM) directly on the LCD
panel (liquid crystal display device) using the segment outputs and common outputs.
• Internal step-up power supply circuit (selectable option).
• Contains an LCD driving voltage split resistor. Moreover, the external division resistance can beconnected.
• Supports a maximum of 4 common outputs (COM0 to COM3) and 40 segment outputs (SEG0 toSEG39). (The number of segment outputs differs between series.
• 20 bytes (40 x 4 bits) of internal display RAM. (The display RAM size differs between series.)
• For the duty, 1/2, 1/3, or 1/4 can be selected (restricted by bias setting).
• The main clock or sub clock can be selected as the operating clock.
• Blinking function (limited by the pin)
• The direct drive of LCD panel can be done.
Table 24.1-1 lists the available bias-duty combinations.
: Recommended mode
×: Interdiction
note
• A single clock system cannot be selected.
• The 1/2 bias setting is for use with external divider resistors and cannot be used in models with aninternal step-up circuit.
Table 24.1-1 Table of Available Bias-duty Combinations
model bias 1/2 duty 1/3 duty 1/4 duty
Model with no-internal step-up
circuit
1/2 bias × ×
1/3 bias ×
Model with internal step-up circuit
1/2 bias × × ×1/3 bias ×
688
24.2 Block Diagram of LCD Controller
The LCD controller consists of the following blocks. Functionally, the unit is divided into a controller section that generates the segment and common signals based on the content of display RAM, and a driver section that drives the LCD.• LCDC control register (LCDCC) • LCDC enable register (LCDCE1 to 6)• LCDC blinking setting register (LCDCB1/2)• Display RAM• Clock selection• Timing control• Circuit for changing to AC• Common driver• Segment driver• Step-up circuit or division resistance (optional selecting)
Block Diagram of LCD Controller
Figure 24.2-1 Block Diagram of LCD Controller
LCDC control register(LCDCC)
LCDC enabled register 1 to 6(LCDCE1 to 6)
LCDC blinking setting register 1/2(LCDCB1/2)
Timing controlClock selection
Mainsystemclock
Subsystemclock
Display RAM40 x 4 bits(20 bytes)
Segm
entdriver
Circuit for
changing to AC
Com
mon
driver
Step-up circuit *C0C1
V3V2V1V0
Internal divisionresistor*
COM0COM1COM2COM3
SEG0
SEG39
::
Internal bus
DriverController
*: It is the selection the step-up circuit or the division resistor.
689
CHAPTER 24 LCD Controller
LCDC Control Register (LCDC)
Selects the clock used to generate the frame period, controls the LCD drive power supply, sets displayblanking on or off, selects the display mode, and sets the frame period clock.
LCDC enable register 1 to 6(LCDCE1 to 6)
Controls the port inputs, blink interval, and pins.
LCDC blinking setting register 1, 2 (LCDCB1/2)
Sets blinking on or off.
Display RAM
40 × 4 bit RAM for segment output signal generation. The content of this RAM memory is readautomatically synchronized with the common signal selection timing and output to the segment output pins.
Prescaler
The frame frequency is generated based on the selection from amongst the eight available frequenciesgenerated by the two clocks.
Timing controller
The common signals and segment signals are controlled based on the frame frequency and register settings.
Circuit for changing to AC
Generates AC waveform for LCD driving from the timing controller signals.
Common driver
This is the LCD common pin driver.
Segment driver
This is the LCD segment pin driver.
Step-up circuit (model with internal step-up circuit)
Step-up power supply circuit for generating the LCD drive voltage. Generates two-times or three-times thereference voltage. Note that the reference voltage must be input externally. Models with an internal step-upcircuit do not have internal divider resistors and the V0, V2, V3, C0, and C1 pins become the externalcapacitance connection pins.
Division resistance (model with no-internal step-up circuit)
Resistors used to generate the LCD drive voltage. The division resistance can put the outside. The V0 to V3pins become the divider resistor connection pins on models without an internal step-up circuit.
Supply voltage of LCD controller
Model with internal step-up circuit
The power supply voltage for the LCD driver is generated by the internal step-up circuit. Supply theexternal reference voltage to the V1 pin.
Model with no-internal step-up circuit
The power supply voltage for the LCD driver is generated using the internal divider resistors or byconnecting divider resistors to the V0 to V3 pins.
690
24.2.1 LCD Controller Power Supply Voltage (Model with Internal Step-up Circuit)
The power supply voltage for the LCD driver is generated by the step-up circuit on models with an internal step-up circuit. The V0, V2, V3, C0, and C1 pins become the external capacitance connection pins. Supply the external reference voltage to the V1 pin.
Model with Internal Step-up Circuit (Only Dual System Clock Model)
Set-up Circuit
Figure 24.2-2 shows how to connect the step-up circuit to generate a voltage of two or three times thereference voltage from the 32 kHz input clock (sub clock) and reference voltage. As the step-up circuit isdriven by the sub clock, it halts when the sub clock is stopped (in sub stop mode, etc.). When using thestep-up circuit, connect capacitors to the V0, V2, V3, C0, and C1 pins as shown in Figure 24.2-2 . As thestep-up circuit cannot generate a 1/2 bias, do not select 1/2 duty output mode (LCDCC:MS1, MS0 = 01B).
t
Figure 24.2-2 External Connection Diagram of Reference Voltage Generation Circuit and Step-up Circuit
Refer to the Data Sheet for the ratings such as the maximum value of the reference voltage that can be input
to the V1 pin.
Sub-clock oscillation circuit
C1
C0
V0
V3
V2
V1
(external input*)
C2 C3
C4 C5
Step-up circuitX0A
C2 : 0.05 µFC3 : 0.1 µFC4 : 0.05 µFC5 : 0.1 µF
X1A
691
CHAPTER 24 LCD Controller
24.2.2 Internal Division Resistance for LCD Controller (Model with No-internal Step-up Circuit)
On models without an internal step-up circuit (with internal divider resistors), the power supply voltage for the LCD driver is generated by the internal divider resistors (external divider resistors can also be connected).
Internal divider resistorInternal divider resistors are included in models that do not have an internal step-up circuit. In addition, the
external split resistor can be connected to the LCD driving power pins (V0 to V3).
The internal and external split resistors are selected by the driving power control bit (LCDCC: VSEL) of
the LCDC control register. When the VSEL bit is set to "1", the internal split resistor is supplied the power.
Set to "1" if not connecting external divider resistors and using the internal divider resistors only.
The LCD controller becomes inactive when LCD operation is halted (LCDCC:MS1, MS0 = 00B), and on
changing to watch mode (STBC:TMD = 1) if halting operation in watch mode is specified (LCDCC:
LCDEN = 0).
If setting 1/2 bias, short-circuit the V2 and V1 pins together.
Figure 24.2-3 shows the equivalent circuit when using the internal divider resistors.
Figure 24.2-3 Equivalent circuit when using
2R
Nch
Pch
R
Nch
Pch
R
Nch
Pch
R
Nch
Pch
LCDC enabled
Nch
V3
V2
V1
V0
VSEL
Vcc
V3
V2
V1
V0
It is shorting at 1/2 bias.
V0 to V3 : Voltage value at V0 to V3 pin
*
* : Only for 3V product
692
Use of internal division resistance and Intensity ControlWhen using the internal divider resistors on a 3V model, the (2R) internal resistor is included and therefore
the V1, V2, and V3 pins are at a lower voltage due to 2R. Figure 24.2-4 shows the case when the internal
divider resistors are used.
If sufficient brightness is not achieved using the internal divider resistors, connect a variable resistor (VR)
externally (between the Vcc and V3 pins) and use this to adjust the V3 voltage. Figure 24.2-5 shows an
example connection using VR.
Figure 24.2-4 State when internal divided resistance is used
Figure 24.2-5 Intensity control when internal division resistance is used
2R
R
R
R
LCDC enabled
Nch
V3
V2
V1
V0
Vcc
V3
V2
V1
V0
2R
R
R
R
LCDCenabled
Nch
V3
V2
V1
V0
Vcc
V2
V1
V0
1/2 bias 1/3 bias
* *
V3
When 5V product When 5V product
V0 to V
3 : Voltage value at V0 to V3 pin
* : Only for 3V product
2R
R
R
R
LCDCenabled
Nch
V3
V2
V1
V0
Vcc
V3
V2
V1
V0
For intensity control
VR
R
R
R
LCDCenabled
Nch
V3
V2
V1
V0
V3
V2
V1
V0
For intensity control
VR
3V product 5V product
V0 to V
3 : Voltage value at V0 to V3 pin
693
CHAPTER 24 LCD Controller
Reference:
As the internal 2R resistor is used when the LCD is operating, this means the VR is connected inparallel with 2R.
694
24.2.3 External Division Resistance of LCD Controller (Model with No-internal Step-up Circuit)
External divider resistors can be connected to the V0 to V3 pins on models that do not have an internal step-up circuit (models with internal divider resistors).Also, the brightness can be adjusted by connecting a variable resistor between the Vcc and V3 pins.
External Division Resistance (Model with No-internal Step-up Circuit) If not using the internal divider resistors on a model that does not have an internal step-up circuit, you can
connect external divider resistors to the LCD drive power supply pins (V0 to V3) instead. Figure 24.2-6
and Table 24.2-1 shows the external division resistance connection and the LCD driving voltage
corresponding to the bias-type.
Figure 24.2-6 Connection example of internal divider resistor
V0 to V3: Voltage of the V0 to V3 pins
VLCD: LCD operating voltage
Vcc
V3
V2
V1
V0
1/2 bias
VR
R
R
VLCD
Vcc
V3
V2
V1
V0
1/3 bias
VR
R
R
VLCDR
*
* : Only for 3V product
*
Table 24.2-1 LCD driving voltage setup
V3 V2 V1 V0
1/2 bias VLCD 1/2 VLCD 1/2 VLCD GND
1/3 bias VLCD 2/3 VLCD 1/3 VLCD GND
695
CHAPTER 24 LCD Controller
Use of external Divider ResistorsAs the V0 pin is connected to Vss (GND) internally via a transistor, when using external divider resistors,
you can prevent current flowing in the resistors when the LCD controller is halted by connecting the Vss
end of the divider resistors to the V0 pin. Figure 24.2-7 shows the status at using the external division
resistor.
Figure 24.2-7 State when using the external divider resistors
1) To prevent the external divider resistors from being affected by the internal divider resistors, you need to
write "0" to the drive voltage control bit in the LCDC control register (LCDCC:VSEL) to disconnect all
the internal divider resistors.
2) When the internal divider resistors are disconnected, writing a value other than "00B" to the display
mode selection bits (MS1 and MS0) in the LCDC control register turns on the LCDC enable transistor
(Q1) and current flows in the external divider resistors.
3) Writing "00B" to the display mode selection bits (MS1 and MS0) turns off the LCDC enable transistor
(Q1) and this stops the current flow in the external divider resistors.
Reference:
The externally connected RX resistors depend on the LCD you are using. Select appropriateresistances to match the LCD.
2R
R
R
R
LCDC enabled Q1
V3
V2
V1
V0
Vcc
V3
V2
V1
V0
VR
RX
RX
RX
V0 to V
3 : Voltage value at V0 to V3 pin
696
24.3 Pins of LCD Controller
This section describes the LCD controller pins.
Pins of LCD ControllerThe LCD controller pins consist of 4 common output pins (COM0 to COM3), 40 segment output pins
(SEG0 to SEG39), and the 4 LCD drive power supply pins (V0 to V3). The number of segment output pins
differs for each MCU series.
Models with an internal step-up circuit also have two capacitor connection pins (C0 and C1).
COM0 to COM3 Pins
The COM0 to COM3 pins are the LCD common outputs.
These pins are shared with the I/O ports.
SEG0 to SEG39
The SEG0 to SEG39 pins are the LCD segment output pins. The number of segment output pins differs for
each MCU series.
These pins are shared with the I/O ports.
V0 to V3
On models with an internal step-up circuit, the V0, V2, and V3 pins become the external capacitance
connection pins and the V1 pin becomes the reference voltage input pin. On models without an internal
step-up circuit, these pins become the power supply pins for driving the LCD.
These pin are shared with the I/O ports.
C0 and C1
On models with an internal step-up circuit, the C0 and C1 pins become the dedicated capacitance
connection pins for the step-up circuit.
On models without an internal step-up circuit, these pins become I/O ports.
note
To use these pins for the LCD, set the corresponding bits in the LCDC enable registers (LCDCE1 to6) to "1".
697
CHAPTER 24 LCD Controller
24.4 LCD Controller Registers
This section describes the LCD controller registers.
Register List of LCD Controller
Figure 24.4-1 LCD Controller Registers
CSS LCDEN VSEL BK MS1 MS0 FP1 FP0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
LCDC control registerLCDCC
PICTL BLSEL VE2 VE1 COM3 COM2 COM0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
LCDC enabled register 1LCDCE1
SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
LCDC enabled register 2LCDCE2
SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
COM1
SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
S1C3 S1C2 S1C1 S1C0 S0C3 S0C2 S0C1 S0C0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
S3C3 S3C2 S3C1 S3C0 S2C3 S2C2 S2C1 S2C0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
LCDC enabled register 3LCDCE3
LCDC enabled register 4LCDCE4
LCDC enabled register 5LCDCE5
LCDC enabled register 6LCDCE6
LCDC blinking setting register 1LCDCB1
LCDC blinking setting register 2LCDCB2
698
24.4.1 LCDC Control Register (LCDCC)
The LCD control register (LCDCC) is used to set the clock, display mode, and power supply control settings.
LCDC Control Register (LCDCC)
Figure 24.4-2 LCDC Control Register (LCDCC)
00010000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
R/W R/W R/W R/W R/W R/W R/W R/W
CSS LCDEN VSEL BK MS1 MS0 FP1 FP0
0
FP1
00 1
011
1
FP0 Frame cycle selection bit
215 x N/FCHSub-clock (CSS=1)Main-clock (CSS=0)
216 x N/FCH217 x N/FCH218 x N/FCH
26 x N/FCL27 x N/FCL28 x N/FCL29 x N/FCL
0MS1
00 1
011
1
MS0 Display mode selection bitLCD operation halt
1/2 duty output mode (time division number N=2)1/3 duty output mode (time division number N=3)1/4 duty output mode (time division number N=4)
Display branking selection bitDisplay
Disply blanking
BK01
LCD drive power supply control bitAt selecting internal division resistor At selecting internal step-up circuit
Using external division resistor
VSEL
0Using internal division resistor1 -
-
Operation enable bit at main stop/watch modeDisabledEnabled
LCDEN01
Clock selection bit for frame cycle oscillationMain-clockSub-clock
CSS01
FCH :FCL :R/W :
:
Main oscillation frequencySub oscillation frequencyRead, write enable (read value = write value)Initial value
699
CHAPTER 24 LCD Controller
Table 24.4-1 Functional description of each bit in LCDC control register (LCDCC)
Bit name Functions
Bit7
CSS:Clock selection bit for generating the frame cycle
• The clock to generate frame cycle for the LVD display is selected.• When this bit is "0", the LCD controller is driven by the output of the timebase timer
(which is driven by the main clock oscillation). When the bit is "1", the LCD controller is driven by the output of the watch prescaler (which is driven by the sub clock).
Note:As the main clock oscillation halts in main stop mode and sub clock mode, the output of the timebase timer cannot be used in these modes.Reference:When running on the output of the timebase timer, changing the main clock speed (using the gear function) does not affect the frame period.
Bit6
LCDEN:Main stop/Operation enable bit under watch mode
• This specifies whether the LCD controller is to continue to operate in main stop and watch (timebase timer) modes.
• When this bit is "1", LCD display continues after the MCU changes to main stop or watch mode. When the bit is "0", LCD display stops.
Note:The sub clock must be selected (CSS=1) to continue operating in main stop or watch mode.
Bit5VSEL:LCD driving power control bit
• In models with an internal divider resistors, this selects whether to connect the internal divider resistors.
• The internal divider resistors are disconnected when this bit is "0" and connected when the bit is "1". This bit must be set to "0" if connecting external divider resistors.
• For the model with internal step-up circuit, this bit is meaningless.
Bit4BK:Display blanking selection bit
• Display/non-display LCD is selected.• For display blanking (no display, BK=1), the segment output changes to a non-selection
waveform (waveform that does not result in display).
Bit3Bit2
MS1,MS0:Display mode selection bits
• Select one of three output waveform duties.• The common pin to be used is determined depending on the selected duty output mode.• When these bits are "00B", the LCD controller/driver stops the display operation.
Note:If the clock used to generate the selected frame period halts when the MCU goes to stop mode, halt operation (MB1, MS0 = 00) before changing mode.
Bit1Bit0
FP1,FP0:Frame cycle selection bits
• Select one of four LCD display frame cycles.Note:According to the LCD module to be used, calculate the optimum frame frequency and set the registers. The frame period is affected by the source oscillation frequency.
700
24.4.2 LCDC Enable Register 1 (LCDCE1)
The LCDC enable register 1 (LCDCE1) settings include port I/O control, blink period, and LCD pin enable.
LCDC Enable Register 1 (LCDCE1)
Figure 24.4-3 LCDC enable register 1 (LCDCE1)
00110000
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
R/W R/W R/W R/W R/W R/W R/W R/W
COM0 selection bitGeneral purpose I/O port
Common output
COM001
PICTL BLSEL VE2 VE1 COM3 COM2 COM0COM1
COM1 selection bitGeneral purpose I/O port
Common output
COM101
COM2 selection bitGeneral purpose I/O port
Common output
COM201
COM3 selection bitGeneral purpose I/O port
Common output
COM301
V2 to V0 selection bitGeneral purpose I/O portV2 to V0 dedicated pin
VE101
V3 selection bitGeneral purpose I/O port
V3 dedicated pin
VE201
Blink interval selection bit0.5 s1.0 s
BLSEL01
Port input control bitPort input disconnectedPort input enabled
PICTL01
R/W ::
Read, write (read value = write value)Initial value
701
CHAPTER 24 LCD Controller
Table 24.4-2 Functional Description of Each Bit in LCDC Enabled Register 1 (LCDCE1)
Bit name Functions
Bit7PICTL:Port input control bit
• Controls the port inputs that share pins with the segment and common lines.• When this bit is "0", the port inputs are disconnected to minimize current flow during LCD
output.• When this bit is "1", the port inputs are enabled. Set "1" when using the pins as ports.Note:As the port inputs are disconnected after a reset, you must set this bit to "1" if you wish to use the pins as port inputs.
Bit6BLSEL:Blink period selection bit
• Select the blink period when blinking is enabled.Reference:Blinking is enabled using LCDC blink setting registers 1 and 2 (LCDCB1, LCDCB2).
Bit5VE2:V3 selection bit
• Select the status of the V3 pin.• When this bit is "0", the pin functions as a general-purpose I/O port.• When this bit is "1", the pin functions as the V3 pin.
Bit4VE1:V2 to V0 selection bit
• Select the status of V2 to V0 pins.• When this bit is "0", the pin functions as a general-purpose I/O port.• When this bit is "1", the pin functions as the V2 to V0 pin.
Bit3COM3:COM3 selection bit
• Select the status of COM3 pin.• When this bit is "0", the pin functions as a general-purpose I/O port.• When this bit is "1", the pin functions as the COM3 pin.
Bit2COM2:COM2 selection bit
• Select the status of COM2 pin.• When this bit is "0", the pin functions as a general-purpose I/O port.• When this bit is "1", the pin functions as the COM2 pin.
Bit1COM1:COM1 selection bit
• Select the status of COM1 pin.• When this bit is "0", the pin functions as a general-purpose I/O port.• When this bit is "1", the pin functions as the COM1 pin.
Bit0COM0:COM0 selection bit
• Select the status of COM0 pin.• When this bit is "0", the pin functions as a general-purpose I/O port.• When this bit is "1", the pin functions as the COM0 pin.
702
24.4.3 LCDC Enable Register 2 to 6 (LCDCE2 to 6)
The LCDC enable registers 2 to 6 (LCDCE2 to 6) enable output for each segment pin.
LCDC Enable Register 2 to 6 (LCDCE2 to 6)
Figure 24.4-4 LCDC enable register 2 to 6 (LCDCE2 to 6)
Note:
The number of segment output pins differs for each MCU series.
LCDCE2
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
LCDCE3
00000000
Initial value
00000000
Initial value
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00000000
Initial value
R/W R/W R/W R/W R/W R/W R/W R/W
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00000000
Initial value
R/W R/W R/W R/W R/W R/W R/W R/W
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00000000
Initial value
R/W R/W R/W R/W R/W R/W R/W R/W
SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08
SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16
SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24
SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32
LCDCE4
LCDCE5
LCDCE6
Segment selection bitGeneral pourpose I/O portSEGxx segment output
SEGxx01
R/W ::
Read, write enable (read value = write value)Initial value
703
CHAPTER 24 LCD Controller
24.4.4 LCDC Blinking Setting Register 1/2 (LCDCB1/2)
LCDC blinking setting registers 1 and 2 (LCDCB1 and 2) turn blinking on or off.
LCDC Blinking Setting Register 1/2(LCDCB1/2)
Figure 24.4-5 LCDC Blinking Setting Register 1/2(LCDCB1/2)
The blinking function applies to the dots corresponding to the specified SEG0 to SEG3 and COM0 to
COM3 pin combination.
The blink period is selected by the BLSEL bit in LCDC enable register 1 (LCDCE1).
All pins in segments for which blinking is turned on blink in synchronization.
LCDCB1
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
LCDCB2
00000000
Initial value
00000000
Initial value
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Sn:Cm:
SEGn (n=0 to 3)COMm (m=0 to 3)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Blinking selection bitBlinking OFF
Blinking of SEGn/COMm ON
SnCm01
S1C3 S1C2 S1C1 S1C0 S0C3 S0C2 S0C1 S0C0
S3C3 S3C2 S3C1 S3C0 S2C3 S2C2 S2C1 S2C0
704
24.5 LCD Controller Display RAM
The display RAM is a 40 × 4-bit (20 bytes) display data memory which is used to generate the segment output signals.
Display RAM and Output PinThe content of display RAM is read automatically synchronized with the common signal selection timing
and outputted to the segment output pins.
This is converted to the selected voltage (LCD display) and outputs when the bit contents are
"1" and converted to the unselected voltage (LCD non-display) and outputs when the bit contents are "0".
As the LCD display operation is performed asynchronously of the CPU operations, the display RAM can
be read or written any timing. Pins that are not assigned as segment output pins can be set as I/O ports and
the corresponding RAM area used as normal RAM. Table 24.5-1 shows the relationship between duty/
common output and display RAM.
The correspondence between the display RAM and common/segment output pins are shown in Figure 24.5-1 .
Figure 24.5-1 Correspondence between display RAM and common/segment output pins
Note:
The number of segment output pins differs for each MCU series.
bit3 bit2 bit1 bit0bit7 bit6 bit5 bit4
SEG00SEG01
Address
bit3 bit2 bit1 bit0bit7 bit6 bit5 bit4
SEG02SEG03
n+1
bit3 bit2 bit1 bit0bit7 bit6 bit5 bit4
SEG04
:
n+2
::
::
::
:: :
SEG05
bit3 bit2 bit1 bit0bit7 bit6 bit5 bit4
SEG34SEG35
n+17
bit3 bit2 bit1 bit0bit7 bit6 bit5 bit4
SEG36SEG37
n+18
bit3 bit2 bit1 bit0bit7 bit6 bit5 bit4
SEG38n+19
SEG39
::
n
COM0COM1COM2COM3
Using area and common pin at 1/2 duty
Using area and common pin at 1/3 duty
Using area and common pin at 1/4 duty
705
CHAPTER 24 LCD Controller
: Used
- : Not used
Table 24.5-1 Relationships between duty/common outputs and display RAM bits used
Duty setting value Using Common OutputUsing Each Display Data Bit
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
1/2 2 pins (COM0 to COM1) - - - -
1/3 3 pins (COM0 to COM2) - -
1/4 4 pins (COM0 to COM3)
706
24.6 Operation of LCD Controller
This section explains the LCD controller operation.
Operation of LCD ControllerFigure 24.6-1 shows the settings required to use the LCD display.
Figure 24.6-1 Setting of LCD controller
CSS LCDEN VSEL BK MS1 MS0 FP1 FP0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
LCDCC
PICTL BLSEL VE2 VE1 COM3 COM2 COM0LCDCE1
SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00LCDCE2
SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08
COM1
SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16
SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24
SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32
S1C3 S1C2 S1C1 S1C0 S0C3 S0C2 S0C1 S0C0
S3C3 S3C2 S3C1 S3C0 S2C3 S2C2 S2C1 S2C0
LCDCE3
LCDCE4
LCDCE5
LCDCE6
LCDCB1
LCDCB2
other than 000
0
Display dataDisplay RAM
0 :Using bitSet 0
707
CHAPTER 24 LCD Controller
• If the settings in Figure 24.6-1 are set and the selected frame period generation clock is running, thecommon and segment output pins (COM0 to COM3 and SEG0 to SEG39) output the LCD panel drivewaveform in accordance with the display RAM and LCDC register.
• Use LCDCE1 to 6 to select the LCD output pins. Pins not selected as LCD outputs become general-purpose I/O ports.
• The clock used to generate the frame period can be changed during LCD display operation. However, asthe display may be distorted when the change occurs, you should always turn off the display temporarily(using the blanking (LCDCC:BK=1) function, for example) when changing the clock.
• The display drive output is a 2-frame alternating waveform selected by bias and duty settings.
• The COM2 and COM3 pin outputs in 1/2 duty mode, and the COM3 pin output in 1/3 duty mode can beused to output the deselected level waveform or as I/O ports.
• To use the blink function, set the corresponding bits in LCDC blink setting registers 1 and 2 (LCDCB1and 2) to "1" (ON). The blink period can be selected from two available settings using the BLSEL bit inthe LCDC control register (LCDCC).
Note:
If the clock used to generate the frame period is halted during LCD display, the alternating currentgeneration circuit also halts and therefore the voltage of a direct current is applied to the liquidcrystal elements. In this case, the LCD display operation must be stopped in advance. Theconditions under which the main clock (timebase timer) and sub clock (watch prescaler) halt dependon the selected clock mode and standby mode. The frame period is also affected if the timebasetimer or watch prescaler is cleared, depending on the frame period clock selection bit (LCDCC:CSS)setting.
Drive waveform for the LCDDue to the characteristics of the LCD, DC driving of the LCD causes the liquid crystal display elements to
be deteriorated due to chemical changes. Therefore, the LCD controller/driver contains an alternating
circuit and drives the LCD by the 2-frame alternating waveform. There are following three types of output
waveform:
• 1/2 bias 1/2-duty output waveforms (only the models without an internal set-up circuit)
• 1/3 bias, 1/4 duty output waveforms
• 1/3 bias, 1/4 duty output waveforms
708
24.6.1 Output Waveform of LCD Controller Operation (1/2 Duty)
The display drive output is a 2-frame alternating waveform of the multiplex driving type.For 1/2 duty, only COM0 and COM1 are used for display. Neither COM2 nor COM3 are used. 1/2 duty is not available on models with an internal step-up circuit.
1/2 bias, 1/2 duty output waveform exampleFor display, the liquid crystal elements that have the maximum potential difference between the common
and segment outputs are set "ON".
The output waveform is shown in Figure 24.6-2 , when the display RAM contents are shown in Table 24.6-
1 .
-: Not used
Table 24.6-1 Example of content for display RAM
SegmentContent of display RAM
COM3 COM2 COM1 COM0
SEG n - - 0 0
SEG n+1 - - 0 1
709
CHAPTER 24 LCD Controller
Figure 24.6-2 1/2 bias, 1/2 duty output waveform example
COM0V3V2=V1V0=Vss
COM1V3V2=V1V0=Vss
COM2V3V2=V1V0=Vss
COM3V3V2=V1V0=Vss
SEG nV3V2=V1V0=Vss
SEG n+1V3V2=V1V0=Vss
Diferrence betweenCOM0 and SEG n
V3(ON)V2Vss-V2-V3(ON)
Diferrence betweenCOM0 and SEG n+1
V3(ON)V2Vss-V2-V3(ON)
Diferrence betweenCOM1 and SEG n
V3(ON)V2Vss-V2-V3(ON)
Diferrence betweenCOM1 and SEG n+1
V3(ON)V2Vss-V2-V3(ON)
1 frame
1 cycle
V0 to V3 : Voltage value of V0 to V3 pin
710
24.6.2 Output Waveform of LCD Controller Operation (1/3 Duty)
For 1/3 duty, COM0, COM1, and COM2 are used for display. COM3 is not used.
1/3 bias, 1/3 duty output waveform exampleFor display, the liquid crystal elements that have the maximum potential difference between the common
and segment outputs are set "ON".
The output waveform is shown Figure 24.6-3 , when the display RAM contents are is shown in Table 24.6-
2 .
- : Not used
Table 24.6-2 Example of content for display RAM
SegmentContent of display RAM
COM3 COM2 COM1 COM0
SEG n - 1 0 0
SEG n+1 - 1 0 1
711
CHAPTER 24 LCD Controller
Figure 24.6-3 1/3 Bias and 1/3 Duty Output Waveform Example
COM0
V3V2
V0=Vss
COM1
COM2
COM3
SEG n
SEG n+1
Diferrence betweenCOM1 and SEG n
Diferrence betweenCOM2 and SEG n
Diferrence betweenCOM0 and SEG n+1
Diferrence betweenCOM1 and SEG n+1
1 frame
1 cycle
V1
V3V2
V0=VssV1
V3V2
V0=VssV1
V3V2
V0=VssV1
V2
V0=VssV1
V2
V0=VssV1
V3
V3
V2
VssV1
-V1-V2-V3(ON)
V2
VssV1
V3(ON)
-V1-V2-V3(ON)
V2
VssV1
V3(ON)
-V1-V2-V3(ON)
V2
VssV1
V3(ON)
-V1-V2-V3(ON)
Diferrence betweenCOM2 and SEG n+1
V2
VssV1
-V1-V2-V3(ON)
V3(ON)
Diferrence betweenCOM0 and SEG n
V2
VssV1
-V1-V2
V3(ON)
-V3(ON)
V3(ON)
V0 to V3 : Voltage value of V0 to V3 pin
712
24.6.3 Output Waveform of LCD Controller Operation (1/4 Duty)
All of COM0, COM1, COM2, and COM3 are used when 1/4 duty is selected for display.
1/3 bias, 1/4 duty output waveform exampleFor display, the liquid crystal elements that have the maximum potential difference between the common
and segment outputs are set "ON".
The output waveform is shown in Fugure 24.6-4 when the display RAM contents are shown in Table 24.6-3 .
Table 24.6-3 Example of content of display RAM
SegmentContent of display RAM
COM3 COM2 COM1 COM0
SEG n 0 1 0 0
SEG n+1 0 1 0 1
713
CHAPTER 24 LCD Controller
Fugure 24.6-4 1/3 Bias and 1/4 Duty Output Waveform Example
COM0
V3V2
V0=Vss
COM1
COM2
COM3
SEG n
SEG n+1
Diferrence betweenCOM1 and SEG n
Diferrence betweenCOM2 and SEG n
Diferrence betweenCOM0 and SEG n+1
Diferrence betweenCOM1 and SEG n+1
1 frame
1 cycle
V1
V3V2
V0=VssV1
V3V2
V0=VssV1
V3V2
V0=VssV1
V2
V0=VssV1
V2
V0=VssV1
V3
V3
V2
VssV1
-V1-V2-V3(ON)
V2
VssV1
V3(ON)
-V1-V2-V3(ON)
V2
VssV1
V3(ON)
-V1-V2-V3(ON)
V2
VssV1
V3(ON)
-V1-V2-V3(ON)
Diferrence betweenCOM3 and SEG n+1
V2
VssV1
-V1-V2-V3(ON)
V3(ON)
Diferrence betweenCOM0 and SEG n
V2
VssV1
-V1-V2
V3(ON)
-V3(ON)
V3(ON)
Diferrence betweenCOM3 and SEG n
V2
VssV1
V3(ON)
-V1-V2-V3(ON)
V3(ON)
Diferrence betweenCOM2 and SEG n+1
V2
VssV1
V3(ON)
-V1-V2-V3(ON)
V0 to V3 : Voltage value of V0 to V3 pin
714
24.7 Notes when Using LCD Controller
This section describes points to note when using the LCD controller.
Notes when Using LCD Controller• The 1/2 bias setting is for use with external divider resistors and cannot be used in models with an
internal step-up circuit.
• When using LCD pins as ports, set the PICTL bit in LCDC enable register 1 (LCDCE1) to "1" and setthe corresponding selection bits (COM/SEG) in LCDC enable registers 1 to 6 to "0".
• If the clock used to generate the frame period is halted during LCD display, the alternating currentgeneration circuit also halts and therefore a direct current is applied to the liquid crystal elements. In thiscase, the LCD display operation must be stopped in advance. The conditions under which the mainclock (timebase timer) and sub clock (watch prescaler) halt depend on the selected clock mode andstandby mode. The frame period is also affected if the timebase timer or watch prescaler is cleared,depending on the frame period clock selection bit (LCDCC:CSS) setting.
715
CHAPTER 24 LCD Controller
24.8 Program Example of LCD Controller
This section shows the program example of LCD controller.
716
CHAPTER 25Low-Voltage Detection Reset
Circuit
This chapter describes the function and operation of the low voltage detection reset circuit.
25.1 Overview of Low-Voltage Detection Reset Circuit
25.2 Block Diagram of Low-Voltage Detection Reset Circuit
25.3 Low-Voltage Detection Reset Circuit Pin
25.4 Operation of Low-Voltage Detection Reset Circuit
717
CHAPTER 25 Low-Voltage Detection Reset Circuit
25.1 Overview of Low-Voltage Detection Reset Circuit
The low-voltage detection reset circuit monitors the power supply voltage and generates a reset signal if the voltage drops below the detection voltage level. (option)
Low-Voltage Detection Reset CircuitThe circuit monitors the power supply voltage and generates a reset signal if the voltage drops below the
detection voltage level. The circuit can be selected as an option on 5V versions only. Refer to the data sheet
for details of the electrical characteristics.
Table 25.1-1 Detection Voltage of Low-Voltage Detection Reset Circuit
Releasing voltage (Typ) 2.7 V
Detecting voltage (Typ) 2.6 V
718
25.2 Block Diagram of Low-Voltage Detection Reset Circuit
Figure 25.2-1 shows a block diagram of the low-voltage detection reset circuit.
Block Diagram of Low-Voltage Detection Reset Circuit
Figure 25.2-1 Block diagram of low-voltage detection reset circuit
Reset signal
VCC
Vref
+-
719
CHAPTER 25 Low-Voltage Detection Reset Circuit
25.3 Low-Voltage Detection Reset Circuit Pin
This section explains the low-voltage detection reset circuit pin.
Pins of Low-Voltage Detection Reset CircuitVcc pin: The low-voltage detection circuit monitors the voltage at this pin.
Vss pin: GND pin used as the reference for voltage detection.
RST pin: The low-voltage detection reset signal is outputted to this pin via an internal connection in the MCU.
However, on models with a clock supervisor function, the low-voltage detection reset signal is only
generated within the MCU and is not outputted to this pin.
720
25.4 Operation of Low-Voltage Detection Reset Circuit
Generates a reset signal if the power supply voltage falls below the detection voltage.
Operation of Low-Voltage Detection Reset CircuitGenerates a reset signal if the power supply voltage falls below the detection voltage. If the voltage is
subsequently detected to have recovered, the circuit outputs a reset for the duration of the oscillation
stabilization delay time and releases.
Refer to the data sheet for details of the electrical characteristics.
Figure 25.4-1 Operation of low-voltage detection reset circuit
Operation in Standby ModeOperates continuously, including in standby modes (stop, sleep, sub, and watch modes).
Vcc
A: Display
B: Oscillation stabilization wait time
A A A
B B B
Detecting/releasingvoltage
Lower operation voltage border
RST signal
721
CHAPTER 25 Low-Voltage Detection Reset Circuit
722
CHAPTER 26Clock Supervisor
This chapter describes the functions and operation of the clock supervisor.
26.1 Overview of Clock Supervisor
26.2 Block Diagram of Clock Supervisor
26.3 Clock Supervisor Registers
26.4 Operation of Clock Supervisor
723
CHAPTER 26 Clock Supervisor
26.1 Overview of Clock Supervisor
The clock supervisor prevents a system crash by monitoring the main or sub clock oscillations (the sub clock is only present on dual clock models) and switching to an internal RC oscillator if the oscillation halts.(option)
Overview of Clock Supervisor• The clock supervisor monitors the main and sub clock oscillations and generates an internal reset if it
detects that the clock has halted. In this case, the clock supervisor switches to the internal RC clock.(The clock of the sub-clock = 2-division of the RC clock)
The reset cause register (RSRR) can be used to determine whether a reset was triggered by the clocksupervisor.
• A main clock oscillation halt is detected if the rising edge of the main clock is not detected for 4 RCclock cycles. Accordingly, a main clock oscillation halt may be detected incorrectly if the period of themain clock is longer than 4 RC clock cycles.
• A sub clock oscillation halt is detected if the rising edge of the sub clock is not detected for 32 RC clockcycles. Accordingly, a sub clock oscillation halt may be detected incorrectly if the period of the subclock is longer than 32 RC clock cycles.
• Monitoring of the main and sub clocks can be disabled independently for each clock.
• When the sub clock is halted in main clock mode, a reset does not occur immediately but instead occursif the MCU goes to sub clock mode. Output of a reset can be disabled by a register setting.
• Although the clock stops in main and sub stop modes, clock monitoring is disabled in this case.
• This function can be selected as an option on 5V versions only.
Note:
Refer to the data sheet for the period and other details about the RC oscillator.
724
26.2 Block Diagram of Clock Supervisor
The clock supervisor consists of the following blocks.• Control circuit• RC oscillation circuit• Main clock monitor• Sub clock monitor• Main clock selection• Sub clock selection• CSV control register (CSVCR)
Block Diagram of Clock SupervisorFigure 26.2-1 shows the block diagram of clock supervisor.
Figure 26.2-1 Block Diagram of Clock Supervisor
Control circuit
Internal bus
CSV control register (CSVCR)
Main-clock monitor
Sub-clock monitor
Main-clock
Sub-clock
EnableDetection
EnableDetection
RC oscillation circuit
Enable
Main-clock selection
Sub-clock selection
1/2
RC clock
Mainselection
Sub selection
Internal reset
Internal main-clock
Internal sub-clock
725
CHAPTER 26 Clock Supervisor
Control circuit
The clocks, resets, and other settings are controlled using the CSV control register (CSVCR).
RC oscillation circuit
Built-in RC oscillation circuit. The oscillation can be turned on or off via a control signal from the control
circuit.
Also used as the internal clock after a clock halted condition is detected.
Main clock monitor
Monitoring the main-clock halting.
Sub clock monitor
Monitoring the sub-clock halting.
Main clock selection
When a main clock halted condition is detected, the RC clock is outputted as the internal main clock.
Sub clock selection
When a sub clock halted condition is detected, the divided clock of the RC clock is outputted as the internal
sub clock.
CSV control register (CSVCR)
Use to control clock monitoring and the RC clock and to check if a clock halt has been detected.
726
26.3 Clock Supervisor Registers
This section describes the clock supervisor registers.
Clock Supervisor RegistersFigure 26.3-1 shows the clock supervisor registers.
Figure 26.3-1 Clock Supervisor Registers
Reserved MM SM RCE MSVE SSVE SRST Reserved
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Clock supervisor control registerCSVCR
727
CHAPTER 26 Clock Supervisor
26.3.1 Clock Supervisor Control Register (CSVCR)
The clock supervisor control register (CSVCR) is used to enable the various functions and to check status information.
Clock Supervisor Control Register (CSVCR)
Figure 26.3-2 Clock Supervisor Control Register (CSVCR)
0
0
1
1
00011100
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial vlaue
R0/W0 R/WX R/WX R/W R/W R/W R/W R0/W0
Always write "0" to this bit.Read value is always "0".
Reserved
R/W :R/WX:
R0/W0::
Read/write enabled (read value = write value)Read only (Readable, No effect on writing operation)Reserved bit (write = 0, read value = 0)Initial value
Sub-clock monitor enable bitSub-clock monitor disable
SSVE0
Sub-clock monitor enable1
Reset generation enable bit *
Not generating resetGenerating reset
SRST01
Reserved MM SM RCE MSVE SSVE SRST Reserved
*: When the sub-clock halting was detected at transision to main mode to sub mode.
Main-clock monitor enable bitMain-clock monitor disable
MSVE
Main-clock monitor enable
RC clock oscillation enable bitRC clock oscillation stop
RCE
RC clock oscillation enable
0
0
Sub-clock halt detection bitUndetection of sub-clock halt
SM
Detection of sub-clock halt
Main-clock halt detection bitUndetection of main-clock halt
MM
Detection of main-clock halt
1
1
Always write "0" to this bit.Read value is always "0".
Reserved
728
Note:
After power-on, the clock supervisor starts monitoring immediately after the oscillation stabilizationdelay time for the main clock elapses. Accordingly, the oscillation stabilization delay time must belonger than the time required for the main and sub clock oscillations to start.
Table 26.3-1 Functional Description of Each Bit in Clock Supervisor Control Register (CSVCR)
Bit name Functions
Bit7 Reserved bitReserved bit• Always write "0" to this bit.The read value is always 0.
Bit6MM: Main-clock halt detection bit
This bit indicates that the clock supervisor function has detected that the main clock oscillation has stopped."1": Main clock oscillation halt detected."0": Main clock oscillation halt not detected.No effect on writing "1" to this bit
Bit5SM: Sub-clock halt detection bit
This bit indicates that the clock supervisor function has detected that the sub clock oscillation has stopped."1": Sub clock oscillation halt detected."0": Sub clock oscillation halt not detected.No effect on writing "1" to this bit
Bit4
RCE:RC clock oscillation enabled bit
This bit enables the RC oscillation."1": Enabled (initial value) "0": DisabledWhen writing "0" to this bit, check that the clock monitor function is disabled and that the MM and SM bits are "0".
Bit3
MSVE:Main-clock monitoring enabled bit
This bit enables monitoring of the main clock oscillation."1": Enables monitoring of the main clock oscillation."0": Disables monitoring of the main clock oscillation.This bit is set to "1" only by a power-on reset.
Bit2
SSVE:Sub-clock monitoring enabled bit
This bit enables monitoring of the sub clock oscillation."1": Enables monitoring of the sub clock oscillation."0": Disables monitoring of the sub clock oscillation.This bit is set to "1" only by a power-on reset.
Bit1SRST: Reset generation enable bit
This bit enables a reset output when changing to sub mode."1": Generates a reset if the MCU goes from main clock mode to sub clock mode when the sub
clock is halted."0": Does not generate a reset if the MCU goes from main clock mode to sub clock mode when
the sub clock is halted.
Bit0 Reserved bitReserved bit• Always write "0" to this bit. The read value is always 0.
729
CHAPTER 26 Clock Supervisor
26.4 Operation of Clock Supervisor
This section describes the operation of the clock supervisor.
Operation of Clock SupervisorThe clock supervisor monitors the main and sub clock oscillations and generates an internal reset if the
clock halts for longer than a certain time. In this case, the clock supervisor switches to the internal RC
clock.
The following describes the operation in each clock mode.
Main clock oscillation halt in main clock mode
In main clock mode, the condition used to detect whether the main clock oscillation has halted is that no
rising edge is detected on the main clock for 4 cycles of the RC clock.
If a main clock halted condition is detected, a reset is generated and the main clock switches over to the RC
clock.
As the RC clock is used to detect whether the main clock has halted, a main clock halt may be detected by
mistake if the main clock is set to a low speed (period longer than 4 RC clock cycles).
The clock supervisor does not detect the main clock during stop mode.
Sub-clock oscillation halting at main-clock mode (only dual system model)
In main clock mode, the condition used to detect whether the sub clock oscillation has halted is that no
rising edge is detected on the sub clock for 32 cycles of the RC clock.
Although no reset is generated immediately if a sub clock halted condition is detected in main clock mode,
the sub clock changes to use the RC clock divided by two.
A reset can be generated when the MCU changes from main clock mode to sub clock mode with a sub
clock halted condition present, depending on the SRST bit setting in the clock supervisor control register
(CSVCR).
As the RC clock is used to detect whether the sub clock has halted, a sub clock halt may be detected by
mistake if the sub clock is set to a low speed (period longer than 32 RC clock cycles).
The clock supervisor does not detect the sub clock during stop mode.
Sub-clock oscillation halting at sub-clock mode (only dual system model)
In sub clock mode, the condition used to detect whether the sub clock oscillation has halted is that no rising
edge is detected on the sub clock for 34 cycles of the RC clock.
If a sub clock halted condition is detected, a reset is generated and the MCU changes to main clock mode.
In this case, the sub clock changes to use the RC clock divided by two.
As the RC clock is used to detect whether the sub clock has halted, a sub clock halt may be detected by
mistake if the sub clock is set to a low speed (period longer than 32 RC clock cycles).
The clock supervisor does not monitor the sub clock during stop mode.
Main-clock oscillation halting at sub-clock mode (only dual system model)
As the main clock is always halted in sub clock mode, the main clock is not detected in this mode.
730
CHAPTER 27480-Kbit Flash Memory
This chapter describes the function and operation of 480-Kbit flash memory.
27.1 Overview of 480-Kbit Flash Memory
27.2 Registers and Sector/Configuration of Flash Memory
27.3 Flash Memory Status Register (FSR)
27.4 Flash Memory Sector Write Control Register (SWRE0/1)
27.5 Flash Memory Auto Algorithm Start-up Method
27.6 Check Execution State of Automatic Algorithm
27.7 Details of Programming/Erasing Flash Memory
27.8 Features of Flash Security
731
CHAPTER 27 480-Kbit Flash Memory
27.1 Overview of 480-Kbit Flash Memory
There are three ways of programming and erasing data to flash memory as follows:• Parallel writer• Programming and erasing using serial writer• Write/delete operation by program executionThis section describes "writing/erasing by program execution".
Overview of 480-Kbit Flash Memory480-KB flash memory is located from 1000H to FFFFH on the CPU memory map. The function of the flash
memory I/F circuit provides read access and program access from the CPU to flash memory.
As flash memory writing or erasing can be performed by an instruction from the CPU via the flash memory
interface circuit, the flash memory chip can be reprogrammed to update program or data while still on the
mounted state.
Data can be updated by executing a program not only in RAM but also in flash memory in dual-operation
mode. In addition, an erase/program and a read can be executed concurrently in the different banks (the
upper and lower banks).
Features of 480-Kbit Flash Memory• Sector configuration: 60K words x 8 bits (4K x 4 + 16K x 2 + 4K x 3)
• Tow-bank configuration, enabling simultaneous execution of an erase/program and a read
• Automatic program algorithm (Embedded AlgorithmTM)
• Erase pause/restart function
• Detects completion of writing/erasing using data polling or toggle bit functions
• Detects completion of writing/erasing by CPU interrupts
• Sector erase function (any combination of sectors)
• Programming/erase count 10,000 (min.)
• Flash read cycle time (min.): 1 machine cycle
• Embedded AlgorithmTM is a registered trademark of Advanced Micro Devices, Inc.
732
Programming and Erasing Flash Memory• It is not possible to write to and read from the same bank of flash memory at the same time.
• When data is written to or erased from the flash memory, the program is executed by the different bankfrom the bank to be written/erased or the program in the flash memory is first copied to RAM andexecuted so that writing to the flash memory can be performed.
733
CHAPTER 27 480-Kbit Flash Memory
27.2 Registers and Sector/Configuration of Flash Memory
This section explains the registers and the sector/bank configuration of flash memory.
List of Flash Memory Register and Initial Value
Figure 27.2-1 List of Flash Memory Register and Initial Value
Sector/Bank Configuration of 480-Kbit Flash MemoryFigure 27.2-2 shows the sector configuration in the 480-Kbit flash memory. The upper and lower addresses
of each sector are given in the figure.
Sector configuration
When the CPU accesses flash memory, SA1 to SA9 are located from 1000H to FFFFH.
Bank configuration
The flash memory consists of lower banks SA1 to SA3 and upper banks SA4 to SA9.
0 00Flash memory status register(FSR)
x00
6 5 4 3 2 1
00
7 0bit
0 00Flash memory sector write control register (SWRE0)
000
6 5 4 3 2 1
00
7 0bit
0 00Flash memory sector write control register (SWRE1)
000 00
bit
x : Indeternimate
6 5 4 3 2 17 0
734
Figure 27.2-2 Sector Configuration of 512 Kbit Flash Memory
1 0 0 0 H
1 F F F H
2 0 0 0 H
2 F F F H
3 0 0 0 H
3 F F F H
CPU address
1 1 0 0 0 H
11FFFH
1 2 0 0 0 H
12FFFH
1 3 0 0 0 H
13FFFH
Writer address*
SA3 (4K byte)
Flash memory
SA1 (4K byte)
SA2 (4K byte)
* : The write address is equivalent to the CPU address when data is written to the flash memory using parallel writer. When a genelal-purpose writer is used for writing/erasing, this address is used for writing/erasing.
Low
er b
ank
4 0 0 0 H
7 F F F H
8 0 0 0 H
B F F F H
C 0 0 0 H
C F F F H
D 0 0 0 H
D F F F H
1 4 0 0 0 H
17FFFH
1 8 0 0 0 H
1BFFFH
1C000H
1CFFFH
1D000H
1DFFFH
SA7 (4K byte)
SA4 (16K byte)
SA5 (16K byte)
SA6 (4K byte)
Upp
er b
ank
E 0 0 0 H
E F F F H
F 0 0 0 H
F F F F H
1E000 H
1EFFFH
1 F 0 0 0 H
1FFFFH
SA8 (4K byte)
SA9 (4K byte)
735
CHAPTER 27 480-Kbit Flash Memory
27.3 Flash Memory Status Register (FSR)
Figure 27.3-1 lists the functions of the flash memory status register (FSR).
Flash Memory Status Register (FSR)
Figure 27.3-1 Flash Memory Status Register (FSR)
Reset value
0 0 0 X 0 0 0 0 B
45 3 2 1 07 6
R0/WX R/W0R/WXR(RM1),W R/WR/WR0/WX R/W
Undefined bit
Reserved
0
Reserved bit
Be sure to set to "0".
RDY
0
1
Flash memory programming/erasing status bit
Data is being programming/erasing (disable programming/erasing next data)
Data programming/erasing has been completed (disable programming/erasing next data)
0
1
Flash memory operation flag bit
Data is being programming/erasing.
Data programming/erasing has been completed.
RDYIRQRead
Clear this bit.
No effect
: IndeterminateX : Reset value
: Read enabled writing value is "0". R/W0 : Read only enabled. Writing has no effect on the operation. R/WX
: Read and write enabledR/W
SSEN
0
1
Sector change enable bit
SA3 is mapped to address 3000H to 3FFFH and SA9 to address F000H to FFFFH.
SA9 is mapped to address 3000H to 3FFFH and SA3 to address F000H to FFFFH.
Undefined bit
Read value is always "0", Writing has no effect on the operation.
RDYIRQ SSENIRQEN WRERDY- - Reserved
WRE
0
1
Flash memory programming/erasing enable bit
Disable programming/erasing flash memory
Enable programming/erasing flash memory
IRQEN
0
1
Interrupt enable bit of programming/erasing flash memory
Disable interrupt by completion of programming/erasing.
Enable interrupt by completion of programming/erasing.
: Read and write enabled ("1" is read at read-modify-write instruction and reading value and writing value are different.)
R(RM1),W
Read value is always "0", Writing has no effect on the operation.
: Reading value is always "0". Writing has no effect on the operation. R0/WX
Write
736
Table 27.3-1 Functions of Flash Memory Status Register (FSR)
Bit Name Functions
Bit7Bit6
-:Undefined bits The read value is always "0". The write does not influence the operation.
Bit5RDYIRQ:Flash memory operation flag bit
This bit shows the operating state of flash memory.The RDYIRQ bit is set to "1" upon completion of the flash memory automatic algorithm when flash memory writing/erasing is completed.• An interrupt request occurs when the RDYIRQ bit is set to "1" if interrupts triggered by the
completion of flash memory writing/erasing have been enabled (FSR:IRQEN = 1).• If the RDYIRQ bit is set to "0" when flash memory writing/erasing is completed, further flash
memory writing/erasing is disabled.When set to 0: The bit is cleared.When the bit is set to 1: No effect."1" is read from the bit whenever a read modify write (RMW) instruction is used.
Bit4RDY: Flash memory programming/erasing status bit
This bit shows the programming/erasing status of flash memory.• Flash memory writing/erasing cannot be performed with the RDY bit set to "0".• A suspend command such as a read/reset command or sector-erase suspend command can be
accepted even when the RDY bit contains "0". The RDY bit is set to "1" upon completion of writing/erasure.
• It takes a delay of two machine clock (MCLK) cycles after the issuance of a write/erase command for the RDY bit to be set to "0". Read this bit after, for example, inserting NOP twice after the issuance of the write/erase command.
Bit3Reserved:Reserved bit
Be sure to set this bit to "0".
Bit2
IRQEN: Interrupt enable bit of programming and erasing flash memory
This bit enables or disables an interrupt request as programming/erasing flash memory is terminated.When the bit is set to "1": An interrupt request occurs when the flash memory operation
flag bit is set to "1" (FSR:RDYIRQ = 1).When the bit is set to "0": No interrupt request occurs even when the flash memory
operation flag bit is set to "1" (FSR:RDYIRQ = 1).
Bit1WRE: Flash memory programming/erasing enable bit
This bit enables or disables the programming/erasing of flash memory area.Set the WRE bit before invoking a flash memory write/erase command.When the bit is set to "0": No write/erase signal is generated even when a write/erase
command is input.When the bit is set to "1": Flash memory writing/erasing can be performed after a write/
erase command is input.• When flash memory is not to be written or erased, set the WRE bit to "0" to prevent it from
being accidentally written or erased.• To program data into the flash memory, set FSR:WRE to 1 to write-enable the flash memory
and set the flash memory write control register (SWRE0/1). When FSR:WRE disables writing (contains "0"), write access to flash memory does not take place even though it is enabled by the flash memory write control register (SWRE0/1).
Bit0SSEN: Sector change enable bit
This setup bit is used to replace the upper bank SA9 containing an interrupt vector with the lower bank SA3 in dual-operation mode.When the bit is set to "0": SA3 and SA9 are mapped to addresses 3000H to 3FFFH and
F000H to FFFFH, respectively.When the bit is set to "1": SA9 and SA3 are mapped to addresses 3000H to 3FFFH and
F000H to FFFFH, respectively.For details, see Chapter xx "Dual-operation Flash Memory".
737
CHAPTER 27 480-Kbit Flash Memory
27.4 Flash Memory Sector Write Control Register (SWRE0/1)
The flash memory sector write control registers (SWRE0/1) exists in the flash memory interface to be used to set the flash memory write-protect feature.
Flash Memory Sector Write Control Registers (SWRE0/1)The flash memory sector write control registers (SWRE0/1) contain the bits to enable/disable writing to
individual sectors (SA1 to SA9). The initial value of each bit is "0" to disable writing. Writing 1 to one of
the bits write-enables the corresponding sector. Writing 0 to it prevents an accidental write from being
executed to the sector. Once you have written 0 to the bit, therefore, you cannot write to the sector even
though you write 1 to the bit. You have to reset the bit before you can write to the sector.
Figure 27.4-1 Flash Memory Sector Write Control Registers (SWRE0/1)
bit 7
R0/WX
SA7E SA6E SA5E SA4E SA3E SA2E
SA9E SA8E
6
R0/WX
5
R0/WX
4
R0/WX
3
R0/WX
2
R0/WX
1
R/W
0
R/W
- - - - - -
SA1E Reserved
R/W R/W R/W R/W R/W R/W R/W R/W0
: Sector write enabled: Sector write disabled [initial value]
: Read and write enabled
SWRE0
SWRE1
Initial value
00000000B
Initial value
00000000B
bit 7 6 5 4 3 2 1 0
: Read enabled. Writing value is "0". : Reading value is always "0". Writing has no effect on the operation.
R/WR/W0R0/WX01
738
Figure 27.4-2 Examples of Flash Memory Write-disabled/-enabled/-protected States by Flash Memory Sector Write Control Registers (SWRE0/1)
Programming disable:
State of "0". The register corresponding to each sector can be write-enabled (set to "1") with no "0"written in the flash memory sector write control register (SWRE0/1). (State immediately after a reset).
Write enabled:
State of "1 ". Data can be written to the corresponding sector.
Write protected:
State of "0 ". The register corresponding to each sector cannot be write-enabled (set to "1") even bywriting "1" to it with "0" written in the flash memory sector write control register (SWRE0/1).
Programmingdisable
Programmingenable
Write protected Programming disable
Programmingdisable Write protected Programming disable
Programmingdisable Write protected Programming disable
Programmingdisable Programming enable Programming disable
RST
SA1E
SA2E
SA3E
SA4E
Initial value Initial valueRegister
writeRegister
write
739
CHAPTER 27 480-Kbit Flash Memory
Flash Memory Sector Write Control Register (SWRE0/1) Setup FlowchartSet the FSR:WRE bit and write-enable or write-protect each sector by setting the corresponding bit in the
flash memory sector write control register (SWRE0/1) to "1" or "0", respectively. Note that data must be
written in words. Note also that no bit manipulation instruction can be used for setting.
Table 27.4-1 Functions of Flash Memory Sector Write Control Registers (SWRE0/1)
Register Name
Bit Name Functions
SWRE0
Bit7Bit6Bit5Bit4Bit3Bit2
-:Undefined bits The read value is always 0. The write does not influence the operation.
Bit1Bit0
SA9E to SA1E: Programing function setting bit
These bits are used to set the accidental write preventive function setting bit for the individual sectors of the flash memory. Writing "1" to one of these bits enables writing the corresponding sector. Writing "0" to the bit write-protects that sector (prevents an accidental write to the sector). Resetting the bit initializes it to 0 (write-protecting the sector).
Writing setup bits and corresponding flash sectors
Write-disabled: State of "0". The register corresponding to each sector can be write-enabled (set to "1") with no "0" written in the flash memory sector write control register (SWRE0/1). (State immediately after a reset).Write-enabled:1 status. Data can be written to the corresponding sector.Accidental write prevented:0 status. The register corresponding to each sector cannot be write-enabled (set to "1") even by writing "1" to it with "0" written in the flash memory sector write control register (SWRE0/1).
SWRE1
Bit7Bit6Bit5Bit4Bit3Bit2Bit1
Bit0 Reserved: reserved bit Be sure to set this bit to "0".
Bit nameSA9ESA8ESA7ESA6ESA5ESA4ESA3ESA2ESA1E
Sector corresponding to flash
SA9SA8SA7SA6SA5SA4SA3SA2SA1
740
Figure 27.4-3 Sample Procedure for Flash Memory Write-enable/protect Setting
Setting of FSR: WRE bitTo write to flash memory, set FSR:WRE to "1" to write-enable it and set the flash memory sector write
control register (SWRE0/1). When FSR:WRE disables writing (contains "0"), write access to flash memory
does not take place even though it is enabled by the flash memory sector write control register (SWRE0/1).
Writing starts
Internal address read
Write command sequence(1) UAAA <- AA(2) U554 <- 55(3) UAAA <- A0(4) Write address <- write data
Next address
Internal address read
FSR: WRE (bit1)Flash memory write-enabled
SWRE0/1Set flash memory write-protected(write-protected sector is 0, and write sector is 1)
Data polling(DQ7)
Data polling(DQ7)
Data
Data
Timing limit(DQ5)
1
Writing completes
0
Last address
YES
NO
FSR: WRE (bit1)Flash momery write-disabled
Erite error
Data
Data
741
CHAPTER 27 480-Kbit Flash Memory
27.5 Flash Memory Auto Algorithm Start-up Method
There are four types of commands that invoke the flash memory automatic algorithm: read/reset, write, chip-erase, and sector-erase. The sector erase command is capable of suspending and resuming.
Command Sequence TableTable 27.5-1 lists the commands used in programming/erasing flash memory.
Note:
• Addresses in the table are the values in the CPU memory map. All addresses and data arehexadecimal values. However, "X" is an arbitrary value.
• Address "U" in the table is not arbitrary, whose four bits (bits 15 to 12) must have the same valueas RA, PA, and SA.
Example: If RA=C48EH, U=C, If PA=1024H, U=1If SA=3000H, U=3,
• The chip erase command is accepted only when all sectors have been write-enabled. The chiperase command is ignored if the bit for any sector in the flash memory sector write control register(SWRE0/1) has been set to "0" (to write-disable or write-protect the sector).
Table 27.5-1 Command Sequence Table
1st bus write cycle
2nd bus write cycle
3rd bus write cycle
4th bus write cycle
5th bus write cycle
6th bus write cycle
Address Data Data Data Data Data DataAddress Address Address Address Address
Command sequence
Read/reset*
Read/reset*
Write
Chip erase
Sector erase suspendSector erase resume
Entering address "UXXX" and data "B0H" suspends erasing during sector erasing
Entering address "UXXX" and data "30H"starts erasing after sector erase suspend
Bus write
access
1
4
4
6
6
XXXXH
UAAAH
UAAAH
XAAAH
UAAAH
F0H
AAH
AAH
AAH
AAH
-
55H
55H
55H
55H
-
F0H
A0H
80H
80H
-
RD
PD
AAH
AAH
-
-
-
55H
55H
-
-
-
10H
30H
-
U554H
U554H
X554H
U554H
-
UAAAH
UAAAH
XAAAH
UAAAH
-
RA
PA
XAAAH
UAAAH
-
-
-
X554H
U554H
-
-
-
XAAAH
SASector erase
RA : Read addressPA : Write addressSA : Sector address (specify arbitrary one address in sector)RD : Read dataPD : Write dataU : Upper 4-bit that is same as RA, PA, and SA* : Both of the two types for read/reset command can reset the flash memory to read mode.
742
Notes on Command IssuancePay attention to the following points when issuing commands in the command sequence table:
Write-enable each required sector before issuing the first command.
The upper address U bits (bits 15 to 12) used when commands are issued must have the same value as RA,
PA, and SA, from the first command on. If the above measures are not followed, commands are not
recognized normally. Execute a reset to initialize the command sequencer in the flash memory.
743
CHAPTER 27 480-Kbit Flash Memory
27.6 Check Execution State of Automatic Algorithm
As the flash memory uses the automatic algorithm for a process flow for writing/erasing, you can check its internal operating status with hardware sequence flags.
Hardware Sequence Flag
Overview of hardware sequence flag
The hardware sequence flag consists of the following 5-bit outputs:
• Data polling flag (DQ7)
• Toggle bit flag (DQ6)
• Timing limit over flag (DQ5)
• Sector Deletion Timer Flag (DQ3)
• Toggle bit 2 flag (DQ2)
The hardware sequence flags tell whether the write, chip-erase, or sector-erase command has been
terminated and whether an erase code write can be performed.
You can refer hardware sequence flags by read access to the address of each relevant sector in flash
memory after setting command sequence. Note, however, that hardware sequence flags are outputted only
for the bank on a command-issued side. Table 27.6-1 gives the bit allocation of the hardware sequence
flags.
• To know whether the automatic write, chip-erase, or sector-erase command is being executed or hasbeen terminated, check the hardware sequence flags or the flash memory write/erase status bit in theflash memory status register (FSR:RDY). Programming/erasing is terminated, returning to the read/resetstate.
• When creating a write/erase program, read data after checking the termination of automatic writing/erasing with the DQ7, DQ6, DQ5, DQ3, and DQ2 flags.
• The hardware sequence flags can also be used to check whether the second sector erase code write andlater are in effect.
Table 27.6-1 Bit Allocation of Hardware Sequence Flags
Bit No. 7 6 5 4 3 2 1 0
Hardware sequence flag DQ7 DQ6 DQ5 - DQ3 DQ2 - -
744
Explanation of hardware sequence flag
Table 27.6-2 lists the functions of the hardware sequence flag.
Table 27.6-2 List of Hardware Sequence Flag Functions
State DQ7 DQ6 DQ5 DQ3 DQ2
State transition at normal operation
Programming → Completed(when program address specified)
DQ7 →DATA: 7
Toggle →DATA: 6
0 →DATA: 5
0 →DATA: 3
1 →DATA:2
Chip and sector erasing → Completed 0 →1 Toggle →Stop 0 →1 1 Toggle →Stop
Sector erasing wait → Started 0 Toggle 0 0 →1 Toggle
Erasing → Sector erasing suspended(Sector being erased)
0 →1 Toggle →1 0 1 →0 Toggle
Sector erasing suspended → Resumed(Sector being erased)
1 →0 1 →Toggle 0 0 →1 Toggle
Sector erasing being suspended(Sector not being erased)
DATA: 7 DATA: 6 DATA: 5 DATA: 3 DATA: 2
Abnormal operationProgramming DQ7 Toggle 1 0 1
Chip and sector erasing 0 Toggle 1 1 *
*: If the DQ5 flag is 1 (timing limit over), the DQ2 flag performs the toggle operation for continuous reading from the programming/erasing sector but does not perform the toggle operation for reading from other sectors.
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CHAPTER 27 480-Kbit Flash Memory
27.6.1 Data Polling Flag (DQ7)
The data polling flag (DQ7) is a hardware sequence flag and is mainly used to notify that the automatic algorithm is executing or has been completed using the data polling function.
Data Polling Flag (DQ7)Table 27.6-3 and Table 27.6-4 give the state transition of the data polling flag.
At programming
When read access takes place during execution of the automatic write algorithm, the flash memory outputsthe inverted value of bit 7 in the last data written to DQ7.
If read access takes place on completion of the automatic write algorithm, the flash memory outputs bit 7 ofthe value read from the read-accessed address to DQ7.
At chip/sector erasing
During executing chip and sector erasing algorithms, when read access is made to the currently beingerasing sector, bit 7 of flash memory outputs "0". When chip erasing/sector erasing is terminated, bit 7 offlash memory outputs "1".
At sector erasing suspension
• When read access takes place with a sector-erase operation suspended, the flash memory outputs "1" toDQ7 if the read address is the sector being erased. If not, the flash memory outputs bit 7 (DATA:7) ofthe value read from the read address to DQ7.
• Referring this flag together with the toggle bit flag (DQ6) permits a decision on whether flash memoryis in the erase suspended state or which sector is being erased.
Note:
Read access to the specified address while the automatic algorithm starts is ignored. Data reading isallowed after the data polling flag (DQ7) is set to "1". Data reading after the end of the automaticalgorithm should be performed following read access after completion of data polling has beenchecked.
Table 27.6-3 State Transition of Data Polling Flag (State Change at Normal Operation)
Operating State
Programming → Completed
Chip, Sector Erasing → Completed
Wait for Sector Erasing →
Started
Sector Erasing → Sector Erasing Temporary Stop(Sector Being
Erased)
Sector Erasing Temporary Stop →
Resume (Sector Being
Erased)
Sector Erasing Now Temporary
Stop(Sector Not
Erased)
DQ7 DQ7 →DATA: 7 0 →1 0 0 →1 1 →0 DATA: 7
Table 27.6-4 State Transition of Data Polling Flag (State Change at Abnormal Operation)
Operating State Programming Chip and Sector Erasing
DQ7 DQ7 0
746
27.6.2 Toggle Bit Flag (DQ6)
The toggle bit flag (DQ6) is a hardware sequence flag and is used to notify that the automatic algorithm is being executed or in the end state using the toggle bit function.
Toggle Bit Flag (DQ6)Table 27.6-5 and Table 27.6-6 give the state transition of the toggle bit flag.
At programming and chip/sector erasing
* When read access is executed continuously during execution of the automatic write algorithm or chip-
erase/sector-erase algorithm, the flash memory toggles the output between "1" and "0" at each access.
* When read access is executed continuously after the automatic write algorithm or chip-erase/sector-erase
algorithm is terminated, the flash memory outputs bit 6 (DATA:6) of the value read from the read address
at each read access.
At sector erasing suspension
If a read access is made in the sector erasing suspension state, flash memory outputs "1" when the read
address is the sector being erased. If a read access is made in the sector erasing suspension state, flash
memory outputs bit 6 (DATA: 6) for the read value of the read address when the read address is not the
sector being erased.
Table 27.6-5 State Transition of Toggle Bit Flag (State Change at Normal Operation)
Operating State
Programming → Completed
Chip, Sector Erasing → Completed
Wait for Sector Erasing →
Started
Sector Erasing → Sector Erasing Temporary Stop(Sector Being
Erased)
Sector Erasing Temporary Stop → Resume (Sector Being Erased)
Sector Erasing Now Temporary
Stop(Sector Not Being
Erased)
DQ6Toggle →DATA:
6Toggle →Stop Toggle Toggle →1 1 →Toggle DATA: 6
Table 27.6-6 State Transition of Toggle Bit Flag (State Change at Abnormal Operation)
Operating State Programming Chip and Sector Erasing
DQ6 Toggle Toggle
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CHAPTER 27 480-Kbit Flash Memory
27.6.3 Timing Limit Over Flag (DQ5)
The timing limit excess flag (DQ5) is a hardware sequence flag indicating that the automatic algorithm has been executed beyond the specified time (required for writing/erasing) internal to the flash memory.
Timing Limit Over Flag (DQ5)Table 27.6-7 and Table 27.6-8 give the state transition of the timing limit over flag.
At programming and chip/sector erasing
When read access is executed with the write or chip-erase/sector-erase automatic algorithm invoked, the
flag outputs "0" when the algorithm execution time is within the specified time (required for writing/
erasing) or "1" when it exceeds that time.
The timing limit excess flag (DQ5) can be used to check whether writing/erasing has succeeded or failed
regardless of whether the automatic algorithm has been running or terminated. When the timing limit
excess flag (DQ5) outputs "1", it indicates that writing has failed if the automatic algorithm is still running
for the data polling or toggle bit function.
If an attempt is made to write "1" to a flash memory address holding "0", for example, the flash memory is
locked, preventing the automatic algorithm from being terminated and valid data from being outputted from
the data polling flag (DQ7). As the toggle bit flag (DQ6) does not stop toggle operation, the time limit is
exceeded and the timing limit excess flag (DQ5) outputs "1". The state that timing limit over flag (DQ5)
outputs "1" means that the flash memory is not being used correctly; it does not mean that the flash
memory is faulty. When this state occurs, execute the reset command.
Table 27.6-7 State Transition of Timing Limit Over Flag (State Change at Normal Operation)
Operating State
Programming → Completed
Chip, Sector Erasing → Completed
Wait for Sector Erasing →
Started
Sector Erasing → Sector Erasing Temporary Stop(Sector Being
Erased)
Sector Erasing Temporary Stop → Resume (Sector Being Erased)
Sector Erasing Now Temporary
Stop(Sector Not Being
Erased)
DQ5 0 →DATA: 5 0 →1 0 0 0 DATA: 5
Table 27.6-8 State Transition of Timing Limit Over Flag (State Change at Abnormal Operation
Operating State Programming Chip and Sector Erasing
DQ5 1 1
748
27.6.4 Sector Deletion Timer Flag (DQ3)
The sector erase timer flag (DQ3) is a hardware sequence flag and is used to notify during the period of waiting for sector erasing after the sector erase command has started.
Sector Deletion Timer Flag (DQ3)Table 27.6-9 and Table 27.6-10 give the state transition of the sector erase timer flag.
At sector erasing
• If a read access made after starting the sector erase command is within a sector erasing wait period, thesector erasing timer flag (DQ3) outputs "0". The flag outputs "1" when the sector erase wait period isexceeded.
• If the sector erasing timer flag (DQ3) is "1", indicating that the automatic algorithm for sector erasing bythe data polling or toggle bit function is in progress (DQ7 = 0; DQ6 produces a toggle output), sectorerasing is performed. If any command other than the sector erasing suspension is set, it is ignored untilsector erasing is terminated.
• If the sector erasing timer flag (DQ3) is "0", flash memory can accept the sector erase command. Toprogram the sector erase command, check that the sector erasing timer flag (DQ3) is "0". If the flag is"1", flash memory may not accept the sector erase command of suspending.
At sector erasing suspension
• If a read access is made in the sector erasing suspension state, flash memory outputs "1" when the readaddress is the sector being erased. If a read access is made in the sector erasing suspension state, flashmemory outputs bit 3 (DATA: 3) for the read value of the read address when the read address is not thesector being erased.
Table 27.6-9 State Transition of Sector Erase Timer Flag (State Change at Normal Operation)
Operating State
Programming → Completed
Chip, Sector Erasing → Completed
Wait for Sector Erasing →
Started
Sector Erasing → Sector Erasing Temporary Stop(Sector Being
Erased)
Sector Erasing Temporary Stop → Resume (Sector Being Erased)
Sector Erasing Now Temporary
Stop(Sector Not Being
Erased)
DQ3 0 →DATA: 3 1 0 →1 1 →0 0 →1 DATA: 3
Table 27.6-10 State Transition of Sector Erase Timer Flag (State Change at Abnormal Operation)
Operating State Programming Chip and Sector Erasing
DQ3 0 1
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CHAPTER 27 480-Kbit Flash Memory
27.6.5 Toggle Bit 2 Flag (DQ2)
The toggle bit 2 flag (DQ2) is a hardware sequence flag that notifies flash memory that sector erasing is being suspended using toggle bit function.
Toggle Bit Flag (DQ2)Table 27.6-11 and Table 27.6-12 give the state transition of the toggle bit flag.
*: If the DQ5 flag is 1 (timing limit over), the DQ2 flag performs the toggle operation for continuous reading from the programming/erasing sector but does not perform the toggle operation for reading from other sectors.
At sector erasing
• If a continuous read access is made during the execution of the automatic algorithm for chip erasing/sector erasing, flash memory toggle-outputs "1" and "0" alternately every reading.
• If read access is continued after chip deletion/sector deletion algorithm ends, the flash memory outputsread value bit 2 (DATA:2) of read address for each read operation.
At sector erasing suspension
• If a read access is made in the sector erasing suspension state, flash memory toggle-outputs "1" and "0"alternately when the read address is the sector being erased. If a read access is made in the sector erasingsuspension state, flash memory outputs bit 2 (DATA: 2) for the read value of the read address when theread address is not the sector being erased.
• If programming is performed in the sector erasing suspension state, flash memory outputs "1" when acontinuous read access is started with the sector that is not in the erasing suspension state.
• The toggle bit 2 flag (DQ2) is used along with the toggle bit flag (DQ6) to detect whether erasing hasbeen suspended. (DQ6 does not perform toggle operation while DQ2 does.)
• The toggle bit 2 flag (DQ2) can also be used to detect the sector being erased as it performs toggleoperation when read access to that sector takes place.
Table 27.6-11 State Transition of Toggle Bit Flag (State Change at Normal Operation)
Operating State
Programming → Completed
Chip, Sector Erasing → Completed
Wait for Sector Erasing →
Started
Sector Erasing → Sector Erasing Temporary Stop(Sector Being
Erased)
Sector Erasing Temporary Stop → Resume (Sector Being Erased)
Sector Erasing Now Temporary
Stop(Sector Not Being
Erased)
DQ2 1 →DATA: 2 Toggle →Stop Toggle Toggle Toggle DATA: 2
Table 27.6-12 State Transition of Toggle Bit Flag (State Change at Abnormal Operation)
Operating State Programming Chip and Sector Erasing
DQ2 1 *
750
27.7 Details of Programming/Erasing Flash Memory
This section describes the individual procedures for flash memory reading/resetting, writing, chip-erasing, sector-erasing, sector-erase suspending, and sector-erase resuming by entering their respective commands to invoke the automatic algorithm.
Details of Programming/Erasing Flash MemoryThe automatic algorithm can be invoked by writing the read/reset, write, chip-erase, sector-erase, sector-
erase suspend, and sector-erase resume command sequence to flash memory from the CPU. Programming
flash memory from the CPU should always be performed continuously. The termination of the automatic
algorithm can be checked by the data polling function. After normal termination, it returns to the read/reset
state.
Each operation is explained in the following order.
• Read/reset state
• Data programming
• All data erasing (chip all erase)
• Any data erasing (sector erase)
• Sector erasing suspension
• Sector erasing resumption
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CHAPTER 27 480-Kbit Flash Memory
27.7.1 Read/Reset State in Flash Memory
This section explains the procedure for inputting the read/reset command to place flash memory in the read/reset state.
Read/Reset State in Flash Memory• Flash memory can be placed in the read/reset state by transmitting the read/reset command in the
command sequence table from CPU to flash memory continuously.
• There are two kinds of read/reset commands: one is executed at one time bus operation, and the other isexecuted at three times bus operations; the command sequence of both is essentially the same.
• Since the read/reset state is the initial state for flash memory, flash memory always enters this state afterpower-on and at the normal termination of command. The read/reset state is also described as the waitstate for command input.
• In the read/reset state, a read access to flash memory enables data to be read. As is the case with maskROM, a program access from the CPU can be made.
• A read access to flash memory does not require the read/reset command. If the command is notterminated normally, use the read/reset command to initialize the automatic algorithm.
752
27.7.2 Data Programming to Flash Memory
This section explains the procedure for inputting the program command to program data to flash memory.
Data Write to Flash Memory• In order to start the data programming automatic algorithm of the flash memory, continuously transmit
the program command in the command sequence table from CPU to flash memory.
• At completion of data programming to a target address in the fourth cycle, the automatic algorithm startsautomatic programming.
How to specify the address
• Writing can be performed even in any order of addresses or across a sector boundary. Data written by asingle write command is only one byte.
Notes on data programming
• Bit data 0 cannot be returned to bit data 1 by programming. When bit data "0" is programmed to bit data"1", the data polling algorithm (DQ7) or toggle operation (DQ6) is not terminated, the flash memoryelement is determined faulty, and the timing limit over flag (DQ5) is determined as error to exceed thespecified write time.
• When data is read in the read/reset state, the bit data remains "0". To return the bit data to "1" from "0",erase flash memory data.
• All commands are ignored during automatic programming.
• If a hardware reset occurs during programming, data being programmed to addresses are not assured.Retry from the chip-erase or sector-erase command.
Data Programming Procedure• Figure 27.7-1 gives an example of the procedure for programming data into flash memory. The
hardware sequence flags can be used to check the operating state of the automatic algorithm in flashmemory. The data polling flag (DQ7) is used for checking the completion of programming to flashmemory in this example.
• Flag check data should be read from the address where data was last written.
• Because the data polling flag (DQ7) and the timing limit over flag (DQ5) change at the same time, thedata polling flag (DQ7) must be checked even when the timing limit over flag (DQ5) is "1".
• Similarly, since the toggle bit flag (DQ6) stops toggling at the same time the timing limit over flag(DQ5) changes to "1", toggle bit flag (DQ6) must be checked.
753
CHAPTER 27 480-Kbit Flash Memory
Figure 27.7-1 Example of Data Programming Procedure for Flash Memory
Writing starts
Internal address read
Write command sequence(1) UAAA <- AA(2) U554 <- 55(3) UAAA <- A0(4) Write address <- write data
Next address
Internal address read
FSR: WRE (bit1)Flash memory write-enabled
SWRE0/1Set flash memory write-protected (Write-protected sector 0, and write sector is 1.)
Data polling(DQ7)
Data polling(DQ7)
Data
Data
Timing limit(DQ5)
1
Writing completes
0
Last address
YES
NO
FSR: WRE (bit1)Flash memory write-disabled
Write error
Data
Data
754
27.7.3 Erasing All Data from Flash Memory (Chip Erase)
This section describes the procedure for issuing the chip erase command to erase all data from flash memory.
Data Erase from Flash Memory (Chip Erase)• All data can be erased from flash memory by continuously transmitting the chip erase command in the
command sequence table from CPU to flash memory.
• The chip erase command is executed in six bus operations. Chip erasing is started at completion of thesixth programming cycle.
• Before chip erasing, the user need not perform programming to flash memory. During execution of theautomatic erasing algorithm, flash memory automatically programs "0" before erasing all cellsautomatically.
Notes on Chip Erasure• The chip erase command is accepted only when all sectors have been write-enabled. The chip erase
command is ignored if the bit for any sector in the flash memory sector write control register (SWRE0/1) has been set to "0" (to write-disable or write-protect the sector).
• If a hardware reset occurs during erasure, the data being erased from flash memory is not guaranteed.
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CHAPTER 27 480-Kbit Flash Memory
27.7.4 Erasing Any Data in Flash Memory (Sector Erasing)
This section explains the procedure for inputting the sector erase command to erase any sector in flash memory. Sector-by-sector erasing is enabled and multiple sectors can be specified at a time.
Erasing Any Data in Flash Memory (Sector Erasing)Any sector in flash memory can be erased by continuously transmitting the sector erase command in the
command sequence table from CPU to flash memory.
Method of specifying a sector
• The sector erase command is executed in six bus operations. A 50 µs sector erase wait is started byspecifying the address for the sixth cycle as the address in the target sector and writing the sector erasecode (30H) as data.
• When erasing more than one sector, the sector erase code (30H) is programmed to the sector address tobe erased, following the above.
Notes on specifying multiple sectors
• Sector erasing is started after a 50 µs period waiting for sector erasing is completed after the last sectorerase code has been programmed.
• When erasing more than one sector simultaneously, the address of erase sector and the sector code (sixthcycle in command sequence) must be input within 50µs. If the sector erase code is inputted 50 µs orlater, it cannot be accepted.
• The sector erase timer flag (DQ3) can be used to check whether it is valid to write consecutive sectorerase codes.
• In this case, the address from which the sector erase timer flag (DQ3) is read should correspond to thesector to be erased.
Erasing Procedure for Flash Memory Sectors• Hardware sequence flags can be used to check the state of the automatic algorithm in flash memory.
Figure 27.7-2 gives an example of the flash memory sector erase procedure. In this example, the togglebit flag (DQ6) is used to check that erase ends.
• DQ6 terminates toggling concurrently with the change of the timing limit over flag (DQ5) to "1". So theDQ6 must be checked even when DQ5 is "1".
• Similarly, the data polling flag (DQ7) changes concurrently with the transition of the DQ5, so DQ7must be checked.
Notes on Erasing Sectors• If a hardware reset occurs during erasure, the data in the sector being erased is not guaranteed. Erase that
sector again.
756
Figure 27.7-2 Example of Sector Erasing Procedure for Flash Memory
Writing starts
(6) Input code to erase sector (30H)
Erase command sequence(1) UAAA <- AA(2) U554 <- 55(3) UAAA <- 80(4) UAAA <- AA(5) U554 <- 55
Next sector
Internal address read
Internal address read
FSR: WRE(bit1)Flash memory write-enabled
Is any other erase sector?
Timing limit(DQ5)
1
Erase completes
0
Last sector
FSR: WRE (bit1)Flash memory write-disabled
Erase error
Internal address read
Sector erase timer(DQ3)
1
0
Internal address read 2
Internal address read 1
Toggle bit (DQ6)Data 1 = Data 2
Toggle bit (DQ6)Data 1 = Data 2
NO
NO
NO
NO
YES
YES
YES
YES
SWRE0/1Set flash memory write-protected(Write-protected sector is 0, and write sector is 1.)
757
CHAPTER 27 480-Kbit Flash Memory
27.7.5 Sector Erase Suspension in Flash Memory
This section explains the procedure for inputting the sector erase suspend command to suspend sector erasing of the flash memory. Data can be read from the sector not being erased.
Sector Erase Suspension in Flash Memory• To cause flash memory sector erasing to suspend, continuously transmit the sector erasing suspend
command in the command sequence table from CPU to flash memory.
• The sector erasing suspend command suspends the sector erase currently being performed, enabling dataread from a sector that is currently not being erased.
• This command is only enabled during the sector erasing period including the erasing wait time; it isignored during the chip erasing period or during programming.
• The sector erasing suspend command is executed when the sector erasing suspend code (B0H) isprogrammed. At this time, specify an arbitrary address in the sector specified for erasure. If the sectorerasing suspend command is reexecuted during sector erasing pause, the command input again isignored.
• When the sector erasing suspend command is inputted during the sector erasing wait period, the sectorerase wait state ends immediately, the erasing is interrupted, and the erase stop state occurs.
• When the erase suspend command is inputted during the sector erasing after the sector erase wait period,the erase suspend state occurs after 20µs max.
NoteBefore issuing a suspend command, wait for 20 ms after issuing the sector erase command or sector erase
resume command.
758
27.7.6 Sector Erase Resumption in Flash Memory
This section explains the procedure for inputting the sector erase resume command to resume erasing of the suspended flash memory sector.
Sector Erase Resumption in Flash Memory• Suspended sector erasing can be resumed by continuously transmitting the sector erase resume
command in the command sequence table from CPU to flash memory.
• The sector erase resume command resumes sector erasing suspended by the sector erase suspendcommand. The sector-erase resume command is executed by writing erase resume code (30H). At thistime, specify an arbitrary address in the sector specified for erasure.
• Inputting the sector erase resume command during sector erasing is ignored.
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CHAPTER 27 480-Kbit Flash Memory
27.8 Features of Flash Security
The flash security controller function prevents the contents of flash memory being read through external pins.
Features of Flash SecurityWriting protection code "01H" to a flash memory address (4000H) restricts access to flash memory, barring
read/write access to flash memory from any external pin. Once flash memory has been protected, the
function cannot be unlocked until the chip erase command is executed.
Note that only addresses 5554H and AAAAH can be read as exceptions.
It is advisable to code the protection code at the end of flash programming. This is to avoid unnecessary
protection during programming.
Once flash memory has been protected, the chip erase operation is required before it can be reprogrammed.
For details, ask your local representative of Fujitsu.
760
CHAPTER 28Dual Operation Flash
This chapter describes the functions and operation of dual operation flash.
28.1 Overview of Dual Operation Flash
28.2 Access Sector Map of Dual Operation Flash
28.3 Operation of Dual Operation Flash
761
CHAPTER 28 Dual Operation Flash
28.1 Overview of Dual Operation Flash
Dual-operation flash consists of upper banks (4K x 3) and lower banks (16K x 2 + 4K x 4). Unlike conventional flash products, this memory can be written/erased and read at the same time in banks.This enables program execution in flash memory and write control using interrupts. In addition, a conventional process of downloading a program to be executed to RAM for writing is not required, thereby saving the download time and eliminating the need for taking care of RAM data from power shutdown.The minimum sector is 4 kilobytes long, which can be handled easily as a program/data area.
Features of Dual Operation FlashTow-bank configuration, enabling simultaneous execution of an erase/program and a read
Minimum sector size of 4 KB contributing to easy-to-use configuration of program/data areas
The dual operation flash can use the following combination.
The bank on one side cannot be written/sector-erased while the bank on the other side is being written/
sector-erased.
Upper bank Lower bank
Write
Write Programming/sector erase
Programming/sector erase Write
Chip erase
762
28.2 Access Sector Map of Dual Operation Flash
This section describes the access sector map when the dual operation flash is operated.
Sector Conversion Enable Bit in Flash Memory Status Register (FSR:SSEN)Upper bank SA9 and lower bank SA3 can be replaced with each other as an area containing an interrupt
vector by setting the sector conversion enable bit (FSR:SSEN) in the flash memory status register during
dual-operation flash operation. Table 28.2-1 shows the relationships between FSR:SSEN and SA9/SA3
sector conversion.
For the flash memory status register (FSR), see "CHAPTER 27 480-Kbit Flash Memory".
Table 28.2-1 Sector Conversion Enable Bit Function in Flash Memory Status Register
FSR:SSEN Sector Conversion Enable Bit in the Flash Memory Status Register
0(Initial value)
SA3 and SA9 are mapped to addresses 3000H to 3FFFH and F000H to FFFFH, respectively.
An interrupt vector exists in SA9.
1SA9 and SA3 are mapped to addresses 3000H to 3FFFH and F000H to FFFFH, respectively.
An interrupt vector exists in SA3.
763
CHAPTER 28 Dual Operation Flash
Access Sector Map Based on Sector Conversion Enable Bit (FSR:SSEN)Figure 28.2-1 is a flash memory access sector map based on the values of the sector conversion enable bit
in the flash memory status register (FSR:SSEN).
Figure 28.2-1 Access Sector Map by FSR: SSEN Value
1000H1FFFH2000H2FFFH3000H3FFFH4000H
7FFFH8000H
BFFFHC000HCFFFHD000HDFFFHE000H EFFFHF000H
FFFFH
SA1:4K
SA2:4K
SA3:4K
SA4:16K
SA5:16K
SA6:4K
SA7:4K
SA8:4K
SA9:4K
SA1:4K
SA2:4K
SA9:4K
SA4:16K
SA5:16K
SA6:4K
SA7:4K
SA8:4K
SA3:4K Interrupt vector
Interrupt vector
CPU address
FSR:SSEN="0" FSR:SSEN="1"
764
28.3 Operation of Dual Operation Flash
Described below is the operation of dual operation flash.Pay attention in particular to the following points when using dual operation flash:• Interrupt generated when upper banks are updated• Procedure of setting the sector conversion enable bit in the flash memory status
register (FSR:SSEN)
Interrupt Generated when Upper Banks are UpdatedThe dual-operation flash consists of banks on two sides. Like conventional flash products, however, it cannot
be erased/written and read at the same time in banks on the same side.
As SA9 contains an interrupt vector, an interrupt vector from the CPU cannot be read normally when an
interrupt occurs during a write to an upper bank. Before an upper bank can be updated, the sector
conversion enable bit must be set to "1" (FSR:SSEN = 1). When an interrupt occurs, therefore, SA3 is
accessed to read interrupt vector data. The same data must be copied to SA3 and SA9 before the sector
conversion enable bit (FSR:SSEN) is set.
Procedure of Setting Sector Conversion Enable Bit (FSR:SSEN)Figure 28.3-1 shows a sample procedure of setting the sector conversion enable bit (FSR:SSEN).
The FSR:SSEN bit must be set to "1" before upper-bank data is updated. It is prohibited to change the
setting of the sector conversion enable bit (FSR:SSEN) during a write to flash memory. Be sure to set the
sector conversion enable bit (FSR:SSEN) either before starting writing to flash memory or after completing
the write.
When setting the FSR:SSEN bit, disable interrupts and enable interrupts after setting the bit.
Figure 28.3-1 Sample Procedure of Setting the Sector Conversion Enable Bit (FSR:SSEN)
Start rewriting FLASH data
Start write operation Copy SA9 data to SA3
Start write operation
Complete rewriting FLASH data
Complete rewriting FLASH data
Set FSR: SSEN ("1")
Set FSR: SSEN ("0")
Rewrite data of upper bankRewrite data of lower bank
765
CHAPTER 28 Dual Operation Flash
Operation during Writing/ErasingIt is prohibited to write to flash memory within an interrupt routine when an interrupt occurs during flash
memory writing/erasing. When two or more write/erase routines exist, let the interrupted write/erase
routine be completed, then execute the others.
During flash memory writing/erasing, it is not allowed to cause state transition from the current mode
(clock mode or standby mode). Cause state transition after writing/erasing is completed.
766
CHAPTER 29Basic Information
This chapter explains I/O map, interrupt list, memory map, pin status, instruction overview and mask option.
29.1 I/O Map
29.2 Table of Interrupt Causes
29.3 Memory Map
29.4 Instruction Overview
767
CHAPTER 29 Basic Information
29.1 I/O Map
This section explains I/O map which is used on this series.
I/O mapThe I/O map divides along with it because the resource that can be used by each terminal mode in this
series is different. Please refer to the terminal mode used.
Table 29.1-1 MB95FV100 (1 / 8)
Address Register abbreviation Register name R/W Initial value
0000 PDR0 Port 0 data register R/W 00000000
0001 DDR0 Port 0 direction register R/W 00000000
0002 PDR1 Port 1 data register R/W 00000000
0003 DDR1 Port 1 direction register R/W 00000000
0004 -- (Vacancy) -- --
0005 WATR Oscillation stabilization wait time setting register R/W 11111111
0006 PLLC PLL control register R/W 00000000
0007 SYCC System clock control register R/W 1010x011
0008 STBC Standby control register R/W 00000000
0009 RSRR Reset cause register R xxxxxxxx
000A TBTC Timebase timer control register R/W 00000000
000B WPCR Watch prescaler control register R/W 00000000
000C WDTC Watchdog timer control register R/W 00000000
000D -- (Vacancy) -- --
000E PDR2 Port 2 data register R/W 00000000
000F DDR2 Port 2 direction register R/W 00000000
0010 PDR3 Port 3 data register R/W 00000000
0011 DDR3 Port 3 direction register R/W 00000000
0012 PDR4 Port 4 data register R/W 00000000
0013 DDR4 Port 4 direction register R/W 00000000
0014 PDR5 Port 5 data register R/W 00000000
0015 DDR5 Port 5 direction register R/W 00000000
0016 PDR6 Port 6 data register R/W 00000000
0017 DDR6 Port 6 direction register R/W 00000000
0018 PDR7 Port 7 data register R/W 00000000
0019 DDR7 Port 7 direction register R/W 00000000
001A PDR8 Port 8 data register R/W 00000000
768
001B DDR8 Port 8 direction register R/W 00000000
001C PDR9 Port 9 data register R/W 00000000
001D DDR9 Port 9 direction register R/W 00000000
001E PDRA Port A data register R/W 00000000
001F DDRA Port A direction register R/W 00000000
0020 PDRB Port B data register R/W 00000000
0021 DDRB Port B direction register R/W 00000000
0022 PDRC Port C data register R/W 00000000
0023 DDRC Port C direction register R/W 00000000
0024 PDRD Port D data register R/W 00000000
0025 DDRD Port D direction register R/W 00000000
0026 PDRE Port E data register R/W 00000000
0027 DDRE Port E direction register R/W 00000000
0028 PDRF Port F data register R/W 00000000
0029 DDRF Port F direction register R/W 00000000
002A PDRG Port G data register R/W 00000000
002B DDRG Port G direction register R/W 00000000
002C PUL0 Port 0 pull-up register R/W 00000000
002D PUL1 Port 1 pull-up register R/W 00000000
002E PUL2 Port 2 pull-up register R/W 00000000
002F PUL3 Port 3 pull-up register R/W 00000000
0030 PUL4 Port 4 pull-up register R/W 00000000
0031 PUL5 Port 5 pull-up register R/W 00000000
0032 PUL7 Port 7 pull-up register R/W 00000000
0033 PUL8 Port 8 pull-up register R/W 00000000
0034 PULE Port E pull-up register R/W 00000000
0035 PULG Port G pull-up register R/W 00000000
0036 T01CR1 Control status register 1 ch0 for 8/16-bit compound timer 01 R/W 00000000
0037 T00CR1 Control status register 1 ch0 for 8/16-bit compound timer 00 R/W 00000000
0038 T11CR1 Control status register 1 ch1 for 8/16-bit compound timer 11 R/W 00000000
0039 T10CR1 Control status register 1 ch1 for 8/16-bit compound timer 10 R/W 00000000
003A PC01 Control register ch0 for 8/16-bit PPG1 R/W 00000000
003B PC00 Control register ch0 for 8/16-bit PPG0 R/W 00000000
003C PC11 Control register ch1 for 8/16-bit PPG1 R/W 00000000
003D PC10 Control register ch1 for 8/16-bit PPG0 R/W 00000000
Table 29.1-1 MB95FV100 (2 / 8)
Address Register abbreviation Register name R/W Initial value
769
CHAPTER 29 Basic Information
003E TMCSRH0 Control status register upper ch0 for 16-bit reload timer R/W 00000000
003F TMCSRL0 Control status register lower ch0 for 16-bit reload timer R/W 00000000
0040 TMCSRH1 Control status register upper ch1 for 16-bit reload timer R/W 00000000
0041 TMCSRL1 Control status register lower ch1 for 16-bit reload timer R/W 00000000
0042 PCNTH0 Control register upper ch0 for 16-bit PPG status R/W 00000000
0043 PCNTL0 Control register lower ch0 for 16-bit PPG status R/W 00000000
0044 PCNTH1 Control register upper ch1 for 16-bit PPG status R/W 00000000
0045 PCNTL1 Control register lower ch1 for 16-bit PPG status R/W 00000000
0046 PCNTH2 Control register upper ch2 for 16-bit PPG status R/W 00000000
0047 PCNTL2 Control register lower ch2 for 16-bit PPG status R/W 00000000
0048 EIC00 Control register ch0/1 for external interrupt circuit R/W 00000000
0049 EIC10 Control register ch2/3 for external interrupt circuit R/W 00000000
004A EIC20 Control register ch4/5 for external interrupt circuit R/W 00000000
004B EIC30 Control register ch6/7 for external interrupt circuit R/W 00000000
004C EIC01 Control register ch8/9 for external interrupt circuit R/W 00000000
004D EIC11 Control register ch10/11 for external interrupt circuit R/W 00000000
004E EIC21 Control register ch12/13 for external interrupt circuit R/W 00000000
004F EIC31 Control register ch14/15 for external interrupt circuit R/W 00000000
0050 SCR LIN-UART serial control register R/W 00000000
0051 SMR LIN-UART serial mode register R/W 00000000
0052 SSR LIN-UART serial status register R/W 00001000
0053 RDR/TDR LIN-UART reception/transmission data register R/W 00000000
0054 ESCR LIN-UART extended status control register R/W 00000100
0055 ECCR LIN-UART extended communication control register R/W 000000XX
0056 SMC10 UART/SIO serial mode control register 1 ch0 R/W 00000000
0057 SMC20 UART/SIO serial mode control register 2 ch0 R/W 00100000
0058 SSR0 UART/SIO serial status register ch0 R/W 00000001
0059 TDR0 UART/SIO serial output data register ch0 R/W 00000000
005A RDR0 UART/SIO serial input data register ch0 R 00000000
005B SMC11 UART/SIO serial mode control register 1 ch1 R/W 00000000
005C SMC21 UART/SIO serial mode control register 2 ch1 R/W 00100000
005D SSR1 UART/SIO serial status register ch1 R/W 00000001
005E TDR1 UART/SIO serial output data register ch1 R/W 00000000
005F RDR1 UART/SIO serial input data register ch1 R 00000000
0060 IBCR00 I2C bus control register 0 ch0 R/W 00000000
Table 29.1-1 MB95FV100 (3 / 8)
Address Register abbreviation Register name R/W Initial value
770
0061 IBCR10 I2C bus control register 1 ch0 R/W 00000000
0062 IBSR0 I2C bus status register ch0 R 00000000
0063 IDDR0 I2C data register ch0 R/W 00000000
0064 IAAR0 I2C address register ch0 R/W 00000000
0065 ICCR0 I2C clock control register ch0 R/W 00000000
0066 IBCR01 I2C bus control register 0 ch1 R/W 00000000
0067 IBCR11 I2C bus control register 1 ch1 R/W 00000000
0068 IBSR1 I2C bus status register ch1 R 00000000
0069 IDDR1 I2C data register ch1 R/W 00000000
006A IAAR1 I2C address register ch1 R/W 00000000
006B ICCR1 I2C clock control register ch1 R/W 00000000
006C ADC1 A/D control register 1 R/W 00000000
006D ADC2 A/D control register 2 R/W 00000000
006E ADDH A/D data register upper R/W 00000000
006F ADDL A/D data register lower R/W 00000000
0070 WCSR Watch counter status register R/W 00000000
0071 -- (Vacancy) -- --
0072 FSR Flash memory status register R/W 000x0000
0073 SWRE0 Flash memory sector write control register 0 R/W 00000000
0074 SWRE1 Flash memory sector write control register 1 R/W 00000000
0075 -- (Vacancy) -- --
0076 WREN Address compare enable register for wild register R/W 00000000
0077 WROR Data test setting register for wild register R/W 00000000
0078 -- ∗ Mirror of RP -- --
0079 ILR0 Interrupt level setting register 0 R/W 11111111
007A ILR1 Interrupt level setting register 1 R/W 11111111
007B ILR2 Interrupt level setting register 2 R/W 11111111
007C ILR3 Interrupt level setting register 3 R/W 11111111
007D ILR4 Interrupt level setting register 4 R/W 11111111
007E ILR5 Interrupt level setting register 5 R/W 11111111
007F -- (Vacancy) -- --
0F80 WRARH0 Address setting register upper ch0 for wild register R/W 00000000
0F81 WRARL0 Address setting register lower ch0 for wild register R/W 00000000
0F82 WRDR0 Data setting register ch0 for wild register R/W 00000000
0F83 WRARH1 Address setting register upper ch1 for wild register R/W 00000000
Table 29.1-1 MB95FV100 (4 / 8)
Address Register abbreviation Register name R/W Initial value
771
CHAPTER 29 Basic Information
0F84 WRARL1 Address setting register lower ch1 for wild register R/W 00000000
0F85 WRDR1 Data setting register ch1 for wild register R/W 00000000
0F86 WRARH2 Address setting register upper ch2 for wild register R/W 00000000
0F87 WRARL2 Address setting register lower ch2 for wild register R/W 00000000
0F88 WRDR2 Data setting register ch2 for wild register R/W 00000000
0F89 -- (Vacancy) -- --
0F8A -- (Vacancy) -- --
0F8B -- (Vacancy) -- --
0F8C -- (Vacancy) -- --
0F8D -- (Vacancy) -- --
0F8E -- (Vacancy) -- --
0F8F -- (Vacancy) -- --
0F90 -- (Vacancy) -- --
0F91 -- (Vacancy) -- --
0F92 T01CR0 Control status register 0 ch0 for 8/16-bit compound timer 01 R/W 00000000
0F93 T00CR0 Control status register 0 ch0 for 8/16-bit compound timer 00 R/W 00000000
0F94 T01DR Data register ch0 for 8/16-bit compound timer 01 R/W 00000000
0F95 T00DR Data register ch0 for 8/16-bit compound timer 00 R/W 00000000
0F96 TMCR0Timer mode control register ch0 for 8/16-bit compound timer 00/01
R/W 00000000
0F97 T11CR0 Control status register 0 ch1for 8/16-bit compound timer 11 R/W 00000000
0F98 T10CR0 Control status register 0 ch1 for 8/16-bit compound timer 10 R/W 00000000
0F99 T11DR Data register ch1 for 8/16-bit compound timer 11 R/W 00000000
0F9A T10DR Data register ch1 for 8/16-bit compound timer 10 R/W 00000000
0F9B TMCR1 Timer mode control register ch1 for 8/16-bit compound timer 10/11
R/W 00000000
0F9C PPS01 Cycle setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9D PPS00 Cycle setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0F9E PDS01 Duty setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9F PDS00 Duty setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0FA0 PPS11 Cycle setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA1 PPS10 Cycle setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA2 PDS11 Duty setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA3 PDS10 Duty setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA4 PPGS Startup register for 8/16-bit PPG R/W 00000000
0FA5 REVC Output reverse register for 8/16-bit PPG R/W 00000000
Table 29.1-1 MB95FV100 (5 / 8)
Address Register abbreviation Register name R/W Initial value
772
0FA6 TMRH0/TMRLRH0 Timer reload register upper ch0 for 16-bit reload timer R/W 00000000
0FA7 TMRL0/TMRLRL0 Timer reload register lower ch0 for 16-bit reload timer R/W 00000000
0FA8 TMRH1/TMRLRH1 Timer reload register upper ch1 for 16-bit reload timer R/W 00000000
0FA9 TMRL1/TMRLRL1 Timer reload register lower ch1 for 16-bit reload timer R/W 00000000
0FAA PDCRH0 Down counter register upper ch0 for 16-bit PPG R 00000000
0FAB PDCRL0 Down counter register lower ch0 for 16-bit PPG R 00000000
0FAC PCSRH0 Cycle setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAD PCSRL0 Cycle setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FAE PDUTH0 Duty setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAF PDUTL0 Duty setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FB0 PDCRH1 Down counter register upper ch1 for 16-bit PPG R 00000000
0FB1 PDCRL1 Down counter register lower ch1 for 16-bit PPG R 00000000
0FB2 PCSRH1 Cycle setting buffer register upper ch1 for 16-bit PPG R/W 11111111
0FB3 PCSRL1 Cycle setting buffer register lower ch1 for 16-bit PPG R/W 11111111
0FB4 PDUTH1 Duty setting buffer register upper ch1 for 16-bit PPG R/W 11111111
0FB5 PDUTL1 Duty setting buffer register lower ch1 for 16-bit PPG R/W 11111111
0FB6 PDCRH2 Down counter register upper ch2 for 16-bit PPG R 00000000
0FB7 PDCRL2 Down counter register lower ch2 for 16-bit PPG R 00000000
0FB8 PCSRH2 Cycle setting buffer register upper ch2 for 16-bit PPG R/W 11111111
0FB9 PCSRL2 Cycle setting buffer register lower ch2 for 16-bit PPG R/W 11111111
0FBA PDUTH2 Duty setting buffer register upper ch2 for 16-bit PPG R/W 11111111
0FBB PDUTL2 Duty setting buffer register lower ch2 for 16-bit PPG R/W 11111111
0FBC BGR1 LIN-UART baud rate generator register 1 R/W 00000000
0FBD BGR0 LIN-UART baud rate generator register 0 R/W 00000000
0FBE PSSR0 UART/SIO prescaler select register ch0 R/W 00000000
0FBF BRSR0 UART/SIO baud rate setting register ch0 R/W 00000000
0FC0 PSSR1 UART/SIO prescaler select register ch1 R/W 00000000
0FC1 BRSR1 UART/SIO baud rate setting register ch1 R/W 00000000
0FC2 AIDRH A/D input disable register upper R/W 00000000
0FC3 AIDRL A/D input disable register lower R/W 00000000
0FC4 LCDCC LCDC control register R/W 00010000
0FC5 LCDCE1 LCDC enable register 1 R/W 00110000
0FC6 LCDCE2 LCDC enable register 2 R/W 00000000
0FC7 LCDCE3 LCDC enable register 3 R/W 00000000
0FC8 LCDCE4 LCDC enable register 4 R/W 00000000
Table 29.1-1 MB95FV100 (6 / 8)
Address Register abbreviation Register name R/W Initial value
773
CHAPTER 29 Basic Information
0FC9 LCDCE5 LCDC enable register 5 R/W 00000000
0FCA LCDCE6 LCDC enable register 6 R/W 00000000
0FCB LCDCB1 LCDC blinking setting register 1 R/W 00000000
0FCC LCDCB2 LCDC blinking setting register 2 R/W 00000000
0FCD
LCDRAM LCDC display RAM R/W 00000000
0FCE
0FCF
0FD0
0FD1
0FD2
0FD3
0FD4
0FD5
0FD6
0FD7
0FD8
0FD9
0FDA
0FDB
0FDC
0FDD
0FDE
0FDF
0FE0
0FE1 DACR D/A converter control data register R/W 00000000
0FE2 DAT D/A converter data register R/W 00000000
0FE3 WCDR Watch counter data register R/W 00111111
0FE4
-- (Vacancy) -- --
0FE5
0FE6
0FE7
0FE8
0FE9 -- (Vacancy) -- --
0FEA CSVCR Clock supervisor control register R/W 00011100
Table 29.1-1 MB95FV100 (7 / 8)
Address Register abbreviation Register name R/W Initial value
774
0FEB-- (Vacancy) -- --
0FEC
0FED -- (Vacancy) -- --
0FEE ILSR Input level select register R/W -0000000
0FEF WICR Interrupt pin control register R/W 01000000
0FF0 --
∗External I/O area
-- --
0FF1 -- -- --
0FF2 -- -- --
0FF3 -- -- --
0FF4 -- -- --
0FF5 -- -- --
0FF6 -- -- --
0FF7 -- -- --
0FF8 -- -- --
0FF9 -- -- --
0FFA -- -- --
0FFB -- -- --
0FFC -- -- --
0FFD -- -- --
0FFE -- -- --
0FFF -- -- --
Table 29.1-1 MB95FV100 (8 / 8)
Address Register abbreviation Register name R/W Initial value
775
CHAPTER 29 Basic Information
Table 29.1-2 SAXOPHONE series (1 / 8)
Address Register abbreviation Register name R/W Initial value
0000 PDR0 Port 0 data register R/W 00000000
0001 DDR0 Port 0 direction register R/W 00000000
0002 PDR1 Port 1 data register R/W 00000000
0003 DDR1 Port 1 direction register R/W 00000000
0004 -- (Vacancy) -- --
0005 WATR Oscillation stabilization wait time setting register R/W 11111111
0006 PLLC PLL control register R/W 00000000
0007 SYCC System clock control register R/W 1010x011
0008 STBC Standby control register R/W 00000000
0009 RSRR Reset cause register R xxxxxxxx
000A TBTC Timebase timer control register R/W 00000000
000B WPCR Watch prescaler control register R/W 00000000
000C WDTC Watchdog timer control register R/W 00000000
000D -- (Vacancy) -- --
000E PDR2 Port 2 data register R/W 00000000
000F DDR2 Port 2 direction register R/W 00000000
0010 PDR3 Port 3 data register R/W 00000000
0011 DDR3 Port 3 direction register R/W 00000000
0012 PDR4 Port 4 data register R/W 00000000
0013 DDR4 Port 4 direction register R/W 00000000
0014 PDR5 Port 5 data register R/W 00000000
0015 DDR5 Port 5 direction register R/W 00000000
0016 PDR6 Port 6 data register R/W 00000000
0017 DDR6 Port 6 direction register R/W 00000000
0018 PDR7 Port 7 data register R/W 00000000
0019 DDR7 Port 7 direction register R/W 00000000
001A PDR8 Port 8 data register R/W 00000000
001B DDR8 Port 8 direction register R/W 00000000
001C-- (Vacancy) -- --
001D
001E PDRA Port A data register R/W 00000000
001F DDRA Port A direction register R/W 00000000
776
0020
-- (Vacancy) -- --0021
0022
0023
0024 PDRD Port D data register R/W 00000000
0025 DDRD Port D direction register R/W 00000000
0026 PDRE Port E data register R/W 00000000
0027 DDRE Port E direction register R/W 00000000
0028-- (Vacancy) -- --
0029
002A PDRG Port G data register R/W 00000000
002B DDRG Port G direction register R/W 00000000
002C -- (Vacancy) -- --
002D PUL1 Port 1 pull-up register R/W 00000000
002E PUL2 Port 2 pull-up register R/W 00000000
002F PUL3 Port 3 pull-up register R/W 00000000
0030 PUL4 Port 4 pull-up register R/W 00000000
0031 PUL5 Port 5 pull-up register R/W 00000000
0032 PUL7 Port 7 pull-up register R/W 00000000
0033 PUL8 Port 8 pull-up register R/W 00000000
0034 PULE Port E pull-up register R/W 00000000
0035 PULG Port G pull-up register R/W 00000000
0036 T01CR1 Control status register 1 ch 0 for 8/16-bit compound timer 01 R/W 00000000
0037 T00CR1 Control status register 1 ch 0 for 8/16-bit compound timer 00 R/W 00000000
0038 T11CR1 Control status register 1 ch 1 for 8/16-bit compound timer 11 R/W 00000000
0039 T10CR1 Control status register 1 ch 1 for 8/16-bit compound timer 10 R/W 00000000
003A PC01 Control register ch0 for 8/16-bit PPG1 R/W 00000000
003B PC00 Control register ch0 for 8/16-bit PPG0 R/W 00000000
003C PC11 Control register ch1 for 8/16-bit PPG1 R/W 00000000
003D PC10 Control register ch0 for 8/16-bit PPG0 R/W 00000000
003E TMCSRH0 Control status register upper ch0 for 16-bit reload timer R/W 00000000
003F TMCSRL0 Control status register lower ch0 for 16-bit reload timer R/W 00000000
0040 TMCSRH1 Control status register upper ch1 for 16-bit reload timer R/W 00000000
0041 TMCSRL1 Control status register lower ch1 for 16-bit reload timer R/W 00000000
0042 PCNTH0 Status control register upper ch0 for 16-bit reload timer R/W 00000000
Table 29.1-2 SAXOPHONE series (2 / 8)
Address Register abbreviation Register name R/W Initial value
777
CHAPTER 29 Basic Information
0043 PCNTL0 Status control register lower ch0 for 16-bit reload timer R/W 00000000
0044 PCNTH1 Status control register upper ch1 for 16-bit reload timer R/W 00000000
0045 PCNTL1 Status control register lower ch1 for 16-bit reload timer R/W 00000000
0046 PCNTH2 Status control register upper ch2 for 16-bit reload timer R/W 00000000
0047 PCNTL2 Status control register lower ch2 for 16-bit reload timer R/W 00000000
0048 EIC00 Control register ch0/1 for external interrupt circuit R/W 00000000
0049 EIC10 Control register ch2/3 for external interrupt circuit R/W 00000000
004A EIC20 Control register ch4/5 for external interrupt circuit R/W 00000000
004B EIC30 Control register ch6/7 for external interrupt circuit R/W 00000000
004C EIC01 Control register ch8/9 for external interrupt circuit R/W 00000000
004D EIC11 Control register ch10/11 for external interrupt circuit R/W 00000000
004E EIC21 Control register ch12/13 for external interrupt circuit R/W 00000000
004F EIC31 Control register ch14/15 for external interrupt circuit R/W 00000000
0050 SCR LIN-UART serial control register R/W 00000000
0051 SMR LIN-UART serial mode register R/W 00000000
0052 SSR LIN-UART serial status register R/W 00001000
0053 RDR/TDR LIN-UART reception/transmission data register R/W 00000000
0054 ESCR LIN-UART extended status control register R/W 00000100
0055 ECCR LIN-UART extended communication control register R/W 000000XX
0056 SMC10 UART/SIO serial mode control register 1 ch0 R/W 00000000
0057 SMC20 UART/SIO serial mode control register 2 ch0 R/W 00100000
0058 SSR0 UART/SIO serial status register ch0 R/W 00000001
0059 TDR0 UART/SIO serial output data register ch0 R/W 00000000
005A RDR0 UART/SIO serial input data register ch0 R 00000000
005B SMC11 UART/SIO serial mode control register 1 ch1 R/W 00000000
005C SMC21 UART/SIO serial mode control register 2 ch1 R/W 00100000
005D SSR1 UART/SIO serial status register ch1 R/W 00000001
005E TDR1 UART/SIO serial output data register ch1 R/W 00000000
005F RDR1 UART/SIO serial input data register ch1 R 00000000
0060 IBCR00 I2C bus control register 0 ch0 R/W 00000000
0061 IBCR10 I2C bus control register 1 ch0 R/W 00000000
0062 IBSR0 I2C bus status register ch0 R 00000000
0063 IDDR0 I2C data register ch0 R/W 00000000
0064 IAAR0 I2C address register ch0 R/W 00000000
0065 ICCR0 I2C clock control register ch0 R/W 00000000
Table 29.1-2 SAXOPHONE series (3 / 8)
Address Register abbreviation Register name R/W Initial value
778
0066 IBCR01 I2C bus control register 0 ch1 R/W 00000000
0067 IBCR11 I2C bus control register 1 ch1 R/W 00000000
0068 IBSR1 I2C bus status register ch1 R 00000000
0069 IDDR1 I2C data register ch1 R/W 00000000
006A IAAR1 I2C address register ch1 R/W 00000000
006B ICCR1 I2C clock control register ch1 R/W 00000000
006C ADC1 A/D control register 1 R/W 00000000
006D ADC2 A/D control register 2 R/W 00000000
006E ADDH A/D data register upper R/W 00000000
006F ADDL A/D data register lower R/W 00000000
0070 WCSR Watch counter status register R/W 00000000
0071 -- (Vacancy) -- --
0072 FSR Flash memory status register R/W 000x0000
0073 SWRE0 Flash memory sector write control register 0 R/W 00000000
0074 SWRE1 Flash memory sector write control register 1 R/W 00000000
0075 -- (Vacancy) -- --
0076 WREN Address compare enable register for wild register R/W 00000000
0077 WROR Data test setting register for wild register R/W 00000000
0078 -- * Mirror of RP -- --
0079 ILR0 Interrupt level setting register 0 R/W 11111111
007A ILR1 Interrupt level setting register 1 R/W 11111111
007B ILR2 Interrupt level setting register 2 R/W 11111111
007C ILR3 Interrupt level setting register 3 R/W 11111111
007D ILR4 Interrupt level setting register 4 R/W 11111111
007E ILR5 Interrupt level setting register 5 R/W 11111111
007F -- (Vacancy) -- --
0F80 WRARH0 Address setting register upper ch0 for wild register R/W 00000000
0F81 WRARL0 Address setting register lower ch0 for wild register R/W 00000000
0F82 WRDR0 Data setting register ch0 for wild register R/W 00000000
0F83 WRARH1 Address setting register upper ch1 for wild register R/W 00000000
0F84 WRARL1 Address setting register lower ch1 for wild register R/W 00000000
0F85 WRDR1 Data setting register ch1 for wild register R/W 00000000
0F86 WRARH2 Address setting register upper ch2 for wild register R/W 00000000
0F87 WRARL2 Address setting register lower ch2 for wild register R/W 00000000
0F88 WRDR2 Data setting register ch2 for wild register R/W 00000000
Table 29.1-2 SAXOPHONE series (4 / 8)
Address Register abbreviation Register name R/W Initial value
779
CHAPTER 29 Basic Information
0F89 -- (Vacancy) -- --
0F8A -- (Vacancy) -- --
0F8B -- (Vacancy) -- --
0F8C -- (Vacancy) -- --
0F8D -- (Vacancy) -- --
0F8E -- (Vacancy) -- --
0F8F -- (Vacancy) -- --
0F90 -- (Vacancy) -- --
0F91 -- (Vacancy) -- --
0F92 T01CR0 Control status register 0 ch0 for 8/16-bit compound timer 01 R/W 00000000
0F93 T00CR0 Control status register 0 ch0 for 8/16-bit compound timer 00 R/W 00000000
0F94 T01DR Data register ch0 for 8/16-bit compound timer 01 R/W 00000000
0F95 T00DR Data register ch0 for 8/16-bit compound timer 00 R/W 00000000
0F96 TMCR0 Timer mode control register ch0 for 8/16-bit compound timer 00/01 R/W 00000000
0F97 T11CR0 Control status register 0 ch1 for 8/16-bit compound timer 11 R/W 00000000
0F98 T10CR0 Control status register 0 ch1 for 8/16-bit compound timer 10 R/W 00000000
0F99 T11DR Data register ch1 for 8/16-bit compound timer 11 R/W 00000000
0F9A T10DR Data register ch1 for 8/16-bit compound timer 10 R/W 00000000
0F9B TMCR1 Timer mode control register ch1 for 8/16-bit compound timer 10/11 R/W 00000000
0F9C PPS01 Cycle setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9D PPS00 Cycle setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0F9E PDS01 Duty setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9F PDS00 Duty setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0FA0 PPS11 Cycle setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA1 PPS10 Cycle setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA2 PDS11 Duty setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA3 PDS10 Duty setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA4 PPGS 8/16-bit PPG startup register R/W 00000000
0FA5 REVC 8/16-bit PPG output reverse register R/W 00000000
0FA6 TMRH0/TMRLRH0 Timer/reload register upper ch0 for 16-bit reload timer R/W 00000000
0FA7 TMRL0/TMRLRL0 Timer/reload register lower ch0 for 16-bit reload timer R/W 00000000
0FA8 TMRH1/TMRLRH1 Timer/reload register upper ch1 for 16-bit reload timer R/W 00000000
0FA9 TMRL1/TMRLRL1 Timer/reload register lower ch1 for 16-bit reload timer R/W 00000000
0FAA PDCRH0 Down counter register upper ch0 for 16-bit PPG R 00000000
0FAB PDCRL0 Down counter register lower ch0 for 16-bit PPG R 00000000
Table 29.1-2 SAXOPHONE series (5 / 8)
Address Register abbreviation Register name R/W Initial value
780
0FAC PCSRH0 Cycle setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAD PCSRL0 Cycle setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FAE PDUTH0 Duty setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAF PDUTL0 Duty setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FB0 PDCRH1 Down counter register upper ch1 for 16-bit PPG R 00000000
0FB1 PDCRL1 Down counter register lower ch1 for 16-bit PPG R 00000000
0FB2 PCSRH1 Cycle setting buffer register upper ch1 for 16-bit PPG R/W 11111111
0FB3 PCSRL1 Cycle setting buffer register lower ch1 for 16-bit PPG R/W 11111111
0FB4 PDUTH1 Duty setting buffer register upper ch1 for 16-bit PPG R/W 11111111
0FB5 PDUTL1 Duty setting buffer register lower ch1 for 16-bit PPG R/W 11111111
0FB6 PDCRH2 Down counter register upper ch2 for 16-bit PPG R 00000000
0FB7 PDCRL2 Down counter register lower ch2 for 16-bit PPG R 00000000
0FB8 PCSRH2 Cycle setting buffer register upper ch2 for 16-bit PPG R/W 11111111
0FB9 PCSRL2 Cycle setting buffer register lower ch2 for 16-bit PPG R/W 11111111
0FBA PDUTH2 Duty setting buffer register upper ch2 for 16-bit PPG R/W 11111111
0FBB PDUTL2 Duty setting buffer register lower ch2 for 16-bit PPG R/W 11111111
0FBC BGR1 LIN-UART baud rate generator register 1 R/W 00000000
0FBD BGR0 LIN-UART baud rate generator register 0 R/W 00000000
0FBE PSSR0 UART/SIO prescaler select register ch0 R/W 00000000
0FBF BRSR0 UART/SIO baud rate setting register ch0 R/W 00000000
0FC0 PSSR1 UART/SIO prescaler select register ch1 R/W 00000000
0FC1 BRSR1 UART/SIO baud rate setting register ch1 R/W 00000000
0FC2 AIDRH A/D input disable register upper R/W 00000000
0FC3 AIDRL A/D input disable register lower R/W 00000000
0FC4 -- (Vacancy) -- --
0FC5 -- (Vacancy) -- --
0FC6 -- (Vacancy) -- --
0FC7 -- (Vacancy) -- --
0FC8 -- (Vacancy) -- --
0FC9 -- (Vacancy) -- --
0FCA -- (Vacancy) -- --
0FCB -- (Vacancy) -- --
0FCC -- (Vacancy) -- --
0FCD -- (Vacancy) -- --
0FCE -- (Vacancy) -- --
Table 29.1-2 SAXOPHONE series (6 / 8)
Address Register abbreviation Register name R/W Initial value
781
CHAPTER 29 Basic Information
0FCF -- (Vacancy) -- --
0FD0 -- (Vacancy) -- --
0FD1 -- (Vacancy) -- --
0FD2 -- (Vacancy) -- --
0FD3 -- (Vacancy) -- --
0FD4 -- (Vacancy) -- --
0FD5 -- (Vacancy) -- --
0FD6 -- (Vacancy) -- --
0FD7 -- (Vacancy) -- --
0FD8 -- (Vacancy) -- --
0FD9 -- (Vacancy) -- --
0FDA -- (Vacancy) -- --
0FDB -- (Vacancy) -- --
0FDC -- (Vacancy) -- --
0FDD -- (Vacancy) -- --
0FDE -- (Vacancy) -- --
0FDF -- (Vacancy) -- --
0FE0 -- (Vacancy) -- --
0FE1 -- (Vacancy) -- --
0FE2 -- (Vacancy) -- --
0FE3 WCDR Watch counter data register R/W 00111111
0FE4 -- (Vacancy) -- --
0FE5 -- (Vacancy) -- --
0FE6 -- (Vacancy) -- --
0FE7 -- (Vacancy) -- --
0FE8 -- (Vacancy) -- --
0FE9 -- (Vacancy) -- --
0FEA CSVCR Clock supervisor control register R/W 00011100
0FEB -- (Vacancy) -- --
0FEC -- (Vacancy) -- --
0FED -- (Vacancy) -- --
0FEE ILSR Input level select register R/W -0000000
0FEF WICR Interrupt pin control register R/W 01000000
0FF0 -- (Vacancy) -- --
0FF1 -- (Vacancy) -- --
Table 29.1-2 SAXOPHONE series (7 / 8)
Address Register abbreviation Register name R/W Initial value
782
0FF2 -- (Vacancy) -- --
0FF3 -- (Vacancy) -- --
0FF4 -- (Vacancy) -- --
0FF5 -- (Vacancy) -- --
0FF6 -- (Vacancy) -- --
0FF7 -- (Vacancy) -- --
0FF8 -- (Vacancy) -- --
0FF9 -- (Vacancy) -- --
0FFA -- (Vacancy) -- --
0FFB -- (Vacancy) -- --
0FFC -- (Vacancy) -- --
0FFD -- (Vacancy) -- --
0FFE -- (Vacancy) -- --
0FFF -- (Vacancy) -- --
Table 29.1-2 SAXOPHONE series (8 / 8)
Address Register abbreviation Register name R/W Initial value
783
CHAPTER 29 Basic Information
Table 29.1-3 RESERVE1 series (1 / 8)
Address Register abbreviation Register name R/W Initial value
0000 PDR0 Port 0 data register R/W 00000000
0001 DDR0 Port 0 direction register R/W 00000000
0002 PDR1 Port 1 data register R/W 00000000
0003 DDR1 Port 1 direction register R/W 00000000
0004 -- (Vacancy) -- --
0005 WATR Oscillation stabilization wait time setting register R/W 11111111
0006 PLLC PLL control register R/W 00000000
0007 SYCC System clock control register R/W 1010x011
0008 STBC Standby control register R/W 00000000
0009 RSRR Reset cause register R xxxxxxxx
000A TBTC Timebase timer control register R/W 00000000
000B WPCR Watch prescaler control register R/W 00000000
000C WDTC Watchdog timer control register R/W 00000000
000D -- (Vacancy) -- --
000E PDR2 Port 2 data register R/W 00000000
000F DDR2 Port 2 direction register R/W 00000000
0010 PDR3 Port 3 data register R/W 00000000
0011 DDR3 Port 3 direction register R/W 00000000
0012 PDR4 Port 4 data register R/W 00000000
0013 DDR4 Port 4 direction register R/W 00000000
0014 PDR5 Port 5 data register R/W 00000000
0015 DDR5 Port 5 direction register R/W 00000000
0016 PDR6 Port 6 data register R/W 00000000
0017 DDR6 Port 6 direction register R/W 00000000
0018 PDR7 Port 7 data register R/W 00000000
0019 DDR7 Port 7 direction register R/W 00000000
001A PDR8 Port 8 data register R/W 00000000
001B DDR8 Port 8 direction register R/W 00000000
784
001C --
(Vacancy)
-- --
001D -- -- --
001E -- -- --
001F -- -- --
0020 -- -- --
0021 -- -- --
0022 -- -- --
0023 -- -- --
0024 -- -- --
0025 -- -- --
0026 PDRE Port E data register R/W 00000000
0027 DDRE Port E direction register R/W 00000000
0028 -- (Vacancy)
-- --
0029
002A PDRG Port G data register R/W 00000000
002B DDRG Port G direction register R/W 00000000
002C -- (Vacancy) -- --
002D PUL1 Port 1 pull-up register R/W 00000000
002E PUL2 Port 2 pull-up register R/W 00000000
002F PUL3 Port 3 pull-up register R/W 00000000
0030 PUL4 Port 4 pull-up register R/W 00000000
0031 PUL5 Port 5 pull-up register R/W 00000000
0032 PUL7 Port 7 pull-up register R/W 00000000
0033 PUL8 Port 8 pull-up register R/W 00000000
0034 PULE Port E pull-up register R/W 00000000
0035 PULG Port G pull-up register R/W 00000000
0036 T01CR1 Control status register 1 ch 0 for 8/16-bit compound timer 01 R/W 00000000
0037 T00CR1 Control status register 1 ch 0 for 8/16-bit compound timer 00 R/W 00000000
0038 T11CR1 Control status register 1 ch 1 for 8/16-bit compound timer 11 R/W 00000000
0039 T10CR1 Control status register 1 ch 1 for 8/16-bit compound timer 10 R/W 00000000
003A PC01 Control register ch0 for 8/16-bit PPG1 R/W 00000000
003B PC00 Control register ch0 for 8/16-bit PPG0 R/W 00000000
003C PC11 Control register ch1 for 8/16-bit PPG1 R/W 00000000
003D PC10 Control register ch1 for 8/16-bit PPG0 R/W 00000000
003E TMCSRH0 Control status register upper ch0 for 16-bit reload timer R/W 00000000
Table 29.1-3 RESERVE1 series (2 / 8)
Address Register abbreviation Register name R/W Initial value
785
CHAPTER 29 Basic Information
003F TMCSRL0 Control status register lower ch0 for 16-bit reload timer R/W 00000000
0040 TMCSRH1 Control status register upper ch1 for 16-bit reload timer R/W 00000000
0041 TMCSRL1 Control status register lower ch1 for 16-bit reload timer R/W 00000000
0042 PCNTH0 Status control register upper ch0 for 16-bit PPG R/W 00000000
0043 PCNTL0 Status control register lower ch0 for 16-bit PPG R/W 00000000
0044 PCNTH1 Status control register upper ch1 for 16-bit PPG R/W 00000000
0045 PCNTL1 Status control register lower ch1 for 16-bit PPG R/W 00000000
0046 PCNTH2 Status control register upper ch2 for 16-bit PPG R/W 00000000
0047 PCNTL2 Status control register lower ch2 for 16-bit PPG R/W 00000000
0048 EIC00 Control register ch0/1 for external interrupt circuit R/W 00000000
0049 EIC10 Control register ch2/3 for external interrupt circuit R/W 00000000
004A EIC20 Control register ch4/5 for external interrupt circuit R/W 00000000
004B EIC30 Control register ch6/7 for external interrupt circuit R/W 00000000
004C EIC01 Control register ch8/9 for external interrupt circuit R/W 00000000
004D EIC11 Control register ch10/11 for external interrupt circuit R/W 00000000
004E EIC21 Control register ch12/13 for external interrupt circuit R/W 00000000
004F EIC31 Control register ch14/15 for external interrupt circuit R/W 00000000
0050 SCR LIN-UART serial control register R/W 00000000
0051 SMR LIN-UART serial mode register R/W 00000000
0052 SSR LIN-UART serial status register R/W 00001000
0053 RDR/TDR LIN-UART reception/transmission data register R/W 00000000
0054 ESCR LIN-UART extended status control register R/W 00000100
0055 ECCR LIN-UART extended communication control register R/W 000000XX
0056 SMC10 UART/SIO serial mode control register 1 ch0 R/W 00000000
0057 SMC20 UART/SIO serial mode control register 2 ch0 R/W 00100000
0058 SSR0 UART/SIO serial status register ch0 R/W 00000001
0059 TDR0 UART/SIO serial output data register ch0 R/W 00000000
005A RR0 UART/SIO serial input data register ch0 R 00000000
005B SMC11 UART/SIO serial mode control register 1 ch1 R/W 00000000
005C SMC21 UART/SIO serial mode control register 2 ch1 R/W 00100000
005D SSR1 UART/SIO serial status register ch1 R/W 00000001
005E TDR1 UART/SIO serial output data register ch1 R/W 00000000
005F RDR1 UART/SIO serial input data register ch1 R 00000000
0060 IBCR00 I2C bus control register 0 ch0 R/W 00000000
0061 IBCR10 I2C bus control register 1 ch0 R/W 00000000
Table 29.1-3 RESERVE1 series (3 / 8)
Address Register abbreviation Register name R/W Initial value
786
0062 IBSR0 I2C bus status register ch0 R 00000000
0063 IDDR0 I2C data register ch0 R/W 00000000
0064 IAAR0 I2C address register ch0 R/W 00000000
0065 ICCR0 I2C clock control register ch0 R/W 00000000
0066 IBCR01 I2C bus control register 0 ch1 R/W 00000000
0067 IBCR11 I2C bus control register 1 ch1 R/W 00000000
0068 IBSR1 I2C bus status register ch1 R 00000000
0069 IDDR1 I2C data register ch1 R/W 00000000
006A IAAR1 I2C address register ch1 R/W 00000000
006B ICCR1 I2C clock control register ch1 R/W 00000000
006C ADC1 A/D control register 1 R/W 00000000
006D ADC2 A/D control register 2 R/W 00000000
006E ADDH A/D data register upper R/W 00000000
006F ADDL A/D data register lower R/W 00000000
0070 WCSR Watch counter status register R/W 00000000
0071 -- (Vacancy) -- --
0072 FSR Flash memory status register R/W 000X0000
0073 SWRE0 Flash memory sector write control register 0 R/W 00000000
0074 SWRE1 Flash memory sector write control register 1 R/W 00000000
0075 -- (Vacancy) -- --
0076 WREN Address compare enable register for wild register R/W 00000000
0077 WROR Data test setting register for wild register R/W 00000000
0078 -- * Mirror of RP -- --
0079 ILR0 Interrupt level setting register 0 R/W 11111111
007A ILR1 Interrupt level setting register 1 R/W 11111111
007B ILR2 Interrupt level setting register 2 R/W 11111111
007C ILR3 Interrupt level setting register 3 R/W 11111111
007D ILR4 Interrupt level setting register 4 R/W 11111111
007E ILR5 Interrupt level setting register 5 R/W 11111111
007F -- (Vacancy) -- --
0F80 WRARH0 Address setting register upper ch0 for wild register R/W 00000000
0F81 WRARL0 Address setting register lower ch0 for wild register R/W 00000000
0F82 WRDR0 Data setting register ch0 for wild register R/W 00000000
0F83 WRARH1 Address setting register upper ch1 for wild register R/W 00000000
0F84 WRARL1 Address setting register lower ch1 for wild register R/W 00000000
Table 29.1-3 RESERVE1 series (4 / 8)
Address Register abbreviation Register name R/W Initial value
787
CHAPTER 29 Basic Information
0F85 WRDR1 Data setting register ch1 for wild register R/W 00000000
0F86 WRARH2 Address setting register upper ch2 for wild register R/W 00000000
0F87 WRARL2 Address setting register lower ch2 for wild register R/W 00000000
0F88 WRDR2 Data setting register ch2 for wild register R/W 00000000
0F89 -- (Vacancy) -- --
0F8A -- (Vacancy) -- --
0F8B -- (Vacancy) -- --
0F8C -- (Vacancy) -- --
0F8D -- (Vacancy) -- --
0F8E -- (Vacancy) -- --
0F8F -- (Vacancy) -- --
0F90 -- (Vacancy) -- --
0F91 -- (Vacancy) -- --
0F92 T01CR0 Control status register 0 ch0 for 8/16-bit compound timer 01 R/W 00000000
0F93 T00CR0 Control status register 0 ch0 for 8/16-bit compound timer 00 R/W 00000000
0F94 T01DR Data register ch0 for 8/16-bit compound timer 01 R/W 00000000
0F95 T00DR Data register ch0 for 8/16-bit compound timer 00 R/W 00000000
0F96 TMCR0 Timer mode control register ch0 for 8/16-bit compound timer 00/01 R/W 00000000
0F97 T11CR0 Control status register 0 ch1 for 8/16-bit compound timer 11 R/W 00000000
0F98 T10CR0 Control status register 0 ch1 for 8/16-bit compound timer 10 R/W 00000000
0F99 T11DR Data register ch1 for 8/16-bit compound timer 11 R/W 00000000
0F9A T10DR Data register ch1 for 8/16-bit compound timer 10 R/W 00000000
0F9B TMCR1 Timer mode control register ch1 for 8/16-bit compound timer 10/11 R/W 00000000
0F9C PPS01 Cycle setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9D PPS00 Cycle setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0F9E PDS01 Duty setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9F PDS00 Duty setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0FA0 PPS11 Cycle setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA1 PPS10 Cycle setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA2 PDS11 Duty setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA3 PDS10 Duty setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA4 PPGS 8/16-bit PPG startup register R/W 00000000
0FA5 REVC 8/16-bit PPG output reverse register R/W 00000000
0FA6 TMRH0/TMRLRH0 Timer/reload register upper ch0 for 16-bit reload timer R/W 00000000
0FA7 TMRL0/TMRLRL0 Timer/reload register lower ch0 for 16-bit reload timer R/W 00000000
Table 29.1-3 RESERVE1 series (5 / 8)
Address Register abbreviation Register name R/W Initial value
788
0FA8 TMRH1/TMRLRH1 Timer/reload register upper ch1 for 16-bit reload timer R/W 00000000
0FA9 TMRL1/TMRLRL1 Timer/reload register lower ch1 for 16-bit reload timer R/W 00000000
0FAA PDCRH0 Down counter register upper ch0 for 16-bit PPG R 00000000
0FAB PDCRL0 Down counter register lower ch0 for 16-bit PPG R 00000000
0FAC PCSRH0 Cycle setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAD PCSRL0 Cycle setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FAE PDUTH0 Duty setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAF PDUTL0 Duty setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FB0 PDCRH1 Down counter register upper ch1 for 16-bit PPG R 00000000
0FB1 PDCRL1 Down counter register lower ch1 for 16-bit PPG R 00000000
0FB2 PCSRH1 Cycle setting buffer register upper ch1 for 16-bit PPG R/W 11111111
0FB3 PCSRL1 Cycle setting buffer register lower ch1 for 16-bit PPG R/W 11111111
0FB4 PDUTH1 Duty setting buffer register upper ch1 for 16-bit PPG R/W 11111111
0FB5 PDUTL1 Duty setting buffer register lower ch1 for 16-bit PPG R/W 11111111
0FB6 PDCRH2 Down counter register upper ch2 for 16-bit PPG R 00000000
0FB7 PDCRL2 Down counter register lower ch2 for 16-bit PPG R 00000000
0FB8 PCSRH2 Cycle setting buffer register upper ch2 for 16-bit PPG R/W 11111111
0FB9 PCSRL2 Cycle setting buffer register lower ch2 for 16-bit PPG R/W 11111111
0FBA PDUTH2 Duty setting buffer register upper ch2 for 16-bit PPG R/W 11111111
0FBB PDUTL2 Duty setting buffer register lower ch2 for 16-bit PPG R/W 11111111
0FBC BGR1 LIN-UART baud rate generator register 1 R/W 00000000
0FBD BGR0 LIN-UART baud rate generator register 0 R/W 00000000
0FBE PSSR0 UART/SIO prescaler select register ch0 R/W 00000000
0FBF BRSR0 UART/SIO baud rate setting register ch0 R/W 00000000
0FC0 PSSR1 UART/SIO prescaler select register ch1 R/W 00000000
0FC1 BRSR1 UART/SIO baud rate setting register ch1 R/W 00000000
0FC2 AIDRH A/D input disable register upper R/W 00000000
0FC3 AIDRL A/D input disable register lower R/W 00000000
Table 29.1-3 RESERVE1 series (6 / 8)
Address Register abbreviation Register name R/W Initial value
789
CHAPTER 29 Basic Information
0FC4
-- (Vacancy) -- --
0FC5
0FC6
0FC7
0FC8
0FC9
0FCA
0FCB
0FCC
0FCD
0FCE
0FCF
0FD0
0FD1
0FD2
0FD3
0FD4
0FD5
0FD6
0FD7
0FD8
0FD9
0FDA
0FDB
0FDC
0FDD
0FDE
0FDF
0FE0
0FE1 -- (Vacancy) -- --
0FE2 -- (Vacancy) -- --
0FE3 WCDR Watch counter data register R/W 00111111
Table 29.1-3 RESERVE1 series (7 / 8)
Address Register abbreviation Register name R/W Initial value
790
0FE4
-- (Vacancy) -- --
0FE5
0FE6
0FE7
0FE8
0FE9 -- (Vacancy) -- --
0FEA CSVCR Clock supervisor control register R/W 00011100
0FEB-- (Vacancy) -- --
0FEC
0FED -- (Vacancy) -- --
0FEE ILSR Input level select register R/W -0000000
0FEF WICR Interrupt pin control register R/W 01000000
0FF0
-- (Vacancy) -- --
0FF1
0FF2
0FF3
0FF4
0FF5
0FF6
0FF7
0FF8
0FF9
0FFA
0FFB
0FFC
0FFD
0FFE
0FFF
Table 29.1-3 RESERVE1 series (8 / 8)
Address Register abbreviation Register name R/W Initial value
791
CHAPTER 29 Basic Information
Table 29.1-4 BASSOON series (1 / 8)
Address Register abbreviation Register name R/W Initial value
0000 PDR0 Port 0 data register R/W 00000000
0001 DDR0 Port 0 direction register R/W 00000000
0002 PDR1 Port 1 data register R/W 00000000
0003 DDR1 Port 1 direction register R/W 00000000
0004 -- (Vacancy) -- --
0005 WATR Oscillation stabilization wait time setting register R/W 11111111
0006 PLLC PLL control register R/W 00000000
0007 SYCC System clock control register R/W 1010x011
0008 STBC Standby control register R/W 00000000
0009 RSRR Reset cause register R xxxxxxxx
000A TBTC Timebase timer control register R/W 00000000
000B WPCR Watch prescaler control register R/W 00000000
000C WDTC Watchdog timer control register R/W 00000000
000D -- (Vacancy) -- --
000E PDR2 Port 2 data register R/W 00000000
000F DDR2 Port 2 direction register R/W 00000000
0010 PDR3 Port 3 data register R/W 00000000
0011 DDR3 Port 3 direction register R/W 00000000
0012 PDR4 Port 4 data register R/W 00000000
0013 DDR4 Port 4 direction register R/W 00000000
0014 PDR5 Port 5 data register R/W 00000000
0015 DDR5 Port 5 direction register R/W 00000000
0016 PDR6 Port 6 data register R/W 00000000
0017 DDR6 Port 6 direction register R/W 00000000
0018 PDR7 Port 7 data register R/W 00000000
0019 DDR7 Port 7 direction register R/W 00000000
001A PDR8 Port 8 data register R/W 00000000
001B DDR8 Port 8 direction register R/W 00000000
792
001C
-- (Vacancy) -- --
001D
001E
001F
0020
0021
0022
0023
0024
0025
0026 PDRE Port E data register R/W 00000000
0027 DDRE Port E direction register R/W 00000000
0028-- (Vacancy) -- --
0029
002A PDRG Port G data register R/W 00000000
002B DDRG Port G direction register R/W 00000000
002C -- (Vacancy) -- --
002D PUL1 Port 1 pull-up register R/W 00000000
002E PUL2 Port 2 pull-up register R/W 00000000
002F PUL3 Port 3 pull-up register R/W 00000000
0030 PUL4 Port 4 pull-up register R/W 00000000
0031 PUL5 Port 5 pull-up register R/W 00000000
0032 PUL7 Port 7 pull-up register R/W 00000000
0033 PUL8 Port 8 pull-up register R/W 00000000
0034 PULE Port E pull-up register R/W 00000000
0035 PULG Port G pull-up register R/W 00000000
0036 T01CR1 Control status register 1 ch 0 for 8/16-bit compound timer 01 R/W 00000000
0037 T00CR1 Control status register 1 ch 0 for 8/16-bit compound timer 00 R/W 00000000
0038 T11CR1 Control status register 1 ch 1 for 8/16-bit compound timer 11 R/W 00000000
0039 T10CR1 Control status register 1 ch 1 for 8/16-bit compound timer 10 R/W 00000000
003A PC01 Control register ch0 for 8/16-bit PPG1 R/W 00000000
003B PC00 Control register ch0 for 8/16-bit PPG0 R/W 00000000
003C PC11 Control register ch1 for 8/16-bit PPG1 R/W 00000000
003D PC10 Control register ch1 for 8/16-bit PPG0 R/W 00000000
003E TMCSRH0 Control status register upper ch0 for 16-bit reload timer R/W 00000000
Table 29.1-4 BASSOON series (2 / 8)
Address Register abbreviation Register name R/W Initial value
793
CHAPTER 29 Basic Information
003F TMCSRL0 Control status register lower ch0 for 16-bit reload timer R/W 00000000
0040-- (Vacancy) -- --
0041
0042 PCNTH0 Status control register upper ch0 for 16-bit PPG R/W 00000000
0043 PCNTL0 Status control register lower ch0 for 16-bit PPG R/W 00000000
0044 PCNTH1 Status control register upper ch1 for 16-bit PPG R/W 00000000
0045 PCNTL1 Status control register lower ch1 for 16-bit PPG R/W 00000000
0046-- (Vacancy) -- --
0047
0048 EIC00 Control register ch0/1 for external interrupt circuit R/W 00000000
0049 EIC10 Control register ch2/3 for external interrupt circuit R/W 00000000
004A EIC20 Control register ch4/5 for external interrupt circuit R/W 00000000
004B EIC30 Control register ch6/7 for external interrupt circuit R/W 00000000
004C EIC01 Control register ch8/9 for external interrupt circuit R/W 00000000
004D EIC11 Control register ch10/11 for external interrupt circuit R/W 00000000
004E-- (Vacancy) -- --
004F
0050 SCR LIN-UART serial control register R/W 00000000
0051 SMR LIN-UART serial mode register R/W 00000000
0052 SSR LIN-UART serial status register R/W 00001000
0053 RDR/TDR LIN-UART reception/transmission data register R/W 00000000
0054 ESCR LIN-UART extended status control register R/W 00000100
0055 ECCR LIN-UART extended communication control register R/W 000000XX
0056 SMC10 UART/SIO serial mode control register 1 ch0 R/W 00000000
0057 SMC20 UART/SIO serial mode control register 2 ch0 R/W 00100000
0058 SSR0 UART/SIO serial status register ch0 R/W 00000001
0059 TDR0 UART/SIO serial output data register ch0 R/W 00000000
005A RDR0 UART/SIO serial input data register ch0 R 00000000
005B
-- (Vacancy) -- --
005C
005D
005E
005F
0060 IBCR00 I2C bus control register 0 ch0 R/W 00000000
0061 IBCR10 I2C bus control register 1 ch0 R/W 00000000
Table 29.1-4 BASSOON series (3 / 8)
Address Register abbreviation Register name R/W Initial value
794
0062 IBSR0 I2C bus status register ch0 R 00000000
0063 IDDR0 I2C data register ch0 R/W 00000000
0064 IAAR0 I2C address register ch0 R/W 00000000
0065 ICCR0 I2C clock control register ch0 R/W 00000000
0066
-- (Vacancy) -- --
0067
0068
0069
006A
006B
006C ADC1 A/D control register 1 R/W 00000000
006D ADC2 A/D control register 2 R/W 00000000
006E ADDH A/D data register upper R/W 00000000
006F ADDL A/D data register lower R/W 00000000
0070 WCSR Watch counter status register R/W 00000000
0071 -- (Vacancy) -- --
0072 FSR Flash memory status register R/W 000x0000
0073 SWRE0 Flash memory sector write control register 0 R/W 00000000
0074 SWRE1 Flash memory sector write control register 1 R/W 00000000
0075 -- (Vacancy) -- --
0076 WREN Address compare enable register for wild register R/W 00000000
0077 WROR Data test setting register for wild register R/W 00000000
0078 -- * Mirror of RP -- --
0079 ILR0 Interrupt level setting register 0 R/W 11111111
007A ILR1 Interrupt level setting register 1 R/W 11111111
007B ILR2 Interrupt level setting register 2 R/W 11111111
007C ILR3 Interrupt level setting register 3 R/W 11111111
007D ILR4 Interrupt level setting register 4 R/W 11111111
007E ILR5 Interrupt level setting register 5 R/W 11111111
007F -- (Vacancy) -- --
0F80 WRARH0 Address setting register upper ch0 for wild register R/W 00000000
0F81 WRARL0 Address setting register lower ch0 for wild register R/W 00000000
0F82 WRDR0 Data setting register ch0 for wild register R/W 00000000
0F83 WRARH1 Address setting register upper ch1 for wild register R/W 00000000
0F84 WRARL1 Address setting register lower ch1 for wild register R/W 00000000
Table 29.1-4 BASSOON series (4 / 8)
Address Register abbreviation Register name R/W Initial value
795
CHAPTER 29 Basic Information
0F85 WRDR1 Data setting register ch1 for wild register R/W 00000000
0F86 WRARH2 Address setting register upper ch2 for wild register R/W 00000000
0F87 WRARL2 Address setting register lower ch2 for wild register R/W 00000000
0F88 WRDR2 Data setting register ch2 for wild register R/W 00000000
0F89 -- (Vacancy) -- --
0F8A -- (Vacancy) -- --
0F8B -- (Vacancy) -- --
0F8C -- (Vacancy) -- --
0F8D -- (Vacancy) -- --
0F8E -- (Vacancy) -- --
0F8F -- (Vacancy) -- --
0F90 -- (Vacancy) -- --
0F91 -- (Vacancy) -- --
0F92 T01CR0 Control status register 0 ch0 for 8/16-bit compound timer 01 R/W 00000000
0F93 T00CR0 Control status register 0 ch0 for 8/16-bit compound timer 00 R/W 00000000
0F94 T01DR Data register ch0 for 8/16-bit compound timer 01 R/W 00000000
0F95 T00DR Data register ch0 for 8/16-bit compound timer 00 R/W 00000000
0F96 TMCR0 Timer mode control register ch0 for 8/16-bit compound timer 00/01 R/W 00000000
0F97 T11CR0 Control status register 0 ch1 for 8/16-bit compound timer 11 R/W 00000000
0F98 T10CR0 Control status register 0 ch1 for 8/16-bit compound timer 10 R/W 00000000
0F99 T11DR Data register ch1 for 8/16-bit compound timer 11 R/W 00000000
0F9A T10DR Data register ch1 for 8/16-bit compound timer 10 R/W 00000000
0F9B TMCR1 Timer mode control register ch1 for 8/16-bit compound timer 10/11 R/W 00000000
0F9C PPS01 Cycle setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9D PPS00 Cycle setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0F9E PDS01 Duty setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9F PDS00 Duty setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0FA0 PPS11 Cycle setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA1 PPS10 Cycle setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA2 PDS11 Duty setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA3 PDS10 Duty setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA4 PPGS 8/16-bit PPG startup register R/W 00000000
0FA5 REVC 8/16-bit PPG output reverse register R/W 00000000
0FA6 TMRH0/TMRLRH0 Timer/reload register upper ch0 for 16-bit reload timer R/W 00000000
0FA7 TMRL0/TMRLRL0 Timer/reload register lower ch0 for 16-bit reload timer R/W 00000000
Table 29.1-4 BASSOON series (5 / 8)
Address Register abbreviation Register name R/W Initial value
796
0FA8-- (Vacancy) -- --
0FA9
0FAA PDCRH0 Down counter register upper ch0 for 16-bit PPG R 00000000
0FAB PDCRL0 Down counter register lower ch0 for 16-bit PPG R 00000000
0FAC PCSRH0 Cycle setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAD PCSRL0 Cycle setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FAE PDUTH0 Duty setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAF PDUTL0 Duty setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FB0 PDCRH1 Down counter register upper ch1 for 16-bit PPG R 00000000
0FB1 PDCRL1 Down counter register lower ch1 for 16-bit PPG R 00000000
0FB2 PCSRH1 Cycle setting buffer register upper ch1 for 16-bit PPG R/W 11111111
0FB3 PCSRL1 Cycle setting buffer register lower ch1 for 16-bit PPG R/W 11111111
0FB4 PDUTH1 Duty setting buffer register upper ch1 for 16-bit PPG R/W 11111111
0FB5 PDUTL1 Duty setting buffer register lower ch1 for 16-bit PPG R/W 11111111
0FB6
-- (Vacancy) -- --
0FB7
0FB8
0FB9
0FBA
0FBB
0FBC BGR1 LIN-UART baud rate generator register 1 R/W 00000000
0FBD BGR0 LIN-UART baud rate generator register 0 R/W 00000000
0FBE PSSR0 UART/SIO prescaler select register ch0 R/W 00000000
0FBF BRSR0 UART/SIO baud rate setting register ch0 R/W 00000000
0FC0-- (Vacancy) -- --
0FC1
0FC2 AIDRH A/D input disable register upper R/W 00000000
0FC3 AIDRL A/D input disable register lower R/W 00000000
0FC4 -- (Vacancy) -- --
0FC5 -- (Vacancy) -- --
0FC6 -- (Vacancy) -- --
0FC7 -- (Vacancy) -- --
0FC8 -- (Vacancy) -- --
0FC9 -- (Vacancy) -- --
0FCA -- (Vacancy) -- --
Table 29.1-4 BASSOON series (6 / 8)
Address Register abbreviation Register name R/W Initial value
797
CHAPTER 29 Basic Information
0FCB -- (Vacancy) -- --
0FCC -- (Vacancy) -- --
0FCD -- (Vacancy) -- --
0FCE -- (Vacancy) -- --
0FCF -- (Vacancy) -- --
0FD0 -- (Vacancy) -- --
0FD1 -- (Vacancy) -- --
0FD2 -- (Vacancy) -- --
0FD3 -- (Vacancy) -- --
0FD4 -- (Vacancy) -- --
0FD5 -- (Vacancy) -- --
0FD6 -- (Vacancy) -- --
0FD7 -- (Vacancy) -- --
0FD8 -- (Vacancy) -- --
0FD9 -- (Vacancy) -- --
0FDA -- (Vacancy) -- --
0FDB -- (Vacancy) -- --
0FDC -- (Vacancy) -- --
0FDD -- (Vacancy) -- --
0FDE -- (Vacancy) -- --
0FDF -- (Vacancy) -- --
0FE0 -- (Vacancy) -- --
0FE1 -- (Vacancy) -- --
0FE2 -- (Vacancy) -- --
0FE3 WCDR Watch counter data register R/W 00111111 1
0FE4
-- (Vacancy) -- --
0FE5
0FE6
0FE7
0FE8
0FE9 -- (Vacancy) -- --
0FEA CSVCR Clock supervisor control register R/W 00011100
0FEB-- (Vacancy) -- --
0FEC
0FED -- (Vacancy) -- --
Table 29.1-4 BASSOON series (7 / 8)
Address Register abbreviation Register name R/W Initial value
798
0FEE ILSR Input level select register R/W -0000000
0FEF WICR Interrupt pin control register R/W 01000000
0FF0
-- (Vacancy) -- --
0FF1
0FF2
0FF3
0FF4
0FF5
0FF6
0FF7
0FF8
0FF9
0FFA
0FFB
0FFC
0FFD
0FFE
0FFF
Table 29.1-4 BASSOON series (8 / 8)
Address Register abbreviation Register name R/W Initial value
799
CHAPTER 29 Basic Information
Table 29.1-5 CLARINET series (1 / 8)
Address Register abbreviation Register name R/W Initial value
0000 PDR0 Port 0 data register R/W 00000000
0001 DDR0 Port 0 direction register R/W 00000000
0002 PDR1 Port 1 data register R/W 00000000
0003 DDR1 Port 1 direction register R/W 00000000
0004 -- (Vacancy) -- --
0005 WATR Oscillation stabilization wait time setting register R/W 11111111
0006 PLLC PLL control register R/W 00000000
0007 SYCC System clock control register R/W 1010x011
0008 STBC Standby control register R/W 00000000
0009 RSRR Reset cause register R xxxxxxxx
000A TBTC Timebase timer control register R/W 00000000
000B WPCR Watch prescaler control register R/W 00000000
000C WDTC Watchdog timer control register R/W 00000000
000D -- (Vacancy) -- --
000E PDR2 Port 2 data register R/W 00000000
000F DDR2 Port 2 direction register R/W 00000000
0010 PDR3 Port 3 data register R/W 00000000
0011 DDR3 Port 3 direction register R/W 00000000
0012-- (Vacancy) -- --
0013
0014 PDR5 Port 5 data register R/W 00000000
0015 DDR5 Port 5 direction register R/W 00000000
0016 PDR6 Port 6 data register R/W 00000000
0017 DDR6 Port 6 direction register R/W 00000000
0018 -- (Vacancy) -- --
0019 -- (Vacancy) -- --
001A -- (Vacancy) -- --
001B -- (Vacancy) -- --
001C -- (Vacancy) -- --
001D -- (Vacancy) -- --
001E -- (Vacancy) -- --
001F -- (Vacancy) -- --
0020 -- (Vacancy) -- --
800
0021 -- (Vacancy) -- --
0022 -- (Vacancy) -- --
0023 -- (Vacancy) -- --
0024 -- (Vacancy) -- --
0025 -- (Vacancy) -- --
0026 -- (Vacancy) -- --
0027 -- (Vacancy) -- --
0028 -- (Vacancy) -- --
0029 -- (Vacancy) -- --
002A PDRG Port G data register R/W 00000000
002B DDRG Port G direction register R/W 00000000
002C -- (Vacancy) -- --
002D PUL1 Port 1 pull-up register R/W 00000000
002E PUL2 Port 2 pull-up register R/W 00000000
002F PUL3 Port 3 pull-up register R/W 00000000
0030
-- (Vacancy) -- --
0031
0032
0033
0034
0035 PULG Port G pull-up register R/W 00000000
0036 T01CR1 Control status register 1 ch 0 for 8/16-bit compound timer 01 R/W 00000000
0037 T00CR1 Control status register 1 ch 0 for 8/16-bit compound timer 00 R/W 00000000
0038 T11CR1 Control status register 1 ch 1 for 8/16-bit compound timer 11 R/W 00000000
0039 T10CR1 Control status register 1 ch 1 for 8/16-bit compound timer 10 R/W 00000000
003A PC01 Control register ch0 for 8/16-bit PPG1 R/W 00000000
003B PC00 Control register ch0 for 8/16-bit PPG0 R/W 00000000
003C PC11 Control register ch1 for 8/16-bit PPG1 R/W 00000000
003D PC10 Control register ch1 for 8/16-bit PPG0 R/W 00000000
003E
-- (Vacancy) -- --003F
0040
0041
0042 PCNTH0 Status control register upper ch0 for 16-bit PPG R/W 00000000
0043 PCNTL0 Status control register lower ch0 for 16-bit PPG R/W 00000000
Table 29.1-5 CLARINET series (2 / 8)
Address Register abbreviation Register name R/W Initial value
801
CHAPTER 29 Basic Information
0044
-- (Vacancy) -- --0045
0046
0047
0048 EIC00 Control register ch0/1 for external interrupt circuit R/W 00000000
0049 EIC10 Control register ch2/3 for external interrupt circuit R/W 00000000
004A EIC20 Control register ch4/5 for external interrupt circuit R/W 00000000
004B EIC30 Control register ch6/7 for external interrupt circuit R/W 00000000
004C
-- (Vacancy) -- --004D
004E
004F
0050 SCR LIN-UART serial control register R/W 00000000
0051 SMR LIN-UART serial mode register R/W 00000000
0052 SSR LIN-UART serial status register R/W 00001000
0053 RDR/TDR LIN-UART reception/transmission data register R/W 00000000
0054 ESCR LIN-UART extended status control register R/W 00000100
0055 ECCR LIN-UART extended communication control register R/W 000000XX
0056 SMC10 UART/SIO serial mode control register 1 ch0 R/W 00000000
0057 SMC20 UART/SIO serial mode control register 2 ch0 R/W 00100000
0058 SSR0 UART/SIO serial status register ch0 R/W 00000001
0059 TDR0 UART/SIO serial output data register ch0 R/W 00000000
005A RDR0 UART/SIO serial input data register ch0 R 00000000
005B
-- (Vacancy) -- --
005C
005D
005E
005F
0060 IBCR00 I2C bus control register 0 ch0 R/W 00000000
0061 IBCR10 I2C bus control register 1 ch0 R/W 00000000
0062 IBSR0 I2C bus status register ch0 R 00000000
0063 IDDR0 I2C data register ch0 R/W 00000000
0064 IAAR0 I2C address register ch0 R/W 00000000
0065 ICCR0 I2C clock control register ch0 R/W 00000000
Table 29.1-5 CLARINET series (3 / 8)
Address Register abbreviation Register name R/W Initial value
802
0066
-- (Vacancy) -- --
0067
0068
0069
006A
006B
006C ADC1 A/D control register 1 R/W 00000000
006D ADC2 A/D control register 2 R/W 00000000
006E ADDH A/D data register upper R/W 00000000
006F ADDL A/D data register lower R/W 00000000
0070 WCSR Watch counter status register R/W 00000000
0071 -- (Vacancy) -- --
0072 FSR Flash memory status register R/W 00X00000
0073 SWRE0 Flash memory sector write control register 0 R/W 00000000
0074 SWRE1 Flash memory sector write control register 1 R/W 00000000
0075 -- (Vacancy) -- --
0076 WREN Address compare enable register for wild register R/W 00000000
0077 WROR Data test setting register for wild register R/W 00000000
0078 -- * Mirror of RP -- --
0079 ILR0 Interrupt level setting register 0 R/W 11111111
007A ILR1 Interrupt level setting register 1 R/W 11111111
007B ILR2 Interrupt level setting register 2 R/W 11111111
007C ILR3 Interrupt level setting register 3 R/W 11111111
007D ILR4 Interrupt level setting register 4 R/W 11111111
007E ILR5 Interrupt level setting register 5 R/W 11111111
007F -- (Vacancy) -- --
0F80 WRARH0 Address setting register upper ch0 for wild register R/W 00000000
0F81 WRARL0 Address setting register lower ch0 for wild register R/W 00000000
0F82 WRDR0 Data setting register ch0 for wild register R/W 00000000
0F83 WRARH1 Address setting register upper ch1 for wild register R/W 00000000
0F84 WRARL1 Address setting register lower ch1 for wild register R/W 00000000
0F85 WRDR1 Data setting register ch1 for wild register R/W 00000000
0F86 WRARH2 Address setting register upper ch2 for wild register R/W 00000000
0F87 WRARL2 Address setting register lower ch2 for wild register R/W 00000000
0F88 WRDR2 Data setting register ch2 for wild register R/W 00000000
Table 29.1-5 CLARINET series (4 / 8)
Address Register abbreviation Register name R/W Initial value
803
CHAPTER 29 Basic Information
0F89 -- (Vacancy) -- --
0F8A -- (Vacancy) -- --
0F8B -- (Vacancy) -- --
0F8C -- (Vacancy) -- --
0F8D -- (Vacancy) -- --
0F8E -- (Vacancy) -- --
0F8F -- (Vacancy) -- --
0F90 -- (Vacancy) -- --
0F91 -- (Vacancy) -- --
0F92 T01CR0 Control status register 0 ch0 for 8/16-bit compound timer 01 R/W 00000000
0F93 T00CR0 Control status register 0 ch0 for 8/16-bit compound timer 00 R/W 00000000
0F94 T01DR Data register ch0 for 8/16-bit compound timer 01 R/W 00000000
0F95 T00DR Data register ch0 for 8/16-bit compound timer 00 R/W 00000000
0F96 TMCR0 Timer mode control register ch0 for 8/16-bit compound timer 00/01 R/W 00000000
0F97 T11CR0 Control status register 0 ch1 for 8/16-bit compound timer 11 R/W 00000000
0F98 T10CR0 Control status register 0 ch1 for 8/16-bit compound timer 10 R/W 00000000
0F99 T11DR Data register ch1 for 8/16-bit compound timer 11 R/W 00000000
0F9A T10DR Data register ch1 for 8/16-bit compound timer 10 R/W 00000000
0F9B TMCR1 Timer mode control register ch1 for 8/16-bit compound timer 10/11 R/W 00000000
0F9C PPS01 Cycle setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9D PPS00 Cycle setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0F9E PDS01 Duty setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9F PDS00 Duty setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0FA0 PPS11 Cycle setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA1 PPS10 Cycle setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA2 PDS11 Duty setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA3 PDS10 Duty setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA4 PPGS 8/16-bit PPG startup register R/W 00000000
0FA5 REVC 8/16-bit PPG output reverse register R/W 00000000
0FA6
-- (Vacancy) -- --0FA7
0FA8
0FA9
0FAA PDCRH0 Down counter register upper ch0 for 16-bit PPG R 00000000
0FAB PDCRL0 Down counter register lower ch0 for 16-bit PPG R 00000000
Table 29.1-5 CLARINET series (5 / 8)
Address Register abbreviation Register name R/W Initial value
804
0FAC PCSRH0 Cycle setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAD PCSRL0 Cycle setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FAE PDUTH0 Duty setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAF PDUTL0 Duty setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FB0
-- (Vacancy) -- --
0FB1
0FB2
0FB3
0FB4
0FB5
0FB6
0FB7
0FB8
0FB9
0FBA
0FBB
0FBC BGR1 LIN-UART baud rate generator register 1 R/W 00000000
0FBD BGR0 LIN-UART baud rate generator register 0 R/W 00000000
0FBE PSSR0 UART/SIO prescaler select register ch0 R/W 00000000
0FBF BRSR0 UART/SIO baud rate setting register ch0 R/W 00000000
0FC0
-- (Vacancy) -- --0FC1
0FC2
0FC3 AIDRL A/D input disable register lower R/W 00000000
0FC4 -- (Vacancy) -- --
0FC5 -- (Vacancy) -- --
0FC6 -- (Vacancy) -- --
0FC7 -- (Vacancy) -- --
0FC8 -- (Vacancy) -- --
0FC9 -- (Vacancy) -- --
0FCA -- (Vacancy) -- --
0FCB -- (Vacancy) -- --
0FCC -- (Vacancy) -- --
0FCD -- (Vacancy) -- --
0FCE -- (Vacancy) -- --
Table 29.1-5 CLARINET series (6 / 8)
Address Register abbreviation Register name R/W Initial value
805
CHAPTER 29 Basic Information
0FCF -- (Vacancy) -- --
0FD0 -- (Vacancy) -- --
0FD1 -- (Vacancy) -- --
0FD2 -- (Vacancy) -- --
0FD3 -- (Vacancy) -- --
0FD4 -- (Vacancy) -- --
0FD5 -- (Vacancy) -- --
0FD6 -- (Vacancy) -- --
0FD7 -- (Vacancy) -- --
0FD8 -- (Vacancy) -- --
0FD9 -- (Vacancy) -- --
0FDA -- (Vacancy) -- --
0FDB -- (Vacancy) -- --
0FDC -- (Vacancy) -- --
0FDD -- (Vacancy) -- --
0FDE -- (Vacancy) -- --
0FDF -- (Vacancy) -- --
0FE0 -- (Vacancy) -- --
0FE1 -- (Vacancy) -- --
0FE2 -- (Vacancy) -- --
0FE3 WCDR Watch counter data register R/W 00111111
0FE4
-- (Vacancy) -- --
0FE5
0FE6
0FE7
0FE8
0FE9 -- (Vacancy) -- --
0FEA CSVCR Clock supervisor control register R/W 00011100
0FEB-- (Vacancy) -- --
0FEC
0FED -- (Vacancy) -- --
0FEE ILSR Input level select register R/W -0000000
0FEF WICR Interrupt pin control register R/W 01000000
Table 29.1-5 CLARINET series (7 / 8)
Address Register abbreviation Register name R/W Initial value
806
0FF0
-- (Vacancy) -- --
0FF1
0FF2
0FF3
0FF4
0FF5
0FF6
0FF7
0FF8
0FF9
0FFA
0FFB
0FFC
0FFD
0FFE
0FFF
Table 29.1-5 CLARINET series (8 / 8)
Address Register abbreviation Register name R/W Initial value
807
CHAPTER 29 Basic Information
Table 29.1-6 OBOE series (1 / 8)
Address Register abbreviation Register name R/W Initial value
0000 PDR0 Port 0 data register R/W 00000000
0001 DDR0 Port 0 direction register R/W 00000000
0002 PDR1 Port 1 data register R/W 00000000
0003 DDR1 Port 1 direction register R/W 00000000
0004 -- (Vacancy) -- --
0005 WATR Oscillation stabilization wait time setting register R/W 11111111
0006 PLLC PLL control register R/W 00000000
0007 SYCC System clock control register R/W 1010x011
0008 STBC Standby control register R/W 00000000
0009 RSRR Reset cause register R xxxxxxxx
000A TBTC Timebase timer control register R/W 00000000
000B WPCR Watch prescaler control register R/W 00000000
000C WDTC Watchdog timer control register R/W 00000000
000D
-- (Vacancy) -- --
000E
000F
0010
0011
0012
0013
0014
0015
0016 PDR6 Port 6 data register R/W 00000000
0017 DDR6 Port 6 direction register R/W 00000000
0018 -- (Vacancy) -- --
0019 -- (Vacancy) -- --
001A -- (Vacancy) -- --
001B -- (Vacancy) -- --
001C -- (Vacancy) -- --
001D -- (Vacancy) -- --
001E -- (Vacancy) -- --
001F -- (Vacancy) -- --
0020 -- (Vacancy) -- --
808
0021 -- (Vacancy) -- --
0022 -- (Vacancy) -- --
0023 -- (Vacancy) -- --
0024 -- (Vacancy) -- --
0025 -- (Vacancy) -- --
0026 -- (Vacancy) -- --
0027 -- (Vacancy) -- --
0028 PDRF Port F data register R/W 00000000
0029 DDRF Port F direction register R/W 00000000
002A PDRG Port G data register R/W 00000000
002B DDRG Port G direction register R/W 00000000
002C PUL0 Port 0 pull-up register R/W 00000000
002D PUL1 Port 1 pull-up register R/W 00000000
002E
-- (Vacancy) -- --
002F
0030
0031
0032
0033
0034
0035 PULG Port G pull-up register R/W 00000000
0036 T01CR1 Control status register 1 ch 0 for 8/16-bit compound timer 01 R/W 00000000
0037 T00CR1 Control status register 1 ch 0 for 8/16-bit compound timer 00 R/W 00000000
0038 T11CR1 Control status register 1 ch 1 for 8/16-bit compound timer 11 R/W 00000000
0039 T10CR1 Control status register 1 ch 1 for 8/16-bit compound timer 10 R/W 00000000
003A PC01 Control register ch0 for 8/16-bit PPG1 R/W 00000000
003B PC00 Control register ch0 for 8/16-bit PPG0 R/W 00000000
003C PC11 Control register ch1 for 8/16-bit PPG1 R/W 00000000
003D PC10 Control register ch1 for 8/16-bit PPG0 R/W 00000000
003E
-- (Vacancy) -- --003F
0040
0041
0042 PCNTH0 Status control register upper ch0 for 16-bit PPG R/W 00000000
0043 PCNTL0 Status control register lower ch0 for 16-bit PPG R/W 00000000
Table 29.1-6 OBOE series (2 / 8)
Address Register abbreviation Register name R/W Initial value
809
CHAPTER 29 Basic Information
0044
-- (Vacancy) -- --0045
0046
0047
0048 EIC00 Control register ch0/1 for external interrupt circuit R/W 00000000
0049 EIC10 Control register ch2/3 for external interrupt circuit R/W 00000000
004A EIC20 Control register ch4/5 for external interrupt circuit R/W 00000000
004B EIC30 Control register ch6/7 for external interrupt circuit R/W 00000000
004C
-- (Vacancy) -- --004D
004E
004F
0050 SCR LIN-UART serial control register R/W 00000000
0051 SMR LIN-UART serial mode register R/W 00000000
0052 SSR LIN-UART serial status register R/W 00001000
0053 RDR/TDR LIN-UART reception/transmission data register R/W 00000000
0054 ESCR LIN-UART extended status control register R/W 00000100
0055 ECCR LIN-UART extended communication control register R/W 000000XX
0056 SMC10 UART/SIO serial mode control register 1 ch0 R/W 00000000
0057 SMC20 UART/SIO serial mode control register 2 ch0 R/W 00100000
0058 SSR0 UART/SIO serial status register ch0 R/W 00000001
0059 TDR2 UART/SIO serial output data register ch0 R/W 00000000
005A RDR0 UART/SIO serial input data register ch0 R 00000000
005B -- (Vacancy) -- --
005C -- (Vacancy) -- --
005D -- (Vacancy) -- --
005E -- (Vacancy) -- --
005F -- (Vacancy) -- --
0060 -- (Vacancy) -- --
0061 -- (Vacancy) -- --
0062 -- (Vacancy) -- --
0063 -- (Vacancy) -- --
0064 -- (Vacancy) -- --
0065 -- (Vacancy) -- --
0066 -- (Vacancy) -- --
Table 29.1-6 OBOE series (3 / 8)
Address Register abbreviation Register name R/W Initial value
810
0067 -- (Vacancy) -- --
0068 -- (Vacancy) -- --
0069 -- (Vacancy) -- --
006A -- (Vacancy) -- --
006B -- (Vacancy) -- --
006C ADC1 A/D control register 1 R/W 00000000
006D ADC2 A/D control register 2 R/W 00000000
006E ADDH A/D data register upper R/W 00000000
006F ADDL A/D data register lower R/W 00000000
0070 WCSR Watch counter status register R/W 00000000
0071 -- (Vacancy) -- --
0072 FSR Flash memory status register R/W 000X0000
0073 SWRE0 Flash memory sector write control register 0 R/W 00000000
0074 SWRE1 Flash memory sector write control register 1 R/W 00000000
0075 -- (Vacancy) -- --
0076 WREN Address compare enable register for wild register R/W 00000000
0077 WROR Data test setting register for wild register R/W 00000000
0078 -- * Mirror of RP -- --
0079 ILR0 Interrupt level setting register 0 R/W 11111111
007A ILR1 Interrupt level setting register 1 R/W 11111111
007B ILR2 Interrupt level setting register 2 R/W 11111111
007C ILR3 Interrupt level setting register 3 R/W 11111111
007D ILR4 Interrupt level setting register 4 R/W 11111111
007E ILR5 Interrupt level setting register 5 R/W 11111111
007F -- (Vacancy) -- --
0F80 WRARH0 Address setting register upper ch0 for wild register R/W 00000000
0F81 WRARL0 Address setting register lower ch0 for wild register R/W 00000000
0F82 WRDR0 Data setting register ch0 for wild register R/W 00000000
0F83 WRARH1 Address setting register upper ch1 for wild register R/W 00000000
0F84 WRARL1 Address setting register lower ch1 for wild register R/W 00000000
0F85 WRDR1 Data setting register ch1 for wild register R/W 00000000
0F86 WRARH2 Address setting register upper ch2 for wild register R/W 00000000
0F87 WRARL2 Address setting register lower ch2 for wild register R/W 00000000
0F88 WRDR2 Data setting register ch2 for wild register R/W 00000000
0F89 -- (Vacancy) -- --
Table 29.1-6 OBOE series (4 / 8)
Address Register abbreviation Register name R/W Initial value
811
CHAPTER 29 Basic Information
0F8A -- (Vacancy) -- --
0F8B -- (Vacancy) -- --
0F8C -- (Vacancy) -- --
0F8D -- (Vacancy) -- --
0F8E -- (Vacancy) -- --
0F8F -- (Vacancy) -- --
0F90 -- (Vacancy) -- --
0F91 -- (Vacancy) -- --
0F92 T01CR0 Control status register 0 ch0 for 8/16-bit compound timer 01 R/W 00000000
0F93 T00CR0 Control status register 0 ch0 for 8/16-bit compound timer 00 R/W 00000000
0F94 T01DR Data register ch0 for 8/16-bit compound timer 01 R/W 00000000
0F95 T00DR Data register ch0 for 8/16-bit compound timer 00 R/W 00000000
0F96 TMCR0 Timer mode control register ch0 for 8/16-bit compound timer 00/01 R/W 00000000
0F97 T11CR0 Control status register 0 ch1 for 8/16-bit compound timer 11 R/W 00000000
0F98 T10CR0 Control status register 0 ch1 for 8/16-bit compound timer 10 R/W 00000000
0F99 T11DR Data register ch1 for 8/16-bit compound timer 11 R/W 00000000
0F9A T10DR Data register ch1 for 8/16-bit compound timer 10 R/W 00000000
0F9B TMCR1 Timer mode control register ch1 for 8/16-bit compound timer 10/11 R/W 00000000
0F9C PPS01 Cycle setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9D PPS00 Cycle setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0F9E PDS01 Duty setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9F PDS00 Duty setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0FA0 PPS11 Cycle setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA1 PPS10 Cycle setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA2 PDS11 Duty setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA3 PDS10 Duty setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA4 PPGS 8/16-bit PPG startup register R/W 00000000
0FA5 REVC 8/16-bit PPG output reverse register R/W 00000000
0FA6
-- (Vacancy) -- --0FA7
0FA8
0FA9
0FAA PDCRH0 Down counter register upper ch0 for 16-bit PPG R 00000000
0FAB PDCRL0 Down counter register lower ch0 for 16-bit PPG R 00000000
0FAC PCSRH0 Cycle setting buffer register upper ch0 for 16-bit PPG R/W 11111111
Table 29.1-6 OBOE series (5 / 8)
Address Register abbreviation Register name R/W Initial value
812
0FAD PCSRL0 Cycle setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FAE PDUTH0 Duty setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAF PDUTL0 Duty setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FB0
-- (Vacancy) -- --
0FB1
0FB2
0FB3
0FB4
0FB5
0FB6
0FB7
0FB8
0FB9
0FBA
0FBB
0FBC BGR1 LIN-UART baud rate generator register 1 R/W 00000000
0FBD BGR0 LIN-UART baud rate generator register 0 R/W 00000000
0FBE PSSR0 UART/SIO prescaler select register ch0 R/W 00000000
0FBF BRSR0 UART/SIO baud rate setting register ch0 R/W 00000000
0FC0
-- (Vacancy) -- --0FC1
0FC2
0FC3 AIDRL A/D input disable register lower R/W 00000000
0FC4 -- (Vacancy) -- --
0FC5 -- (Vacancy) -- --
0FC6 -- (Vacancy) -- --
0FC7 -- (Vacancy) -- --
0FC8 -- (Vacancy) -- --
0FC9 -- (Vacancy) -- --
0FCA -- (Vacancy) -- --
0FCB -- (Vacancy) -- --
0FCC -- (Vacancy) -- --
0FCD -- (Vacancy) -- --
0FCE -- (Vacancy) -- --
0FCF -- (Vacancy) -- --
Table 29.1-6 OBOE series (6 / 8)
Address Register abbreviation Register name R/W Initial value
813
CHAPTER 29 Basic Information
0FD0 -- (Vacancy) -- --
0FD1 -- (Vacancy) -- --
0FD2 -- (Vacancy) -- --
0FD3 -- (Vacancy) -- --
0FD4 -- (Vacancy) -- --
0FD5 -- (Vacancy) -- --
0FD6 -- (Vacancy) -- --
0FD7 -- (Vacancy) -- --
0FD8 -- (Vacancy) -- --
0FD9 -- (Vacancy) -- --
0FDA -- (Vacancy) -- --
0FDB -- (Vacancy) -- --
0FDC -- (Vacancy) -- --
0FDD -- (Vacancy) -- --
0FDE -- (Vacancy) -- --
0FDF -- (Vacancy) -- --
0FE0 -- (Vacancy) -- --
0FE1 -- (Vacancy) -- --
0FE2 -- (Vacancy) -- --
0FE3 WCDR Watch counter data register R/W 00111111
0FE4
-- (Vacancy) -- --
0FE5
0FE6
0FE7
0FE8
0FE9 -- (Vacancy) -- --
0FEA CSVCR Clock supervisor control register R/W 00011100
0FEB-- (Vacancy) -- --
0FEC
0FED -- (Vacancy) -- --
0FEE ILSR Input level select register R/W -0000000
0FEF WICR Interrupt pin control register R/W 01000000
Table 29.1-6 OBOE series (7 / 8)
Address Register abbreviation Register name R/W Initial value
814
0FF0
-- (Vacancy) -- --
0FF1
0FF2
0FF3
0FF4
0FF5
0FF6
0FF7
0FF8
0FF9
0FFA
0FFB
0FFC
0FFD
0FFE
0FFF
Table 29.1-6 OBOE series (8 / 8)
Address Register abbreviation Register name R/W Initial value
815
CHAPTER 29 Basic Information
Table 29.1-7 FLUTE series (1 / 8)
Address Register abbreviation Register name R/W Initial value
0000 PDR0 Port 0 data register R/W 00000000
0001 DDR0 Port 0 direction register R/W 00000000
0002 PDR1 Port 1 data register R/W 00000000
0003 DDR1 Port 1 direction register R/W 00000000
0004 -- (Vacancy) -- --
0005 WATR Oscillation stabilization wait time setting register R/W 11111111
0006 PLLC PLL control register R/W 00000000
0007 SYCC System clock control register R/W 1010x011
0008 STBC Standby control register R/W 00000000
0009 RSRR Reset cause register R xxxxxxxx
000A TBTC Timebase timer control register R/W 00000000
000B WPCR Watch prescaler control register R/W 00000000
000C WDTC Watchdog timer control register R/W 00000000
000D -- (Vacancy) -- --
000E -- (Vacancy) -- --
000F -- (Vacancy) -- --
0010 -- (Vacancy) -- --
0011 -- (Vacancy) -- --
0012 -- (Vacancy) -- --
0013 -- (Vacancy) -- --
0014 -- (Vacancy) -- --
0015 -- (Vacancy) -- --
0016 -- (Vacancy) -- --
0017 -- (Vacancy) -- --
0018 -- (Vacancy) -- --
0019 -- (Vacancy) -- --
001A -- (Vacancy) -- --
001B -- (Vacancy) -- --
001C -- (Vacancy) -- --
001D -- (Vacancy) -- --
001E -- (Vacancy) -- --
001F -- (Vacancy) -- --
0020 -- (Vacancy) -- --
816
0021 -- (Vacancy) -- --
0022 -- (Vacancy) -- --
0023 -- (Vacancy) -- --
0024 -- (Vacancy) -- --
0025 -- (Vacancy) -- --
0026 -- (Vacancy) -- --
0027 -- (Vacancy) -- --
0028 PDRF Port F data register R/W 00000000
0029 DDRF Port F direction register R/W 00000000
002A PDRG Port G data register R/W 00000000
002B DDRG Port G direction register R/W 00000000
002C PUL0 Port 0 pull-up register R/W 00000000
002D PUL1 Port 1 pull-up register R/W 00000000
002E
-- (Vacancy) -- --
002F
0030
0031
0032
0033
0034
0035 PULG Port G pull-up register R/W 00000000
0036 T01CR1 Control status register 1 ch 0 for 8/16-bit compound timer 01 R/W 00000000
0037 T00CR1 Control status register 1 ch 0 for 8/16-bit compound timer 00 R/W 00000000
0038-- (Vacancy) -- --
0039
003A PC01 Control register ch0 for 8/16-bit PPG1 R/W 00000000
003B PC00 Control register ch0 for 8/16-bit PPG0 R/W 00000000
003C
-- (Vacancy) -- --
003D
003E
003F
0040
0041
0042 PCNTH0 Status control register upper ch0 for 16-bit PPG R/W 00000000
0043 PCNTL0 Status control register lower ch0 for 16-bit PPG R/W 00000000
Table 29.1-7 FLUTE series (2 / 8)
Address Register abbreviation Register name R/W Initial value
817
CHAPTER 29 Basic Information
0044
-- (Vacancy) -- --0045
0046
0047
0048 EIC00 Control register ch0/1 for external interrupt circuit R/W 00000000
0049 EIC10 Control register ch2/3 for external interrupt circuit R/W 00000000
004A EIC20 Control register ch4/5 for external interrupt circuit R/W 00000000
004B EIC30 Control register ch6/7 for external interrupt circuit R/W 00000000
004C
-- (Vacancy) -- --004D
004E
004F
0050 SCR LIN-UART serial control register R/W 00000000
0051 SMR LIN-UART serial mode register R/W 00000000
0052 SSR LIN-UART serial status register R/W 00001000
0053 RDR/TDR LIN-UART reception/transmission data register R/W 00000000
0054 ESCR LIN-UART extended status control register R/W 00000100
0055 ECCR LIN-UART extended communication control register R/W 000000XX
0056 SMC10 UART/SIO serial mode control register 1 ch0 R/W 00000000
0057 SMC20 UART/SIO serial mode control register 2 ch0 R/W 00100000
0058 SSR0 UART/SIO serial status register ch0 R/W 00000001
0059 TDR0 UART/SIO serial output data register ch0 R/W 00000000
005A RDR0 UART/SIO serial input data register ch0 R 00000000
005B -- (Vacancy) -- --
005C -- (Vacancy) -- --
005D -- (Vacancy) -- --
005E -- (Vacancy) -- --
005F -- (Vacancy) -- --
0060 -- (Vacancy) -- --
0061 -- (Vacancy) -- --
0062 -- (Vacancy) -- --
0063 -- (Vacancy) -- --
0064 -- (Vacancy) -- --
0065 -- (Vacancy) -- --
0066 -- (Vacancy) -- --
Table 29.1-7 FLUTE series (3 / 8)
Address Register abbreviation Register name R/W Initial value
818
0067 -- (Vacancy) -- --
0068 -- (Vacancy) -- --
0069 -- (Vacancy) -- --
006A -- (Vacancy) -- --
006B -- (Vacancy) -- --
006C ADC1 A/D control register 1 R/W 00000000
006D ADC2 A/D control register 2 R/W 00000000
006E ADDH A/D data register upper R/W 00000000
006F ADDL A/D data register lower R/W 00000000
0070 WCSR Watch counter status register R/W 00000000
0071 -- (Vacancy) -- --
0072 FSR Flash memory status register R/W 000x0000
0073 SWRE0 Flash memory sector write control register 0 R/W 00000000
0074 SWRE1 Flash memory sector write control register 1 R/W 00000000
0075 -- (Vacancy) -- --
0076 WREN Address compare enable register for wild register R/W 00000000
0077 WROR Data test setting register for wild register R/W 00000000
0078 -- * Mirror of RP -- --
0079 ILR0 Interrupt level setting register 0 R/W 11111111
007A ILR1 Interrupt level setting register 1 R/W 11111111
007B ILR2 Interrupt level setting register 2 R/W 11111111
007C ILR3 Interrupt level setting register 3 R/W 11111111
007D ILR4 Interrupt level setting register 4 R/W 11111111
007E ILR5 Interrupt level setting register 5 R/W 11111111
007F -- (Vacancy) -- --
0F80 WRARH0 Address setting register upper ch0 for wild register R/W 00000000
0F81 WRARL0 Address setting register lower ch0 for wild register R/W 00000000
0F82 WRDR0 Data setting register ch0 for wild register R/W 00000000
0F83 WRARH1 Address setting register upper ch1 for wild register R/W 00000000
0F84 WRARL1 Address setting register lower ch1 for wild register R/W 00000000
0F85 WRDR1 Data setting register ch1 for wild register R/W 00000000
0F86 WRARH2 Address setting register upper ch2 for wild register R/W 00000000
0F87 WRARL2 Address setting register lower ch2 for wild register R/W 00000000
0F88 WRDR2 Data setting register ch2 for wild register R/W 00000000
0F89 -- (Vacancy) -- --
Table 29.1-7 FLUTE series (4 / 8)
Address Register abbreviation Register name R/W Initial value
819
CHAPTER 29 Basic Information
0F8A -- (Vacancy) -- --
0F8B -- (Vacancy) -- --
0F8C -- (Vacancy) -- --
0F8D -- (Vacancy) -- --
0F8E -- (Vacancy) -- --
0F8F -- (Vacancy) -- --
0F90 -- (Vacancy) -- --
0F91 -- (Vacancy) -- --
0F92 T01CR0 Control status register 0 ch0 for 8/16-bit compound timer 01 R/W 00000000
0F93 T00CR0 Control status register 0 ch0 for 8/16-bit compound timer 00 R/W 00000000
0F94 T01DR Data register ch0 for 8/16-bit compound timer 01 R/W 00000000
0F95 T00DR Data register ch0 for 8/16-bit compound timer 00 R/W 00000000
0F96 TMCR0 Timer mode control register ch0 for 8/16-bit compound timer 00/01 R/W 00000000
0F97
-- (Vacancy) -- --
0F98
0F99
0F9A
0F9B
0F9C PPS01 Cycle setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9D PPS00 Cycle setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0F9E PDS01 Duty setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9F PDS00 Duty setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0FA0
-- (Vacancy) -- --0FA1
0FA2
0FA3
0FA4 PPGS 8/16-bit PPG startup register R/W 00000000
0FA5 REVC 8/16-bit PPG output reverse register R/W 00000000
0FA6
-- (Vacancy) -- --0FA7
0FA8
0FA9
0FAA PDCRH0 Down counter register upper ch0 for 16-bit PPG R 00000000
0FAB PDCRL0 Down counter register lower ch0 for 16-bit PPG R 00000000
0FAC PCSRH0 Cycle setting buffer register upper ch0 for 16-bit PPG R/W 11111111
Table 29.1-7 FLUTE series (5 / 8)
Address Register abbreviation Register name R/W Initial value
820
0FAD PCSRL0 Cycle setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FAE PDUTH0 Duty setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAF PDUTL0 Duty setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FB0
-- (Vacancy) -- --
0FB1
0FB2
0FB3
0FB4
0FB5
0FB6
0FB7
0FB8
0FB9
0FBA
0FBB
0FBC BGR1 LIN-UART baud rate generator register 1 R/W 00000000
0FBD BGR0 LIN-UART baud rate generator register 0 R/W 00000000
0FBE PSSR0 UART/SIO prescaler select register ch0 R/W 00000000
0FBF BRSR0 UART/SIO baud rate setting register ch0 R/W 00000000
0FC0
-- (Vacancy) -- --0FC1
0FC2
0FC3 AIDRL A/D input disable register lower R/W 00000000
0FC4 -- (Vacancy) -- --
0FC5 -- (Vacancy) -- --
0FC6 -- (Vacancy) -- --
0FC7 -- (Vacancy) -- --
0FC8 -- (Vacancy) -- --
0FC9 -- (Vacancy) -- --
0FCA -- (Vacancy) -- --
0FCB -- (Vacancy) -- --
0FCC -- (Vacancy) -- --
0FCD -- (Vacancy) -- --
0FCE -- (Vacancy) -- --
0FCF -- (Vacancy) -- --
Table 29.1-7 FLUTE series (6 / 8)
Address Register abbreviation Register name R/W Initial value
821
CHAPTER 29 Basic Information
0FD0 -- (Vacancy) -- --
0FD1 -- (Vacancy) -- --
0FD2 -- (Vacancy) -- --
0FD3 -- (Vacancy) -- --
0FD4 -- (Vacancy) -- --
0FD5 -- (Vacancy) -- --
0FD6 -- (Vacancy) -- --
0FD7 -- (Vacancy) -- --
0FD8 -- (Vacancy) -- --
0FD9 -- (Vacancy) -- --
0FDA -- (Vacancy) -- --
0FDB -- (Vacancy) -- --
0FDC -- (Vacancy) -- --
0FDD -- (Vacancy) -- --
0FDE -- (Vacancy) -- --
0FDF -- (Vacancy) -- --
0FE0 -- (Vacancy) -- --
0FE1 -- (Vacancy) -- --
0FE2 -- (Vacancy) -- --
0FE3 WCDR Watch counter data register R/W 00111111
0FE4
-- (Vacancy) -- --
0FE5
0FE6
0FE7
0FE8
0FE9 -- (Vacancy) -- --
0FEA CSVCR Clock supervisor control register R/W 00011100
0FEB-- (Vacancy) -- --
0FEC
0FED -- (Vacancy) -- --
0FEE ILSR Input level select register R/W -0000000
0FEF WICR Interrupt pin control register R/W 01000000
Table 29.1-7 FLUTE series (7 / 8)
Address Register abbreviation Register name R/W Initial value
822
0FF0
-- (Vacancy) -- --
0FF1
0FF2
0FF3
0FF4
0FF5
0FF6
0FF7
0FF8
0FF9
0FFA
0FFB
0FFC
0FFD
0FFE
0FFF
Table 29.1-7 FLUTE series (8 / 8)
Address Register abbreviation Register name R/W Initial value
823
CHAPTER 29 Basic Information
Table 29.1-8 PICCOLO series (1 / 8)
Address Register abbreviation Register name R/W Initial value
0000 PDR0 Port 0 data register R/W 00000000
0001 DDR0 Port 0 direction register R/W 00000000
0002 PDR1 Port 1 data register R/W 00000000
0003 DDR1 Port 1 direction register R/W 00000000
0004 -- (Vacancy) -- --
0005 WATR Oscillation stabilization wait time setting register R/W 11111111
0006 PLLC PLL control register R/W 00000000
0007 SYCC System clock control register R/W 1010x011
0008 STBC Standby control register R/W 00000000
0009 RSRR Reset cause register R xxxxxxxx
000A TBTC Timebase timer control register R/W 00000000
000B WPCR Watch prescaler control register R/W 00000000
000C WDTC Watchdog timer control register R/W 00000000
000D -- (Vacancy) -- --
000E -- (Vacancy) -- --
000F -- (Vacancy) -- --
0010 -- (Vacancy) -- --
0011 -- (Vacancy) -- --
0012 -- (Vacancy) -- --
0013 -- (Vacancy) -- --
0014 -- (Vacancy) -- --
0015 -- (Vacancy) -- --
0016 -- (Vacancy) -- --
0017 -- (Vacancy) -- --
0018 -- (Vacancy) -- --
0019 -- (Vacancy) -- --
001A -- (Vacancy) -- --
001B -- (Vacancy) -- --
001C -- (Vacancy) -- --
001D -- (Vacancy) -- --
001E -- (Vacancy) -- --
001F -- (Vacancy) -- --
0020 -- (Vacancy) -- --
824
0021 -- (Vacancy) -- --
0022 -- (Vacancy) -- --
0023 -- (Vacancy) -- --
0024 -- (Vacancy) -- --
0025 -- (Vacancy) -- --
0026 -- (Vacancy) -- --
0027 -- (Vacancy) -- --
0028 -- (Vacancy) -- --
0029 -- (Vacancy) -- --
002A PDRG Port G data register R/W 00000000
002B DDRG Port G direction register R/W 00000000
002C PUL0 Port 0 pull-up register R/W 00000000
002D PUL1 Port 1 pull-up register R/W 00000000
002E
-- (Vacancy) -- --
002F
0030
0031
0032
0033
0034
0035 PULG Port G pull-up register R/W 00000000
0036 T01CR1 Control status register 1 ch 0 for 8/16-bit compound timer 01 R/W 00000000
0037 T00CR1 Control status register 1 ch 0 for 8/16-bit compound timer 00 R/W 00000000
0038-- (Vacancy) -- --
0039
003A PC01 Control register ch0 for 8/16-bit PPG1 R/W 00000000
003B PC00 Control register ch0 for 8/16-bit PPG0 R/W 00000000
003C
-- (Vacancy) -- --
003D
003E
003F
0040
0041
0042 PCNTH0 Status control register upper ch0 for 16-bit PPG R/W 00000000
0043 PCNTL0 Status control register lower ch0 for 16-bit PPG R/W 00000000
Table 29.1-8 PICCOLO series (2 / 8)
Address Register abbreviation Register name R/W Initial value
825
CHAPTER 29 Basic Information
0044
-- (Vacancy) -- --0045
0046
0047
0048 EIC00 Control register ch0/1 for external interrupt circuit R/W 00000000
0049 EIC10 Control register ch2/3 for external interrupt circuit R/W 00000000
004A EIC20 Control register ch4/5 for external interrupt circuit R/W 00000000
004B EIC30 Control register ch6/7 for external interrupt circuit R/W 00000000
004C
-- (Vacancy) -- --004D
004E
004F
0050 SCR LIN-UART serial control register R/W 00000000
0051 SMR LIN-UART serial mode register R/W 00000000
0052 SSR LIN-UART serial status register R/W 00001000
0053 RDR/TDR LIN-UART reception/transmission data register R/W 00000000
0054 ESCR LIN-UART extended status control register R/W 00000100
0055 ECCR LIN-UART extended communication control register R/W 000000XX
0056 SMC10 UART/SIO serial mode control register 1 ch0 R/W 00000000
0057 SMC20 UART/SIO serial mode control register 2 ch0 R/W 00100000
0058 SSR0 UART/SIO serial status register ch0 R/W 00000001
0059 TDR0 UART/SIO serial output data register ch0 R/W 00000000
005A RDR0 UART/SIO serial input data register ch0 R 00000000
005B -- (Vacancy) -- --
005C -- (Vacancy) -- --
005D -- (Vacancy) -- --
005E -- (Vacancy) -- --
005F -- (Vacancy) -- --
0060 -- (Vacancy) -- --
0061 -- (Vacancy) -- --
0062 -- (Vacancy) -- --
0063 -- (Vacancy) -- --
0064 -- (Vacancy) -- --
0065 -- (Vacancy) -- --
0066 -- (Vacancy) -- --
Table 29.1-8 PICCOLO series (3 / 8)
Address Register abbreviation Register name R/W Initial value
826
0067 -- (Vacancy) -- --
0068 -- (Vacancy) -- --
0069 -- (Vacancy) -- --
006A -- (Vacancy) -- --
006B -- (Vacancy) -- --
006C ADC1 A/D control register 1 R/W 00000000
006D ADC2 A/D control register 2 R/W 00000000
006E ADDH A/D data register upper R/W 00000000
006F ADDL A/D data register lower R/W 00000000
0070 WCSR Watch counter status register R/W 00000000
0071 -- (Vacancy) -- --
0072 FSR Flash memory status register R/W 000x0000
0073 SWRE0 Flash memory sector write control register 0 R/W 00000000
0074 SWRE1 Flash memory sector write control register 1 R/W 00000000
0075 -- (Vacancy) -- --
0076 WREN Address compare enable register for wild register R/W 00000000
0077 WROR Data test setting register for wild register R/W 00000000
0078 -- * Mirror of RP -- --
0079 ILR0 Interrupt level setting register 0 R/W 11111111
007A ILR1 Interrupt level setting register 1 R/W 11111111
007B ILR2 Interrupt level setting register 2 R/W 11111111
007C ILR3 Interrupt level setting register 3 R/W 11111111
007D ILR4 Interrupt level setting register 4 R/W 11111111
007E ILR5 Interrupt level setting register 5 R/W 11111111
007F -- (Vacancy) -- --
0F80 WRARH0 Address setting register upper ch0 for wild register R/W 00000000
0F81 WRARL0 Address setting register lower ch0 for wild register R/W 00000000
0F82 WRDR0 Data setting register ch0 for wild register R/W 00000000
0F83 WRARH1 Address setting register upper ch1 for wild register R/W 00000000
0F84 WRARL1 Address setting register lower ch1 for wild register R/W 00000000
0F85 WRDR1 Data setting register ch1 for wild register R/W 00000000
0F86 WRARH2 Address setting register upper ch2 for wild register R/W 00000000
0F87 WRARL2 Address setting register lower ch2 for wild register R/W 00000000
0F88 WRDR2 Data setting register ch2 for wild register R/W 00000000
0F89 -- (Vacancy) -- --
Table 29.1-8 PICCOLO series (4 / 8)
Address Register abbreviation Register name R/W Initial value
827
CHAPTER 29 Basic Information
0F8A -- (Vacancy) -- --
0F8B -- (Vacancy) -- --
0F8C -- (Vacancy) -- --
0F8D -- (Vacancy) -- --
0F8E -- (Vacancy) -- --
0F8F -- (Vacancy) -- --
0F90 -- (Vacancy) -- --
0F91 -- (Vacancy) -- --
0F92 T01CR0 Control status register 0 ch0 for 8/16-bit compound timer 01 R/W 00000000
0F93 T00CR0 Control status register 0 ch0 for 8/16-bit compound timer 00 R/W 00000000
0F94 T01DR Data register ch0 for 8/16-bit compound timer 01 R/W 00000000
0F95 T00DR Data register ch0 for 8/16-bit compound timer 00 R/W 00000000
0F96 TMCR0 Timer mode control register ch0 for 8/16-bit compound timer 00/01 R/W 00000000
0F97
-- (Vacancy) -- --
0F98
0F99
0F9A
0F9B
0F9C PPS01 Cycle setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9D PPS00 Cycle setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0F9E PDS01 Duty setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9F PDS00 Duty setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0FA0
-- (Vacancy) -- --0FA1
0FA2
0FA3
0FA4 PPGS 8/16-bit PPG startup register R/W 00000000
0FA5 REVC 8/16-bit PPG output reverse register R/W 00000000
0FA6
-- (Vacancy) -- --0FA7
0FA8
0FA9
0FAA PDCRH0 Down counter register upper ch0 for 16-bit PPG R 00000000
0FAB PDCRL0 Down counter register lower ch0 for 16-bit PPG R 00000000
0FAC PCSRH0 Cycle setting buffer register upper ch0 for 16-bit PPG R/W 11111111
Table 29.1-8 PICCOLO series (5 / 8)
Address Register abbreviation Register name R/W Initial value
828
0FAD PCSRL0 Cycle setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FAE PDUTH0 Duty setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAF PDUTL0 Duty setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FB0
-- (Vacancy) -- --
0FB1
0FB2
0FB3
0FB4
0FB5
0FB6
0FB7
0FB8
0FB9
0FBA
0FBB
0FBC BGR1 LIN-UART baud rate generator register 1 R/W 00000000
0FBD BGR0 LIN-UART baud rate generator register 0 R/W 00000000
0FBE PSSR0 UART/SIO prescaler select register ch0 R/W 00000000
0FBF BRSR0 UART/SIO baud rate setting register ch0 R/W 00000000
0FC0
-- (Vacancy) -- --0FC1
0FC2
0FC3 AIDRL A/D input disable register lower R/W 00000000
0FC4 -- (Vacancy) -- --
0FC5 -- (Vacancy) -- --
0FC6 -- (Vacancy) -- --
0FC7 -- (Vacancy) -- --
0FC8 -- (Vacancy) -- --
0FC9 -- (Vacancy) -- --
0FCA -- (Vacancy) -- --
0FCB -- (Vacancy) -- --
0FCC -- (Vacancy) -- --
0FCD -- (Vacancy) -- --
0FCE -- (Vacancy) -- --
0FCF -- (Vacancy) -- --
Table 29.1-8 PICCOLO series (6 / 8)
Address Register abbreviation Register name R/W Initial value
829
CHAPTER 29 Basic Information
0FD0 -- (Vacancy) -- --
0FD1 -- (Vacancy) -- --
0FD2 -- (Vacancy) -- --
0FD3 -- (Vacancy) -- --
0FD4 -- (Vacancy) -- --
0FD5 -- (Vacancy) -- --
0FD6 -- (Vacancy) -- --
0FD7 -- (Vacancy) -- --
0FD8 -- (Vacancy) -- --
0FD9 -- (Vacancy) -- --
0FDA -- (Vacancy) -- --
0FDB -- (Vacancy) -- --
0FDC -- (Vacancy) -- --
0FDD -- (Vacancy) -- --
0FDE -- (Vacancy) -- --
0FDF -- (Vacancy) -- --
0FE0 -- (Vacancy) -- --
0FE1 -- (Vacancy) -- --
0FE2 -- (Vacancy) -- --
0FE3 WCDR Watch counter data register R/W 00111111
0FE4
-- (Vacancy) -- --
0FE5
0FE6
0FE7
0FE8
0FE9 -- (Vacancy) -- --
0FEA CSVCR Clock supervisor control register R/W 00011100
0FEB-- (Vacancy) -- --
0FEC
0FED -- (Vacancy) -- --
0FEE ILSR Input level select register R/W -0000000
0FEF WICR Interrupt pin control register R/W 01000000
Table 29.1-8 PICCOLO series (7 / 8)
Address Register abbreviation Register name R/W Initial value
830
0FF0
-- (Vacancy) -- --
0FF1
0FF2
0FF3
0FF4
0FF5
0FF6
0FF7
0FF8
0FF9
0FFA
0FFB
0FFC
0FFD
0FFE
0FFF
Table 29.1-8 PICCOLO series (8 / 8)
Address Register abbreviation Register name R/W Initial value
831
CHAPTER 29 Basic Information
Table 29.1-9 TUBA series (1 / 8)
Address Register abbreviation Register name R/W Initial value
0000 PDR0 Port 0 data register R/W 00000000
0001 DDR0 Port 0 direction register R/W 00000000
0002 PDR1 Port 1 data register R/W 00000000
0003 DDR1 Port 1 direction register R/W 00000000
0004 -- (Vacancy) -- --
0005 WATR Oscillation stabilization wait time setting register R/W 11111111
0006 PLLC PLL control register R/W 00000000
0007 SYCC System clock control register R/W 1010x011
0008 STBC Standby control register R/W 00000000
0009 RSRR Reset cause register R xxxxxxxx
000A TBTC Timebase timer control register R/W 00000000
000B WPCR Watch prescaler control register R/W 00000000
000C WDTC Watchdog timer control register R/W 00000000
000D -- (Vacancy) -- --
000E PDR2 Port 2 data register R/W 00000000
000F DDR2 Port 2 direction register R/W 00000000
0010 PDR3 Port 3 data register R/W 00000000
0011 DDR3 Port 3 direction register R/W 00000000
0012 PDR4 Port 4 data register R/W 00000000
0013 DDR4 Port 4 direction register R/W 00000000
0014 PDR5 Port 5 data register R/W 00000000
0015 DDR5 Port 5 direction register R/W 00000000
0016 PDR6 Port 6 data register R/W 00000000
0017 DDR6 Port 6 direction register R/W 00000000
0018 PDR7 Port 7 data register R/W 00000000
0019 DDR7 Port 7 direction register R/W 00000000
001A-- (Vacancy) -- --
001B
001C PDR9 Port 9 data register R/W 00000000
001D DDR9 Port 9 direction register R/W 00000000
001E PDRA Port A data register R/W 00000000
001F DDRA Port A direction register R/W 00000000
0020 PDRB Port B data register R/W 00000000
832
0021 DDRB Port B direction register R/W 00000000
0022 PDRC Port C data register R/W 00000000
0023 DDRC Port C direction register R/W 00000000
0024 PDRD Port D data register R/W 00000000
0025 DDRD Port D direction register R/W 00000000
0026 PDRE Port E data register R/W 00000000
0027 DDRE Port E direction register R/W 00000000
0028-- (Vacancy) -- --
0029
002A PDRG Port G data register R/W 00000000
002B DDRG Port G direction register R/W 00000000
002C -- (Vacancy) -- --
002D PUL1 Port 1 pull-up register R/W 00000000
002E PUL2 Port 2 pull-up register R/W 00000000
002F PUL3 Port 3 pull-up register R/W 00000000
0030 PUL4 Port 4 pull-up register R/W 00000000
0031 PUL5 Port 5 pull-up register R/W 00000000
0032 PUL7 Port 7 pull-up register R/W 00000000
0033-- (Vacancy) -- --
0034
0035 PULG Port G pull-up register R/W 00000000
0036 T01CR1 Control status register 1 ch 0 for 8/16-bit compound timer 01 R/W 00000000
0037 T00CR1 Control status register 1 ch 0 for 8/16-bit compound timer 00 R/W 00000000
0038 T11CR1 Control status register 1 ch 1 for 8/16-bit compound timer 11 R/W 00000000
0039 T10CR1 Control status register 1 ch 1 for 8/16-bit compound timer 10 R/W 00000000
003A PC01 Control register ch0 for 8/16-bit PPG1 R/W 00000000
003B PC00 Control register ch0 for 8/16-bit PPG0 R/W 00000000
003C PC11 Control register ch1 for 8/16-bit PPG1 R/W 00000000
003D PC10 Control register ch1 for 8/16-bit PPG0 R/W 00000000
003E TMCSRH0 Control status register upper ch0 for 16-bit reload timer R/W 00000000
003F TMCSRL0 Control status register lower ch0 for 16-bit reload timer R/W 00000000
0040-- (Vacancy) -- --
0041
0042 PCNTH0 Status control register upper ch0 for 16-bit PPG R/W 00000000
0043 PCNTL0 Status control register lower ch0 for 16-bit PPG R/W 00000000
Table 29.1-9 TUBA series (2 / 8)
Address Register abbreviation Register name R/W Initial value
833
CHAPTER 29 Basic Information
0044 PCNTH1 Status control register upper ch1 for 16-bit PPG R/W 00000000
0045 PCNTL1 Status control register lower ch1 for 16-bit PPG R/W 00000000
0046-- (Vacancy) -- --
0047
0048 EIC00 Control register ch0/1 for external interrupt circuit R/W 00000000
0049 EIC10 Control register ch2/3 for external interrupt circuit R/W 00000000
004A EIC20 Control register ch4/5 for external interrupt circuit R/W 00000000
004B EIC30 Control register ch6/7 for external interrupt circuit R/W 00000000
004C EIC01 Control register ch8/9 for external interrupt circuit R/W 00000000
004D EIC11 Control register ch10/11 for external interrupt circuit R/W 00000000
004E-- (Vacancy) -- --
004F
0050 SCR LIN-UART serial control register R/W 00000000
0051 SMR LIN-UART serial mode register R/W 00000000
0052 SSR LIN-UART serial status register R/W 00001000
0053 RDR/TDR LIN-UART reception/transmission data register R/W 00000000
0054 ESCR LIN-UART extended status control register R/W 00000100
0055 ECCR LIN-UART extended communication control register R/W 000000XX
0056 SMC10 UART/SIO serial mode control register 1 ch0 R/W 00000000
0057 SMC20 UART/SIO serial mode control register 2 ch0 R/W 00100000
0058 SSR0 UART/SIO serial status register ch0 R/W 00000001
0059 TDR0 UART/SIO serial output data register ch0 R/W 00000000
005A RDR0 UART/SIO serial input data register ch0 R 00000000
005B
-- (Vacancy) -- --
005C
005D
005E
005F
0060 IBCR00 I2C bus control register 0 ch0 R/W 00000000
0061 IBCR10 I2C bus control register 1 ch0 R/W 00000000
0062 IBSR0 I2C bus status register ch0 R 00000000
0063 IDDR0 I2C data register ch0 R/W 00000000
0064 IAAR0 I2C address register ch0 R/W 00000000
0065 ICCR0 I2C clock control register ch0 R/W 00000000
Table 29.1-9 TUBA series (3 / 8)
Address Register abbreviation Register name R/W Initial value
834
0066
-- (Vacancy) -- --
0067
0068
0069
006A
006B
006C ADC1 A/D control register 1 R/W 00000000
006D ADC2 A/D control register 2 R/W 00000000
006E ADDH A/D data register upper R/W 00000000
006F ADDL A/D data register lower R/W 00000000
0070 WCSR Watch counter status register R/W 00000000
0071 -- (Vacancy) -- --
0072 FSR Flash memory status register R/W 000x0000
0073 SWRE0 Flash memory sector write control register 0 R/W 00000000
0074 SWRE1 Flash memory sector write control register 1 R/W 00000000
0075 -- (Vacancy) -- --
0076 WREN Address compare enable register for wild register R/W 00000000
0077 WROR Data test setting register for wild register R/W 00000000
0078 -- * Mirror of RP -- --
0079 ILR0 Interrupt level setting register 0 R/W 11111111
007A ILR1 Interrupt level setting register 1 R/W 11111111
007B ILR2 Interrupt level setting register 2 R/W 11111111
007C ILR3 Interrupt level setting register 3 R/W 11111111
007D ILR4 Interrupt level setting register 4 R/W 11111111
007E ILR5 Interrupt level setting register 5 R/W 11111111
007F -- (Vacancy) -- --
0F80 WRARH0 Address setting register upper ch0 for wild register R/W 00000000
0F81 WRARL0 Address setting register lower ch0 for wild register R/W 00000000
0F82 WRDR0 Data setting register ch0 for wild register R/W 00000000
0F83 WRARH1 Address setting register upper ch1 for wild register R/W 00000000
0F84 WRARL1 Address setting register lower ch1 for wild register R/W 00000000
0F85 WRDR1 Data setting register ch1 for wild register R/W 00000000
0F86 WRARH2 Address setting register upper ch2 for wild register R/W 00000000
0F87 WRARL2 Address setting register lower ch2 for wild register R/W 00000000
0F88 WRDR2 Data setting register ch2 for wild register R/W 00000000
Table 29.1-9 TUBA series (4 / 8)
Address Register abbreviation Register name R/W Initial value
835
CHAPTER 29 Basic Information
0F89 -- (Vacancy) -- --
0F8A -- (Vacancy) -- --
0F8B -- (Vacancy) -- --
0F8C -- (Vacancy) -- --
0F8D -- (Vacancy) -- --
0F8E -- (Vacancy) -- --
0F8F -- (Vacancy) -- --
0F90 -- (Vacancy) -- --
0F91 -- (Vacancy) -- --
0F92 T01CR0 Control status register 0 ch0 for 8/16-bit compound timer 01 R/W 00000000
0F93 T00CR0 Control status register 0 ch0 for 8/16-bit compound timer 00 R/W 00000000
0F94 T01DR Data register ch0 for 8/16-bit compound timer 01 R/W 00000000
0F95 T00DR Data register ch0 for 8/16-bit compound timer 00 R/W 00000000
0F96 TMCR0 Timer mode control register ch0 for 8/16-bit compound timer 00/01 R/W 00000000
0F97 T11CR0 Control status register 0 ch1 for 8/16-bit compound timer 11 R/W 00000000
0F98 T10CR0 Control status register 0 ch1 for 8/16-bit compound timer 10 R/W 00000000
0F99 T11DR Data register ch1 for 8/16-bit compound timer 11 R/W 00000000
0F9A T10DR Data register ch1 for 8/16-bit compound timer 10 R/W 00000000
0F9B TMCR1 Timer mode control register ch1 for 8/16-bit compound timer 10/11 R/W 00000000
0F9C PPS01 Cycle setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9D PPS00 Cycle setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0F9E PDS01 Duty setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9F PDS00 Duty setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0FA0 PPS11 Cycle setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA1 PPS10 Cycle setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA2 PDS11 Duty setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA3 PDS10 Duty setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA4 PPGS 8/16-bit PPG startup register R/W 00000000
0FA5 REVC 8/16-bit PPG output reverse register R/W 00000000
0FA6 TMRH0/TMRLRH0 Timer/reload register upper ch0 for 16-bit reload timer R/W 00000000
0FA7 TMRL0/TMRLRL0 Timer/reload register lower ch0 for 16-bit reload timer R/W 00000000
0FA8-- (Vacancy) -- --
0FA9
0FAA PDCRH0 Down counter register upper ch0 for 16-bit PPG R 00000000
0FAB PDCRL0 Down counter register lower ch0 for 16-bit PPG R 00000000
Table 29.1-9 TUBA series (5 / 8)
Address Register abbreviation Register name R/W Initial value
836
0FAC PCSRH0 Cycle setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAD PCSRL0 Cycle setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FAE PDUTH0 Duty setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAF PDUTL0 Duty setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FB0 PDCRH1 Down counter register upper ch1 for 16-bit PPG R 00000000
0FB1 PDCRL1 Down counter register lower ch1 for 16-bit PPG R 00000000
0FB2 PCSRH1 Cycle setting buffer register upper ch1 for 16-bit PPG R/W 11111111
0FB3 PCSRL1 Cycle setting buffer register lower ch1 for 16-bit PPG R/W 11111111
0FB4 PDUTH1 Duty setting buffer register upper ch1 for 16-bit PPG R/W 11111111
0FB5 PDUTL1 Duty setting buffer register lower ch1 for 16-bit PPG R/W 11111111
0FB6
-- (Vacancy) -- --
0FB7
0FB8
0FB9
0FBA
0FBB
0FBC BGR1 LIN-UART baud rate generator register 1 R/W 00000000
0FBD BGR0 LIN-UART baud rate generator register 0 R/W 00000000
0FBE PSSR0 UART/SIO prescaler select register ch0 R/W 00000000
0FBF BRSR0 UART/SIO baud rate setting register ch0 R/W 00000000
0FC0-- (Vacancy) -- --
0FC1
0FC2 AIDRH A/D input disable register upper R/W 00000000
0FC3 AIDRL A/D input disable register lower R/W 00000000
0FC4 LCDCC LCDC control register R/W 00010000
0FC5 LCDCE1 LCDC enable register 1 R/W 00110000
0FC6 LCDCE2 LCDC enable register 2 R/W 00000000
0FC7 LCDCE3 LCDC enable register 3 R/W 00000000
0FC8 LCDCE4 LCDC enable register 4 R/W 00000000
0FC9 LCDCE5 LCDC enable register 5 R/W 00000000
0FCA LCDCE6 LCDC enable register 6 R/W 00000000
0FCB LCDCB1 LCDC blinking setting register 1 R/W 00000000
0FCC LCDCB2 LCDC blinking setting register 2 R/W 00000000
Table 29.1-9 TUBA series (6 / 8)
Address Register abbreviation Register name R/W Initial value
837
CHAPTER 29 Basic Information
0FCD
LCDRAM LCDC display RAM R/W 00000000
0FCE
0FCF
0FD0
0FD1
0FD2
0FD3
0FD4
0FD5
0FD6
0FD7
0FD8
0FD9
0FDA
0FDB
0FDC
0FDD
0FDE
0FDF
0FE0
0FE1 -- (Vacancy) -- --
0FE2 -- (Vacancy) -- --
0FE3 WCDR Watch counter data register R/W 00111111
0FE4
-- (Vacancy) -- --
0FE5
0FE6
0FE7
0FE8
0FE9 -- (Vacancy) -- --
0FEA CSVCR Clock supervisor control register R/W 00011100
0FEB-- (Vacancy) -- --
0FEC
0FED -- (Vacancy) -- --
0FEE ILSR Input level select register R/W -0000000
0FEF WICR Interrupt pin control register R/W 01000000
Table 29.1-9 TUBA series (7 / 8)
Address Register abbreviation Register name R/W Initial value
838
0FF0
-- (Vacancy) -- --
0FF1
0FF2
0FF3
0FF4
0FF5
0FF6
0FF7
0FF8
0FF9
0FFA
0FFB
0FFC
0FFD
0FFE
0FFF
Table 29.1-9 TUBA series (8 / 8)
Address Register abbreviation Register name R/W Initial value
839
CHAPTER 29 Basic Information
Table 29.1-10 REDERVE2 series (1 / 8)
Address Register abbreviation Register name R/W Initial value
0000 PDR0 Port 0 data register R/W 00000000
0001 DDR0 Port 0 direction register R/W 00000000
0002 PDR1 Port 1 data register R/W 00000000
0003 DDR1 Port 1 direction register R/W 00000000
0004 -- (Vacancy) -- --
0005 WATR Oscillation stabilization wait time setting register R/W 11111111
0006 PLLC PLL control register R/W 00000000
0007 SYCC System clock control register R/W 1010x011
0008 STBC Standby control register R/W 00000000
0009 RSRR Reset cause register R xxxxxxxx
000A TBTC Timebase timer control register R/W 00000000
000B WPCR Watch prescaler control register R/W 00000000
000C WDTC Watchdog timer control register R/W 00000000
000D -- (Vacancy) -- --
000E PDR2 Port 2 data register R/W 00000000
000F DDR2 Port 2 direction register R/W 00000000
0010-- (Vacancy) -- --
0011
0012 PDR4 Port 4 data register R/W 00000000
0013 DDR4 Port 4 direction register R/W 00000000
0014 PDR5 Port 5 data register R/W 00000000
0015 DDR5 Port 5 direction register R/W 00000000
0016 PDR6 Port 6 data register R/W 00000000
0017 DDR6 Port 6 direction register R/W 00000000
0018
-- (Vacancy) -- --0019
001A
001B
001C PDR9 Port 9 data register R/W 00000000
001D DDR9 Port 9 direction register R/W 00000000
001E PDRA Port A data register R/W 00000000
001F DDRA Port A direction register R/W 00000000
0020 PDRB Port B data register R/W 00000000
840
0021 DDRB Port B direction register R/W 00000000
0022 PDRC Port C data register R/W 00000000
0023 DDRC Port C direction register R/W 00000000
0024-- (Vacancy) -- --
0025
0026 PDRE Port E data register R/W 00000000
0027 DDRE Port E direction register R/W 00000000
0028-- (Vacancy) -- --
0029
002A PDRG Port G data register R/W 00000000
002B DDRG Port G direction register R/W 00000000
002C PUL0 Port 0 pull-up register R/W 00000000
002D PUL1 Port 1 pull-up register R/W 00000000
002E PUL2 Port 2 pull-up register R/W 00000000
002F -- (Vacancy) -- --
0030 PUL4 Port 4 pull-up register R/W 00000000
0031 PUL5 Port 5 pull-up register R/W 00000000
0032
-- (Vacancy) -- --0033
0034
0035 PULG Port G pull-up register R/W 00000000
0036 T01CR1 Control status register 1 ch 0 for 8/16-bit compound timer 01 R/W 00000000
0037 T00CR1 Control status register 1 ch 0 for 8/16-bit compound timer 00 R/W 00000000
0038 T11CR1 Control status register 1 ch 1 for 8/16-bit compound timer 11 R/W 00000000
0039 T10CR1 Control status register 1 ch 1 for 8/16-bit compound timer 10 R/W 00000000
003A PC01 Control register ch0 for 8/16-bit PPG1 R/W 00000000
003B PC00 Control register ch0 for 8/16-bit PPG0 R/W 00000000
003C PC11 Control register ch1 for 8/16-bit PPG1 R/W 00000000
003D PC10 Control register ch1 for 8/16-bit PPG0 R/W 00000000
003E
-- (Vacancy) -- --003F
0040
0041
0042 PCNTH0 Status control register upper ch0 for 16-bit PPG R/W 00000000
0043 PCNTL0 Status control register lower ch0 for 16-bit PPG R/W 00000000
Table 29.1-10 REDERVE2 series (2 / 8)
Address Register abbreviation Register name R/W Initial value
841
CHAPTER 29 Basic Information
0044 PCNTH1 Status control register upper ch1 for 16-bit PPG R/W 00000000
0045 PCNTL1 Status control register lower ch1 for 16-bit PPG R/W 00000000
0046-- (Vacancy) -- --
0047
0048 EIC00 Control register ch0/1 for external interrupt circuit R/W 00000000
0049 EIC10 Control register ch2/3 for external interrupt circuit R/W 00000000
004A EIC20 Control register ch4/5 for external interrupt circuit R/W 00000000
004B EIC30 Control register ch6/7 for external interrupt circuit R/W 00000000
004C EIC01 Control register ch8/9 for external interrupt circuit R/W 00000000
004D EIC11 Control register ch10/11 for external interrupt circuit R/W 00000000
004E-- (Vacancy) -- --
004F
0050 SCR LIN-UART serial control register R/W 00000000
0051 SMR LIN-UART serial mode register R/W 00000000
0052 SSR LIN-UART serial status register R/W 00001000
0053 RDR/TDR LIN-UART reception/transmission data register R/W 00000000
0054 ESCR LIN-UART extended status control register R/W 00000100
0055 ECCR LIN-UART extended communication control register R/W 000000XX
0056 SMC10 UART/SIO serial mode control register 1 ch0 R/W 00000000
0057 SMC20 UART/SIO serial mode control register 2 ch0 R/W 00100000
0058 SSR0 UART/SIO serial status register ch0 R/W 00000001
0059 TDR0 UART/SIO serial output data register ch0 R/W 00000000
005A RDR0 UART/SIO serial input data register ch0 R 00000000
005B
-- (Vacancy) -- --
005C
005D
005E
005F
0060 IBCR00 I2C bus control register 0 ch0 R/W 00000000
0061 IBCR10 I2C bus control register 1 ch0 R/W 00000000
0062 IBSR0 I2C bus status register ch0 R 00000000
0063 IDDR0 I2C data register ch0 R/W 00000000
0064 IAAR0 I2C address register ch0 R/W 00000000
0065 ICCR0 I2C clock control register ch0 R/W 00000000
Table 29.1-10 REDERVE2 series (3 / 8)
Address Register abbreviation Register name R/W Initial value
842
0066
-- (Vacancy) -- --
0067
0068
0069
006A
006B
006C ADC1 A/D control register 1 R/W 00000000
006D ADC2 A/D control register 2 R/W 00000000
006E ADDH A/D data register upper R/W 00000000
006F ADDL A/D data register lower R/W 00000000
0070 WCSR Watch counter status register R/W 00000000
0071 -- (Vacancy) -- --
0072 FSR Flash memory status register R/W 000x0000
0073 SWRE0 Flash memory sector write control register 0 R/W 00000000
0074 SWRE1 Flash memory sector write control register 1 R/W 00000000
0075 -- (Vacancy) -- --
0076 WREN Address compare enable register for wild register R/W 00000000
0077 WROR Data test setting register for wild register R/W 00000000
0078 -- * Mirror of RP -- --
0079 ILR0 Interrupt level setting register 0 R/W 11111111
007A ILR1 Interrupt level setting register 1 R/W 11111111
007B ILR2 Interrupt level setting register 2 R/W 11111111
007C ILR3 Interrupt level setting register 3 R/W 11111111
007D ILR4 Interrupt level setting register 4 R/W 11111111
007E ILR5 Interrupt level setting register 5 R/W 11111111
007F -- (Vacancy) -- --
0F80 WRARH0 Address setting register upper ch0 for wild register R/W 00000000
0F81 WRARL0 Address setting register lower ch0 for wild register R/W 00000000
0F82 WRDR0 Data setting register ch0 for wild register R/W 00000000
0F83 WRARH1 Address setting register upper ch1 for wild register R/W 00000000
0F84 WRARL1 Address setting register lower ch1 for wild register R/W 00000000
0F85 WRDR1 Data setting register ch1 for wild register R/W 00000000
0F86 WRARH2 Address setting register upper ch2 for wild register R/W 00000000
0F87 WRARL2 Address setting register lower ch2 for wild register R/W 00000000
0F88 WRDR2 Data setting register ch2 for wild register R/W 00000000
Table 29.1-10 REDERVE2 series (4 / 8)
Address Register abbreviation Register name R/W Initial value
843
CHAPTER 29 Basic Information
0F89 -- (Vacancy) -- --
0F8A -- (Vacancy) -- --
0F8B -- (Vacancy) -- --
0F8C -- (Vacancy) -- --
0F8D -- (Vacancy) -- --
0F8E -- (Vacancy) -- --
0F8F -- (Vacancy) -- --
0F90 -- (Vacancy) -- --
0F91 -- (Vacancy) -- --
0F92 T01CR0 Control status register 0 ch0 for 8/16-bit compound timer 01 R/W 00000000
0F93 T00CR0 Control status register 0 ch0 for 8/16-bit compound timer 00 R/W 00000000
0F94 T01DR Data register ch0 for 8/16-bit compound timer 01 R/W 00000000
0F95 T00DR Data register ch0 for 8/16-bit compound timer 00 R/W 00000000
0F96 TMCR0 Timer mode control register ch0 for 8/16-bit compound timer 00/01 R/W 00000000
0F97 T11CR0 Control status register 0 ch1 for 8/16-bit compound timer 11 R/W 00000000
0F98 T10CR0 Control status register 0 ch1 for 8/16-bit compound timer 10 R/W 00000000
0F99 T11DR Data register ch1 for 8/16-bit compound timer 11 R/W 00000000
0F9A T10DR Data register ch1 for 8/16-bit compound timer 10 R/W 00000000
0F9B TMCR1 Timer mode control register ch1 for 8/16-bit compound timer 10/11 R/W 00000000
0F9C PPS01 Cycle setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9D PPS00 Cycle setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0F9E PDS01 Duty setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9F PDS00 Duty setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0FA0 PPS11 Cycle setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA1 PPS10 Cycle setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA2 PDS11 Duty setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA3 PDS10 Duty setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA4 PPGS 8/16-bit PPG startup register R/W 00000000
0FA5 REVC 8/16-bit PPG output reverse register R/W 00000000
0FA6
-- (Vacancy) -- --0FA7
0FA8
0FA9
0FAA PDCRH0 Down counter register upper ch0 for 16-bit PPG R 00000000
0FAB PDCRL0 Down counter register lower ch0 for 16-bit PPG R 00000000
Table 29.1-10 REDERVE2 series (5 / 8)
Address Register abbreviation Register name R/W Initial value
844
0FAC PCSRH0 Cycle setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAD PCSRL0 Cycle setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FAE PDUTH0 Duty setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAF PDUTL0 Duty setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FB0 PDCRH1 Down counter register upper ch1 for 16-bit PPG R 00000000
0FB1 PDCRL1 Down counter register lower ch1 for 16-bit PPG R 00000000
0FB2 PCSRH1 Cycle setting buffer register upper ch1 for 16-bit PPG R/W 11111111
0FB3 PCSRL1 Cycle setting buffer register lower ch1 for 16-bit PPG R/W 11111111
0FB4 PDUTH1 Duty setting buffer register upper ch1 for 16-bit PPG R/W 11111111
0FB5 PDUTL1 Duty setting buffer register lower ch1 for 16-bit PPG R/W 11111111
0FB6
-- (Vacancy) -- --
0FB7
0FB8
0FB9
0FBA
0FBB
0FBC BGR1 LIN-UART baud rate generator register 1 R/W 00000000
0FBD BGR0 LIN-UART baud rate generator register 0 R/W 00000000
0FBE PSSR0 UART/SIO prescaler select register ch0 R/W 00000000
0FBF BRSR0 UART/SIO baud rate setting register ch0 R/W 00000000
0FC0-- (Vacancy) -- --
0FC1
0FC2 AIDRH A/D input disable register upper R/W 00000000
0FC3 AIDRL A/D input disable register lower R/W 00000000
0FC4 LCDCC LCDC control register R/W 00010000
0FC5 LCDCE1 LCDC enable register 1 R/W 00110000
0FC6 LCDCE2 LCDC enable register 2 R/W 00000000
0FC7 LCDCE3 LCDC enable register 3 R/W 00000000
0FC8 LCDCE4 LCDC enable register 4 R/W 00000000
0FC9 LCDCE5 LCDC enable register 5 R/W 00000000
0FCA -- (Vacancy) -- --
0FCB LCDCB1 LCDC blinking setting register 1 R/W 00000000
0FCC LCDCB2 LCDC blinking setting register 2 R/W 00000000
Table 29.1-10 REDERVE2 series (6 / 8)
Address Register abbreviation Register name R/W Initial value
845
CHAPTER 29 Basic Information
0FCD
LCDRAM LCDC display RAM R/W 00000000
0FCE
0FCF
0FD0
0FD1
0FD2
0FD3
0FD4
0FD5
0FD6
0FD7
0FD8
0FD9
0FDA
0FDB
0FDC
0FDD -- (Vacancy) -- --
0FDE -- (Vacancy) -- --
0FDF -- (Vacancy) -- --
0FE0 -- (Vacancy) -- --
0FE1 -- (Vacancy) -- --
0FE2 -- (Vacancy) -- --
0FE3 WCDR Watch counter data register R/W 00111111
0FE4
-- (Vacancy) -- --
0FE5
0FE6
0FE7
0FE8
0FE9 -- (Vacancy) -- --
0FEA -- Clock supervisor control register -- --
0FEB-- (Vacancy) -- --
0FEC
0FED -- (Vacancy) -- --
0FEE ILSR Input level select register R/W -0000000
0FEF WICR Interrupt pin control register R/W 01000000
Table 29.1-10 REDERVE2 series (7 / 8)
Address Register abbreviation Register name R/W Initial value
846
0FF0
-- (Vacancy) -- --
0FF1
0FF2
0FF3
0FF4
0FF5
0FF6
0FF7
0FF8
0FF9
0FFA
0FFB
0FFC
0FFD
0FFE
0FFF
Table 29.1-10 REDERVE2 series (8 / 8)
Address Register abbreviation Register name R/W Initial value
847
CHAPTER 29 Basic Information
Table 29.1-11 TROMBONE series (1 / 8)
Address Register abbreviation Register name R/W Initial value
0000 PDR0 Port 0 data register R/W 00000000
0001 DDR0 Port 0 direction register R/W 00000000
0002 PDR1 Port 1 data register R/W 00000000
0003 DDR1 Port 1 direction register R/W 00000000
0004 -- (Vacancy) -- --
0005 WATR Oscillation stabilization wait time setting register R/W 11111111
0006 PLLC PLL control register R/W 00000000
0007 SYCC System clock control register R/W 1010x011
0008 STBC Standby control register R/W 00000000
0009 RSRR Reset cause register R xxxxxxxx
000A TBTC Timebase timer control register R/W 00000000
000B WPCR Watch prescaler control register R/W 00000000
000C WDTC Watchdog timer control register R/W 00000000
000D -- (Vacancy) -- --
000E PDR2 Port 2 data register R/W 00000000
000F DDR2 Port 2 direction register R/W 00000000
0010
-- (Vacancy) -- --
0011
0012
0013
0014
0015
0016 PDR6 Port 6 data register R/W 00000000
0017 DDR6 Port 6 direction register R/W 00000000
0018
-- (Vacancy) -- --0019
001A
001B
001C PDR9 Port 9 data register R/W 00000000
001D DDR9 Port 9 direction register R/W 00000000
001E PDRA Port A data register R/W 00000000
001F DDRA Port A direction register R/W 00000000
0020 PDRB Port B data register R/W 00000000
848
0021 DDRB Port B direction register R/W 00000000
0022 PDRC Port C data register R/W 00000000
0023 DDRC Port C direction register R/W 00000000
0024
-- (Vacancy) -- --
0025
0026
0027
0028
0029
002A PDRG Port G data register R/W 00000000
002B DDRG Port G direction register R/W 00000000
002C -- (Vacancy) -- --
002D PUL1 Port 1 pull-up register R/W 00000000
002E PUL2 Port 2 pull-up register R/W 00000000
002F
-- (Vacancy) -- --
0030
0031
0032
0033
0034
0035 PULG Port G pull-up register R/W 00000000
0036 T01CR1 Control status register 1 ch 0 for 8/16-bit compound timer 01 R/W 00000000
0037 T00CR1 Control status register 1 ch 0 for 8/16-bit compound timer 00 R/W 00000000
0038 T11CR1 Control status register 1 ch 1 for 8/16-bit compound timer 11 R/W 00000000
0039 T10CR1 Control status register 1 ch 1 for 8/16-bit compound timer 10 R/W 00000000
003A PC01 Control register ch0 for 8/16-bit PPG1 R/W 00000000
003B PC00 Control register ch0 for 8/16-bit PPG0 R/W 00000000
003C PC11 Control register ch1 for 8/16-bit PPG1 R/W 00000000
003D PC10 Control register ch1 for 8/16-bit PPG0 R/W 00000000
003E
-- (Vacancy) -- --003F
0040
0041
0042 PCNTH0 Status control register upper ch0 for 16-bit PPG R/W 00000000
0043 PCNTL0 Status control register lower ch0 for 16-bit PPG R/W 00000000
Table 29.1-11 TROMBONE series (2 / 8)
Address Register abbreviation Register name R/W Initial value
849
CHAPTER 29 Basic Information
0044
-- (Vacancy) -- --0045
0046
0047
0048 EIC00 Control register ch0/1 for external interrupt circuit R/W 00000000
0049 EIC10 Control register ch2/3 for external interrupt circuit R/W 00000000
004A EIC20 Control register ch4/5 for external interrupt circuit R/W 00000000
004B EIC30 Control register ch6/7 for external interrupt circuit R/W 00000000
004C
-- (Vacancy) -- --004D
004E
004F
0050 SCR LIN-UART serial control register R/W 00000000
0051 SMR LIN-UART serial mode register R/W 00000000
0052 SSR LIN-UART serial status register R/W 00001000
0053 RDR/TDR LIN-UART reception/transmission data register R/W 00000000
0054 ESCR LIN-UART extended status control register R/W 00000100
0055 ECCR LIN-UART extended communication control register R/W 000000XX
0056 SMC10 UART/SIO serial mode control register 1 ch0 R/W 00000000
0057 SMC20 UART/SIO serial mode control register 2 ch0 R/W 00100000
0058 SSR0 UART/SIO serial status register ch0 R/W 00000001
0059 TDR0 UART/SIO serial output data register ch0 R/W 00000000
005A RDR0 UART/SIO serial input data register ch0 R 00000000
005B
-- (Vacancy) -- --
005C
005D
005E
005F
0060 IBCR00 I2C bus control register 0 ch0 R/W 00000000
0061 IBCR10 I2C bus control register 1 ch0 R/W 00000000
0062 IBSR0 I2C bus status register ch0 R 00000000
0063 IDDR0 I2C data register ch0 R/W 00000000
0064 IAAR0 I2C address register ch0 R/W 00000000
0065 ICCR0 I2C clock control register ch0 R/W 00000000
Table 29.1-11 TROMBONE series (3 / 8)
Address Register abbreviation Register name R/W Initial value
850
0066
-- (Vacancy) -- --
0667
0068
0069
006A
006B
006C ADC1 A/D control register 1 R/W 00000000
006D ADC2 A/D control register 2 R/W 00000000
006E ADDH A/D data register upper R/W 00000000
006F ADDL A/D data register lower R/W 00000000
0070 WCSR Watch counter status register R/W 00000000
0071 -- (Vacancy) -- --
0072 FSR Flash memory status register R/W 000x0000
0073 SWRE0 Flash memory sector write control register 0 R/W 00000000
0074 SWRE1 Flash memory sector write control register 1 R/W 00000000
0075 -- (Vacancy) -- --
0076 WREN Address compare enable register for wild register R/W 00000000
0077 WROR Data test setting register for wild register R/W 00000000
0078 -- * Mirror of RP -- --
0079 ILR0 Interrupt level setting register 0 R/W 11111111
007A ILR1 Interrupt level setting register 1 R/W 11111111
007B ILR2 Interrupt level setting register 2 R/W 11111111
007C ILR3 Interrupt level setting register 3 R/W 11111111
007D ILR4 Interrupt level setting register 4 R/W 11111111
007E ILR5 Interrupt level setting register 5 R/W 11111111
007F -- (Vacancy) -- --
0F80 WRARH0 Address setting register upper ch0 for wild register R/W 00000000
0F81 WRARL0 Address setting register lower ch0 for wild register R/W 00000000
0F82 WRDR0 Data setting register ch0 for wild register R/W 00000000
0F83 WRARH1 Address setting register upper ch1 for wild register R/W 00000000
0F84 WRARL1 Address setting register lower ch1 for wild register R/W 00000000
0F85 WRDR1 Data setting register ch1 for wild register R/W 00000000
0F86 WRARH2 Address setting register upper ch2 for wild register R/W 00000000
0F87 WRARL2 Address setting register lower ch2 for wild register R/W 00000000
0F88 WRDR2 Data setting register ch2 for wild register R/W 00000000
Table 29.1-11 TROMBONE series (4 / 8)
Address Register abbreviation Register name R/W Initial value
851
CHAPTER 29 Basic Information
0F89 -- (Vacancy) -- --
0F8A -- (Vacancy) -- --
0F8B -- (Vacancy) -- --
0F8C -- (Vacancy) -- --
0F8D -- (Vacancy) -- --
0F8E -- (Vacancy) -- --
0F8F -- (Vacancy) -- --
0F90 -- (Vacancy) -- --
0F91 -- (Vacancy) -- --
0F92 T01CR0 Control status register 0 ch0 for 8/16-bit compound timer 01 R/W 00000000
0F93 T00CR0 Control status register 0 ch0 for 8/16-bit compound timer 00 R/W 00000000
0F94 T01DR Data register ch0 for 8/16-bit compound timer 01 R/W 00000000
0F95 T00DR Data register ch0 for 8/16-bit compound timer 00 R/W 00000000
0F96 TMCR0 Timer mode control register ch0 for 8/16-bit compound timer 00/01 R/W 00000000
0F97 T11CR0 Control status register 0 ch1 for 8/16-bit compound timer 11 R/W 00000000
0F98 T10CR0 Control status register 0 ch1 for 8/16-bit compound timer 10 R/W 00000000
0F99 T11DR Data register ch1 for 8/16-bit compound timer 11 R/W 00000000
0F9A T10DR Data register ch1 for 8/16-bit compound timer 10 R/W 00000000
0F9B TMCR1 Timer mode control register ch1 for 8/16-bit compound timer 10/11 R/W 00000000
0F9C PPS01 Cycle setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9D PPS00 Cycle setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0F9E PDS01 Duty setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9F PDS00 Duty setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0FA0 PPS11 Cycle setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA1 PPS10 Cycle setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA2 PDS11 Duty setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA3 PDS10 Duty setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA4 PPGS 8/16-bit PPG startup register R/W 00000000
0FA5 REVC 8/16-bit PPG output reverse register R/W 00000000
0FA6
-- (Vacancy) -- --0FA7
0FA8
0FA9
0FAA PDCRH0 Down counter register upper ch0 for 16-bit PPG R 00000000
0FAB PDCRL0 Down counter register lower ch0 for 16-bit PPG R 00000000
Table 29.1-11 TROMBONE series (5 / 8)
Address Register abbreviation Register name R/W Initial value
852
0FAC PCSRH0 Cycle setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAD PCSRL0 Cycle setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FAE PDUTH0 Duty setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAF PDUTL0 Duty setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FB0
-- (Vacancy) -- --
0FB1
0FB2
0FB3
0FB4
0FB5
0FB6
0FB7
0FB8
0FB9
0FBA
0FBB
0FBC BGR1 LIN-UART baud rate generator register 1 R/W 00000000
0FBD BGR0 LIN-UART baud rate generator register 0 R/W 00000000
0FBE PSSR0 UART/SIO prescaler select register ch0 R/W 00000000
0FBF BRSR0 UART/SIO baud rate setting register ch0 R/W 00000000
0FC0
-- (Vacancy) -- --0FC1
0FC2
0FC3 AIDRL A/D input disable register lower R/W 00000000
0FC4 LCDCC LCDC control register R/W 00010000
0FC5 LCDCE1 LCDC enable register 1 R/W 00110000
0FC6 LCDCE2 LCDC enable register 2 R/W 00000000
0FC7 LCDCE3 LCDC enable register 3 R/W 00000000
0FC8 LCDCE4 LCDC enable register 4 R/W 00000000
0FC9 LCDCE5 LCDC enable register 5 R/W 00000000
0FCA -- (Vacancy) -- --
0FCB LCDCB1 LCDC blinking setting register 1 R/W 00000000
0FCC LCDCB2 LCDC blinking setting register 2 R/W 00000000
Table 29.1-11 TROMBONE series (6 / 8)
Address Register abbreviation Register name R/W Initial value
853
CHAPTER 29 Basic Information
0FCD
LCDRAM LCDC display RAM R/W 00000000
0FCE
0FCF
0FD0
0FD1
0FD2
0FD3
0FD4
0FD5
0FD6
0FD7
0FD8
0FD9
0FDA
0FDB
0FDC
0FDD -- (Vacancy) -- --
0FDE -- (Vacancy) -- --
0FDF -- (Vacancy) -- --
0FE0 -- (Vacancy) -- --
0FE1 -- (Vacancy) -- --
0FE2 -- (Vacancy) -- --
0FE3 WCDR Watch counter data register R/W 00111111
0FE4
-- (Vacancy) -- --
0FE5
0FE6
0FE7
0FE8
0FE9 -- (Vacancy) -- --
0FEA CSVCR Clock supervisor control register R/W 00011100
0FEB-- (Vacancy) -- --
0FEC
0FED -- (Vacancy) -- --
0FEE ILSR Input level select register R/W -0000000
0FEF WICR Interrupt pin control register R/W 01000000
Table 29.1-11 TROMBONE series (7 / 8)
Address Register abbreviation Register name R/W Initial value
854
0FF0
-- (Vacancy) -- --
0FF1
0FF2
0FF3
0FF4
0FF5
0FF6
0FF7
0FF8
0FF9
0FFA
0FFB
0FFC
0FFD
0FFE
0FFF
Table 29.1-11 TROMBONE series (8 / 8)
Address Register abbreviation Register name R/W Initial value
855
CHAPTER 29 Basic Information
Table 29.1-12 TRUMPET series (1 / 8)
Address Register abbreviation Register name R/W Initial value
0000 PDR0 Port 0 data register R/W 00000000
0001 DDR0 Port 0 direction register R/W 00000000
0002 PDR1 Port 1 data register R/W 00000000
0003 DDR1 Port 1 direction register R/W 00000000
0004 -- (Vacancy) -- --
0005 WATR Oscillation stabilization wait time setting register R/W 11111111
0006 PLLC PLL control register R/W 00000000
0007 SYCC System clock control register R/W 1010x011
0008 STBC Standby control register R/W 00000000
0009 RSRR Reset cause register R xxxxxxxx
000A TBTC Timebase timer control register R/W 00000000
000B WPCR Watch prescaler control register R/W 00000000
000C WDTC Watchdog timer control register R/W 00000000
000D
-- (Vacancy) -- --
000E
000F
0010
0011
0012
0013
0014
0015
0016 PDR6 Port 6 data register R/W 00000000
0017 DDR6 Port 6 direction register R/W 00000000
0018
-- (Vacancy) -- --0019
001A
001B
001C PDR9 Port 9 data register R/W 00000000
001D DDR9 Port 9 direction register R/W 00000000
001E PDRA Port A data register R/W 00000000
001F DDRA Port A direction register R/W 00000000
0020 PDRB Port B data register R/W 00000000
856
0021 DDRB Port B direction register R/W 00000000
0022
-- (Vacancy) -- --
0023
0024
0025
0026
0027
0028
0029
002A PDRG Port G data register R/W 00000000
002B DDRG Port G direction register R/W 00000000
002C PUL0 Port 0 pull-up register R/W 00000000
002D PUL1 Port 1 pull-up register R/W 00000000
002E
-- (Vacancy) -- --
002F
0030
0031
0032
0033
0034
0035 PULG Port G pull-up register R/W 00000000
0036 T01CR1 Control status register 1 ch 0 for 8/16-bit compound timer 01 R/W 00000000
0037 T00CR1 Control status register 1 ch 0 for 8/16-bit compound timer 00 R/W 00000000
0038 T11CR1 Control status register 1 ch 1 for 8/16-bit compound timer 11 R/W 00000000
0039 T10CR1 Control status register 1 ch 1 for 8/16-bit compound timer 10 R/W 00000000
003A PC01 Control register ch0 for 8/16-bit PPG1 R/W 00000000
003B PC00 Control register ch0 for 8/16-bit PPG0 R/W 00000000
003C PC11 Control register ch1 for 8/16-bit PPG1 R/W 00000000
003D PC10 Control register ch1 for 8/16-bit PPG0 R/W 00000000
003E
-- (Vacancy) -- --003F
0040
0041
0042 PCNTH0 Status control register upper ch0 for 16-bit PPG R/W 00000000
0043 PCNTL0 Status control register lower ch0 for 16-bit PPG R/W 00000000
Table 29.1-12 TRUMPET series (2 / 8)
Address Register abbreviation Register name R/W Initial value
857
CHAPTER 29 Basic Information
0044
-- (Vacancy) -- --0045
0046
0047
0048 EIC00 Control register ch0/1 for external interrupt circuit R/W 00000000
0049 EIC10 Control register ch2/3 for external interrupt circuit R/W 00000000
004A EIC20 Control register ch4/5 for external interrupt circuit R/W 00000000
004B EIC30 Control register ch6/7 for external interrupt circuit R/W 00000000
004C
-- (Vacancy) -- --004D
004E
004F
0050 SCR LIN-UART serial control register R/W 00000000
0051 SMR LIN-UART serial mode register R/W 00000000
0052 SSR LIN-UART serial status register R/W 00001000
0053 RDR/TDR LIN-UART reception/transmission data register R/W 00000000
0054 ESCR LIN-UART extended status control register R/W 00000100
0055 ECCR LIN-UART extended communication control register R/W 000000XX
0056 SMC10 UART/SIO serial mode control register 1 ch0 R/W 00000000
0057 SMC20 UART/SIO serial mode control register 2 ch0 R/W 00100000
0058 SSR0 UART/SIO serial status register ch0 R/W 00000001
0059 TDR0 UART/SIO serial output data register ch0 R/W 00000000
005A RDR0 UART/SIO serial input data register ch0 R 00000000
005B -- (Vacancy) -- --
005C -- (Vacancy) -- --
005D -- (Vacancy) -- --
005E -- (Vacancy) -- --
005F -- (Vacancy) -- --
0060 -- (Vacancy) -- --
0061 -- (Vacancy) -- --
0062 -- (Vacancy) -- --
0063 -- (Vacancy) -- --
0064 -- (Vacancy) -- --
0065 -- (Vacancy) -- --
0066 -- (Vacancy) -- --
Table 29.1-12 TRUMPET series (3 / 8)
Address Register abbreviation Register name R/W Initial value
858
0067 -- (Vacancy) -- --
0068 -- (Vacancy) -- --
0069 -- (Vacancy) -- --
006A -- (Vacancy) -- --
006B -- (Vacancy) -- --
006C ADC1 A/D control register 1 R/W 00000000
006D ADC2 A/D control register 2 R/W 00000000
006E ADDH A/D data register upper R/W 00000000
006F ADDL A/D data register lower R/W 00000000
0070 WCSR Watch counter status register R/W 00000000
0071 -- (Vacancy) -- --
0072 FSR Flash memory status register R/W 000x0000
0073 SWRE0 Flash memory sector write control register 0 R/W 00000000
0074 SWRE1 Flash memory sector write control register 1 R/W 00000000
0075 -- (Vacancy) -- --
0076 WREN Address compare enable register for wild register R/W 00000000
0077 WROR Data test setting register for wild register R/W 00000000
0078 -- * Mirror of RP -- --
0079 ILR0 Interrupt level setting register 0 R/W 11111111
007A ILR1 Interrupt level setting register 1 R/W 11111111
007B ILR2 Interrupt level setting register 2 R/W 11111111
007C ILR3 Interrupt level setting register 3 R/W 11111111
007D ILR4 Interrupt level setting register 4 R/W 11111111
007E ILR5 Interrupt level setting register 5 R/W 11111111
007F -- (Vacancy) -- --
0F80 WRARH0 Address setting register upper ch0 for wild register R/W 00000000
0F81 WRARL0 Address setting register lower ch0 for wild register R/W 00000000
0F82 WRDR0 Data setting register ch0 for wild register R/W 00000000
0F83 WRARH1 Address setting register upper ch1 for wild register R/W 00000000
0F84 WRARL1 Address setting register lower ch1 for wild register R/W 00000000
0F85 WRDR1 Data setting register ch1 for wild register R/W 00000000
0F86 WRARH2 Address setting register upper ch2 for wild register R/W 00000000
0F87 WRARL2 Address setting register lower ch2 for wild register R/W 00000000
0F88 WRDR2 Data setting register ch2 for wild register R/W 00000000
0F89 -- (Vacancy) -- --
Table 29.1-12 TRUMPET series (4 / 8)
Address Register abbreviation Register name R/W Initial value
859
CHAPTER 29 Basic Information
0F8A -- (Vacancy) -- --
0F8B -- (Vacancy) -- --
0F8C -- (Vacancy) -- --
0F8D -- (Vacancy) -- --
0F8E -- (Vacancy) -- --
0F8F -- (Vacancy) -- --
0F90 -- (Vacancy) -- --
0F91 -- (Vacancy) -- --
0F92 T01CR0 Control status register 0 ch0 for 8/16-bit compound timer 01 R/W 00000000
0F93 T00CR0 Control status register 0 ch0 for 8/16-bit compound timer 00 R/W 00000000
0F94 T01DR Data register ch0 for 8/16-bit compound timer 01 R/W 00000000
0F95 T00DR Data register ch0 for 8/16-bit compound timer 00 R/W 00000000
0F96 TMCR0 Timer mode control register ch0 for 8/16-bit compound timer 00/01 R/W 00000000
0F97 T11CR0 Control status register 0 ch1 for 8/16-bit compound timer 11 R/W 00000000
0F98 T10CR0 Control status register 0 ch1 for 8/16-bit compound timer 10 R/W 00000000
0F99 T11DR Data register ch1 for 8/16-bit compound timer 11 R/W 00000000
0F9A T10DR Data register ch1 for 8/16-bit compound timer 10 R/W 00000000
0F9B TMCR1 Timer mode control register ch1 for 8/16-bit compound timer 10/11 R/W 00000000
0F9C PPS01 Cycle setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9D PPS00 Cycle setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0F9E PDS01 Duty setting buffer register ch0 for 8/16-bit PPG1 R/W 11111111
0F9F PDS00 Duty setting buffer register ch0 for 8/16-bit PPG0 R/W 11111111
0FA0 PPS11 Cycle setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA1 PPS10 Cycle setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA2 PDS11 Duty setting buffer register ch1 for 8/16-bit PPG1 R/W 11111111
0FA3 PDS10 Duty setting buffer register ch1 for 8/16-bit PPG0 R/W 11111111
0FA4 PPGS 8/16-bit PPG startup register R/W 00000000
0FA5 REVC 8/16-bit PPG output reverse register R/W 00000000
0FA6
-- (Vacancy) -- --0FA7
0FA8
0FA9
0FAA PDCRH0 Down counter register upper ch0 for 16-bit PPG R 00000000
0FAB PDCRL0 Down counter register lower ch0 for 16-bit PPG R 00000000
0FAC PCSRH0 Cycle setting buffer register upper ch0 for 16-bit PPG R/W 11111111
Table 29.1-12 TRUMPET series (5 / 8)
Address Register abbreviation Register name R/W Initial value
860
0FAD PCSRL0 Cycle setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FAE PDUTH0 Duty setting buffer register upper ch0 for 16-bit PPG R/W 11111111
0FAF PDUTL0 Duty setting buffer register lower ch0 for 16-bit PPG R/W 11111111
0FB0
-- (Vacancy) -- --
0FB1
0FB2
0FB3
0FB4
0FB5
0FB6
0FB7
0FB8
0FB9
0FBA
0FBB
0FBC BGR1 LIN-UART baud rate generator register 1 R/W 00000000
0FBD BGR0 LIN-UART baud rate generator register 0 R/W 00000000
0FBE PSSR0 UART/SIO prescaler select register ch0 R/W 00000000
0FBF BRSR0 UART/SIO baud rate setting register ch0 R/W 00000000
0FC0
-- (Vacancy) -- --0FC1
0FC2
0FC3 AIDRL A/D input disable register lower R/W 00000000
0FC4 LCDCC LCDC control register R/W 00010000
0FC5 LCDCE1 LCDC enable register 1 R/W 00110000
0FC6 LCDCE2 LCDC enable register 2 R/W 00000000
0FC7 LCDCE3 LCDC enable register 3 R/W 00000000
0FC8 -- (Vacancy) -- --
0FC9 -- (Vacancy) -- --
0FCA -- (Vacancy) -- --
0FCB LCDCB1 LCDC blinking setting register 1 R/W 00000000
0FCC LCDCB2 LCDC blinking setting register 2 R/W 00000000
Table 29.1-12 TRUMPET series (6 / 8)
Address Register abbreviation Register name R/W Initial value
861
CHAPTER 29 Basic Information
0FCD
LCDRAM LCDC display RAM R/W 00000000
0FCE
0FCF
0FD0
0FD1
0FD2
0FD3
0FD4
0FD5 -- (Vacancy) -- --
0FD6 -- (Vacancy) -- --
0FD7 -- (Vacancy) -- --
0FD8 -- (Vacancy) -- --
0FD9 -- (Vacancy) -- --
0FDA -- (Vacancy) -- --
0FDB -- (Vacancy) -- --
0FDC -- (Vacancy) -- --
0FDD -- (Vacancy) -- --
0FDE -- (Vacancy) -- --
0FDF -- (Vacancy) -- --
0FE0 -- (Vacancy) -- --
0FE1 -- (Vacancy) -- --
0FE2 -- (Vacancy) -- --
0FE3 WCDR Watch counter data register R/W 00111111
0FE4
-- (Vacancy) -- --
0FE5
0FE6
0FE7
0FE8
0FE9 -- (Vacancy) -- --
0FEA CSVCR Clock supervisor control register R/W 00011100
0FEB-- (Vacancy) -- --
0FEC
0FED -- (Vacancy) -- --
0FEE ILSR Input level select register R/W -0000000
0FEF WICR Interrupt pin control register R/W 01000000
Table 29.1-12 TRUMPET series (7 / 8)
Address Register abbreviation Register name R/W Initial value
862
0FF0
-- (Vacancy) -- --
0FF1
0FF2
0FF3
0FF4
0FF5
0FF6
0FF7
0FF8
0FF9
0FFA
0FFB
0FFC
0FFD
0FFE
0FFF
Table 29.1-12 TRUMPET series (8 / 8)
Address Register abbreviation Register name R/W Initial value
863
CHAPTER 29 Basic Information
29.2 Table of Interrupt Causes
This section describes the table of interrupt causes used in this series.
Table of interrupt causesIn this series, the resource that can be used by each terminal mode is different, therefore the interruption
cause table divides.
Refer to Chapter 3 "CPU" for interrupt operation.
864
Table 29.2-1 MB95FV100 (1 / 2)
Interrupt causesInterrupt request number
Address of vector table Bit name of interrupt level
setting register
The same level priority level
(Concurrence)Upper Lower
External interrupt ch0IRQ0 FFFAH FFFBH L00 [1:0]
High
External interrupt ch4
External interrupt ch1IRQ1 FFF8H FFF9H L01 [1:0]
External interrupt ch5
External interrupt ch2IRQ2 FFF6H FFF7H L02 [1:0]
External interrupt ch6
External interrupt ch3IRQ3 FFF4H FFF5H L03 [1:0]
External interrupt ch7
UART/SIO ch0 IRQ4 FFF2H FFF3H L04 [1:0]
8/16-bit timer ch0 (lower) IRQ5 FFF0H FFF1H L05 [1:0]
8/16-bit timer ch0 (upper) IRQ6 FFEEH FFEFH L06 [1:0]
LIN-UART (reception) IRQ7 FFECH FFEDH L07 [1:0]
LIN-UART (transmission) IRQ8 FFEAH FFEBH L08 [1:0]
8/16-bit PPG ch1 (lower)IRQ9 FFE8H FFE9H L09 [1:0]
UART/SIO ch1
8/16-bit PPG ch1 (upper)IRQ10 FFE6H FFE7H L10 [1:0]
I2C ch1
16-bit reload timer ch0IRQ11 FFE4H FFE5H L11 [1:0]
Custom ch0
8/16-bit PPG ch0 (upper) IRQ12 FFE2H FFE3H L12 [1:0]
8/16-bit PPG ch0 (lower) IRQ13 FFE0H FFE1H L13 [1:0]
8/16-bit timer ch1 (upper) IRQ14 FFDEH FFDFH L14 [1:0]
16-bit PPG ch0IRQ15 FFDCH FFDDH L15 [1:0]
16-bit PPG ch2
16-bit reload timer ch1IRQ16 FFDAH FFDBH L16 [1:0]
I2C ch0
16-bit PPG ch1 IRQ17 FFD8H FFD9H L17 [1:0]
10-bit A/D IRQ18 FFD6H FFD7H L18 [1:0]
Timebase timer IRQ19 FFD4H FFD5H L19 [1:0]
Watch timer/counter IRQ20 FFD2H FFD3H L20 [1:0]
865
CHAPTER 29 Basic Information
External interrupt ch8
IRQ21 FFD0H FFD1H L21 [1:0]External interrupt ch9
External interrupt ch10
External interrupt ch11
8/16-bit timer ch1 (lower)
IRQ22 FFCEH FFCFH L22 [1:0]
External interrupt ch12
External interrupt ch13
External interrupt ch14
External interrupt ch15
FLASHIRQ23 FFCCH FFCDH L23 [1:0]
Custom ch1 Low
Table 29.2-1 MB95FV100 (2 / 2)
Interrupt causesInterrupt request number
Address of vector table Bit name of interrupt level
setting register
The same level priority level
(Concurrence)Upper Lower
866
Table 29.2-2 SAXOPHONE,RESERVE1 series (1 / 2)
Interrupt causesInterrupt request number
Address of vector table Bit name of interrupt level
setting register
The same level priority level
(Concurrence)Upper Lower
External interrupt ch0IRQ0 FFFAH FFFBH L00 [1:0]
High
External interrupt ch4
External interrupt ch1IRQ1 FFF8H FFF9H L01 [1:0]
External interrupt ch5
External interrupt ch2IRQ2 FFF6H FFF7H L02 [1:0]
External interrupt ch6
External interrupt ch3IRQ3 FFF4H FFF5H L03 [1:0]
External interrupt ch7
UART/SIO ch0 IRQ4 FFF2H FFF3H L04 [1:0]
8/16-bit timer ch0 (lower) IRQ5 FFF0H FFF1H L05 [1:0]
8/16-bit timer ch0 (upper) IRQ6 FFEEH FFEFH L06 [1:0]
LIN-UART (reception) IRQ7 FFECH FFEDH L07 [1:0]
LIN-UART (transmission) IRQ8 FFEAH FFEBH L08 [1:0]
8/16-bit PPG ch1 (lower)IRQ9 FFE8H FFE9H L09 [1:0]
UART/SIO ch1
8/16-bit PPG ch1 (upper)IRQ10 FFE6H FFE7H L10 [1:0]
I2C ch1
16-bit reload timer ch0IRQ11 FFE4H FFE5H L11 [1:0]
Custom ch0
8/16-bit PPG ch0 (upper) IRQ12 FFE2H FFE3H L12 [1:0]
8/16-bit PPG ch0 (lower) IRQ13 FFE0H FFE1H L13 [1:0]
8/16-bit timer ch1 (upper) IRQ14 FFDEH FFDFH L14 [1:0]
16-bit PPG ch0IRQ15 FFDCH FFDDH L15 [1:0]
16-bit PPG ch2
16-bit reload timer ch1IRQ16 FFDAH FFDBH L16 [1:0]
I2C ch0
16-bit PPG ch1 IRQ17 FFD8H FFD9H L17 [1:0]
10-bit A/D IRQ18 FFD6H FFD7H L18 [1:0]
Timebase timer IRQ19 FFD4H FFD5H L19 [1:0]
Watch timer/counter IRQ20 FFD2H FFD3H L20 [1:0]
External interrupt ch8
IRQ21 FFD0H FFD1H L21 [1:0]External interrupt ch9
External interrupt ch10
External interrupt ch11 Low
867
CHAPTER 29 Basic Information
8/16-bit timer ch1 (lower)
IRQ22 FFCEH FFCFH L22 [1:0]
High
External interrupt ch12
External interrupt ch13
External interrupt ch14
External interrupt ch15
FLASH IRQ23 FFCCH FFCDH L23 [1:0] Low
Table 29.2-2 SAXOPHONE,RESERVE1 series (2 / 2)
Interrupt causesInterrupt request number
Address of vector table Bit name of interrupt level
setting register
The same level priority level
(Concurrence)Upper Lower
868
Table 29.2-3 TUBA,BASSOON series
Interrupt causesInterrupt request number
Address of vector table
Bit name of interrupt level
setting register
The same level priority
level (Concurrence)Upper Lower
External interrupt ch0IRQ0 FFFAH FFFBH L00 [1:0]
High
External interrupt ch4
External interrupt ch1IRQ1 FFF8H FFF9H L01 [1:0]
External interrupt ch5
External interrupt ch2IRQ2 FFF6H FFF7H L02 [1:0]
External interrupt ch6
External interrupt ch3IRQ3 FFF4H FFF5H L03 [1:0]
External interrupt ch7
UART/SIO ch0 IRQ4 FFF2H FFF3H L04 [1:0]
8/16-bit timer ch0 (lower) IRQ5 FFF0H FFF1H L05 [1:0]
8/16-bit timer ch0 (upper) IRQ6 FFEEH FFEFH L06 [1:0]
LIN-UART (reception) IRQ7 FFECH FFEDH L07 [1:0]
LIN-UART (transmission) IRQ8 FFEAH FFEBH L08 [1:0]
8/16-bit PPG ch1 (lower) IRQ9 FFE8H FFE9H L09 [1:0]
8/16-bit PPG ch1 (upper) IRQ10 FFE6H FFE7H L10 [1:0]
16-bit reload timer ch0 IRQ11 FFE4H FFE5H L11 [1:0]
8/16-bit PPG ch0 (upper) IRQ12 FFE2H FFE3H L12 [1:0]
8/16-bit PPG ch0 (lower) IRQ13 FFE0H FFE1H L13 [1:0]
8/16-bit timer ch1 (upper) IRQ14 FFDEH FFDFH L14 [1:0]
16-bit PPG ch0 IRQ15 FFDCH FFDDH L15 [1:0]
I2C ch0 IRQ16 FFDAH FFDBH L16 [1:0]
16-bit PPG ch1 IRQ17 FFD8H FFD9H L17 [1:0]
10-bit A/D IRQ18 FFD6H FFD7H L18 [1:0]
Timebase timer IRQ19 FFD4H FFD5H L19 [1:0]
Watch timer/counter IRQ20 FFD2H FFD3H L20 [1:0]
External interrupt ch8
IRQ21 FFD0H FFD1H L21 [1:0]External interrupt ch9
External interrupt ch10
External interrupt ch11
8/16-bit timer ch1 (lower) IRQ22 FFCEH FFCFH L22 [1:0]
FLASH IRQ23 FFCCH FFCDH L23 [1:0] Low
869
CHAPTER 29 Basic Information
Table 29.2-4 RESERVE2 series
Interrupt causesInterrupt request number
Address of vector table
Bit name of interrupt level
setting register
The same level priority
level (Concurrence)Upper Lower
External interrupt ch0IRQ0 FFFAH FFFBH L00 [1:0]
High
External interrupt ch4
External interrupt ch1IRQ1 FFF8H FFF9H L01 [1:0]
External interrupt ch5
External interrupt ch2IRQ2 FFF6H FFF7H L02 [1:0]
External interrupt ch6
External interrupt ch3IRQ3 FFF4H FFF5H L03 [1:0]
External interrupt ch7
UART/SIO ch0 IRQ4 FFF2H FFF3H L04 [1:0]
8/16-bit timer ch0 (lower) IRQ5 FFF0H FFF1H L05 [1:0]
8/16-bit timer ch0 (upper) IRQ6 FFEEH FFEFH L06 [1:0]
LIN-UART (reception) IRQ7 FFECH FFEDH L07 [1:0]
LIN-UART (transmission) IRQ8 FFEAH FFEBH L08 [1:0]
8/16-bit PPG ch1 (lower) IRQ9 FFE8H FFE9H L09 [1:0]
8/16-bit PPG ch1 (upper) IRQ10 FFE6H FFE7H L10 [1:0]
(Unused) IRQ11 FFE4H FFE5H L11 [1:0]
8/16-bit PPG ch0 (upper) IRQ12 FFE2H FFE3H L12 [1:0]
8/16-bit PPG ch0 (lower) IRQ13 FFE0H FFE1H L13 [1:0]
8/16-bit timer ch1 (upper) IRQ14 FFDEH FFDFH L14 [1:0]
16-bit PPG ch0 IRQ15 FFDCH FFDDH L15 [1:0]
I2C ch0 IRQ16 FFDAH FFDBH L16 [1:0]
16-bit PPG ch1 IRQ17 FFD8H FFD9H L17 [1:0]
10-bit A/D IRQ18 FFD6H FFD7H L18 [1:0]
Timebase timer IRQ19 FFD4H FFD5H L19 [1:0]
Watch timer/counter IRQ20 FFD2H FFD3H L20 [1:0]
External interrupt ch8
IRQ21 FFD0H FFD1H L21 [1:0]External interrupt ch9
External interrupt ch10
External interrupt ch11
8/16-bit timer ch1 (lower) IRQ22 FFCEH FFCFH L22 [1:0]
FLASH IRQ23 FFCCH FFCDH L23 [1:0] Low
870
Table 29.2-5 TROMBONE,CLARINET series
Interrupt causesInterrupt request number
Address of vector table
Bit name of interrupt level
setting register
The same level priority
level (Concurrence)Upper Lower
External interrupt ch0IRQ0 FFFAH FFFBH L00 [1:0]
High
External interrupt ch4
External interrupt ch1IRQ1 FFF8H FFF9H L01 [1:0]
External interrupt ch5
External interrupt ch2IRQ2 FFF6H FFF7H L02 [1:0]
External interrupt ch6
External interrupt ch3IRQ3 FFF4H FFF5H L03 [1:0]
External interrupt ch7
UART/SIO ch0 IRQ4 FFF2H FFF3H L04 [1:0]
8/16-bit timer ch0 (lower) IRQ5 FFF0H FFF1H L05 [1:0]
8/16-bit timer ch0 (upper) IRQ6 FFEEH FFEFH L06 [1:0]
LIN-UART (reception) IRQ7 FFECH FFEDH L07 [1:0]
LIN-UART (transmission) IRQ8 FFEAH FFEBH L08 [1:0]
8/16-bit PPG ch1 (lower) IRQ9 FFE8H FFE9H L09 [1:0]
8/16-bit PPG ch1 (upper) IRQ10 FFE6H FFE7H L10 [1:0]
(Unused) IRQ11 FFE4H FFE5H L11 [1:0]
8/16-bit PPG ch0 (upper) IRQ12 FFE2H FFE3H L12 [1:0]
8/16-bit PPG ch0 (lower) IRQ13 FFE0H FFE1H L13 [1:0]
8/16-bit timer ch1 (upper) IRQ14 FFDEH FFDFH L14 [1:0]
16-bit PPG ch0 IRQ15 FFDCH FFDDH L15 [1:0]
(Unused) IRQ16 FFDAH FFDBH L16 [1:0]
(Unused) IRQ17 FFD8H FFD9H L17 [1:0]
10-bit A/D IRQ18 FFD6H FFD7H L18 [1:0]
Timebase timer IRQ19 FFD4H FFD5H L19 [1:0]
Watch timer/counter IRQ20 FFD2H FFD3H L20 [1:0]
(Unused) IRQ21 FFD0H FFD1H L21 [1:0]
8/16-bit timer ch1 (lower) IRQ22 FFCEH FFCFH L22 [1:0]
FLASH IRQ23 FFCCH FFCDH L23 [1:0] Low
871
CHAPTER 29 Basic Information
Table 29.2-6 TRUMPET,OBOE series
Interrupt causesInterrupt request number
Address of vector table
Bit name of interrupt level
setting register
The same level priority
level (Concurrence)Upper Lower
External interrupt ch0IRQ0 FFFAH FFFBH L00 [1:0]
High
External interrupt ch4
External interrupt ch1IRQ1 FFF8H FFF9H L01 [1:0]
External interrupt ch5
External interrupt ch2IRQ2 FFF6H FFF7H L02 [1:0]
External interrupt ch6
External interrupt ch3IRQ3 FFF4H FFF5H L03 [1:0]
External interrupt ch7
UART/SIO ch0 IRQ4 FFF2H FFF3H L04 [1:0]
8/16-bit timer ch0 (lower) IRQ5 FFF0H FFF1H L05 [1:0]
8/16-bit timer ch0 (upper) IRQ6 FFEEH FFEFH L06 [1:0]
LIN-UART (reception) IRQ7 FFECH FFEDH L07 [1:0]
LIN-UART (transmission) IRQ8 FFEAH FFEBH L08 [1:0]
8/16-bit PPG ch1 (lower) IRQ9 FFE8H FFE9H L09 [1:0]
8/16-bit PPG ch1 (upper) IRQ10 FFE6H FFE7H L10 [1:0]
(Unused) IRQ11 FFE4H FFE5H L11 [1:0]
8/16-bit PPG ch0 (upper) IRQ12 FFE2H FFE3H L12 [1:0]
8/16-bit PPG ch0 (lower) IRQ13 FFE0H FFE1H L13 [1:0]
8/16-bit timer ch1 (upper) IRQ14 FFDEH FFDFH L14 [1:0]
16-bit PPG ch0 IRQ15 FFDCH FFDDH L15 [1:0]
(Unused) IRQ16 FFDAH FFDBH L16 [1:0]
(Unused) IRQ17 FFD8H FFD9H L17 [1:0]
10-bit A/D IRQ18 FFD6H FFD7H L18 [1:0]
Timebase timer IRQ19 FFD4H FFD5H L19 [1:0]
Watch timer/counter IRQ20 FFD2H FFD3H L20 [1:0]
(Unused) IRQ21 FFD0H FFD1H L21 [1:0]
8/16-bit timer ch1 (lower) IRQ22 FFCEH FFCFH L22 [1:0]
FLASH IRQ23 FFCCH FFCDH L23 [1:0] Low
872
Table 29.2-7 FLUTE series
Interrupt causesInterrupt request number
Address of vector table
Bit name of interrupt level
setting register
The same level priority
level (Concurrence)Upper Lower
External interrupt ch0IRQ0 FFFAH FFFBH L00 [1:0]
High
External interrupt ch4
External interrupt ch1IRQ1 FFF8H FFF9H L01 [1:0]
External interrupt ch5
External interrupt ch2IRQ2 FFF6H FFF7H L02 [1:0]
External interrupt ch6
External interrupt ch3IRQ3 FFF4H FFF5H L03 [1:0]
External interrupt ch7
UART/SIO ch0 IRQ4 FFF2H FFF3H L04 [1:0]
8/16-bit timer ch0 (lower) IRQ5 FFF0H FFF1H L05 [1:0]
8/16-bit timer ch0 (upper) IRQ6 FFEEH FFEFH L06 [1:0]
LIN-UART (reception) IRQ7 FFECH FFEDH L07 [1:0]
LIN-UART (transmission) IRQ8 FFEAH FFEBH L08 [1:0]
(Unused) IRQ9 FFE8H FFE9H L09 [1:0]
(Unused) IRQ10 FFE6H FFE7H L10 [1:0]
(Unused) IRQ11 FFE4H FFE5H L11 [1:0]
8/16-bit PPG ch0 (upper) IRQ12 FFE2H FFE3H L12 [1:0]
8/16-bit PPG ch0 (lower) IRQ13 FFE0H FFE1H L13 [1:0]
(Unused) IRQ14 FFDEH FFDFH L14 [1:0]
16-bit PPG ch0 IRQ15 FFDCH FFDDH L15 [1:0]
(Unused) IRQ16 FFDAH FFDBH L16 [1:0]
(Unused) IRQ17 FFD8H FFD9H L17 [1:0]
10-bit A/D IRQ18 FFD6H FFD7H L18 [1:0]
Timebase timer IRQ19 FFD4H FFD5H L19 [1:0]
Watch timer/counter IRQ20 FFD2H FFD3H L20 [1:0]
(Unused) IRQ21 FFD0H FFD1H L21 [1:0]
(Unused) IRQ22 FFCEH FFCFH L22 [1:0]
FLASH IRQ23 FFCCH FFCDH L23 [1:0] Low
873
CHAPTER 29 Basic Information
Table 29.2-8 PICCOLO series
Interrupt causesInterrupt request number
Address of vector table
Bit name of interrupt level
setting register
The same level priority
level (Concurrence)Upper Lower
External interrupt ch0IRQ0 FFFAH FFFBH L00 [1:0]
High
External interrupt ch4
External interrupt ch1IRQ1 FFF8H FFF9H L01 [1:0]
External interrupt ch5
External interrupt ch2IRQ2 FFF6H FFF7H L02 [1:0]
External interrupt ch6
External interrupt ch3IRQ3 FFF4H FFF5H L03 [1:0]
External interrupt ch7
UART/SIO ch0 IRQ4 FFF2H FFF3H L04 [1:0]
8/16-bit timer ch0 (lower) IRQ5 FFF0H FFF1H L05 [1:0]
8/16-bit timer ch0 (upper) IRQ6 FFEEH FFEFH L06 [1:0]
LIN-UART (reception) IRQ7 FFECH FFEDH L07 [1:0]
LIN-UART (transmission) IRQ8 FFEAH FFEBH L08 [1:0]
(Unused) IRQ9 FFE8H FFE9H L09 [1:0]
(Unused) IRQ10 FFE6H FFE7H L10 [1:0]
(Unused) IRQ11 FFE4H FFE5H L11 [1:0]
8/16-bit PPG ch0 (upper) IRQ12 FFE2H FFE3H L12 [1:0]
8/16-bit PPG ch0 (lower) IRQ13 FFE0H FFE1H L13 [1:0]
(Unused) IRQ14 FFDEH FFDFH L14 [1:0]
16-bit PPG ch0 IRQ15 FFDCH FFDDH L15 [1:0]
(Unused) IRQ16 FFDAH FFDBH L16 [1:0]
(Unused) IRQ17 FFD8H FFD9H L17 [1:0]
10-bit A/D IRQ18 FFD6H FFD7H L18 [1:0]
Timebase timer IRQ19 FFD4H FFD5H L19 [1:0]
(Unused) IRQ20 FFD2H FFD3H L20 [1:0]
(Unused) IRQ21 FFD0H FFD1H L21 [1:0]
(Unused) IRQ22 FFCEH FFCFH L22 [1:0]
FLASH IRQ23 FFCCH FFCDH L23 [1:0] Low
874
29.3 Memory Map
This section shows the memory map of MB95XXX series.
Memory map
Figure 29.3-1 Memory map
FFC0H
FFFFH
I/O area
0000H
0100H
0200H
Register bank(General-purpose
register area)
047FH
0080H
0F80H
0FFFH
Data area
Extended direct addressing area
Extended I/O area
Program area
Vector table*
*: Vector table (reset, interrupt and vector call instruction)
875
CHAPTER 29 Basic Information
29.4 Instruction Overview
This section explains the instructions used in F2MC-8FX.
Instruction overview of F2MC-8FX
In F2MC-8FX, there is one byte machine instruction of 140 kinds of (As the map, 256 bytes), and the
instruction code is composed of the instruction and the operand following it.
Figure 29.4-1 shows the correspondence of the instruction code and the instruction map.
Figure 29.4-1 Instruction Code and Instruction Map
• The instruction is classified into following four types; forwarding system, operation system, divergencesystem and others.
• There is various methods of addressing, and ten kinds of addressing can be selected by the selection andthe operand specification of the instruction.
• This provides with the bit operation instruction, and the read modification write can operate.
• There is an instruction that directs special operation.
Instruction code
*1 byteMachine instruction Operand Operand
[Instruction map]
0 to 2 bytes are given depending on instructions.
Higher 4 bits
Low
er 4
bits
876
Explanation of display sign of instructionTable 29.4-1 shows the explanation of the sign used by explaining the instruction code of this appendix B.
Table 29.4-1 Explanation of sign in instruction table
Sign Signification
dir Direct address (8-bit length)
off Offset (8-bit length)
ext Extended address (16-bit length)
#vct Vector table number (3-bit length)
#d8 Immediate data (8-bit length)
#d16 Immediate data (16-bit length)
dir:b Bit direct address (8-bit length: 3-bit length)
rel Divergence relative address (8-bit length)
@ Register indirect (Example:@A,@IX,@EP)
A Accumulator (Whether 8- bit length or 16- bit length is decided by the instruction used.)
AH Upper 8-bit of accumulator (8-bit length)
AL Lower 8-bit of accumulator (8-bit length)
TTemporary accumulator(Whether 8- bit length or 16- bit length is decided by the instruction used.)
TH Upper 8-bit of temporary accumulator (8-bit length)
TL Lower 8-bit of temporary accumulator (8-bit length)
IX Index register (16-bit length)
EP Extra pointer (16-bit length)
PC Program counter (16-bit length)
SP Stack pointer (16-bit length)
PS Program status (16-bit length)
dr Either of accumulator or index register (16-bit length)
CCR Condition code register (8-bit length)
RP Register bank pointer (5-bit length)
DP Direct bank pointer (3-bit length)
Ri General-purpose register (8-bit length, i=0 to 7)
× This shows that × is immediate data. (Whether 8- bit length or 16- bit length is decided by the instruction used.)
(×)This shows that contents of × are objects of the access. (Whether 8- bit length or 16- bit length is decided by the instruction used.)
((×))This shows that the address that contents of × show is an object of the access. (Whether 8- bit length or 16- bit length is decided by the instruction used.)
877
CHAPTER 29 Basic Information
Explanation of item in instruction table
Table 29.4-2 Explanation of item in instruction table
Item Description
MNEMONIC The assembly description of the instruction is shown.
~ Cycle of the instruction number is shown. One instruction cycle is a machine cycle. Note:Moreover, cycle of the instruction number might be extended in the access to the IO area.
# The number of bytes for the instruction is shown.
Operation The operations for the instruction is shown.
TL, TH, AH The change (call forwarding from A to T) in the content when TL, TH, and AH each instruction is executed is shown. The sign in the column indicates the following respectively. "−" shows no change. dH is higher 8 bits of the data described in operation. AL and AH must become content immediately before the instruction execution00 must become 00
N, Z, V, C The instruction into which the flag corresponding to respectively is changed is shown. The sign in the column shows the following respectively. −: Not changed+: ChangedR: Become 0S: Become 1
OP CPDE The code of the instruction is shown. When a pertinent instruction occupies two or more codes, it follows the following description rules. [Example] 48 to 4F: This shows 48, 49....4F.
878
29.4.1 Addressing
There is the following ten kinds of addressing of F2MC-8FX. • Direct addressing• Extended addressing• Bit direct addressing• Index addressing• Pointer addressing• General-purpose register addressing• Immediate addressing• Vector addressing• Relative addressing• Inherent addressing
Explanation of addressing
Direct addressing
This is used when accessing the direct area of "0000H" to "047FH" with addressing indicated "dir" in
instruction table. In this addressing, when the operand address is "00H" to "7FH", it is accessed into
"0000H" to "007FH". Moreover, when the operand address is "80H" to "FFH", the access can be mapped in
"0080H" to "047FH" by setting of direct bank pointer DP.
Figure 29.4-2 Example of Direct Addressing
Extended addressing
This is used when the area of the entire 64 Kbyte is accessed by addressing shown "ext" in the instruction
table. In this addressing, one high rank byte of the address is specified in the first operand and one
subordinate position byte of the address is specified by the second operand.
Figure 29.4-3 shows the example.
Figure 29.4-3 Example of Extended Addressing
MOV 92H, A
A DP 001B 0112H 45H 45H
MOVW A, 1234H
A
1234H
1235H
56H
78H5678H
879
CHAPTER 29 Basic Information
Bit direct addressing
This is used when accessed direct area of "0000H" to "047FH" by bit unit with the addressing shown "dir:b"
in instruction table. In this addressing, when the operand address is "00H" to "7FH", it accesses into
"0000H" to "007FH". Moreover, when the operand address is "80H" to "FFH", the access can be mapped in
"0080H" to "047FH" by setting of direct bank pointer DP. The position of the bit in the specified address is
specified by the value of the instruction code of three subordinate position bits.
Figure 29.4-4 shows the example.
Figure 29.4-4 Example of Bit Direct Addressing
Index addressing
This is used when the area of the entire 64 Kbyte is accessed by addressing shown, "@IX+off" in the
instruction table. In this addressing, the content of the first operand is added to IX (index register) after the
sign is enhanced and the result is assumed to be an address. Figure 29.4-5 shows the example.
Figure 29.4-5 Example of Index Addressing
Pointer addressing
This is used when the area of the entire 64 Kbyte is accessed by addressing shown, "@EP" in the
instruction table. In this addressing, the content of EP (extra pointer) is assumed to be an address. Figure
29.4-6 shows the example.
Figure 29.4-6 Example of Pointer Addressing
SETB 34H : 2
X X X X X 1 X XB
7 6 5 4 3 2 1 0 xxx B DP 0034H
MOVW A, @IX+5 AH
AI X 27A5H 27FFH
2800H1234H
12H
34H
MOVW A, @EP
AEP
1234H27A5H 27A5H
27A6H
12H
34H
880
General-purpose register addressing
This is used when accessing the register bank in general-purpose register with the addressing shown "Ri" in
instruction table. In this addressing, one high rank byte of the address is fixed to "01", one subordinate
position byte is made from three subordinate position bits (the content and the operation code of RP
(register bank pointer)) and it accesses this address. Figure 29.4-7 show the example.
Figure 29.4-7 Example of General-purpose Register Addressing
Immediate addressing
This is used when immediate data is needed in addressing shown "# d8" in the instruction table. In this
addressing, the operand becomes immediate data as it is. The specification of byte/word is decided
according to the operation code. Figure 29.4-8 shows the example.
Figure 29.4-8 Example of Immediate Addressing
Vector addressing
This is used when diverging to the subroutine address registered in the table by addressing shown "vct" in
the instruction table. In this addressing, information on "vct" is contained in the operation code, and the
address of the table is made by correspond of showing in Table 29.4-3.
0 1 5 6 H ARP 01010B
MOV A, R 6
A BH A BH
5 6 HA
MOV A, #56H
Table 29.4-3 Vector table address corresponding to "vct"
#vct Vector table address (high-ranking address at jump destination: subordinate position address)
0 FFCOH : FFC1H
1 FFC2H : FFC3H
2 FFC4H : FFC5H
3 FFC6H : FFC7H
4 FFC8H : FFC9H
5 FFCAH : FFCBH
6 FFCCH : FFCDH
7 FFCEH : FFCFH
881
CHAPTER 29 Basic Information
Figure 29.4-9 shows the example.
Figure 29.4-9 Example of Vector Addressing
Relative addressing
This is used when diverging to the area in 128 bytes before and behind PC (program counter) by addressing
shown, "rel" in the instruction table. In this addressing, the content of the operand is added to PC with the
sign, and the result is stored in PC. Figure 29.4-10 shows an example.
Figure 29.4-10 Example of Relative Addressing
It becomes an infinite loop as a result because it jumps to the address where the operation code of BNE is
stored in this example.
Inherent addressing
This is used when the operation decided by the operation code is done by addressing without the operand in
the instruction table. Operation is different in this addressing at each instruction. Figure 29.4-11 shows an
example.
Figure 29.4-11 Example of Inherent Addressing
FFCAH
CALLV #5
FEDCHPCFEH
DCHFFCBH
(Conversion)
9ABA H
BNE FEH
New PC9A BCHOld PC9AB0H+FFFEH
9A BDH
NOP
New PC9A BCHOld PC
882
29.4.2 Special instruction
This section explains special instructions other than addressing.
Special instruction
JMP @A
This instruction is to diverge the content of A (accumulator) to PC (program counter) as an address. The
jump destination of N piece is arranged on the table, and one of the contents is selected and transferred to
A. N divergence processing can be done by executing this instruction.
Figure 29.4-12 shows the outline chart.
Figure 29.4-12 JMP @A
MOVW A,PC
This instruction does operation opposite to "JMP @A". That is, the one to store the content of PC in A.
This instruction is executed in the main routine, and when setting it by the call of a specific subroutine, the
value to which the content of A is decided in the subroutine can be confirmed. Divergence from the part
that cannot be expected can be identified, and this is possible to use for the reckless driving judgment.
Figure 29.4-13 shows the outline chart.
Figure 29.4-13 MOVW A,PC
The content of A when this instruction is executed reaches the same value as not the address where the
operation code of this instruction is stored but the following instruction is stored. Therefore, in Figure 29.4-
13, the value "1234H" stored in A is corresponding to the address where the following operation code of
"MOVW A,PC" is stored.
1234HA
XXXXH
A
(Before executing) (After executing)
Old PC New PC
1234H
1234H
A A
(Before executing) (After executing)
Old PC New PC
1234H
1234H1233H
XXXXH
883
CHAPTER 29 Basic Information
MULU A
This instruction performs an unsigned multiplication of AL (lower eight bits of the accumulator) and TL
(lower eight bits of the temporary accumulator), and stores the 16-bit result in A. The contents of T
(temporary accumulator) do not change. The contents of AH (higher eight bits of the accumulator) and TH
(higher eight bits of the temporary accumulator) before execution of the instruction are not used for the
operation. The instruction does not change the flags, and therefore care must be taken when a branch may
occur depending on the result of a multiplication.
Figure 29.4-14 "MULU A" shows a summary of the instruction.
Figure 29.4-14 MULU A
DIVU A
This instruction divides the 16-bit value in T by the unsigned 16-bit value in A, and stores the 16-bit result
and the 16-bit remainder in A and T, respectively. When the value in A before execution of instruction is
"0", the Z flag becomes "1" to indicate zero-division is executed.
The instruction does not change other flags, and therefore care must be taken when a branch may occur
depending on the result of a division.
Figure 29.4-5 "DIVU A" shows a summary of the instruction.
Figure 29.4-15 DIVU A
A
T
A
T
(Before execution) (After execution)
5678H
1234H 1234H
1860H
A
T
A
T
(Before execution) (After execution)
1234H
5678H
0004H
0DA8H
884
XCHW A,PC
This instruction swaps the contents of A and PC, resulting in a branch to the address contained in A before
execution of the instruction. After the instruction is executed, A contains the address that follows the
address of the operation code of XCHW A, PC. This instruction is effective especially when it is used in
the main routine to specify a table for use in a subroutine.
Figure 29.4-16 "XCHW A, PC" shows a summary of the instruction.
Figure 29.4-16 XCHW A,PC
After the XCHW A, PC instruction is executed, A contains the address of the operation code of the next
instruction, rather than the address of the operation code of XCHW A, PC. Accordingly, Figure 29.4-16
"XCHW A, PC" shows that A contains 1235H, which is the address of the operation code of the instruction
that follows XCHW A, PC. This is why 1235H is stored instead of 1234H.
Figure 29.4-17 "Example of using XCHW A, PC" shows an assembly language example.
Figure 29.4-17 Example of using XCHW A,PC
A
PC
A
PC
(Before execution) (After execution)
5678H
1234H
1235H
5678H
MOVW
XCHW
DB
MOVW
A, #PUTSUB
A, PC
'PUT OUT DATA', EOLA, 1234H
. .
..
. .
XCHW A, EP
PUSHW A
MOV A, @EP
INCW EP
MOV IO, A
CMP A, #EOL
BNE PTS1
POPW A
XCHW A, EP
JMP @A
PUTSUB
PTS1
(Main routine) (Subroutine)
Output table data here
885
CHAPTER 29 Basic Information
CALLV #vct
This instruction is used to branch to a subroutine address stored in the vector table. The instruction saves
the return address (contents of PC) in the location at the address contained in SP (stack pointer), and uses
vector addressing to cause a branch to the address stored in the vector table. Because CALLV #vct is a 1-
byte instruction, the use of this instruction for frequently used subroutines can reduce the entire program
size.
Figure 29.4-18 "Example of executing CALLV #3" shows a summary of the instruction.
Figure 29.4-18 Example of executing CALLV #3
After the CALLV #vct instruction is executed, the contents of PC saved on the stack area are the address of
the operation code of the next instruction, rather than the address of the operation code of CALLV #vct.
Accordingly, Figure 29.4-18 "Example of executing CALLV #3" shows that the value saved in the stack
(1232H and 1233H) is 5679H, which is the address of the operation code of the instruction that follows
CALLV #vct (return address).
PC
SP
PC
SP(-2)
(Before execution) (After execution)
5678H
1234H 1232H
1232H
1233H
FFC6H
FFC7H
1232H
1233H
FFC6H
FFC7H
FEDCH
XXH
XXH
FEH
DCH
56H
79H
FEH
DCH
886
29.4.3 Bit Manipulation Instructions (SETB, CLRB)
Some bits of peripheral function registers include bits that are read by a bit manipulation instruction differently than usual.
Read-modify-write operationBy using these bit manipulation instructions, only the specified bit in a register or RAM location can be set
to 1 (SETB) or cleared to 0 (CLRB). However, as the CPU operates on data in 8-bit units, the actual
operation (read-modify-write operation) involves a sequence of steps: 8-bit data is read, the specified bit is
changed, and the data is written back to the location at the original address.
Table 29.4-4 "Bus operation for bit manipulation instructions" shows bus operation for bit manipulation
instructions.
Read operation upon the execution of bit manipulation instructionsFor some I/O ports and for the interrupt request flag bits, the value to be read differs between a normal read
operation and a read-modify-write operation.
I/O ports (during a bit manipulation)
From some I/O ports, an I/O pin value is read during a normal read operation, while an port data register
value is read during a bit manipulation. This prevents the other port data register bits from being changed
accidentally, regardless of the I/O directions and states of the pins.
Interrupt request flag bits (during a bit manipulation)
An interrupt request flag bit functions as a flag bit indicating whether an interrupt request exists during a
normal read operation. However, 1 is always read from this bit during a bit manipulation. This prevents the
flag from being cleared accidentally by a value of 0 which would otherwise be written to the interrupt
request flag bit when another bit is manipulated.
Table 29.4-4 Bus operation for bit manipulation instructions
CODE MNEMONIC To Cycle Address bus Data bus RD WR RMW
A0 to A7
A8 to AF
CLRB dir:b
SETB dir:b
4 1234
N+2dir addressdir addressN+3
Next instructionDataDataInstruction that follt instruction
1101
0010
1100
887
CHAPTER 29 Basic Information
29.4.4 F2MC-8FX Instructions
Table 29.4-5 "Transfer instructions" to Table 29.4-8 "Other instructions" show the
instructionsused by the F2MC-8FX.
Transfer instructions
Table 29.4-5 Transfer instructions
No. MNEMONIC ~ # Operation TL TH AH N Z V C OP CODE
1 MOV dir,A 3 2 (dir)← (A) - - - - - - - 45
2 MOV @IX + off,A 3 2 ((IX) + off)← (A) - - - - - - - 46
3 MOV ext,A 4 3 (ext)← (A) - - - - - - - 61
4 MOV @EP,A 2 1 ((EP))← (A) - - - - - - - 47
5 MOV Ri,A 2 1 (Ri)← (A) - - - - - - - 48~4F
6 MOV A,#d8 2 2 (A)← d8 AL - - + + - - 04
7 MOV A,dir 3 2 (A)← (dir) AL - - + + - - 05
8 MOV A,@IX + off 3 2 (A)← ((IX) + off) AL - - + + - - 06
9 MOV A,ext 4 3 (A)← (ext) AL - - + + - - 60
10 MOV A,@A 2 1 (A)← ((A)) AL - - + + - - 92
11 MOV A,@EP 2 1 (A)← ((EP)) AL - - + + - - 07
12 MOV A,Ri 2 1 (A)← (Ri) AL - - + + - - 08~0F
13 MOV dir,#d8 4 3 (dir)← d8 - - - - - - - 85
14 MOV @IX + off,#d8 4 3 ((IX) + off)← d8 - - - - - - - 86
15 MOV @EP,#d8 3 2 ((EP))← d8 - - - - - - - 87
16 MOV Ri,#d8 3 2 (Ri)← d8 - - - - - - - 88~8F
17 MOVW dir,A 4 2 (dir)← (AH), (dir + 1)← (AL) - - - - - - - D5
18 MOVW @IX + off ,A 4 2 ((IX) + off )← (AH),((IX) + off + 1)← (AL) - - - - - - - D6
19 MOVW ext,A 5 3 (ext)← (AH), (ext + 1)← (AL) - - - - - - - D4
20 MOVW @EP,A 3 1 ((EP))← (AH), ((EP) + 1)← (AL) - - - - - - - D7
21 MOVW EP,A 1 1 (EP)← (A) - - - - - - - E3
22 MOVW A,#d16 3 3 (A)← d16 AL AH dH + + - - E4
23 MOVW A,dir 4 2 (AH)← (dir), (AL)← (dir + 1) AL AH dH + + - - C5
24 MOVW A,@IX + off 4 2 (AH)← ((IX) + off), (AL)← ((IX) + off + 1) AL AH dH + + - - C6
25 MOVW A,ext 5 3 (AH)← (ext), (AL)← (ext + 1) AL AH dH + + - - C4
888
Note:
In automatic transfer to T during byte transfer to A, AL is transferred to TL.
If an instruction has two or more operands, they are assumed to be saved in the order indicated byMNEMONIC.
26 MOVW A,@A 3 1 (AH)← ((A)), (AL)← ((A) + 1) AL AH dH + + - - 93
27 MOVW A,@EP 3 1 (AH)← ((EP)), (AL)← ((EP) + 1) AL AH dH + + - - C7
28 MOVW A,EP 1 1 (A)← (EP) - - dH - - - - F3
29 MOVW EP,#d16 3 3 (EP)← d16 - - - - - - - E7
30 MOVW IX,A 1 1 (IX)← (A) - - - - - - - E2
31 MOVW A,IX 1 1 (A)← (IX) - - dH - - - - F2
32 MOVW SP,A 1 1 (SP)← (A) - - - - - - - E1
33 MOVW A,SP 1 1 (A)← (SP) - - dH - - - - F1
34 MOV @A,T 2 1 ((A))← (T) - - - - - - - 82
35 MOVW @A,T 3 1 ((A))← (TH),((A) + 1)← (TL) - - - - - - - 83
36 MOVW IX,#d16 3 3 (IX)← d16 - - - - - - - E6
37 MOVW A,PS 1 1 (A)← (PS) - - dH - - - - 70
38 MOVW PS,A 1 1 (PS)← (A) - - - + + + + 71
39 MOVW SP,#d16 3 3 (SP)← d16 - - - - - - - E5
40 SWAP 1 1 (AH)↔ (AL) - - AL - - - - 10
41 SETB dir:b 4 2 (dir):b ← 1 - - - - - - - A8~AF
42 CLRB dir:b 4 2 (dir):b ← 0 - - - - - - - A0~A7
43 XCH A,T 1 1 (AL)↔(TL) AL - - - - - - 42
44 XCHW A,T 1 1 (A)↔(T) AL AH dH - - - - 43
45 XCHW A,EP 1 1 (A)↔(EP) - - dH - - - - F7
46 XCHW A,IX 1 1 (A)↔(IX) - - dH - - - - F6
47 XCHW A,SP 1 1 (A)↔(SP) - - dH - - - - F5
48 MOVW A,PC 2 1 (A)← (PC) - - dH - - - - F0
Table 29.4-5 Transfer instructions
No. MNEMONIC ~ # Operation TL TH AH N Z V C OP CODE
889
CHAPTER 29 Basic Information
Arithmetic instructionsTable 29.4-6 Arithmetic operation instruction
No. MNEMONIC ~ # Operation TL TH AH N Z V C OP CODE
1 ADDC A,Ri 2 1 (A)← (A) + (Ri) + C - - - + + + + 28~2F
2 ADDC A,#d8 2 2 (A)← (A) + d8 + C - - - + + + + 24
3 ADDC A,dir 3 2 (A)← (A) + (dir) + C - - - + + + + 25
4 ADDC A,@IX + off 3 2 (A)← (A) + ((IX) + off) + C - - - + + + + 26
5 ADDC A,@EP 2 1 (A)← (A) + ((EP)) + C - - - + + + + 27
6 ADDCW A 1 1 (A)← (A) + (T) + C - - dH + + + + 23
7 ADDC A 1 1 (AL)← (AL) + (TL) + C - - - + + + + 22
8 SUBC A,Ri 2 1 (A)← (A) - (Ri) - C - - - + + + + 38~3F
9 SUBC A,#d8 2 2 (A)← (A) - d8 - C - - - + + + + 34
10 SUBC A,dir 3 2 (A)← (A) - (dir) - C - - - + + + + 35
11 SUBC A,@IX + off 3 2 (A)← (A) - ((IX) + off) - C - - - + + + + 36
12 SUBC A,@EP 2 1 (A)← (A) - ((EP)) - C - - - + + + + 37
13 SUBCW A 1 1 (A)← (T) - (A) - C - - dH + + + + 33
14 SUBC A 1 1 (AL)← (TL) - (AL) - C - - - + + + + 32
15 INC Ri 3 1 (Ri)← (Ri) + 1 - - - + + + - C8~CF
16 INCW EP 1 1 (EP)← (EP) + 1 - - - - - - - C3
17 INCW IX 1 1 (IX)← (IX) + 1 - - - - - - - C2
18 INCW A 1 1 (A)← (A) + 1 - - dH + + - - C0
19 DEC Ri 3 1 (Ri)← (Ri) - 1 - - - + + + - D8~DF
20 DECW EP 1 1 (EP)← (EP) - 1 - - - - - - - D3
21 DECW IX 1 1 (IX)← (IX) - 1 - - - - - - - D2
22 DECW A 1 1 (A)← (A) - 1 - - dH + + - - D0
23 MULU A 8 1 (A)← (AL)×(TL) - - dH - - - - 01
24 DIVU A 17 1 (A)← (T)/(A),MOD →(T) dL dH dH - + - - 11
25 ANDW A 1 1 (A)← (A)^(T) - - dH + + R - 63
26 ORW A 1 1 (A)← (A)v(T) - - dH + + R - 73
27 XORW A 1 1 (A)← (A) (T) - - dH + + R - 53
28 CMP A 1 1 (TL) - (AL) - - - + + + + 12
29 CMPW A 1 1 (T) - (A) - - - + + + + 13
30 RORC A 1 1 C→A - - - + + - + 03
31 ROLC A 1 1 C← A - - - + + - + 02
32 CMP A,#d8 2 2 (A) - d8 - - - + + + + 14
33 CMP A,dir 3 2 (A) - (dir) - - - + + + + 15
34 CMP A,@EP 2 1 (A) - ((EP)) - - - + + + + 17
35 CMP A,@IX + off 3 2 (A) - ((IX) + off) - - - + + + + 16
A
890
36 CMP A,Ri 2 1 (A) - (Ri) - - - + + + + 18~1F
37 DAA 1 1 decimal adjust for addition - - - + + + + 84
38 DAS 1 1 decimal adjust for subtraction - - - + + + + 94
39 XOR A 1 1 (A)← (AL) (TL) - - - + + R - 52
40 XOR A,#d8 2 2 (A)← (AL) d8 - - - + + R - 54
41 XOR A,dir 3 2 (A)← (AL) (dir) - - - + + R - 55
42 XOR A,@EP 2 1 (A)← (AL) ((EP)) - - - + + R - 57
43 XOR A,@IX + off 3 2 (A)← (AL) ((IX) + off) - - - + + R - 56
44 XOR A,Ri 2 1 (A)← (AL) (Ri) - - - + + R - 58~5F
45 AND A 1 1 (A)← (AL)^(TL) - - - + + R - 62
46 AND A,#d8 2 2 (A)← (AL)^ d8 - - - + + R - 64
47 AND A,dir 3 2 (A)← (AL)^(dir) - - - + + R - 65
48 AND A,@EP 2 1 (A)← (AL)^((EP)) - - - + + R - 67
49 AND A,@IX + off 3 2 (A)← (AL)^((IX) + off) - - - + + R - 66
50 AND A,Ri 2 1 (A)← (AL)^(Ri) - - - + + R - 68~6F
51 OR A 1 1 (A)← (AL)v(TL) - - - + + R - 72
52 OR A,#d8 2 2 (A)← (AL)v d8 - - - + + R - 74
53 OR A,dir 3 2 (A)← (AL)v(dir) - - - + + R - 75
54 OR A,@EP 2 1 (A)← (AL)v((EP)) - - - + + R - 77
55 OR A,@IX + off 3 2 (A)← (AL)v((IX) + off) - - - + + R - 76
56 OR A,Ri 2 1 (A)← (AL)v(Ri) - - - + + R - 78~7F
57 CMP dir ,#d8 4 3 (dir) - d8 - - - + + + + 95
58 CMP @EP,#d8 3 2 ((EP)) - d8 - - - + + + + 97
59 CMP @IX + off,#d8 4 3 ((IX) + off) - d8 - - - + + + + 96
60 CMP Ri,#d8 3 2 (Ri) - d8 - - - + + + + 98~9F
61 INCW SP 1 1 (SP)← (SP) + 1 - - - - - - - C1
62 DECW SP 1 1 (SP)← (SP) - 1 - - - - - - - D1
Table 29.4-6 Arithmetic operation instruction
No. MNEMONIC ~ # Operation TL TH AH N Z V C OP CODE
AA
AAAA
891
CHAPTER 29 Basic Information
Branch instructions
Other instructions
Table 29.4-7 Branch instructions
No. MNEMONIC ~ # Operation TL TH AH N Z V C OP CODE
1 BZ/BEQ rel(at branch) 4 2 if Z=1 then PC← PC + rel - - - - - - - FD
BZ/BEQ rel(at no branch) 2
2 BNZ/BNE rel(at branch) 4 2 if Z=0 then PC← PC + rel - - - - - - - FC
BNZ/BNE rel(at no branch) 2
3 BC/BLO rel(at branch) 4 2 if C=1 then PC← PC + rel - - - - - - - F9
BC/BLO rel(at no branch) 2
4 BNC/BHS rel(at branch) 4 2 if C=0 then PC← PC + rel - - - - - - - F8
BNC/BHS rel(at no branch) 2
5 BN rel(at branch) 4 2 if N=1 then PC← PC + rel - - - - - - - FB
BN rel(at no branch) 2
6 BP rel(at branch) 4 2 if N=0 then PC← PC + rel - - - - - - - FA
BP rel(at no branch) 2
7 BLT rel(at branch) 4 2 if V N=1 then PC← PC + rel - - - - - - - FF
BLT rel(at no branch) 2
8 BGE rel(at branch) 4 2 if V N=0 then PC← PC + rel - - - - - - - FE
BGE rel(at no branch) 2
9 BBC dir:b,rel 5 3 if(dir:b)=0 then PC← PC + rel - - - - + - - B0 ~B7
10 BBS dir:b,rel 5 3 if(dir:b)=1 then PC← PC + rel - - - - + - - B8 ~BF
11 JMP @A 3 1 (PC)← (A) - - - - - - - E0
12 JMP ext 4 3 (PC)← ext - - - - - - - 21
13 CALLV #vct 7 1 vector call - - - - - - - E8~EF
14 CALL ext 6 3 subroutine call - - - - - - - 31
15 XCHW A,PC 3 1 (PC)← (A),(A)← (PC) + 1 - - dH - - - - F4
16 RET 6 1 return from subroutine - - - - - - - 20
17 RETI 8 1 return from interrupt - - - restore 30
Table 29.4-8 Other instructions
No. MNEMONIC ~ # Operation TL TH AH N Z V C OP CODE
1 PUSHW A 4 1 - - - - - - - 40
2 POPW A 3 1 - - dH - - - - 50
3 PUSHW IX 4 1 - - - - - - - 41
4 POPW IX 3 1 - - - - - - - 51
5 NOP 1 1 - - - - - - - 00
6 CLRC 1 1 - - - - - - R 81
7 SETC 1 1 - - - - - - S 91
8 CLRI 1 1 - - - - - - - 80
9 SETI 1 1 - - - - - - - 90
A
A
892
29.4.5 Instruction map
Table 29.4-9 "Instruction map of F2MC-8FX" shows the instruction map of F2MC-8FX.
893
CHAPTER 29 Basic Information
Instruction mapTable 29.4-9 Instruction map of F2MC-8FX
NO
P
MU
LU
A
ROLC
A
RORC
A
MO
V
A, #
d8
MO
V
A, d
ir
MO
V
A, @
IX+d
MO
V
A, @
EP
MO
V
A
, R0
MO
V
A
, R1
MO
V
A
, R2
MO
V
A
, R3
MO
V
A
, R4
MO
V
A
, R5
MO
V
A
, R6
MO
V
A
, R7
SWA
P
DIV
U
A
CMP
A
CMPW
A
CMP
A, #
d8
CMP
A
, dir
CMP
A, @
IX+d
CMP
A, @
EP
CMP
A
, R0
CMP
A
, R1
CMP
A
, R2
CMP
A
, R3
CMP
A
, R4
CMP
A
, R5
CMP
A
, R6
CMP
A
, R7
RET
JMP
addr
16
AD
DC
A
AD
DCW
A
AD
DC
A, #
d8
AD
DC
A
, dir
AD
DC
A, @
IX+d
AD
DC
A, @
EP
AD
DC
A
, R0
AD
DC
A
, R1
AD
DC
A
, R2
AD
DC
A
, R3
AD
DC
A
, R4
AD
DC
A
, R5
AD
DC
A
, R6
AD
DC
A
, R7
RETI
CALL
addr
16
SUBC
A
SUBC
W
A
SUBC
A, #
d8
SUBC
A
, dir
SUBC
A, @
IX+d
SUBC
A, @
EP
SUBC
A
, R0
SUBC
A
, R1
SUBC
A
, R2
SUBC
A
, R3
SUBC
A
, R4
SUBC
A
, R5
SUBC
A
, R6
SUBC
A
, R7
PUSH
W
A
PUSH
W
IX
XCH
A
, T
XCH
W
A
, T
MO
V
d
ir, A
MO
V
@IX
+d, A
MO
V
@EP
, A
MO
V
R
0, A
MO
V
R
1, A
MO
V
R
2, A
MO
V
R
3, A
MO
V
R
4, A
MO
V
R
5, A
MO
V
R
6, A
MO
V
R
7, A
POPW
A
POPW
IX
XO
R
A
XO
RW
A
XO
R
A, #
d8
XO
R
A
, dir
XO
R
A, @
IX+d
XO
R
A, @
EP
XO
R
A
, R0
XO
R
A
, R1
XO
R
A
, R2
XO
R
A
, R3
XO
R
A
, R4
XO
R
A
, R5
XO
R
A
, R6
XO
R
A
, R7
MO
V
A
, ext
MO
V
ex
t, A
AN
D
A
AN
DW
A
AN
D
A, #
d8
AN
D
A
, dir
AN
D
A, @
IX+d
AN
D
A, @
EP
AN
D
A
, R0
AN
D
A
, R1
AN
D
A
, R2
AN
D
A
, R3
AN
D
A
, R4
AN
D
A
, R5
AN
D
A
, R6
AN
D
A
, R7
MO
VW
A
, PS
MO
VW
PS
, A
OR
A
ORW
A
OR
A, #
d8
OR
A
, dir
OR
A, @
IX+d
OR
A, @
EP
OR
A
, R0
OR
A
, R1
OR
A
, R2
OR
A
, R3
OR
A
, R4
OR
A
, R5
OR
A
, R6
OR
A
, R7
CLRI
CLRC
MO
V
@A
, T
MO
VW
@A
, T
DA
A
MO
V
dir,
#d8
MO
V
@IX
+d,#
d8
MO
V
@
EP, #
d8
MO
V
R0,
#d8
MO
V
R1,
#d8
MO
V
R2,
#d8
MO
V
R3,
#d8
MO
V
R4,
#d8
MO
V
R5,
#d8
MO
V
R6,
#d8
MO
V
R7,
#d8
SETI
SETC
MO
V
A, @
A
MO
VW
A, @
A
DA
S
CMP
dir,
#d8
CMP
@IX
+d,#
d8
CMP
@
EP, #
d8
CMP
R0,
#d8
CMP
R1,
#d8
CMP
R2,
#d8
CMP
R3,
#d8
CMP
R4,
#d8
CMP
R5,
#d8
CMP
R6,
#d8
CMP
R7,
#d8
CLRB
d
ir : 0
CLRB
d
ir : 1
CLRB
d
ir : 2
CLRB
d
ir : 3
CLRB
d
ir : 4
CLRB
d
ir : 5
CLRB
d
ir : 6
CLRB
d
ir : 7
SETB
d
ir : 0
SETB
d
ir : 1
SETB
d
ir : 2
SETB
d
ir : 3
SETB
d
ir : 4
SETB
d
ir : 5
SETB
d
ir : 6
SETB
d
ir : 7
BBC
di
r : 0
, rel
BBC
di
r : 1
, rel
BBC
di
r : 2
, rel
BBC
di
r : 3
, rel
BBC
di
r : 4
, rel
BBC
di
r : 5
, rel
BBC
di
r : 6
, rel
BBC
di
r : 7
, rel
BBS
di
r : 0
, rel
BBS
di
r : 1
, rel
BBS
di
r : 2
, rel
BBS
di
r : 3
, rel
BBS
di
r : 4
, rel
BBS
di
r : 5
, rel
BBS
di
r : 6
, rel
BBS
di
r : 7
, rel
INCW
A
INCW
SP
INCW
IX
INCW
EP
MO
VW
A
, ext
MO
VW
A
, dir
MO
VW
A, @
IX+d
MO
VW
A, @
EP
INC
R0
INC
R1
INC
R2
INC
R3
INC
R4
INC
R5
INC
R6
INC
R7
DEC
W
A
DEC
W
SP
DEC
W
IX
DEC
W
EP
MO
VW
ex
t, A
MO
VW
d
ir, A
MO
VW
@IX
+d, A
MO
VW
@EP
, A
DEC
R0
DEC
R1
DEC
R2
DEC
R3
DEC
R4
DEC
R5
DEC
R6
DEC
R7
JMP
@A
MO
VW
SP
, A
MO
VW
IX
, A
MO
VW
EP
, A
MO
VW
A, #
d16
MO
VW
S
P, #
d16
MO
VW
I
X, #
d16
MO
VW
E
P, #
d16
CALL
V
#0
CALL
V
#1
CALL
V
#2
CALL
V
#3
CALL
V
#4
CALL
V
#5
CALL
V
#6
CALL
V
#7
MO
VW
A
, PC
MO
VW
A
, SP
MO
VW
A
, IX
MO
VW
A
, EP
XCH
W
A
, PC
XCH
W
A
, SP
XCH
W
A
, IX
XCH
W
A
, EP
BNC
rel
BC
rel
BP
rel
BN
rel
BNZ
rel
BZ
rel
BGE
rel
BLT
rel
894
Preliminary 2004.09.01
FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL
F2MCTM-8FX
8-bit Microcontroller
MB95FV100
HARDWARE MANUAL
Preliminary 2004.09.01
Published FUJITSU LIMITED Electronic Devices
Edited
896