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Author's Accepted Manuscript Experimental evaluation of a sleep-aware dynamic bandwidth allocation in a multi- ONU 10G-EPON testbed Dung Pham Van, Luca Valcarenghi, Michele Chincoli, Piero Castoldi PII: S1573-4277(14)00007-1 DOI: http://dx.doi.org/10.1016/j.osn.2014.01.006 Reference: OSN277 To appear in: Optical Switching and Networking Received date: 8 August 2013 Revised date: 13 January 2014 Accepted date: 15 January 2014 Cite this article as: Dung Pham Van, Luca Valcarenghi, Michele Chincoli, Piero Castoldi, Experimental evaluation of a sleep-aware dynamic bandwidth allocation in a multi-ONU 10G-EPON testbed, Optical Switching and Networking, http://dx.doi.org/10.1016/j.osn.2014.01.006 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting galley proof before it is published in its final citable form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain. www.elsevier.com/locate/osn
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Experimental evaluation of a sleep-aware dynamic bandwidth allocation in a multi-ONU 10G-EPON testbed

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Page 1: Experimental evaluation of a sleep-aware dynamic bandwidth allocation in a multi-ONU 10G-EPON testbed

Author's Accepted Manuscript

Experimental evaluation of a sleep-awaredynamic bandwidth allocation in a multi-ONU 10G-EPON testbed

Dung Pham Van, Luca Valcarenghi, MicheleChincoli, Piero Castoldi

PII: S1573-4277(14)00007-1DOI: http://dx.doi.org/10.1016/j.osn.2014.01.006Reference: OSN277

To appear in: Optical Switching and Networking

Received date: 8 August 2013Revised date: 13 January 2014Accepted date: 15 January 2014

Cite this article as: Dung Pham Van, Luca Valcarenghi, Michele Chincoli, PieroCastoldi, Experimental evaluation of a sleep-aware dynamic bandwidthallocation in a multi-ONU 10G-EPON testbed, Optical Switching and Networking,http://dx.doi.org/10.1016/j.osn.2014.01.006

This is a PDF file of an unedited manuscript that has been accepted forpublication. As a service to our customers we are providing this early version ofthe manuscript. The manuscript will undergo copyediting, typesetting, andreview of the resulting galley proof before it is published in its final citable form.Please note that during the production process errors may be discovered whichcould affect the content, and all legal disclaimers that apply to the journalpertain.

www.elsevier.com/locate/osn

Page 2: Experimental evaluation of a sleep-aware dynamic bandwidth allocation in a multi-ONU 10G-EPON testbed

Experimental Evaluation of a Sleep-Aware Dynamic Bandwidth Allocation in aMulti-ONU 10G-EPON Testbed

Dung Pham Vana, Luca Valcarenghia, Michele Chincolib, Piero Castoldia

aScuola Superiore Sant’Anna, Pisa, ItalybCNIT, Pisa, Italy

Abstract

In this paper, a sleep-aware dynamic bandwidth allocation (SDBA) algorithm and the supporting protocol areproposed for maximizing energy efficiency while satisfying all the end-user QoS constraints on downstream (DS) andupstream (US) transmissions in 10G-EPONs. The SDBA maximizes the Optical Network Unit (ONU) polling cycle toincrease the time for which each ONU sleeps outside the allocated timeslot. The polling cycle, however, is computedby considering QoS constraints (i.e., frame delay and loss rate) of all the transmissions given their finite data buffers toprovide the users with the requested QoS. Moreover, based on the observed traffic conditions, the SDBA can allow anONU to sleep for the whole or for a part of the allocated timeslot by assigning just enough bandwidth to transmit bothDS and US traffic accumulated during ONU sleep time. FGPA-based design and evaluation of 10G-EPON systemsfeaturing the proposed SDBA are thoroughly described. Experimental results show that the SDBA maximizes ONUenergy saving while guaranteeing the strictest end-user QoS requirements for any considered data rate scenario.

Keywords: Energy Efficiency, PONs, DBA, MPCP, FPGA, Testbed, QoS.

1. Introduction

The utilization of optical access networks is expectedto decrease the energy consumption per bit of currentxDSL-based wired access. However, it is estimated thatthe wired optical access networks (e.g., Passive OpticalNetworks (PON) or Point to Point (P2P) optical accessnetworks) will be the largest energy consumers amongthe wired optical networks for the next ten years yet [1].In [1], it is also shown that the ONUs contribute over65% to the total PON power consumption. Therefore,most of the studies conducted by research institutionsand standardization authorities have been targeting solu-tions for decreasing ONU energy consumption [2, 3, 4].

One of the most popular methods to decrease ONUenergy consumption is based on turning off the ONU,or some of its subsystems, in a cyclic manner. Thismethod, known as the cyclic sleep or fast sleep, hasbeen first introduced in ITU-T G.Sup45 [5], then stan-dardized for XG-PON [6]. Recently, a similar method

Email addresses: [email protected] (Dung Pham Van),[email protected] (Luca Valcarenghi),[email protected] (Michele Chincoli),[email protected] (Piero Castoldi)

has been standardized for EPON and 10G-EPON in theIEEE standard P1904.1 Service Interoperability in Eth-ernet Passive Optical Networks (SIEPON) as well [7].The challenging tasks of a cyclic sleep mechanism areto determine when the ONU is switched to sleep, forhow long an ONU can sleep, and how to combine thesleep mode with bandwidth allocation algorithms.

In the literature, there have been several studies thatimplement cyclic sleep in combination with bandwidthallocation algorithms, while considering certain levelsof quality of service (QoS) guarantee [8, 9, 10, 11, 12,13, 14]. To the best of the authors’ knowledge, mostof the studies deal with the issue of energy efficiencyin PONs by means of mathematical analysis or simula-tions and only few of them target experimental evalua-tion with only partial implementation of energy-efficientTDM-PONs [15, 16]. Moreover, although methods fordetermining ONU sleep time based on upstream (US)frame delay constraint only [11, 13], downstream (DS)frame delay constraint only [17], and on both US andDS delay constraints [12] have been thoroughly inves-tigated, implementation and, especially, experimentalevaluation is needed yet.

This paper proposes a sleep-aware dynamic band-width allocation (SDBA) scheme that maximizes ONU

Preprint submitted to Elsevier January 23, 2014

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energy saving while guaranteeing QoS requirements forboth US and DS traffic. Then, it implements and exper-imentally evaluates the proposed scheme in an FPGA-based testbed with multiple ONUs taking into accountasymmetric traffic.

The contribution of this paper is threefold. First,given the QoS constraints, in terms of frame delay andloss rate, and the system conditions, in terms of databuffer capacities, the cycle time is maximized to im-prove energy saving. Second, the SDBA is designed sothat within a cycle, the ONU enters sleep mode at mostone time thus reducing total overhead time required bythe ONU to transit between active and sleep state furtherimproving energy saving. Moreover, the SDBA per-forms online contentionless scheduling avoiding delayscaused by off-line bandwidth allocation thereof maxi-mizing ONU energy saving.

2. Related Work

In the SIEPON standard [7], mechanisms and pro-tocols for reducing the ONU power consumption aredescribed. The standard supports two power savingmodes. In the Tx mode, the ONU disables only thetransmit data path, whereas in the TRx mode, bothtransmit and receive data paths are disabled. The sav-ing mechanism can be in form of OLT-driven mecha-nism or Cooperative mechanism, i.e., sleep cycles areestablished based on mutual consent of the OLT andONU. The ONU may enter power saving mode for sin-gle sleep cycle or multiple sleep cycles. However, de-termining when to initiate a power saving cycle, howlong the ONU can sleep, and how to combine powersaving mechanisms with a specific bandwidth alloca-tion (DBA) scheme are outside the scope of the stan-dard leaving room to vendors and access providers forfurther investigation. For example, the authors in [18]performs a simple analysis to evaluate the power con-sumption dependence on the sleep duration using thespecified power-saving mechanisms. A variant of thecooperative sleep mechanism with variable ONU sleeptime determined as a function of traffic conditions isimplemented and experimentally evaluated for a 10G-EPON in [19, 20] yet with only one ONU system.

The introduction of power saving techniques hasa great impact on operations of existing DBA algo-rithms [21, 22] raising the necessity for designing powersaving aware DBA algorithms. In [8], the authors pro-pose and evaluate two energy management mechanisms,the upstream centric (UCS) and the downstream centric(DCS) scheme. In the UCS scheme, the ONU sleepsoutside its assigned US bandwidth allocation and US

and DS traffic transmission are locked. This means thatONU sleep time is highly US traffic dependent. In theDCS scheme, the ONU must be awake not only dur-ing its US bandwidth allocation but also when the OLTschedules DS transmission for it. However, the DStransmission scheduling depends on DS traffic only andit is not synchronized with US scheduling.

The authors in [11] propose a green bandwidth allo-cation (GBA) framework that implements batch-modetransmission at OLT and ONUs and an UCS-based dy-namic bandwidth allocation. Two analytical models areproposed [10, 17] to maximize ONU sleep time whilesatisfying either US or DS maximum delay constraints.In a bidirectional traffic scenario, in [11], the authorssuggest to set the ONU sleep time to the minimum be-tween DS-based and US-based sleep time and analyti-cally evaluate this in [12]. In [12], the authors furtherpropose a sleep-time sizing and scheduling scheme tooperate under the GBA framework. A thorough an-alytical model is utilized to compute the ONU sleeptime taking into account the expected delay for eachUS Class of Service (CoS). To avoid possible collisiondue to simultaneous accesses from multiple ONUs afterwaking up, a Sort-And-Shift (SAS) scheme is furtherproposed in [12].

The GBA performs off-line bandwidth alloca-tion [22]. However, as mentioned in [23], off-line band-width allocation causes extra delay and idle times be-tween successive cycles. Furthermore, under GBA,the ONU enters sleep mode twice in a sleep cycle:upon receiving the GATE message until its transmis-sion start time (OLT-based sleep); after sending theREPORT message and until receiving the next GATE(ONU-based sleep). Sleeping twice in a cycle impliestwo overhead times as well. In addition, with two sleepperiods in a cycle, the OLT needs to specify more pa-rameters for a GATE message increasing the complexityof the framework.

In [13], a modification of the Interleaved Pollingwith Adaptive Cycle Time (IPACT) [24] to enable ONUsleep mode is proposed. In particular, when an ONUrequests no bandwidth for US transmission, the OLTsends a grant message with a sleep notification and theassigned sleep period to trigger the sleep mode. Simi-larly to [10], the authors propose an analytical model toanalyze the mean US packet delay, then derive sleep pe-riod for a given maximum mean US packet delay. How-ever, this work limits the operations of the scheduler aswell as sleep time computation to depend only on UStraffic conditions and constraints.

The authors in [14] propose two sleep/doze dy-namic bandwidth allocation algorithms: just-in-time

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with varying polling cycle times (JIT) and just-in-time with fixed polling cycle times (J-FIT). The algo-rithms exploit the capability of quickly transitioningfrom doze/sleep to active state of ONUs equipped withvertical-cavity surface-emitting laser (VCSEL) [25].The DS and US transmission are locked within the USassigned timeslot so that the ONU can be switched offoutside the slot. Similarly to the GBA framework [11],the JIT and J-FIT perform off-line bandwidth alloca-tion. The JIT determines the cycle time based on theaverage US requested bandwidth, similar to IPACT al-gorithm [24]. Hence, when the US traffic load is low, thepossible ONU sleep time within a cycle is short. More-over, deciding timeslot duration based only on US trafficload can lead to the high traffic delay or/and traffic lossin case of asymmetric traffic scenarios, especially, forexample, in 10/1G-EPONs. On the contrary, the J-FITallows a longer ONU sleep time by fixing the pollingcycle time irrespective of either US or DS traffic load.

The SDBA scheme proposed in this paper aims atcombining cyclic sleep mechanisms with DBA whileconsidering QoS constraints. Differently from studiesbased on GBA framework [10, 11, 12, 17], the proposedSDBA scheme implements an online-based schedulingin attempt to avoid delay caused by offline schedul-ing while guaranteeing no collision among ONUs whenwaking up. Moreover, the SDBA schedules at most onesleep period for every ONU within one cycle reducingthe incurred overhead given the same amount of cy-cle time, further improving energy efficiency. Further-more, unlike [13] and [14], the SDBA considers bothUS and DS traffic conditions in the implementation ofsleep mode and sleep time determination.

3. Sleep-Aware Dynamic Bandwidth Allocation

This subsection describes the operations of the pro-posed Sleep-Aware Dynamic Bandwidth Allocation(SDBA) scheme and it details how the different quanti-ties involved in are computed. Such quantities are sum-marized in Table 1. If not specified in Table 1, they aredefined throughout the text.

3.1. SDBA Protocol Description

Fig. 1 illustrates the operation of the proposed SDBAscheme. The main characteristics of the proposedSDBA scheme consist in:

• the cycle time T c is maximized given the instan-taneous estimated data rates Rus

i and Rdsi , instan-

taneous average frame delay constraints Dusi and

Table 1: Relevant NotationsNotation Description Unit

RTTi OLT-ONU i Round trip time sT c Polling cycle time sTg Guard time between two timeslots s

T sloti Timeslot for OLT-ONU i pair s

Tmsg Message processing time in a cycle sLendata

i Data sub-slot for OLT-ONU i pair sLeni Transmission slot for OLT-ONU i pair sT sout

i Sleep time outside timeslot of ONU i sT sin

i Sleep time inside timeslot of ONU i sT si Total sleep time in a cycle of ONU i s

S tarti Start of timeslot for ONU i solt clk OLT global clock s

onu clki ONU i local clock sT oh

i ONU i overhead time sN Number of ONU in system ONU

Dusi Mean US i frame delay s

Ddsi Mean DS i frame delay s

Dusi Mean US i frame delay constraint s

Ddsi Mean DS i frame delay constraint s

D Global delay constraint sBus

i Capacity of US i data buffer bitBds

i Capacity of DS i data buffer bitRus

i Estimated US i data rate bit/sRds

i Estimated DS i data rate bit/sRcap Transmission capacity of system bit/sIusi US i average frame interarrival time s

Idsi DS i average frame interarrival time s

Ftime Data frame transmission time sFsize Data frame size byte

Ddsi , and limited data buffer capacities Bus

i and Bdsi ,

of all considered transmissions;

• within a cycle, all ONUs are assigned the sametimeslot T slot (i.e., T slot

i = T slot,∀i);

• within an assigned timeslot, depending on the datarate Rus

i and Rdsi , a minimum part of the timeslot,

i.e., the transmission slot Leni, is allocated for bothDS and US data and control message transmission;

• outside the allocated transmission slot, the ONU iis switched to sleep mode for saving energy.

In this paper, the considered QoS requirements in-clude the average frame delays and frame loss rates.The stricter (i.e., the lower) the QoS requirements are,the shorter the cycle time is (see section 3.2 for details).For example, in Fig. 1, the ONU 1 has the strictest QoS

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ONU1

ONU2

ONU3

ONU4

Data transmission Control message transmission

Slot11 Slot12 Slot13 Slot14 Slot21 Slot22 Slot23 Slot24

Sleep outside slot

Cycle1 Cycle2

Sleep inside slot Overhead time

Figure 1: Illustration of SDBA operation.

requirements that determine the cycle time for the wholeTDM-PON. ONU 1 utilizes all the assigned timeslotfor data and control message transmission and it enterssleep mode outside its timeslot only. Other ONUs areallocated the same timeslot duration as ONU 1. How-ever, because they have looser requirements, they onlyutilize part of the timeslot for data and control messagetransmission and enter sleep mode for the rest of thetimeslot and outside their timeslot. In SDBA, even ifONUs do not need to send/receive data, as in the caseof ONU 4 in Fig. 1, they are required to send/receiveREPORT/GATE message in every cycle. Hence, eachONU must wake up in its timeslot for the control mes-sage exchange at least.

The SDBA allocates bandwidth to all ONUs equallylike the static bandwidth allocation (static slot assign-ment) (SBA) [26] to guarantee the fairness among theONUs, i.e., to avoid the situation where an ONU occu-pies the media for most of the cycle time. However, thedynamic nature of the SDBA is that given the assignedtimeslot, it just allocates a minimum slot for both DSand US transmission in a locked fashion and enablesthe ONU to sleep for the rest of the cycle.

Fig. 2 details how the protocol supporting the SDBAscheme operates in case of two ONUs. A timeslot T slot

iis divided into three parts: a data sub-slot Lendata

i forUS and DS data transmission; a control sub-slot (T msg

at OLT and Tmsg + RTTi at the ONU i) for US and DScontrol message exchange; and a sleep slot T sin

i whereONU i is allowed to sleep. Tmsg is the time for process-ing a GATE message and a REPORT message in a times-lot. Tmsg is assumed to be constant and the same for theOLT and all ONUs. Within a cycle T c, the total sleeptime T si of ONU i consists of the sleep time outside itstimeslot T sout

i and of the sleep time inside the timeslotT sin

i . Hence, for every ONU i, T c is decomposed into

Lendatai , Tmsg + RTTi, T sin

i , and T souti . In Fig. 2, the

first index of an annotation indicates the cycle number,whereas the second index, if any, indicates the slot/ONUID within the cycle.

To perform online scheduling [23], the OLT main-tains a time pointer T sched that represents a futuretime up to which a timeslot has been allocated to anONU. A new timeslot assigned to ONU i has durationT slot

i = T c/N − Tg and start time S tarti = T sched + Tg.The OLT maintains a global clock olt clk, while eachONU i maintains its local clock onu clki that is assignedto olt clk embedded in GATE messages for synchroniza-tion purpose [27]. All protocol operations are based onthe comparison between the clocks and time variables.

In SDBA, both GATE and REPORTMPCPDU in legacyEPON are modified to include sleep-related parameters(as will be described in next section). In short, the ex-tended GATE contains the round trip time RTT measuredby the OLT [27] so that the ONU can use it to specify thedata sub-slot and control sub-slot duration given its as-signed transmission slot duration in the received GATE.Whereas, the extended REPORT contains US delay con-straint Dus

i and estimated US data rate Rusi . They are

used for bandwidth allocation computation at the OLT.

Initially, the two ONUs are assumed to be registeredso that the OLT is aware of all RTT s. The OLT grantseach ONU a minimal bandwidth for sending a REPORT

through which each ONU provides the OLT with neces-sary US information. Upon receiving the REPORT fromONU i, the OLT extracts Dus

i and Rusi . When all the ini-

tial REPORT messages are received, the OLT performs,only for the first normal polling cycle, off-line schedul-ing. First, the OLT computes T c, T slot

i , and GATE-relatedparameters including S tarti, T si, and Lendata

i for eachONU i (described in next subsection). Then, the OLTgenerates and sends consecutively GATE messages to all

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G1

US1

US1

DS1

R1

R1

G1 DS1

G1

G1Sleep

US2 R2Sleep

DS2 G2Sleep

DS2

US2 R2

G2

US1

US1

DS1

R1

R1

DS1

OLT

ONU1

ONU2

Len Len

Ts

G1

G1

Len

TsTs

Start

T

+RTT

G: Gate message R: Report message US: Upstream data DS: Downstream data

Start

Len

Start

G2

G2

in11

data11

in12

data12

in21

data21

11 12 21

11Len

12

1

Tg Tg

1

T11

slotT

12

slot T21

slot

Toh2

Toh1

Tidle

12

Len21

Tmsg

+RTT2

Tmsg

Sleep

Ts11

out

Tidle

11

Tmsg Tmsg Tmsg

c

US2 R2

DS2 G2

DS2

US2 R2

G2

Len

Ts

Start

in22

data22

22

Len22

Tg

T22

Toh2

Tmsg

Sleep

G1

G1

G2

G2

R1

R1

R2

R2

Offline initialization phase

Figure 2: Detailed operation of SDBA in case of two ONUs.

ONUs, each one containing S tarti and transmission slotduration Leni = Lendata

i + Tmsg. After generating theGATE for ONU i, T sched is updated to S tarti + T slot

i .When the GATE for ONU i is sent, the OLT starts buffer-ing DS traffic destined to ONU i and waits until olt clk= S tarti to transmit/receive traffic.

Upon receiving a GATE from the OLT, ONU i extractsolt clk embedded in the GATE and assigns onu clki tothat value. The ONU also extracts the updated RTT i

from the GATE. Then, it extracts S tarti and Leni, andcalculates idle time T idle

i from the current instant of timeuntil the start of the next transmission slot (i.e., T idle

i =

S tarti - onu clki (see Fig. 2)). If T idlei is greater than

ONU i’s overhead time T ohi [2], the ONU transits to

SLEEP state, during which its transceiver is switchedoff for saving energy while a sleep timer is incrementedand US traffic is buffered. When the sleep timer expires,the ONU transits to and sojourns in POST SLEEP statefor T oh

i time to perform waking up operation. Other-wise, it stays awake (i.e., ACTIVE state) and buffersUS traffic. In any case, when onu clki = S tarti, theONU enters data sub-slot (i.e., ACTIVE state) to trans-mit/receive US/DS traffic to/from the OLT.

Being aware of the bandwidth needed for control sub-slot, when onu clki = S tarti+Leni−Tmsg−RTTi, ONUi stops transmitting US traffic to generate and send aREPORT message carrying updated Dus

i and Rusi to the

OLT. As ONU i transmitter is idle since the REPORT

is sent until when the replying GATE is received, i.e.,RTTi, depending on whether RTT i is greater than thesleep/doze overhead time [14], the ONU i can considerto enter sleep/doze mode [6] to further save energy.

Upon receiving a REPORT from ONU i, the OLT stopstransmitting DS traffic. Again, it extracts Dus

i and Rusi .

The OLT computes parameters for the GATE to ONU iusing new values of Rds

i , and Rusi and current T c. Then,

the GATE message containing newly computed S tart i

and Leni is generated and sent to the ONU. The OLT,then, updates the value of T sched to S tart i + T slot

i ,sends the GATE, and starts buffering DS traffic. If theREPORT is the last one in a cycle to receive, the OLTrecomputes the cycle time T c for the next cycle.

3.2. Cycle Time and Transmission Slot Computation

The determination of cycle time and transmission slotduration described in the previous section is one of themain challenges of the SDBA. The two quantities arecomputed based on the strictest QoS requirements ofall the traffic sent/received by all the ONUs: no frameloss and the minimum required average frame delay.Therefore, even though there may exist different traf-fic belonging to different Classes of Service (CoS) withlooser requirements, the proposed SDBA treats all thedata traffic as it belonged to the CoS with the strictest re-quirements. Determining cycle time and differentiatingtransmission slot duration based on QoS requirementsof each CoS to which data traffic belongs is not consid-ered in this paper and requires further investigation.

To compute T c for the next cycle, the OLT needs Dusi ,

Ddsi , Rus

i , Rusi . While the DS variables are estimated and

stored in runtime at the OLT, the US variables are car-ried by means of the REPORT messages. Dus

i is assumedto be loaded into a table in the ONU i memory [28].The OLT and ONUs monitor data frames arriving at the

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user network interface (UNI) to specify average frameinterarrival times Ius

i , Idsi and to estimate Rus

i and Rdsi .

Without loss of generality, this paper assumes that theOLT is equipped with a DS queue per ONU and eachONU is equipped with a US queue. Let Bus

i /Rusi and

Bdsi /R

dsi be the US and DS buffer capacities (in second)

for the OLT-ONU i pair. T capi is defined as buffering

time that avoids both US i and DS i frame loss:

T capi = min

⎧⎪⎪⎨⎪⎪⎩Bus

i −C

Rusi

,Bds

i −C

Rdsi

⎫⎪⎪⎬⎪⎪⎭ , (1)

where C is a safety margin (in bits). Indeed, becauseRus

i and Rdsi are estimated values, there is a possibil-

ity that the actual traffic arrives more heavily than ex-pected causing the buffer overflow. The safety marginC is to leave some space in the buffer to avoid this situa-tion. The longer the margin, the lower the probability offrame loss, yet the shorter the value of T cap

i . Thus, thebuffer capacity T cap that avoids frame loss in the wholesystem can be defined as:

T cap = min{T cap

1 , Tcap2 , . . . , T

capN

}. (2)

By assuming that an ONU can sleep for almost thewhole cycle time T c, i.e., there is no data during the cy-cle and Tmsg is negligible, it results that, to avoid framelosses:

T c ≤ T cap. (3)

The cycle time computation given an average delayconstraint is based on the mean frame delay in a pollingcycle. This paper assumes that the data arrivals of alltransmissions are Poisson-distributed, data frame sizeFsize is constant (similar to [29]), and frame transmis-sion time Ftime is negligible compared to average frameinterarrival times. Also data buffers are assumed to beable to accommodate all incoming data frames during asleep period. Let Mus

i be the number of US data framesthat arrive to the US buffer of ONU i within T c. It ispossible to write:

T c = Musi Ius

i . (4)

Then, the frame of order M usi arriving to the buffer

at last waits 0 second before being sent. The frame oforder Mus

i −1 has to wait Iusi +Ftime � Ius

i seconds beforebeing sent, and so on. Thus, the average frame delay ofthis US transmission is computed as:

Dusi =

Iusi + 2Ius

i ... + (Musi − 1)Ius

i

Musi

=(Mus

i − 1)Iusi

2.(5)

From Eq.(4) and Eq.(5), it is possible to write:

Dusi =

T c − Iusi

2. (6)

To guarantee that no US transmission violates theglobal average frame delay constraint in the next cy-cle D = min

{Dus

1 , Dds1 , D

us2 , D

ds2 , . . . , D

usN , D

dsN

}, for any

i, Dusi must satisfy:

Dusi ≤ D. (7)

From Eq.(6), for any i, T c must satisfy:

T c ≤ 2D + Iusi . (8)

By assuming Iusi is negligible with respect to D, and

applying the same derivation to DS transmissions, toguarantee the average frame delay constraints for wholesystem, T c must satisfy the following constraint:

T c ≤ 2D. (9)

Finally, to fulfill both buffer capacity and average de-lay constraint, from Eq.(3) and Eq.(9), T c must be com-puted as:

T c = min {2D, T cap} . (10)

The fact that T c for the next cycle is computed at theend of the current cycle using updated values of R ds

i , Rusi ,

Ddsi , and Dus

i enables the SDBA to limit frame delaysand avoid frame losses for the next cycle. Meanwhile,GATE parameters are computed whenever a REPORT isreceived using current value of T c and updated valuesof Rds

i and Rusi ensuring that the next transmission slot is

allocated to support both US and DS transmission.T slot

i is computed as in the SBA [26]:

T sloti = T slot =

T c

N− Tg. (11)

ONU i sleep time T si can be written as:

T si = T souti + T sin

i . (12)

T souti can be expressed as a function of T c as follows:

T souti = T c − T slot =

N − 1N

T c + Tg. (13)

As mentioned earlier, a timeslot T sloti is divided into

three components. Thus, it is possible to write:

T slot = T sini + Lendata

i + Tmsg. (14)

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Lendatai of the OLT-ONU i pair in the next cycle is the

time required by both the OLT and the ONU to transmitall data arriving from the current time, the time of gen-erating the current GATE message, until start of the nexttimeslot. Assume that the interval from the current GATEgeneration to the next one is equal to the current cycletime T c. For example, this is the time from G1 in T slot

11to G1 in T slot

21 in Fig. 2. Then, Lendatai is the time needed

to transmit data arriving during T c − Lendatai . Let Rmax

ibe the maximum between the DS and US data rate, i.e.,Rmax

i = max{Rds

i ,Rusi

}. Lendata

i for the next transmissionslot is computed as:

Lendatai = (T c − Lendata

i )Rmax

i

Rcap. (15)

Hence, Lendatai is derived as:

Lendatai = T c Rmax

i

Rmaxi + Rcap

. (16)

From Eq.(12), (13), (14), and (16), T s i is derived as:

T si = T c Rcap

Rmaxi + Rcap

− Tmsg. (17)

In the SDBA scheme, while T slot is equal for allONUs, T si and Lendata

i are variable. From Eq.(16) andEq.(17), given the cycle time T c, Lendata

i and T si aredynamically adjusted accordingly to the traffic charac-teristics (i.e., Rmax

i ) and system configuration (i.e., Rcapi

and Tmsg). Furthermore, from Eq.(17), given a systemconfiguration and a T c, the total sleep time of an ONU idepends only on the US and DS data rate from/to it, i.e.,Rmax

i .Note that, on one hand, because the US data sub-

slot is Lendatai − RTTi, Lendata

i must be lower boundedby RTTi. On the other hand, from Eq.(14), Len data

i =

T sloti − Tmsg − T sin

i ≤ T sloti − Tmsg. Therefore, if Eq.(16)

provides a value either lower than RTT i or higher thanT slot

i − Tmsg, Lendatai is set to the corresponding bound.

It is worth to note that, in this paper, the delay con-straint based cycle time is computed with the assump-tion that the frame transmission time is negligible withrespect to average frame interarrival times. However,in the scenarios where frames are generated in an un-predictable burst, different analytical models would berequired (e.g., solutions proposed in [12, 13, 17]).

4. Hardware Implementation

4.1. System OverviewFig. 3 shows the architecture and the functional

blocks of the 10G-EPON OLT and ONU implementa-tion featuring the SDBA scheme. The main blocks are:

the SDBA Ctrl, the MAC Ctrl, the Multipoint Ctrl, andthe Ethernet Subsystem. In this paper, all the ONUs areimplemented sharing a single common Ethernet Subsys-tem. All the blocks are implemented in FPGAs. Themain differences between the OLT and the ONU imple-mentation are in the SDBA Ctrl block.

The two SDBA Ctrls implement the operation of theSDBA scheme as described in previous section. TheOLT SDBA Ctrl is responsible for ONU bandwidth al-location. It interacts with the replicas of OLT MACCtrl, one per ONU, to assign transmission slot and en-able DS/US data frame and control message transmis-sion to/from each ONU. Meanwhile, the ONU SDBACtrl is responsible for bandwidth consumption and sleepmode controlling. It has multiple instantiations, each in-teracts with the corresponding instance of ONU MACCtrl to enable US/DS data frame and control messagetransmission and to/from OLT. Also each ONU SDBACtrl drives ONU state accordingly to its assigned trans-mission slots. In both OLT design and ONU design, theSDBA Ctrls inform the Multipoint Ctrl the transmissionslots assigned to the OLT-ONU pairs to facilitate the se-lection of output stream from the appropriate MAC Ctrlinstance to send to the lower layer.

The MAC Ctrl blocks implemented in OLT and ONUdesign are a variant of the standard Multipoint MACControl for 10G-EPON specified in clause 77 section3, IEEE 802.3-2012 [27]. To offer a point-to-point em-ulation (P2PE) service between the OLT and the ONUs,both OLT design and ONU design have the same num-ber of MAC Ctrl instances that is equal to the numberof ONUs. In this work, however, because DS and UStransmission are locked in a timeslot for each OLT-ONUpair, the OLT does not send downstream broadcast traf-fic to ONUs. Therefore, the auxiliary single copy broad-cast (SCB) instance of MAC Ctrl defined in the standardfor handling downstream broadcast traffic, is not imple-mented in the OLT design.

Each instance of the MAC Ctrl consists of followingblocks: GATE Processing, REPORT Processing, Gen,Buffer Ctrl, Control Parser, and a Sleep finite state ma-chine (FSM) in the ONU MAC Ctrl block. Amongthose, the Control Parser, REPORT Processing, andGATE Processing are implemented as specified in sub-section 77.2.2, 77.3.4, and 77.3.5 in the standard, re-spectively. In this paper, however, instead of generatingthe message itself, the OLT GATE Processing and ONUREPORT Processing trigger the DS Gen and US Genfor message generation. Hence, the Gen is responsiblefor generating both synthetic data frames and controlmessages. Buffer Ctrl includes a Data FIFO and a CtrlFIFO for storing data and control messages so that the

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OLT SDBA Ctrl

DS Gen

Gate Processing

DS DataFIFO

DS CtrlFIFO

Report Processing

ControlParser

Multipoint TxCtrl

MAC Ctrl N

Downstream

Upstream

10G-MAC

10GBASER

OLT design ONU design

Buffer Ctrl

US Gen

Report Processing

US DataFIFO

US CtrlFIFO

Gate Processing

ControlParser

Multipoint TxCtrl

MAC Ctrl N

10G-MAC

10GBASER

Buffer Ctrl

ONUi SDBA SchedulerONUi SDBA Scheduler

ONU1 SDBA Ctrl

Multipoint RxCtrl

Multipoint RxCtrl

Control path Data and control path

Sleep FSM

Multipoint CtrlMultipoint Ctrl

Ethernet SubsystemEthernet Subsystem

MAC Ctrl 1MAC Ctrl 1

AlteraIP cores

Figure 3: Energy efficient 10G-EPON system architecture featuring SDBA scheme.

messages can have priority over the data frames. TheONU Sleep FSM drives ONU states accordingly to thestart and duration of the assigned transmission slot.

The Multipoint Ctrl comprises Multipoint Tx Ctrland Multipoint Rx Ctrl that realize point-to-multipointtransmission on a single underlying Ethernet subsystem.The Multipoint Tx block is responsible for multiplexingthe incoming data from different instances of MAC Ctrlthen forwarding all to the common underlying Ethernetsubsystem as specified in subsection 77.2.2 in the stan-dard. It allows only one MAC Ctrl instance to transmitat any given time. Conversely, the Multipoint Rx Ctrlis responsible for demultiplexing then forwarding theincoming data from the common underlying Ethernetsubsystem to destinated instance of MAC Ctrl.

The Ethernet Subsystem including a 10 Gb/s MAClayer and a 10 Gb/s Physical layer is realized by utiliz-ing two Altera Intellectual Property (IP) cores. In partic-ular, the Altera 10GbE MAC is used for 10 Gb/s MAClayer while the Altera 10G BASE-R PHY IP is used for10 Gb/s PHY layer, respectively.

4.2. Data Path Description

Transmit PathIn the transmit path, the MAC Ctrl generates data

frames based on the traffic arrival model implemented

in the US Gen and DS Gen blocks and stores themin the corresponding Data FIFO. When requested bythe SDBA Ctrl to generate a control message, the OLTGATE Processing/ONU REPORT Processing specifiesrelevant parameters. The message is then generated bythe Gen block, and forwarded to Ctrl FIFO.

As the REPORT and GATE message are also used asa keep-alive mechanism [27], if the SDBA Ctrl doesnot issue a request to generate a REPORT/GATE mes-sage for a predefined period of time, the ONU REPORTprocessing/OLT GATE processing is also responsiblefor triggering generation of a periodic REPORT/GATE.The timeout for the REPORT and GATE message arereport timeout and gate timeout, respectively, as spec-ified in 77.3.4.2 and 64.3.5.2 in the standard.

In both the OLT and the ONU design, the SDBA Ctrlpasses information about allocated transmission slot tothe MAC Ctrl and the Multipoint Ctrl. Based on thisinformation, the MAC Ctrl manages operation of theBuffer Ctrl, i.e., buffering or forwarding data frames/control messages. Meanwhile, based on this informa-tion, the Multipoint Ctrl decides to take data frames andmessages from the associated instance of MAC Ctrl andforwards them to the common underlying MAC layer.

Receive PathIn the receive path, the Multipoint Ctrl receives data

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DestAddr[48]

SourceAddr[48]

Length/Type0x8808

Opcode0x0002

Timestamp[64]

CRC[32]

Message length = 64 bytes

Num of grants/flag[8]

Start[64]

Pad[152]

Len[32]

Num of grants 001

Discovery/normal Gate0

Force report bitmap0001

(a) Format of extended GATE message

DestAddr[48]

SourceAddr[48]

Length/Type0x8808

Opcode0x0003

Timestamp[64]

CRC[32]Num queue

sets 0x01

Bitmap0x01

Pad[184]

Queuereport [16]

(b) Format of extended REPORT message

Data rate [32]

Delayallow [32]

Pad[192]

RTT[32]

Figure 4: Control message format.

frames and control messages from the common MAClayer, identifies MAC address of the sending ONU, andforwards them to corresponding instance of MAC Ctrl.

The Control Parser identifies whether the receivedframe is a GATE/REPORT message or not. If so, the RTT(at the OLT design only) and the timestampdrift, i.e., thedifference between the local clock and received clockembedded in the message are measured. An error insynchronization process is reported if timestampdrift isgreater than guardThreshold as described in 77.2.2 inthe standard. The synchronization error is used for de-bugging purpose in this paper only.

The OLT REPORT Processing/ONU GATE Process-ing extracts relevant US/DS information from the re-ceived REPORT and GATE messages. The OLT REPORTProcessing passes extracted US information to the OLTSDBA Ctrl for computing bandwidth for the next trans-mission slot. Meanwhile, the ONU GATE Process-ing passes DS extracted information to ONU SDBACtrl for specifying its transmission slot. The ONUSDBA Ctrl also drives its Sleep FSM state, i.e., SLEEP,POST SLEEP, or ACTIVE accordingly to the start ofits assigned transmission slot. In this paper, becausethe FPGA-based implementation aims at verifying thefunctionalities of the proposed SDBA scheme, and allthe ONUs are implemented sharing a single transceiver,the ONU transceivers are not physically turned off dur-ing the SLEEP state.

The collected statistics includes bandwidth utiliza-tion, data volume, number of messages, average framedelays, frame loss rates, time portion in each ONU state.The statistics for the receive path are collected in theControl Parser, the ONU GATE Processing, the OLTREPORT Processing, while the statistics for the trans-mit path are collected in the DS Gen and the US Gen,the OLT GATE Processing, the ONU REPORT Process-ing, the Data FIFO, and the Ctrl FIFO. The performancestatistics related to bandwidth assignment are collectedby the two SDBA Ctrls.

4.3. Control Message Format

The control messages used in this paper are extendedGATE and REPORT similar to the conventional GATE andREPORT MPCPDU defined in [27], subsection 77.3.6.For the simplicity, the extended GATE carries a singlegrant and the extended REPORT carries a single queueset. Furthermore, the two types of message carry someadditional parameters in their padding bits. Fig. 4(a)shows the format of the extended GATE message. TheGATE message has the Discovery/normal Gate field setto 0 indicating normal type of GATE MPCPDU. Thenumber of grants field is fixed at 1. The Force reportbitmap field is set to 1 requesting the receiving ONUto send a REPORT in any of assigned timeslot. TheGATE message contains a 32-bit field RTT as the mea-sured RTT the OLT wants to inform ONUs. Fig. 4 (b)shows the format of the extended REPORTmessage. TheREPORT message contains a 32-bit field Data rate as theinstantaneous US data rate Rus

i estimated by the sendingONU. Besides, another 32-bit field Delay allow is usedto carry the updated US delay constraint.

5. Experimental Evaluation

5.1. Testbed Configuration

Because of the hardware resource limitation, onlytwo ONUs are implemented. The two ONUs share asingle 10 Gb/s MAC and 10GBASE-R (see Fig. 3). Thetestbed configuration is illustrated as in Fig. 5(a). Thatis, there is only one physical channel consisting of oneupstream transmission link and one downstream trans-mission link between the OLT design and the ONU de-sign rather than the tree-based topology of legacy PONs.As discussed earlier, at the ONU design, the Multi-point Ctrl plays a role of a multiplexer/demultiplexerthat combines/splits US/DS traffic to forward data to theMAC layer/MAC Ctrl block. By sharing the same phys-ical transmission, this configuration works as long as the

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OLT

OLT FPGA

ONU1

ONU FPGA

ONU2

MultipiontTx/RxCtrlDS

US

(a) Testbed Configuration (b) Testbed Picture

Figure 5: Testbed of energy efficient 10G-EPON featuring SDBA.

total US data rate, i.e., Rus1 + Rus

2 , is less than or equal tothe transmission rate (i.e., Rcap).

Fig. 5(b) shows a picture of the real testbed. Theenergy-efficient 10G-EPON system is implemented intwo Altera Transceiver Signal Integrity DevelopmentKits equipped with Stratix IV GT edition FPGA (i.e.,featured device EP4S100G2F40I1N) that is capableof supporting up to 11.3 Gb/s. The FPGA deviceis featured with embedded electrical transceivers thatprovide physical coding sublayer (PCS) and physicalmedium attachment (PMA) support for 10 Gb/s trans-mit and receive channels. The development kits pro-vide SubMiniature version A (SMA) connectors to sup-port transceiver channels from/to the FPGA device. The(SMA) inputs and outputs of the OLT and the ONU canbe either directly interconnected by means of coaxialcables or connected to the optical module SFP/SFP+ torealize the optical transmission as shown by the figure.

The main purpose of the experiments is to verify thecorrectness of the proposed sleep protocol and the en-ergy efficient 10G-EPON design. Thus, the input trafficis synthetic traffic generated by the generators inside theFPGA designs. Having actual traffic from real applica-tions or a data trace requires the FPGA designs to inter-face with external traffic feeders. Such implementationdepends on the available interfaces provided by the uti-lized FPGA boards (e.g., Ethernet port), and requiresmore investigation.

5.2. Performance Metrics

The considered performance metrics include averageenergy saving, average frame delay and average frameloss rate, and bandwidth utilization. Frame delay ismeasured as the buffering delay, i.e., the time the framestays in data buffer. Frame loss rate is the ratio betweenthe number of lost frames and the total number of gen-erated frames. Bandwidth utilization is defined as theratio between the transmission slot duration of ONU i

and the cycle duration, i.e., T slot/T c in case of no sleepmode enabled and Leni/T c in the other cases.

Average energy saving of ONU i is computed as therelative energy consumption decrease with respect tothe energy consumption without sleep mode enabled:

ηi = 1−Pai T active

i + Psi T sleep

i

Pai (T active

i + T sleepi )

=(Pa

i − Psi )T

sleepi

Pai (T active

i + T sleepi )

,(18)

where Pai and Ps

i are the power consumption of ONU i

in active and sleep state; T activei and T sleep

i are the aver-age time the ONU i sojourns in active and sleep statewithin one polling cycle in experiments, respectively.Note that, T active

i includes also overhead time T ohi be-

cause ONUs are assumed to be fully powered duringthe POST SLEEP state.

From the SDBA operation, it is possible to find a the-oretical energy saving ηre f

i for an ONU i by substituting

T activei = Leni and T sleep

i = T si in Eq.( 18):

ηre fi =

(Pai − Ps

i )T si

Pai (Leni + T si)

, (19)

where T si and Leni are computed using configured testparameters.

5.3. Experiment Scenarios and Parameters

To compare the performance of the proposed SDBAscheme with existing solutions, this paper implementsthe J-FIT [14] that also synchronizes the US and DStransmission within an allocated transmission slot andallows the ONU to sleep/doze outside it. However,the J-FIT performs an off-line scheduling, i.e., theOLT computes transmission duration for all ONUs atonce when all REPORTs are received, then sends theGATE messages to all ONUs in sequence. Further-more, the J-FIT determines transmission slot duration

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Table 2: Hardware Test Constants and ParametersName Variable Value Unit

Number of ONUs N 1 and 2 ONUTransmission rate Rcap 10 Gb/s

US buffer size Bus1 , Bus

2 1 MbDS buffer size Bds

1 , Bds2 1 Mb

Safety margin C 0.1 or 0 MbGuard time Tg 0.001 ms

GATE timeout gate timeout 50 msREPORT timeout report timeout 50 ms

Message time Tmsg 0.0256 msRound-trip time RTTi 0.006 msOverhead time T oh

i 0.3 msONU power ratio Pa

i /Psi 10 times

DS data rate 1 Rds1 varying Mb/s

US data rate 1 Rus1 128 Mb/s

DS data rate 2 Rds2 128 Mb/s

US data rate 2 Rus2 128 Mb/s

Delay constraint D 2 or 4 ms

based only on the average US requested bandwidth re-ported in REPORT messages irrespective of the DS traf-fic. To provide a reference point for the comparison,the value of T c computed using Eq.( 10) is used forboth SDBA and J-FIT. Instead of using the bandwidthrequest in REPORTs, in the J-FIT implemented in thispaper, Lendata

i is determined based on the average of allRus

i , i.e., Rus. Thus, in J-FIT, Eq.( 16) becomes:

Lendatai = T c Rus

Rus + Rcap. (20)

In addition, to compare the SDBA performance withsystems without sleep mode enable, this paper also im-plements a 10G-EPON system featuring static band-width allocation (SBA). The three systems are denotedas follows: System A consists of one OLT and twoONUs with SDBA enabled; System B consists of oneOLT and two ONUs with J-FIT enabled; and System Cconsists of one OLT and two ONUs with SBA enabled.Three experiment scenarios are conducted as follows:

Experiment Scenario 1:This experiment scenario is to compare the perfor-

mance of SDBA with J-FIT and SBA. The parametersC and constraint D are fixed at 1 Mb and 2 ms, respec-tively. Frame size Fsize is constant and set to 1250 bytes.Results of one ONU with different DS/US data rate ra-tios are shown. Performance metrics include averageenergy saving, frame delay, frame loss rate, and band-width utilization.

Experiment Scenario 2:

Figure 6: Example of On-chip verification at ONU design.

In this scenario, the impact of delay constraint D andsafety margin C on the performance of SDBA is investi-gated. Frame size Fsize is constant and set to 1250 bytes.Results of one ONU with different DS/US data rate ra-tios are shown. Performance metrics include averageenergy saving and frame loss rate.

Experiment Scenario 3:In this scenario, the impact of configured traffic pro-

file on the performance of SDBA is investigated. Pois-son traffic with geometrically distributed burst size [30]is synthesized to compare with the case of constant burstsize (i.e, one frame). Only downstream transmissions(from OLT to ONU1 and ONU2) are fed by geometri-cally distributed traffic. Results of one ONU with dif-ferent DS/US data rate ratios are shown. Performancemetrics include average energy saving, frame delay, andframe loss rate.

Constants and parameters are summarized in Tab. 2.The frame arrival process is Poisson. For all transmis-sions, OLT and ONU are programmed to run the experi-ment for a configured experiment duration, e.g., 1, 5, or10 seconds. Due to the limited memory of the utilizedFPGAs, the OLT and ONUs all utilize a 1 Mb FIFO asdata buffer. OLT-ONU 2 transmission is configured tohave symmetric traffic with constant data rate. Rus

1 isconstant and Rds

1 is varying. The real waking-up time ofthe FPGA transceivers is found to be ≈ 0.3 ms. Hence,the value of T oh

i is set to 0.3. The power ratio Pai /P

si [31]

is assumed to be 10 that is set by reference to [32].In this work, however, the two ONU’ transceivers are

not physically turned off because they are arranged inthe same transceiver block on the FPGA, whereas thedevice supports to power down the whole block onlyrather than individual transceivers. Besides, because theexperiments aim at performing functional verification ofthe 10G-EPON system featuring the proposed SDBAscheme, the testbed is configured to have short SMAcables connecting OLT and ONUs (see Fig. 5). In par-

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ticular, the value of RTT is 0.006 ms for both ONUs.Because of such short RTT , the additional sleep/dozemode mentioned in section 3 is not evaluated. How-ever, evaluation with the longer RTT can be realized byeither installing an optical distribution network (ODN)with long fiber links or by designing a delay elementin the data paths inside the FPGA designs. In the lat-ter case, for example, to have a RTT of 0.1 ms (equalto 10-km fiber link), the design requires about 1.2 Mbmemory. This is left for future implementation.

5.4. On-chip Verification

Fig. 6 shows an example of transition among statesof the two ONUs as a snapshot captured from AlteraSignalTap II, an On-chip debugging tool. Altera Signal-Tap II allows designers to observe behavior of the sig-nals and registers of the design running inside the FPGAchip in real time. The tap is captured at the ONU designwhen running experiments for the System A.

The figure shows that the behavior of the two ONUsfollows the SDBA protocol described in section 2. Inparticular, the transmission slots of the two ONUs arenext to each other in a TDM allocation fashion. EachONU successfully transits among three states ACTIVE,SLEEP, and POST SLEEP. For example, the transi-tion to SLEEP state of ONU1 is triggered by the bi-nary signal sleep1 trigger that is asserted right af-ter a GATE message is received (indicated by the as-sertion of the signal Gate1 rcvd). When waking up,the ONU1 transmits US traffic and receives DS trafficin burst (indicated by the two signals DS1 frame rcvd

and US1 frame sent). Moreover, the reception ofGATEmessage (indicated by the signal Gate1 rcvd andthe dispatch of REPORTmessage (indicated by the signalReport1 sent occur within the reserved control sub-slot (indicated by the signal Ctrl1 slot), while thedata transmission takes place only during ACTIVE stateand outside the control sub-slot.

5.5. Experimental Results

For each set of data rates, the experiments are runwith multiple random seeds for traffic generation. Theobtained results are within a relative confidence inter-val of 92% or better at 95% confidence level for all theperformance metrics.

Fig. 7 shows the cycle time with varying data rateof downstream transmission to ONU1 for two values ofdelay constraints, i.e., 2 ms and 4 ms. The same valueof cycle time is used in all the three 10G-EPON sys-tems, i.e., system with SDBA enabled, with J-FIT en-abled, and without sleep mode enabled, in experiment

Figure 7: Cycle time with various delay constraints.

scenarios for performance comparison. As seen in thefigure, given the fixed values of DS2 and US2, and US1data rate (128 Mb/s), the cycle time T c decreases whenDS1 data rate Rds

1 increases and is greater than a cer-tain value regardless of the minimum delay constraint.This is because when Rds

1 is high so that T cap ≤ 2D, T c

is set to the T cap that is inversely proportional to Rds1

(see Eq.( 10)). By solving the relevant equations, i.e.,Eq.( 1, 2), and Eq.( 10), it is possible to find that T c isset to the T cap when Rds

1 ≥ 249.3 Mb/s. The value ofT c is decreased when Rds

1 increases in order to avoid theframe loss given the limited data buffer utilized.

Fig. 8(a) shows the energy saving obtained by ONU1 in scenario 1 together with the upper bound saving ofthe SDBA scheme. From the figure, given the same cy-cle time and same data rate configuration, the J-FIT andSDBA achieve similar energy saving when Rds

1 < Rus1 ,.

But when Rds1 ≥ Rus

1 , the J-FIT saves some percentagesmore then the SDBA. Meanwhile, without sleep modeenabled, the SBA saves no energy. The actual savingof SDBA approximates its upper bound saving for anydata rate ratio, that is, the saving is maximized. In thefigure, for both J-FIT and SDBA, the saving decreasewhen Rds

1 ≥ 249.3 Mb/s as a result of lower value of T c.

Fig. 8(b) shows the average frame delays experiencedby US and DS traffic in scenario 1. As seen, the SBAoffers the lowest frame delays for both US and DS traf-fic as traffic is only buffered outside the ONU’s timeslot.The US delay of both J-FIT and SDBA are similar forany range of Rds

1 because of the same cycle time is cho-sen and the data sub-slot duration is always enough forUS traffic in both cases. For the DS delay, when Rds

1≤ Rus1 , as the J-FIT and SDBA choose the same dura-

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(a) Average energy saving (b) Average frame delay

Figure 8: Energy saving and frame delay, SDBA vs other schemes.

(a) Average downstream frame loss rate (b) Average bandwidth utilization

Figure 9: Frame loss rate and bandwidth utilization, SDBA vs other schemes.

(a) Average energy saving (b) Average DS and US frame loss rate

Figure 10: SDBA performance with various delay constraints and safety margins.

13

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(a) Average energy saving (b) Average DS frame delay

Figure 11: SDBA performance with different traffic profiles.

tion of data sub-slot (see Eq.(16)) and Eq.(20), the DSdelay are similar in the two schemes. However, whenRds

1 ≥ Rus1 , as the J-FIT determines data sub-slot based

only Rus1 , the DS frame delay suddenly increases, higher

than the delay constraint (2 ms). The delay curves, es-pecially the US delay, have the same trend as the energysaving in Fig. 8(a) because the T c is shortened to avoidthe frame loss. As seen, both US and DS frame delayincurred in SDBA are bounded by the constraint delayfor any considered data rate ratio.

Fig. 9(a) shows the DS average frame loss rate ob-served in scenario 1. The SBA offers no frame loss.Thanks to the safety margin C set to 0.1 Mb, the SDBAguarantees also no frame loss for any data rate ratios.The J-FIT also offers no frame loss when Rds

1 ≤ Rus1 .

However, when Rds1 ≥ Rus

1 , the incurred DS frame lossrate is uncontrollable. This is because even though thetimeslot is long enough for transmitting both DS andUS traffic, the J-FIT decides the data sub-slot to favoronly US traffic making the DS buffer overflow. Combin-ing with the energy saving obtained in Fig. 8(a) and theframe delay incurred in Fig. 8(b), the SDBA shows thatit could manage to guarantee QoS requirements whileproviding almost the same amount of saving comparedto the J-FIT. Even not shown in the figure, the US frameloss is zero in all the schemes.

Fig. 9(b) shows the bandwidth utilization of the threeimplemented schemes in scenario 1. Given the twoONUs in the system, the SBA spends the most band-width, about a half of cycle time to transmit traffic. TheJ-FIT offers the lowest bandwidth utilization as it de-pends only on the US data rates. The proposed SDBAdynamically allocates bandwidth to favor both US andDS traffic resulting in higher bandwidth utilization com-pared to the J-FIT scheme. Compared to the SBA, theSDBA could exploit the majority of ONU’s assigned

timeslot to allow it to sleep. For example, even whenRds

1 = 2 Gb/s, the SDBA has the utilization of 20.5%,i.e., it can schedule to put the ONU in sleep mode for79.5% of the cycle time.

Fig. 10 shows the energy saving and frame loss ratesof the ONU 1 utilizing SDBA in scenario 2 for differentvalues of configured parameters. Delay constraint D isset to either 2 ms or 4 ms, while the safety margin C isset to either 0.1 Mb or 0. In Fig. 10(a), when D is morerelaxed, the obtained energy saving is higher. How-ever, due to the limitation of the data buffers, even withmore relaxing delay constraint, the cycle time thereofsleep time is reduced when Rds

1 ≥ 249.3 Mb/s resultingin lower energy saving. Moreover, the two values ofC give quite similar energy saving. In Fig. 10(b), av-erage frame loss rates are shown for both US and DStraffic. As seen, when C is 0.1 Mb, i.e., all the databuffers leave one tenth of the buffer capacity to com-pensate for underestimation situation, there is no frameloss observed in both US and DS transmission. How-ever, when C is set to 0, there is a number of frame lossobserved in both transmission directions. Also, the lossrate increases with the increase in data rates.

Performance of SDBA with different traffic profiles isshown in Fig. 11. In this scenario, the burstiness in syn-thetic traffic is emulated using geometric distribution ofburst sizes. Namely, each burst consists of a numberof frames generated continuously that follows the ge-ometric distribution. The success probability used forboth DS1 and DS2 traffic p is set to 0.2 [30]. FromFig. 11(a), the obtained energy saving in case of geo-metrically distributed burst size (Geodist in the figure)is just several percentages less than that in case of con-stant frame size, revealing that the proposed SDBA cansave significant amount of energy for bursty traffic aswell. However, Fig. 11(b) shows that the incurred DS

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frame can be higher than the constrained delay. Thisrequires the proposed SDBA to take into account theburstiness nature of traffic when determining the cycletime and sleep time. With the 2 ms delay constraint and1 Mb safety margin, the all the incurred loss rates in thisscenario are negligible.

6. Conclusion

In this paper, a sleep aware dynamic bandwidth al-location (SDBA) scheme was proposed that aims atmaximizing energy efficiency while guaranteeing thestrictest QoS requirements given the system conditionsin terms of buffer capacities. The SDBA increasesthe polling cycle as much as possible (i.e., as long asthe QoS constraints are not violated) to extend ONUsleep time outside its assigned timeslot. Then, basedon the observed data rates, the SDBA allows an ONUto sleep further inside its timeslot by allocating justenough bandwidth to transmit traffic accumulated dur-ing its sleep time.

An FGPA-based design and evaluation of 10G-EPONsystems featuring the proposed SDBA were presented indetails. For performance evaluation, this paper imple-mented three 10G-EPON systems, i.e., a system withSDBA enabled, a system with J-FIT [14] enabled, and asystem with SBA scheme enabled. Experimental resultsshowed that even with small data buffers utilized at OLTand the two ONUs, the SDBA could schedule the DSand US transmission and sleep mode to save significantamounts of ONU energy. Moreover, the SDBA outper-formed the J-FIT and SBA in that it maximized savingwhile guaranteeing the upper bound frame delays andcapable of maintaining acceptable frame loss rate.

The results also revealed that the energy saving andnetwork performances in terms of frame delays and lossrates experienced by US and DS traffic depend muchon the delay constraint, configuration parameters suchas buffer sizes, safety margin, and traffic profile. Deter-mining the cycle time and transmission duration thereofsleep time based on QoS requirements of each CoSor/and each transmission requires further investigationand left for future work.

Acknowledgment

This work was funded in part by the “Novel ONUsfor Energy efficient optical access networks (NOE)”project, part of the joint higher education project “Pro-viding training for applied and technological research(FORTEC)”, co-financed by the Region of Tuscany

within the framework “POR CRO FSE 2007-2013 AsseIV - Capitale Umano” and by the Italian Ministry ofUniversity and Research through ROAD-NGN project(PRIN2010-2011).

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