Digital Alarm System Experiment 9
Jan 15, 2016
Digital Alarm System
Experiment 9
Experiment 8: Random Notes
• Timing diagrams need to be annotated – it’s not the reader’s job to figure out what is going on or what
is important• Don’t forget circuit diagrams
– circuits you designed/experimented with– answers to questions
• Take more space: use blank lines in code and in experiment write-up
Instructional Objectives:
• Using VHDL behavioral modeling in the design of a Finite State Machine (FSM)
• To combine previously designed VHDL modules into a complete digital alarm system using structural modeling
Finite State Machine
•A Finite State Machine (FSM) is a digital circuit whose state changes based on both the current state (of the FSM) and the current inputs
•The outputs of a FSM are functions of the current state (Moore Model) --or-- functions current state and current inputs (Mealy Model)
•Synchronous FSMs change their state with respect to a clock input and maintain their state (store their state) in flip-flops
FSM ModelsStandard Architecture
VHDL Behavioral Model
VHDL Behavioral Models for FSMVHDL Dependent PS/NS Architecture:
• Next State Sequencing
• Output DecoderX’s
External Control
(CLR, En, PRE)• State Memory• Clock EdgeSynchronization• Ext. Controls (clr, en, preset)
Z’s
Ref: Low-Carb VHDL TutorialCPE 169 Experiment 9
Dependent PS / NS Coding Style: (2 Processes)– Synchronous Process
• Clocking / Control (clears, enables, presets)– Combinatorial Process
• Next State Sequencing• Output Decoding Logic
Y’s
Experiment 9 Overview
P1: Finite State Machine Design1. Using Your State Transition Diagram & PS/NS Table
2. Using the “Dependent PS/NS” VHDL Architecture
3. Simulate to Verify (Test Cases?)
P2: Digital Alarm System– Integrate earlier modules into a working system– Verify the complete system (instructor signoff)– Detailed schematic!!