EXOGAM2 Status - Tata Institute of Fundamental Researchpell/talkpdf_webpage/gdfrance_pic13.pdf · •GTS trigger processor is the XpressGen2V5-200 PCi board Status •GTS trigger

EXOGAM2 Status

• Design specifications

• General layout and status

• Organization

G. de France, GANIL for the EXOGAM2 collaboration

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13

1. EXOGAM physics case and design specs

• Array for small and medium -ray

multiplicity

• 20% efficiency @ 1.3 MeV

• Anti-Compton shield

• 16 segmented HPGe detectors

• Modularity

• Coupling with other detectors

UK – France – Finland – Denmark – Hungary – Sweden – Germany

40% - 40% - 20%

• Physics case: -ray spectroscopy of

exotic nuclei using the exotic

radioactive beams from SPIRAL

Use of EXOGAM

•SPIRAL1 beams (6,8

He; 76

Kr; 24,26

Ne; 44

Ar) (VAMOS, TIARA, MUST, NWall)

•RIBs from fragmentation (LISE, SPEG, VAMOS)

•SIBs from CSS1or CIME (VAMOS, Nwall, DIAMANT)

•All kind of reaction mechanisms (f.e.; transfer; knock-out; DIC; Coulex; decay

studies;…)

•v/c: 0 to 30%

•beam intensity: ~105

– ~1010

pps

Original design specs cannot cope

In addition:

•~40% of approved experiments request EXOGAM

•Maintenance problems (normal maintenance and aging). Critical: Ortec,

VXI electronics

Heavy use and maintenance problems

•LINAG beams

•SPIRAL2 beams

Use of EXOGAM in the future

New physics case and additional constraints

•Much larger intensities (SIBs and RIBs)

•Harder environment: Rutherford, beam halo, beam

dump,…

Need for an upgrade

The physics case at LINAG/SPIRAL2 (CS July 2007)

•Spectroscopy of N~Z nuclei:

–Self-conjugate systems and isospin symmetry

–Structure around 100

Sn

–T=0 pairing

–Spectroscopy beyond the p-drip line

•Spectroscopy of n-rich nuclei populated in DIC and inverse kinematics:

–Structure around closed shells

•Shapes and deformations:

–Shape coexistence; shape isomers

–Exotic deformations

–Role of hyper intrudal (N+3) in N~120 region

•Spectroscopy of heavy elements (No, Rf,..):

–s.p. orbitals and their role

–Collectivity of nuclei around islands of deformation (~ 254

No, 270

Hs).

–Role of K-isomerism on “stability”.

–Angular dependence of the fission barriers.

•Gamma-ray spectroscopy with reaction at intermediate energies:

–Inelastic scattering; Coulomb excitation

See the SPIRAL2 white paper/blue book!

Main new design specifications:

•Full digital electronics

•PSA « of the poor man »

•Very high rates (>50 kHz/crystal?)… whilst maintening an

« optimum » resolution. R&D.

•Triggerless as well as triggered (multiplicity, auxiliary det.)

•Time resolution: 10ns baseline project. 1ns under study.

•Two energy ranges: 6 MeV and 20 MeV.

•Shield energy resolution (calorimetry) not critical.

Need for an upgrade: EXOGAM2

Preamplifiers

16 clovers=

64 crystals

Global Trigger and

Synchronization

1 GTS supervisor and

34 GTS mezzanines

7 differentialanalog links

per NIM board

DAQ

KALMAN processing

1 optical link per NIM board (< 2 Gb/s)

7 analog signals per crystal(ICR < 100kHz per crystal)

1 optical link per NIM board

Connexionbox

One test per crystal64 crystals

=>64 boxes

Digitizing,Processing

andDating

1 crystal Per

NIM board=>

64 NIM boards

Differential stagesand

test pulse generator

Control link

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NIM 1900W

Ethernet Switch

1 linkper NIM board

( 6 MB/s per crystal)

Preamplifiers

16 clovers=

64 crystals

Global Trigger and

Synchronization

1 GTS supervisor and

7 differentialanalog links

per NIM board

DAQ

KALMAN processing

1 optical link per NIM board (< 2 Gb/s)

7 analog signals per crystal(ICR < 100kHz per crystal)

1 optical link per NIM board

Connexionbox

One test per crystal64 crystals

=>64 boxes

Digitizing,Processing

andDating

1 crystal Per

NIM board=>

64 NIM boards

Differential stagesand

test pulse generator

Control link

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NUMEO2

NIM 1900W

Ethernet Switch

1 linkper NIM board

( 6 MB/s per crystal)

2. General layout and status

Connexion box

Role:• Translate the 7 signals of one crystal from common mode to digital mode. • Test generator.

Specs:16 clovers 64 connection boxes•Detector channels:

-Analog inputs: 1 Ge inner, 4 Ge outer, 1 BGO, 1 CsI-Analog outputs: differential 100Ω-Gain: G=1 for Ge ; 3<G<15 tuned with potentiometer for BGO and CsI

•Test generator:-Pulse output: 0 to 1V on 50Ω; polarity and amplitude are software controlled-Tail pulse: 10ms

• Rate and trigger: software or NIM trigger input controlled

Connexion box

Results of the first prototype tests• Power: 2W on +/- 6V• 10m MDR cable attenuation: 0.5dB (Tr = 100ns, Tf= 50µs)• Differential stages : noise contribution < 100eV• Test generator: SPI control is OK, 10 ms decay time not reached

Modifications to do for the second prototype• To duplicate the differential outputs of the inner channel• To add a 4µs integrator stages to BGO and CsI channels • To power supply the box from the +24V voltage of the digitizer• To replace MDR connectors with HDMI connectors • To implement a VHDL component to fix the 10ms decay time

Actions• Technical document has been updated• Modifications have been done in the design files• Second prototype will be delivered mid January

FADC mezzanine status

Main features• 4 differential inputs : -4V < Ve < +4V, HDMI connector • 4 FADC s, 14 bits, 250MHz• SPI control of FADC offset and frequency sampling

Electrical tests on 1st prototype• SPI is OK•Power: 6W (4 channels @ 200MHz)• Base line noise : σ = 3LSB (FADC: 14 bits, Fs= 200MHz)• Crosstalk: - 90dB • Frequency bandwidth (-3dB) : 50MHz• DNL : +/- 0,2 LSB• INL : 0,02% FS (Fin = 200kHz, Fs = 200MHz)• FWHM = 1,8keV (BNC pulse generator + MWD on ML605)

Dual FADC

Dual FADCHDMI

SAMTEC

PLL

Test bench

First prototype of the FADC mezzanine,top and bottom

Modifications already implemented in the preserie prototype:1) To fix the readout of SPI components2) To reduce the base line noise level :

a) To replace the AD8002 by the AD8139b) To connect the reference DAC to the FADC reference voltagec) To connect the DAC bipolar stage to the FADC reference voltaged) To route tracks at low impedance

3) To implement the 1.5V common mode voltage input circuit (S3 detector specification)

Actions 1) Modifications were done in the design files except 2) 8 preserie FADC mezzanines are manufactured by IFIC 3) Tests of the FADC mezzanines (version Spain) are being tested4) 1 preserie FADC mezzanine (version India) has been manufactured by BARC. It should be tested at GANIL on early January5) Comprehensive and user friendly test bench must be developed

Done: noise reducedfrom 3 to 1.4 LSB

FADC mezzanine status

MGT

Clocks

Fast serial links

Parallel links

Slow control

Serial link

NUMEXO2 digitizer

ADC Logic- FADC samples collection

- Digital Processing

- Trigger

- Data formatting

Inspection control

- Oscilloscope

-

PPC

Common Logic

GTS Fanin ADC Logic Interface

Clocks(Local &

Recovered)

Delay Line

Optical

Link

Flash (Linux)

FIFO

Ethernet

Gigabit

PCIe

(4 lanes)

16*FADC

14 bits

200 MHz

(ADS62P49)

DACs(Test, control,

inspection)

RS232

link

DDR2

Mux

CLK

Data

to

PC

Ie

Data

to

Eth

ern

et

STOP

PROM

PROM

The NUMEXO2 digitizer

PCB of the NUMEXO2 digitizer

Main features• 16 layers• 4 FADC mezzanines• 1 Gb Ethernet link• 4 PCIe lanes• 4 Inspection lines• GTS leaf embedded in Virtex 5FX70T• Digital processing in Virtex 6 LX130T• SPI links to front end

FADC mezzanine 4

FADC mezzanine 3

FADC mezzanine 2

FADC mezzanine 1

DC/DCDC/DC

Virtex6(bot)

Virtex5(bot)

RJ45 Eth

MPO PCIe

SFP PCIE CLK

SFP GTS

FIFO

HDRSPI

FADC mezzanine 4

FADC mezzanine 3

FADC mezzanine 2

FADC mezzanine 1

DC/DCDC/DC

Virtex6

Virtex5

RJ45 Eth

MPO PCIe

SFP PCIE CLK

SFP GTS

FIFO

HDRSPI

Status: • 2 PCB prototypes delivered• Cabling finished end of September• Tests started early November: progress very well until now (power supplies, FADC-V5-V6 communication, embedded Linux, setup,…)• 3 test benches will be set : full set test, firmware developments, GTS implementation.

The NUMEXO2 digitizer

Virtex 6 LX130 firmware

Main features:• 16 * 7 differential links @ 400 Mb/s IOSERDES• 4 oscilloscope channels, 4*32kB memory depth• 2 analog and digital inspection lines• Digital processing unit• 1 processed data readout channel (rate < 8MB/s)• 1 raw data readout channel @ 400B/s

Status• IOSERDES @ 400Mb/s: OK• MWD: OK• Pile up rejection: OK• DCFD: OK• Oscilloscope: OK• Readout channels: To test• Inspection lines: To test

Oscilloscope output MWD output (sourced from clover Ge)

ConnexionBox (P1)

ML605

ADS62P49Evaluation board

Main features:• Ethernet Gb link• 4 lanes PCIe link• SPI controllers• GTS leaf• Event filtering and tagging unit

Status:• XPS project with peripheral components managed by Linux OS : OK• SPI controllers : OK• Gb Ethernet readout : OK (rate 20MB/s) • PCIe IP : OK (rate 465 MB/s)• GTS leaf IP: to be implemented• ADC interface IP : being implemented

Virtex 5 FX70T firmwareGANIL

Caen

IPNO

Orsay

CSNSM

Orsay

IUAC

New Delhi

IFJPAN

krakow

8

ML507

Vir

tex

5 :

IPs

and

per

iph

eral

s

GTS leaf

DATA _PATH

TRIGGER_CORE

COUNTER

CLOCK _PATH

GTXTX

RX

GT

_T

XD

ATA

(mg

t da

ta o

ut)

GT

_R

XD

ATA

(mg

t da

ta i

n)

TX

_C

HA

RIS

K

TST_TX (sfp data out)

TST_RX (sfp data in)

DATA CLK (clk user)

DATA CLK (clk user)

DATA CLK (clk user)

GTS_REC_CLK

LOCAL CLK

DRP CTRL

MG

T T

ES

T D

ATA CLK RAW 100

(to PLL)

CLK BASE 100

Clk fb clean 100

CLK MICTOR

CLK

TO

DIG

ITIZ

ER

SY

NC

TO

DIG

ITIZ

ER

MG

T U

SE

R D

ATA

IN

(up

str

eam

maste

r le

af)

MG

T U

SE

R D

ATA

OU

T

(do

wnstr

eam

maste

r le

af)

TRIGGER SIGNALS

GLOBAL SYNC RESET

PLL LOCKED

Light GTS tree running at GANIL(Contrôle PPC + trigger_core IP + GTX IP)

GTS leaf IP

GTS root GTS leafLMK 3001 ML507

GTS leaf like

Status: • Light GTS leaf has been implemented in ML507 =>

100MHz clock is recovered, GTS cycle is sourced• GTS leaf on ML507 is controlled by Linux embedded software. • Light GTS leaf on NUMEXO2 prototype : delayed• GTS leaf with its Datapath, Clockpath and PLB cracus IPs: Implementation on NUMEXO2 delayed. • GTS leaf upgrade (16 TR) : done

Features• 4 GTS V3 mezzanines housed in one GTS NIM carrier

Status• Two GTS NIM carrier prototypes are manufactured• Test of the GTS NIM carrier prototype is underway• 11 GTS NIM carriers should be delivered on early 2013

EXOGAM2 GTS tree : 4 GTS mezzanines in one NIM module

LC Adapters(Option)

SFP1

SFP2

SFP3

SFP4

Mic

tor

SFP1

SFP2

SFP3

SFP4

Mic

tor

SFP1

SFP2

SFP3

SFP4

Mic

tor

SFP1

SFP2

SFP3

SFP4

Mic

tor

+12Vpower

NIM connector

To

GTS tree Bottom

To

GTS treeTop

GTS

mezzanine

GTS

mezzanine

GTS

mezzanine

GTS

mezzanine

GTS_NIM

EthernetPhysic and switches

RJ45

CLK input

RS232 links

switches

SUB D

JTAG

JTAG

JTAG

JTAG

CLK output

Synchro output

SYNCHRO input

TOPBOTTOM

GTS Carrier

GTS system status and limitations

Features• GTS tree made of 18*GTSV3 (17 fanin-fanout and 1 root) => 5 GTS NIM carriers• GTS trigger processor is the XpressGen2V5-200 PCi board

Status• GTS trigger processor: current firmware and software will be retrieved from AGATA• XpressGen2V5 is being tested with PLDA software tools

Limitations 1) One TR per GTS optical link 2) GTS latency (leaf level) : 80ns between two consecutive TR3) Total # of TR limited to 2554) Total # TR processed by the current trigger processor limited to 40

GTS upgrade is needed.Current upgrade aims to fix:

- point 1 : Number TR is extended to 16- point 2 : No latency

Suggestions to fix points 3 and 4 : - point 3: IP number should be on 16 bits- point 4: PCI board could be changed or replaced by a

software trigger

TRIGGERPROCESSOR

NUMEXO2

GTS(root)

GTS(Fanin-Fanout)

GTS(Fanin-Fanout)

GTS(Fanin-Fanout)

GTS(Fanin-Fanout)

GTS(Fanin-Fanout)

GTS(Fanin-Fanout)

NUMEXO2

Embedded

GTSEmbedded

GTS32 NUMEXO2 modules (with embedded GTS leaf functions)

11 GTS V3 mezzanines

4 GTS V3 mezzanines

Optical link

1

2 3

4 7

8 18

XpressGen2V5

-

200 development board

SFP with Gbit links: SFP HSI

GTS Root node

GTS trigger processor

EXOGAM2 GTS tree

DAQ software

Status:

• Embedded software:- PPC virtex 5 managed by Linux OS: OK- Register server: OK- Data readout : OK- GTS leaf controller migration (VxWorks to Linux): underway

• Software:- Vigru specific developments (FFT, oscilloscope trace): OK - NUMEXO2 digitizer in the ‘Ganil Electronics Control’: underway- Development of the ‘actor’ in Narval data flow: test is underway- GTS tree control software: to be tested- Data readout software validation: to be done- Development of the event buider for merging all NUMEXO2 readout channels: to be done- PCIe data integrity : to be done

Test of a single digital channel prototype with an

EXOGAM Clover inner + source

B3

FADC mezzanine

ML605

Source Co60

1.1732 MeV

1.3325 MeV

Seuil de déclenchement Rayons X

25 KeV 39.9 KeV 45.7 KeV

Source Eu152

BNC Co60

Frequency 1kHz 1 kHz 20kHz 50kHz 90kHz 150kHz 190kHz

Resolution 1.2keV 3keV 3.2keV 3.4keV 3.7keV 4.5keV 4.6keV

Trapezoidal filter k=m=2μs

Conclusion:- Resolution:

with generator : OKwith clover: To improve => CEM problems must be fixed

- Threshold: 30keV OK- Pile up rejection : Pretty good resolution @ 190kHz : OK

3. Collaboration, budget and manpower

• Collaboration agreement active (more than 3 parties have signed)• Collaborators: GANIL, CNRS/IN2P3/CSNSM, KTH Stockholm*, ATOMKI Debrecen, NigdeUniv. , CNRS/IN2P3/IPNO, IFJ PAN Krakow, IUAC New Delhi, TIFR Mumbai.

• Signature of India through a general SPIRAL2 MoU (no signatures of individual agreement)• No significant deviation from the planned funding and manpower projected involvement

• Total cost: ~600 k€ (all included)

Human resources

2

6 13 19

27

29

3155

86

INFN Padova

IUAC NewDelhi

IFIC Valencia

CSNSM Orsay

DRT CEA Saclay

IPN Orsay

IFJPAN Krakow

BARC Mumbaï

GANIL Caen

- EXOGAM2 phase 2 project : 4 years, 2011- 2014- Resources consolidated since 2011 (IFIC, INFN,IPNO, CSNSM, BARC)- Synergies with NEDA, AGATA, S3 and PARIS

Total = 268 mm

The preserie module of NUMEXO2 digitizer should be available on Q3 2013

4. Planning

5. Conclusion

• Revision of schedule in 2010; on schedule since then.

• Important milestones in 2012: o Finalization of the design of the digitizer, detailed check and 2 prototypes orderedo Final design of the FADC. Synergies with NEDA, S3, PARIS (?). Prototypes tested OK. Preserial modules available in October from Spain.o Feasibility of the FADC in India: answer in early 2013o Test of the prototype digitizer started early November 2012 and progress very wello Validation of firmware V6 and V5 using the complete chain with a test board and a Clovero Integration of the GTS leaf IP => postponed to 2013

• Most of 2013 dedicated to full test and characterization of the digitizer equipped with 4 FADCs and the connection box. Order of pre serie modules in EU and India. Extensive tests and comparison before ordering mass production

• Budget as expected. Excellent synergies (NEDA, S3, PARIS). Good for support.

• Full documentation of the project is up to date