-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.s o l u t i o n s f o r c h a p
t e r 2
s o l u t i o n 2 . 1 a) The truth table for is
b) The truth table for is
c) The truth table for is
0 0 0 00 0 1 00 1 0 10 1 1 01 0 0 11 0 1 11 1 0 11 1 1 1
0 0 0 00 0 1 10 1 0 10 1 1 01 0 0 11 0 1 01 1 0 01 1 1 1
0 0 0 0 0 1 00 0 0 1 0 0 00 0 1 0 0 0 00 0 1 1 0 0 00 1 0 0 1 1
1
a b c+a b c a b c+
x y z x y z x y z
a b+( ) c d+( )a b c d a b+ c d+ a b+( ) c d+( )5
0 1 0 1 1 0 00 1 1 0 1 0 0
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.6 s o l u t i o n s f o r c h a
p t e r 2
s o l u t i o n 2 . 2 a) The schematic diagram for is:
b) The schematic diagram for is:
c) The schematic diagram for is:
s o l u t i o n 2 . 3
0 1 1 1 1 0 01 0 0 0 1 1 11 0 0 1 1 0 01 0 1 0 1 0 01 0 1 1 1 0
01 1 0 0 1 1 11 1 0 1 1 0 01 1 1 0 1 0 01 1 1 1 1 0 0
a b c d a b+ c d+ a b+( ) c d+( )
a b c+
abc
x y z
xyz
a b+( ) c d+( )
abcd
f a b c a b c a b c + +=
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.s o l u t i o n s f o r c h a p
t e r 2 7
s o l u t i o n 2 . 4 The sum-of-minterms equation can be
implement-
ed directly as shown below left. A simplified equation, , can be
implemented as shown below right.
s o l u t i o n 2 . 5 The truth table is
s o l u t i o n 2 . 6 The Boolean equation derived directly from
the circuit is:
The Boolean equation in the form of a sum of minterms is:
s o l u t i o n 2 . 7 The truth table is
f a b c b c+=
a
f
b
c
a
f
bc
0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 01 1 1 1
0 0 0 0
x y z f
f x y y z( )+=
f x y z x y z x y z x y z + + +=
a b c M0 0 1 00 1 0 0
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.8 s o l u t i o n s f o r c h a
p t e r 2
s o l u t i o n 2 . 8 a) The truth table for and is shown below.
Since the values in each row for the two expressions are the same,
the expressions are equivalent.
b) The truth table for and is shown below. Since the values in
each row for the two expressions are the same, the expressions are
equivalent.
0 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1
0 0 0 0 00 0 1 0 00 1 0 0 00 1 1 0 01 0 0 1 11 0 1 1 11 1 0 1 11
1 1 0 0
0 0 1 10 1 0 01 0 0 01 1 1 1
a b c M
x y z( ) x y x z+
x y z x y z( ) x y x z+
x y x y
x y x y x y
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.s o l u t i o n s f o r c h a p
t e r 2 9
s o l u t i o n 2 . 9 One arrangement for the buffer tree
is:
s o l u t i o n 2 . 1 0 A reduced truth table is:
s o l u t i o n 2 . 1 1 The augmented truth table is:
x y z f0 0 10 1 01 1
a b c f f0 f1 f2 f30 0 0 0 0 0 0 00 0 1 1 1 1 1 10 1 0 0 0 0 0
00 1 1 0 1 0 11 0 0 0 0 1 11 0 1 1 1 1 1 11 1 0 1 1 1 1 11 1 1 0 0
0 0 0
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.10 s o l u t i o n s f o r c h a
p t e r 2
s o l u t i o n 2 . 1 2 In the following, the top two circuits
are equiva-lent, and the bottom two circuits are equivalent:
s o l u t i o n 2 . 1 3 The identity law 2.13 can be proven as
follows:
= by complement law 2.9
= by identity law 2.8
= by complement law 2.9
= by distributive law 2.5
= by complement law 2.10
= by identity law 2.7
= by complement law 2.9
Law 2.14 follows, since it is the dual of law 2.13.
The absorption law 2.15 can be proven as follows:
= by identity law 2.8
= by distributive law 2.6
= by commutative law 2.1= ... using same steps as proof of=
identity law 2.13
= by identity law 2.8
Law 2.16 follows, since it is the dual of law 2.15.
s o l u t i o n 2 . 1 4 The transformation is:
= DeMorgan Law
= Distributive Law
xy
xyz
xz
xy
xyz
xz
x 1+ x x x+ +
x x+( ) 1 x+x x+( ) x x+( ) x+
x x x( ) x+ +x 0 x+ +
x x+
1
x x y( )+ x 1 x y( )+x 1 y+( )x y 1+( )
x 1x
w y+( ) x z+( ) w y( ) x z+( )w y x w y z +
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.s o l u t i o n s f o r c h a p
t e r 2 11
s o l u t i o n 2 . 1 5 One possible proof is:
Idempotence twice
Commutative
Commutative
DistributiveComplementIdentityCommutative
s o l u t i o n 2 . 1 6 a) The module definition is:
module exercise_2_16_a ( output m, input a, b, c );
assign m = a & b | b & c | a & c;
endmodule
b) The module definition is:
module exercise_2_16_b ( output s, input x, y, z );
assign s = ~(x | y) & (x | ~z);
endmodule
c) The module definition is:
module exercise_2_16_c ( output y, input a, b, c );
assign y = (a ^ b) & (a | c);
endmodule
s o l u t i o n 2 . 1 7 Since there are seven values to be
represented, a minimal-length code has bits. One possible code is
on-
hook: (0, 0, 0), dial-tone: (0, 0, 1), dialing: (0, 1, 0), busy:
(0, 1, 1), con-nected: (1, 0, 0), disconnected: (1, 0, 1), ringing:
(1, 1, 0).
a b c a b c a b c a b c + + + a b c a b c a b c a b c a b c a b
c + + + + +=a b c a b c a b c a b c a b c a b c + + + + +=a b c a b
c b a c b a c c a b c a b + + + + +=a a+( ) b c b b+( ) a c c c+( )
a b + +=
1 b c 1 a c 1 a b + +=b c a c a b+ +=
a b b c a c++
log27 3=
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.12 s o l u t i o n s f o r c h a
p t e r 2
s o l u t i o n 2 . 1 8 Given the code bits ( , , ), the
equation
can be expressed as a sum-of-minterms by inspecting the code
words for the off-hook states:
s o l u t i o n 2 . 1 9 Since there are seven values to be
represented, a one-hot code has seven bits. One possible code
is:
on-hook: (1, 0, 0, 0, 0, 0, 0)dial-tone: (0, 1, 0, 0, 0, 0,
0)dialing: (0, 0, 1, 0, 0, 0, 0)busy: (0, 0, 0, 1, 0, 0,
0)connected: (0, 0, 0, 0, 1, 0, 0)disconnected: (0, 0, 0, 0, 0, 1,
0)ringing: (0, 0, 0, 0, 0, 0, 1)
s o l u t i o n 2 . 2 0 The module definition is:
module hook_detector ( output off_hook, input [2:0] p ); assign
off_hook = ~p[2] & ~p[1] & p[0] | ~p[2] & p[1] &
~p[0] | ~p[2] & p[1] & p[0] | p[2] & ~p[1] & ~p[0]
| p[2] & ~p[1] & p[0];endmodule
s o l u t i o n 2 . 2 1 The equations for green and yellow are
un-changed, since they only activate the respective lights on valid
one-hot code words. The equation for red must be revised to include
only the first term that activates the red light on the valid
one-hot code word for red. The equations are:
green = s_red s_yellow s_green
yellow = s_red s_yellow s_green
red = s_red s_yellow s_green
s o l u t i o n 2 . 2 2 Since odd parity is the logical negation
of even parity, we can form the parity trees for odd parity by
negating the output of the parity trees for even parity. We can do
this by substituting an
p2 p1 p0
off-hook p2 p1 p0 p2 p1 p0 p2 p1 p0 p2 p1 p0 p2 p1 p0 + + +
+=
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.s o l u t i o n s f o r c h a p
t e r 2 13
XNOR gate for the XOR gate that produces the output of the tree.
The odd-parity generator (left) and checker (right) are:
s o l u t i o n 2 . 2 3 Suppose we have a code word 00000000.
Aug-menting this with an even parity bit gives 000000000 and with
an odd parity bit gives 00000001. (The parity bit is the rightmost
bit in both cas-es.) Now suppose the leftmost two bits of each
augmented code word are flipped. The corrupted code words are
110000000 and 110000001, which have even and odd parity,
respectively, as expected for uncorrupted code words. Thus, the
errors are not detected.
s o l u t i o n 2 . 2 4 For an encoded 3-bit input signal, (i2,
i1, i0), the Boolean equations for the decoded outputs are:
s o l u t i o n 2 . 2 5 The module definition is:
module alarm_decoder ( output [1:8] z, input [2:0] i );
a0a1a2a3a4a5a6a7
a0a1a2a3a4a5a6a7
p
error
p
z1 i2 i1 i0 =z2 i2 i1 i0 =z3 i2 i1 i0 =z4 i2 i1 i0 =z5 i2 i1 i0
=z6 i2 i1 i0 =z7 i2 i1 i0 =z8 i2 i1 i0 = assign z[1] = ~i[2] &
~i[1] & ~i[0]; assign z[2] = ~i[2] & ~i[1] & i[0];
assign z[3] = ~i[2] & i[1] & ~i[0];
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.14 s o l u t i o n s f o r c h a
p t e r 2
assign z[4] = ~i[2] & i[1] & i[0]; assign z[5] = i[2]
& ~i[1] & ~i[0]; assign z[6] = i[2] & ~i[1] & i[0];
assign z[7] = i[2] & i[1] & ~i[0]; assign z[8] = i[2] &
i[1] & i[0];endmodule
s o l u t i o n 2 . 2 6 The Boolean equations to produce a 3-bit
encod-ed signal (c2, c1, c0) are:
For pairs of inputs both being 1, the resulting code words
are:black and cyan: (0, 1, 1) = magentablack and magenta: (0, 1, 1)
= magentablack and yellow: (1, 0, 1) = light_cyanblack and
light_cyan: (1, 0, 1) = light_cyanblack and light_magenta: (1, 1,
1) = illegal code wordcyan and magenta: (0, 1, 1) = magentacyan and
yellow: (1, 1, 0) = light_magentacyan and light_cyan: (1, 1, 1) =
illegal code wordcyan and light_magenta: (1, 1, 0) =
light_magentamagenta and yellow: (1, 1, 1) = illegal code
wordmagenta and light_cyan: (1, 1, 1) = illegal code wordmagenta
and light_magenta: (1, 1, 1) = illegal code wordyellow and
light_cyan: (1, 0, 1) = light_cyanyellow and light_magenta: (1, 1,
0) = light_magentalight_cyan and light_magenta: (1, 1, 1) = illegal
code word
s o l u t i o n 2 . 2 7 Since no priority ordering is specified,
we as-sume the following order, from highest to lowest priority:
black, cyan, magenta, yellow, light cyan, light magenta. For the
inputs, color[1] is black, color[2] is cyan, etc.
module ink_encoder (output [2:0] encoded_color, output valid,
input [1:6] color);
assign encoded_color = color[1] ? 3'b001 : color[2] ? 3'b010 :
color[3] ? 3'b011 :
c2 yellow light_cyan light_magenta =c1 cyan magenta
light_magenta =
c0 black magenta light_cyan = color[4] ? 3'b100 : color[5] ?
3'b101 :
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.s o l u t i o n s f o r c h a p
t e r 2 15
color[6] ? 3'b110 : 3'b000;
assign valid = color[1] | color[2] | color[3] | color[4] |
color[5] | color[6];
endmodule
s o l u t i o n 2 . 2 8 For a 4-bit BCD input signal, (i3, i2,
i1, i0), the Boolean equations for the decoded outputs are:
We assume here that invalid input code words cannot occur, and
so we have simplified the equations for y8 and y9. A circuit for
the decoder is:
y0 i3 i2 i1 i0 =y1 i3 i2 i1 i0 =y2 i3 i2 i1 i0 =y3 i3 i2 i1 i0
=y4 i3 i2 i1 i0 =y5 i3 i2 i1 i0 =y6 i3 i2 i1 i0 =y7 i3 i2 i1 i0
=
y8 i3 i0=y9 i3 i0=
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.16 s o l u t i o n s f o r c h a
p t e r 2
s o l u t i o n 2 . 2 9 The module definition is:
module bcd_decoder ( output [0:9] y, input [3:0] i );
assign y[0] = ~i[3] & ~i[2] & ~i[1] & ~i[0]; assign
y[1] = ~i[3] & ~i[2] & ~i[1] & i[0]; assign y[2] =
~i[3] & ~i[2] & i[1] & ~i[0]; assign y[3] = ~i[3] &
~i[2] & i[1] & i[0]; assign y[4] = ~i[3] & i[2] &
~i[1] & ~i[0]; assign y[5] = ~i[3] & i[2] & ~i[1] &
i[0]; assign y[6] = ~i[3] & i[2] & i[1] & ~i[0]; assign
y[7] = ~i[3] & i[2] & i[1] & i[0]; assign y[8] = i[3]
& ~i[0]; assign y[9] = i[3] & i[0];
i0i1i2i3
y0
y1
y2
y3
y4
y5
y6
y7
y8
y9endmodule
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.s o l u t i o n s f o r c h a p
t e r 2 17
s o l u t i o n 2 . 3 0 For a multiplexer with data inputs a0
and a1, se-lect input s, and data output y, the Boolean equation
is:
A circuit to implement a multiplexer is:
s o l u t i o n 2 . 3 1 The circuit is
s o l u t i o n 2 . 3 2 The module definition is:
module expression_mux ( output z, input enable, sel, a, b, c, x,
y ); assign z = enable & ~sel ? a & (b | ~c) : x ^
y;endmodule
y s a0 s a1+=
a0
a1s
y
0
1
xyabc
enablesel
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.18 s o l u t i o n s f o r c h a
p t e r 2
s o l u t i o n 2 . 3 3 The circuit is:
s o l u t i o n 2 . 3 4 The module definition is:
module mux_3bit_4_to_1 ( output reg [0:2] z, input [0:2] a0, a1,
a2, a3, input [1:0] sel );
always @* case (sel) 2'b00: z = a0; 2'b01: z = a1; 2'b10: z =
a2; 2'b11: z = a3; endcase
endmodule
a0(0)
a1(0)
a2(0)
a3(0)
z(0)
sel(1...0)
0123
a0(1)
a1(1)
a2(1)
a3(1)
z(1)0123
a0(2)
a1(2)
a2(2)
a3(2)
z(2)0123
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.s o l u t i o n s f o r c h a p
t e r 2 19
s o l u t i o n 2 . 3 5 The revised circuit is:
s o l u t i o n 2 . 3 6 The revised structural model is:
module vat_buzzer_n_struct ( output buzzer_n, input above_25_0,
above_30_0, low_level_0_n, input above_25_1, above_30_1,
low_level_1_n, input select_vat_1 );
wire low_level_0, below_25_0, temp_bad_0, wake_up_0; wire
low_level_1, below_25_1, temp_bad_1, wake_up_1; wire buzzer;
// components for vat 0 not inv_0a (low_level_0, low_level_0_n);
not inv_0b (below_25_0, above_25_0); or or_0a (temp_bad_0,
above_30_0, below_25_0); or or_0b (wake_up_0, temp_bad_0,
low_level_0);
// components for vat 1 not inv_1a (low_level_1, low_level_1_n);
not inv_1b (below_25_1, above_25_1); or or_1a (temp_bad_1,
above_30_1, below_25_1); or or_1b (wake_up_1, temp_bad_1,
low_level_1);
>30C
low level
buzzer
>25C
>30C
low level
>25C
0
1
vat 0
vat 1 select vat 1
select vat 0
+V mux2 select_mux (buzzer, select_vat_1, wake_up_0,
wake_up_1);
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.20 s o l u t i o n s f o r c h a
p t e r 2
not inv_out (buzzer_n, buzzer);
endmodule
The revised behavioral model is:
module vat_buzzer_n_behavior ( output buzzer_n, input
above_25_0, above_30_0, low_level_0_n, input above_25_1,
above_30_1, low_level_1_n, input select_vat_1 );
assign buzzer_n = ~(select_vat_1 ? ~low_level_1_n | (above_30_1
| ~above_25_1) : ~low_level_0_n | (above_30_0 | ~above_25_0));
endmodule
s o l u t i o n 2 . 3 7 A testbench for the structural vat
buzzer design in Example 1.5 is:
`timescale 1ms/1ms
module vat_buzzer_testbench;
wire buzzer; reg above_25_0, above_30_0, low_level_0,
above_25_1, above_30_1, low_level_1, select_vat_1;
task apply_test ( input above_25_0_test, above_30_0_test,
low_level_0_test, above_25_1_test, above_30_1_test,
low_level_1_test, select_vat_1_test ); begin above_25_0 =
above_25_0_test; above_30_0 = above_30_0_test; low_level_0 =
low_level_0_test; above_25_1 = above_25_1_test; above_30_1 =
above_30_1_test; low_level_1 = low_level_1_test; select_vat_1 =
select_vat_1_test; #1000;
end endtask
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.s o l u t i o n s f o r c h a p
t e r 2 21
vat_buzzer_struct duv ( .buzzer(buzzer),
.above_25_0(above_25_0), .above_30_0(above_30_0),
.low_level_0(low_level_0), .above_25_1(above_25_1),
.above_30_1(above_30_1), .low_level_1(low_level_1),
.select_vat_1(select_vat_1) );
initial begin // normal operation: buzzer should be 0
apply_test(1, 0, 0, 1, 0, 0, 0); apply_test(1, 0, 0, 1, 1, 0, 0);
apply_test(1, 0, 0, 0, 0, 1, 0); apply_test(1, 0, 0, 1, 0, 0, 1);
apply_test(1, 1, 0, 1, 0, 0, 1); apply_test(0, 0, 1, 1, 0, 0, 1);
// alarm operation: buzzer should be 1 apply_test(1, 1, 0, 1, 0, 0,
0); apply_test(0, 0, 0, 1, 0, 0, 0); apply_test(1, 0, 1, 1, 0, 0,
0); apply_test(1, 0, 0, 1, 1, 0, 1); apply_test(1, 0, 0, 0, 0, 0,
1); apply_test(1, 0, 0, 1, 0, 1, 1); // sensor fault operation:
buzzer should be 1 apply_test(0, 1, 0, 1, 0, 0, 0); apply_test(1,
0, 0, 0, 1, 0, 1); $finish; end
always @( above_25_0, above_30_0, low_level_0, above_25_1,
above_30_1, low_level_1, select_vat_1 ) begin #10 if
(!select_vat_1) if (above_25_0 & !above_30_0 &
!low_level_0) begin if (buzzer) $display("Error: buzzer on for vat
0"); end else begin if (!buzzer) $display("Error: buzzer off for
vat 0"); end else
if (above_25_1 & !above_30_1 & !low_level_1) begin if
(buzzer)
-
Peter J. Ashenden, Digital Design: An Embedded Systems Approach
Using Verilog 21 September 2007. 2007 by Elsevier Inc. Reproduced
with permission from the publisher.22 s o l u t i o n s f o r c h a
p t e r 2
$display("Error: buzzer on for vat 1"); end else if (!buzzer)
begin $display("Error: buzzer off for vat 1"); end end
endmodule
The testbench for the behavioral design in Example 1.6 is the
same, except that the module name vat_buzzer_struct is replaced by
vat_buzzer_behavior in the instantiation of the design under
verifica-tion.