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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Lesson 14:Example of the Pipelined CISC and RISC
Processors
Chapter 06: Instruction Pipelining and Parallel Processing
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Objective
•• To understand pipelines and parallel pipelines in CISC and RISC Processors by Examples
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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Most modern processors
• Improve performance —SunSparc, Pentiums, PowerPCs are the superscalars and examples of pipelining and parallel processing of instructions
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Pentium and PowerPC pipelines in parallel
• Performance improves in processors by allowing independent instructions to execute simultaneously (instruction-level parallelism)
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Pentiums
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Pentiums
• The superscalar processors• Have simple I-bit-technique─ based dynamic
branch prediction
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Pentiums Two pipelines
• Named as U and V• V pipeline─ for simple instructions and • U─ for any instruction• 64-bit wide external data bus• The conditional jump was made a second
instruction among the two running in parallel
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Pentium U and V pipelines
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Two instructions proceed through the parallel pipelines
• Two instructions proceed through the parallel pipelines at one stage per cycle, until they reach the register (result) write-back (WB) stage
• At WB the execution of instruction In is complete in pipeline 1 and In+1 in 2
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Pentium U and V pipelines
• In earlier versions, Pentium processors executed two integer instructions or two floating-point instructions in parallel
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Pentium U and V pipelines
• Pentium’s later versions had three independent units, two for integer operations and one for floating-point operations
• Pentium Pro version had an additional pipeline and supported two integer operations and two floating-point operations in four pipelines
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Pentium U and V pipelines
• Pentium II versions had additional MMX instructions
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Pentium MMX
(a) 128-bit MMX registers, each for two packed 64-bit floating-point operations and pipelines has 20-stages
(b) 128-bit MMX registers, each for two packed 64-bit floating-point operations and pipelines has 10-stages
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Pentium MMX
(c) Two number 64-bit MMX registers, each for one packed 64-bit floating-point operations and pipelines has 5 stages
(d) Four number 32-bit MMX registers, each for two packed 64-bit floating-point operations and pipelines has four sets of 5-stage pipelines.
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Pentium III versions
• Introduced single instruction multiple data SIMD instructions with extension for execution of streaming floating point operations in pipelines
• Pipelines had 10 stages
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Pentium IV versions
• Introduced in the twenty-first century with 1GHz plus clock cycles
• 128-bit XMM (extended multi media) registers, each for two packed 64-bit floating-point operations
• The 128-bit registers handle long integers also• Pipelines have 20 stages
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PowerPC Processor
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PowerPC
• IBM, Motorola, and Apple developed the PowerPC superscalars
• An RISC design but provides for more than 200 instructions at the instruction set
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PowerPC
• Load and store architecture (only the LD and ST access the memory and not the arithmetic and logic instructions)
• Separate GPRs and floating-point registers
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PowerPC
• PowerPC 601 and 603 have three pipelines each─ one for branch processing, one for integers (E-integer Pipeline), and one for floating-point (E-floating point Pipeline) operations
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Uneven number of Stages in Pipelines
• There are five stages in the integer-processing pipeline, six in the floating-point pipeline, and two in the branch-processing pipeline stages
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Stages in Pipelines
• The second stage in E-integer line decodes, reads, and dispatches operands
• The third stage in E-integer line executes and computes memory addresses
• The fourth stage is cache access
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E-unit Integer Operations Pipeline
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E-unit Floating point operations pipeline
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E-branch pipeline
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PowerPC version 604
• Six pipelines• Three integer and one floating-point
instruction in parallel per clock cycle.• There were six independent units, two for
integer operations, two for floating-point operations, and two for branch processing
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PowerPC version 620
• PowerPC 620 had 64-bit operations. It also had six pipelines and three integers and one floating-point instruction in parallel per clock cycle
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PowerPC 750 series
• Introduced in twenty-first century and has many features.
• MPC7XXX has eleven independent pipeline units load and store processing unit, branch-processing unit, floating-point unit, four integer operations, and two for floating-point operations and packed data operations.
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ARM
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ARM (Advance RISC Machines)
• ARM (Advance RISC Machines) developed the large variations in superscalars as per application-specific needs
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ARM (Advance RISC Machines)
• It has separate 16 GPRs, CPSR, and SPSR (Current Process Saved Status Register and Saved Process Status Register)
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ARM RISC design
• ARM7TDMI had three stages pipeline
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ARM7 three stage pipeline
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Pipelines in StrongARM and ARM 9
Stage 1 Stage 2 Stage 3
Five Clock Cycle Stages Pipeline
• StrongARM has 5-stage pipeline and a high-speed multiplier circuitry
• ARM9 has 5-stage pipeline
Stage 4 Stage 5
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Pipelines in ARM 10
Stage 1 Stage 2 Stage 3
Five Stages Clock Cycle Pipeline
ARM10 has 6-stage pipelines
Stage 4 Stage 6Stage 5
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Summary
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We learnt
• Superscalar Processors Pentium, PowerPC• ARM pipelines
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End of Lesson 14 on Example of the Pipelined CISC and
RISC Processors