EX1 - digsys.upc.esdigsys.upc.es/.../EX/EX3/CSD_Curs_10-11_Q1_EX3.docx · Web view... and synthesise in a FLEX10K a synchronous 4-bit counter ... let’s take 5 Hz; (2) the digital

EX3: Designing sequential systems using FSM

EX 3 DIGITAL CIRCUITS AND SYSTEMS

Designing sequential systems using FSM

1.1 Cooperative groupTEAM NUMBER: ___________

DUE DATE: ________________ 1st review due date: ________________

STUDY TIME:

Study time

(in hours)

Group work Classroom and laboratory sessions

Sessions out of classroom

Individual Student 1

Student 2

Student 3

STATEMENT:

My signature below indicates that I have (1) made equitable contribution to EX 3 as a member of the group, (2) read and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document, and (3) acknowledged by name anyone outside this group who assisted this learning team or any individual member in the completion of this document.

Today’s date: __________________

Active members Roles: (reporter, simulator, etc.)

(1) ________________________________________ _______________

(2) _________________________________________ _______________

(3) _________________________________________ _______________

Acknowledgement of individual(s) who assisted this group in completing this document:

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EPSC – CSD: Digital Circuits and Systems

(1) _______________________

(2) _______________________

1.2 Abstract Explain here the most significant developments, results or conclusions about the exercise. Use the remaining space in this sheet (200 words maximum).

(This section is mandatory. You must complete it in order to get a mark.)

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CONTENT

Designing sequential systems using FSM....................................................................................................1

1.1 Cooperative group.....................................................................................................................................1

1.2 Abstract.....................................................................................................................................................1

1.3 Description................................................................................................................................................3

1.4 Topics........................................................................................................................................................3

1.5 Studying a synchronous canonical expandable 1-digit BCD counter.......................................................4

1.6 Designing clock frequency dividers..........................................................................................................5

1.6.1 Plan a quartz oscillator frequency divider chip................................................................................5

1.6.2 Design a T-FF as a simple FSM.......................................................................................................5

1.6.3 Design synchronous cascadable binary counters as FSM................................................................5

1.7 Designing standard sequential modules....................................................................................................5

1.7.1 The 16-bit data registers in the simple machine...............................................................................6

1.7.2 A 16-bit shift register........................................................................................................................6

1.7.3 A 16-bit ring and Johnson counter....................................................................................................6

1.8 Designing the 16-key keypad scanning decoder.......................................................................................6

1.8.1 Keypad characteristics and wiring...................................................................................................6

1.8.2 Plan and code in VHDL the state diagram for the component.........................................................6

1.8.3 Complete the project adding clock and display modules..................................................................7

1.8.4 Synthesise the matrix keyboard application into a CPLD or a FPGA chip......................................7

1.9 Debouncing keys.......................................................................................................................................8

1.9.1 Visualise the problem of mechanical pushbuttons interfaced to digital systems..............................8

1.9.2 Solve the problem..............................................................................................................................8

1.10 A simple LED sequencer..........................................................................................................................8

1.11 Problem solution (títol 2)........................................................................................................................10

1.11.1 Part 1 (títol 3)..................................................................................................................................10

1.12 References...............................................................................................................................................11

1.13 Study plan to solve the exercise..............................................................................................................12

1.14 Topics and activities checklist................................................................................................................13

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1.15 Grading grid............................................................................................................................................13

1.16 Questions in solving EX2........................................................................................................................14

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Units 2.2 and 2.3 The theory of synchronous canonical FSM and its

application on the design of a basic counter

Design a frequency divider to generate CLK (using expandable counters and toggle flip-flops T-FF)

Design basic standard sequential blocks

Design a simple application

Functional simulations: the

VHDL code

A 16-keys matrix keyboard encoder

A push-button debouncing filter

A LED sequencer

Johnson/oneshot counter

Shift register Data register

Timed /gate-level simulations: the

synthesised (*.vho) flattened circuit on a given

technology (delays *.sdo/sdf)


1.3 DescriptionIn this third exercise, basic sequential systems will be implemented and tested. We learn how to describe any synchronous sequential system through the architecture of a FSM consisting of three blocks: (1) the state register, (2) the next state logic and (3) the output logic. The state register based on D-FF will be written in VHDL using a clock sensitive process, while the next state and output logic will be specified as combinational blocks. For example, the T-FF which will be used to obtain squared waveforms from pulsed ones will be conceived as a simple FSM. Any other basic or standard sequential block, as a counter or a data register will be implemented in the same way.

In Part 1, let’s introduce the basics of a FSM by means of the design of a BCD counter.

Part 2 will be devoted to the study of structured frequency dividers, so that we will be able to generate the required clock frequencies for our digital systems from an external high-frequency crystal oscillator.

Part 3 will be focused on the design of a standard simple sequential block, for instance: a Johnson counter, a parallel data register, a shift register, or the like.

In Part 4, the general architecture or a finite state machine (FSM) will be studied and used once more to implement any kind of sequential system, like, a matrix keypad encoder, a traffic light controller, or a debouncing filter (a kind of digital filter) for mechanical push-buttons and switches.

As in previous EX2, all the projects have to be simulated functionally in ModelSim or ActiveHDL so that their major bugs will be detected before attempting the final phase of prototyping. Furthermore, in this exercise, the gate-level or timed simulation of the final synthesised circuit will also be introduced and executed using the same TCL *.do macros and timing diagrams. ModelSim Altera Edition or ActiveHDL Lattice Web edition will be required to access all the vendors’ libraries which contain all the synthesised components in the flattened system.

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Fig. 1 A simple exercise roadmap

1.4 Topics The following topics have been listed from the course’s specific and cross-curricular learning objectives1: #9, #10 and #11. After studying Chapter 2 and successfully completing all the assignments in this task, you will be able to:

------------- Part 1 -------------

1. Explain the FSM architecture consisting of: (1) the state register, (2) the next state logic and (3) the output logic.

2. Explain the use of the state diagram and the timing diagram to specify sequential systems and to speed to writing of TCL macros.

3. Specify FSM coding styles “sequencial”, “gray”, onehot”, etc in VHDL using ATTRIBUTE statements.

4. Explain the use of the special signals CLK and CD.

5. Identify the all the blocks, which are written as processes, in the VHDL file to describe FSM for the basic BCD counter.

6. Use the Quartus II tool: state machine netlist to produce automatically a state diagram from the VHDL listing.

7. Check the list of resources used in the synthesised circuit, specially the numbers of registers (in order to avoid inferred latches to bad VHDL coding). Do gate-level simulations in ModelSim using VHO and DSO files. A view on the structural flattened circuit generated by the synthesiser (technology map viewer).

8. Installation and use of the Active-HDL Lattice Edition or the ModelSim Altera Edition simulators.

------------- Part 2 -------------

9. Design a structured synchronous crystal oscillator frequency divider using expandable counters and other basic components.

10. Design a toggle flip-flop (T-FF) to square pulsed signals or to divide by two the input frequencies.

11. Generate a real-time square waveform of 1Hz from a high frequency crystal oscillator.

12. Use the oscilloscope and other laboratory instruments to measure digital signals’ parameters like frequency, period, propagation delay, power dissipation, etc.

------------- Part 3 -------------

13. Design basic sequential blocks like a parallel data register, a Johnson counter, a one-hot counter, a shift register, etc.

1 http://digsys.upc.es/ed//CSD/units/CSD_Guia_docent_esborrany.doc

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http://digsys.upc.es/ed//CSD/units/CSD_Guia_docent_esborrany.doc

CDClear direct input

Count enable input

4

TC16

(Terminal count output)

CE

CLK

Synchronous expandable4-bits binary counter

Q(3..0) (This is the output vector in binary code)


------------- Part 4 -------------

14. Explain how a matrix keypad encoder works and design one of them for a 16 keys keypad.

15. Other simple FSM-based applications: a push-button debouncing filter

16. A LED sequencer.

1.5 Studying a synchronous canonical expandable 1-digit BCD counter a) Read the VHDL description for the counter in Unit 2.3. Modify the code to obtain a similar circuit like a 4-

bit expandable binary counter represented in Fig. 2. Prepare the documentation of the block in a similar way: (1) specifications using symbol, state diagrams, timing diagrams; (2) functional simulation; (3) RTL diagrams and state machine diagrams.

Fig. 2 The 4-bit binary counter to be designed

b) Perform a timed simulation or the counter starting a new project in ModelSim Altera Edition or Active-HDL Lattice Edition from the synthesiser output files (*.vho, *.sdf/sdo). Check by means of a timing diagram that the delays are the ones predicted by the technology. Use a CPLD from Lattice (ispMach4128V) or one from Altera (FLEX10K) as the target device. Check the list of resources used in the synthesised circuit, specially the numbers of registers (in order to avoid inferred latches to bad VHDL coding).

1.6 Designing clock frequency dividers 1.6.1 Plan a quartz oscillator frequency divider chip

c) Draw the block diagram of a synchronous frequency divider for a crystal oscillator of 25.175 MHz. The system has to produce four clock signals: (1) the buffered input CLK, (2 and 3) pulsed waveforms of 200 Hz and 4 Hz, and (4) a final square wave of 1Hz. Explore the many ways to do it analysing the VHDL files available on the website (Unit 2.5), and choose an optimum architecture like the one represented in Fig. 3 which is similar to the one that you need. Write down the main differences in the VHDL writing styles, and explain why the last style (Fig. 3), the one using cascaded blocks instantiating components into a top design is the best option in terms of programming clarity and chip resources optimisation.

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http://digsys.upc.es/ed/CSD/units/Ch2/U2_05/Unit2_5.html

CDClear direct input

Toggle input Q

T

CLK

T-FF


CD

CE

CLK

TC25

CD

CE

CLK

TC1007

CD

CE

CLK

TC5000

CD

CLKCE

CLK_1MHzCLK_1kHz

CLK_02Hz

freq_div_5000:Freq_div_5000_Comp1freq_div_1007:Freq_div_1007_Comp1freq_div_25:Freq_div_25_Comp1

Fig. 3 RTL netlist view for a given frequency divider (third design style) which produces pulsed waveforms of 1 Mhz, 1 kHz and 200 mHz

1.6.2 Design a T-FF as a simple FSM

d) Design a project and simulate using the FSM style a toggle flip-flop (T-FF) like the one represented in Fig.4. Represent the timing diagram to show that the output of the system is the input frequency divided by 2.

Fig. 4 Block diagram for the entity toggle flip-flop (T-FF)

1.6.3 Design synchronous cascadable binary counters as FSM

e) Find or invent the VHDL code, using the FSM style, but defining state variables as STD_LOGIC_VECTOR, for a synchronous cascadable (CE and TC) modulo-N binary counter with asynchronous clear direct (CD). Perform a functional simulation to demonstrate the way it works. For large values of N, in order to speed up simulations, the code must be modified (reduce the max_count constant to a lower value).

f) Using the previous components, design the top structure of the synchronous clock divider system to obtain all the 4 outputs. Implement a Quartus-II project for the FLEX10K chip in the UP2 and use the laboratory instruments (oscilloscope or logic analyser) to measure the output waveform parameters. Check the signals synchronicity with respect to the input clock and measure the circuit propagation delays.

1.7 Designing standard sequential modules The following designs are typical sequential modules which may be designed as FSM using our CSD style. All of them may also be demonstrated in prototyping boards or even at the Proteus-ISIS in case of fitting into a single sPLD. Study them first, searching the specific chapters in books or at the Internet. As always, every block has to be associated to a symbol, a function table, and either, a state diagram or timing diagram before

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attempting to design them. And probably, an option to design the 16-bit units proposed, is to design first a 4-bit component which can be conveniently cascaded to implement larger block of the same kind.

1.7.1 The 16-bit data registers in the simple machine

g) Plan, develop, simulate, and synthesise in a FLEX10K the synchronous parallel input – parallel output data register.

1.7.2 A 16-bit shift register

h) Plan, develop, simulate, and synthesise in a FLEX10K a 16-bit shift register able to parallel load and to shift data to the left or to the right depending on the control signals.

1.7.3 A 4-bit one-hot and Johnson counter

i) Plan, develop, simulate, and synthesise in a FLEX10K a synchronous 4-bit counter with the following signals: CLK: clock input; CD: asynchronous clear direct; CE: synchronous active-high count enable; J: synchronous signal to determine the counter encoding: J = 1 Johnson (0000, 0001, 0011, 0111, 1111, 1110, 1100, 1000, 0000, …), J = 0 One-hot (0001, 0010, 0100, 1000, 0001, …).

1.8 Designing the 16-key keypad scanning decoder 1.8.1 Keypad characteristics and wiring

j) Find the characteristics of a commercial 16-key keypad like the one represented in Fig. 5. You may run the project downloading the Proteus design from the web page.

1 2 3

654

8 97

0

TS

HS

MS

SSENTER24H/AM-PM

A

B

C

D

1 2 43

Fig. 5 Example of a commercial matrix keypad and the value obtained when pressing key “E” while scanning (setting a “0”) at RowD. Indeed, the DEC2:4 will be an integrated part of the scanning chip, and so, only the 4 pull-up resistors are the necessary hardware for the interface. An adapted keyboard can be easily obtained sticking new plastic labels on the keys (in Proteus-VSM, you can decompose a component, make the required modifications and adding the new component to the library)

The keyboard will be available in the laboratory and ready to be connected to the FLEX_EXPAN_A connector of the UP2 board. The pin assignment is as follows:

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Row : OUT std_logic_vector(3 downto 0); -- Flex_EXPAN (41, 43, 45, 47) == pins (79, 81, 83, 86)

Column : IN std_logic_vector(3 downto 0); -- Flex_EXPAN (49, 51, 53, 55) == pins (88, 95, 98, 100)

-- Flex_EXPAN (57, 59) == VCC

1.8.2 Plan and code in VHDL the state diagram for the component

k) Invent what is usually called intellectual property (IP): a scanning chip for the 16-key keypad, which in some way has to be similar the commercial chip MM74C922. The chip has to be based essentially in a VHDL-written FSM running a state diagram for scanning rows and decoding the key pressed. Fig. 6 shows an approximate block for the entity suggesting the number of inputs and outputs needed.

Fig. 6 RTL netlist view for the keyboard decoder identified as a component

l) Write the VHDL code for the chip’s state diagram and verify by a functional simulation. Compile the project and use the Quartus II tool: State diagram netlist to verify if the state diagram that implements the FSM coincides with the one specified.

m) In case of having used any of the projects in Unit 2.8, which really represents a complete solution of the previous section l), fix the problem that appears when clicking simultaneously 2 keys of the same column. For example, the solution can be to introduce a final tri-state buffer to deactivate/disconnect all the rows which are not driven at logic low. See Fig. 7.

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(1)

VHDL source files

(2)

Functional simulation(*.vhd)

(5)

Technology map viewer

(6)

Gate-level simulation (*.vho /*sdf)

(7)

Device programming

(8)

Verification using a prototype board

(3)

RTL view

(4) Device selection, pin assignment (constraints) and project synthesis


Fig. 7 A short-circuit is produced when clicking several keys in the same column. Driving the row through tri-state buffers can be a possible solution to this problem

1.8.3 Complete the project adding clock and display modules

n) Complete the project adding: (1) a hex-7segment decoder so that the hexadecimal code captured when pressing key will be displayed into the 7 segment display of the UP2 board; (b) the frequency divider from Section 1.6, thus the keyboard scanner entity will be driven by the 200 Hz pulse waveform.

1.8.4 Synthesise the matrix keyboard application into a CPLD or a FPGA chip

o) Synthesise the module into the CPLD 7128S of the UP2 board and test it.

Fig. 8 Main steps in the programmable chip design flow

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1.9 Debouncing keys 1.9.1 Visualise the problem of mechanical pushbuttons interfaced to digital systems

p) Studying examples in Unit 2.8, and state the problem which arises when connecting a mechanical key, pushbutton or switch as an input to a digital system (synchronisation, glitches, bounces). See Fig. 9.

1.9.2 Solve the problem

q) Solve the problem designing a debouncing filter as a FSM to produce a clean and synchronised waveform considering any of these two options for the output: (1) Qa, a single pulse of one clock period wide; (2) Qb, a pulse that will last for all the push and release action.

RP10k

KEY

VccCLK

PB_L

Qa

Qb

DEBOUNCING CIRCUIT

KEY_FILTER

QaQbCLK

PB_L

Fig. 9 The problem of pressing and releasing mechanical keys and a circuit to solve it.

1.10 A simple LED sequencer r) We want to design a simple driver to shown a sequence of movement, clockwise and counter-clockwise, in

a single 7-segment display. In Fig. 10 the main diagram for this application is shown. The circuit components are basically: (1) a clock to produce a rectangular wave with a given frequency, let’s take 5 Hz; (2) the digital system; and (3) the 7-segment display (common cathode) with its current-limiting resistors.

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Fig. 10 Block diagram for the indicator of sequence of movement

The system has to work as specified in Fig. 11, depending on the logic levels of the synchronous input signals: UD_L (Up (active high) /Down (active-low) and ST (stop). ST signal has precedence over UD_L. Design the circuit based on the standard FSM style, and implement a prototype for the FLEX10K chip at the UP2 Altera board, or for the LC4128V Lattice chip at die Experimentierplatine für die Digitaltechnik.

t

a)

b)

Fig. 11 a) Sequence of switching LED segments for UD_L = ‘1’ (up) and ST = ‘0’; b) Indication for ST = ‘1’

Do not modify the text from page 3 to page 9

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1.11 Problem solution (títol 2)1.11.1 Part 1 (títol 3)

Part 1.1 (títol 4)

És necessari que seguiu aquestes indicacions per qualsevol dels vostres documents en aquesta assignatura. Aprendre-les forma part de la competència de comunicació escrita. Adapteu els vostres documents al format subministrat per aquesta plantilla.

Si alguna indicació o format no l’acabeu d’entendre bé, pregunteu-nos-ho o aclariu els dubtes, però no lliureu mai res que no compleixi aquestes indicacions perquè no us ho corregirem i perdreu el temps.

Afegiu aquí el vostre text (estil normal) encapçalat amb títols (Títol 2 i 3 i 4), amb figures (estil “llegenda” o “epígrafe”) i referències creuades en el text com aquesta Fig. 12 (és una referència creuada a la llegenda, veureu que surt en color gris quan la cliqueu) a les figures que inseriu. Fixeu-vos que la primera vegada que obrireu aquest document en Word 2007, no us sortirà aquesta llegenda “Fig.”, així que haureu de crear-ne una, i després, encara que la esborreu,ja us quedarà la referència. Veureu també que la numeració de les figures és un paràmetre automàtic. Si seleccioneu tot el document, i premeu “F9” actualitzareu tota la numeració.

També l’índex de la pag. 2 és completament automàtic. Es genera sol ( a partir de referències, índex de continguts, Inseriu un índex de continguts) i s’actualitza sol a partir també de “F9” havent seleccionat tot el text de document. És possible que la primera vegada que l’actualitzeu desaparegui. No passa res, simplement cal tornar-lo a generar a partir del menú referències i taula de contingut.

Fixeu-vos en la Fig. 12. Les imatges han d’estar centrades i alineades amb el text. Si voleu posar un parell d’imatges a la mateixa línia, inseriu primer una taula d’un parell de columnes i tot seguit feu invisibles les vores. El millor que podeu fer és “cut & paste” de la pròpia taula que veieu, i, canviar les figures per les vostres.

Feu referència també en el text a les fonts bibliogràfiques o de web que consulteu d’aquesta manera [1] (és una referència creuada a l’element numerat [1]). Expliqueu perquè les heu consultat i quina informació útil heu trobat.

Per corregir la primera versió del vostre treball, no imprimiu ni lliureu des de les pàgines 3 a la 5. És l’enunciat del problema. Sols cal que imprimiu les 2 primeres pàgines que contenen els detalls personals, el resum i l’índex, i a partir d’aquesta mateixa pàgina 6. Però feu-ho amb la numeració correcta. És a dir, treballeu sempre sobre aquest document, i en tot cas, importeu altres textos que tingueu cap a aquest mateix document i formateu-los correctament.

Insistim sobre això mateix: treballeu sempre sobre aquest mateix fitxer per preparar la vostra solució. Així usareu tots els estils i formats que ja té predefinits aquest document.

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Fig. 12 Exemple de peu de figura que segueix la numeració de l’enunciat (llegenda).

Heu d’instal·lar els correctors ortogràfics en català, espanyol i anglès en el vostre paquet d’eines office. I sobretot, corregir qualsevol error mentre escriviu. Si treballeu això estalviareu molta feina als vostres companys i instructors.

1.12 References Modify or add new references to this section. Follow the same format.

[1] http://epsc.upc.edu/projectes/ed/ . Comment: Course wed page where to find a lot of resources for the course. Specially, materials from previous editions. Read the section on theory about digital systems. [visited 12/2009]

[2] Brown,S., Vranesic, Z., “Fundamentals of digital logic with VHDL design”, McGraw-Hill, 2005. Comment: Figure 1. 7 contains an example of design flow for logic circuits and Figure 2.29 the structure of a typical CAD/EDA system.

[3] An image to define a concept map: http://redie.uabc.mx/contenido/vol2no1/art-11-eng/contenido-ruiz-figura1.png

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http://redie.uabc.mx/contenido/vol2no1/art-11-eng/contenido-ruiz-figura1.png

http://redie.uabc.mx/contenido/vol2no1/art-11-eng/contenido-ruiz-figura1.png

http://epsc.upc.edu/projectes/ed/


1.13 Study plan to solve the exercise

Establish a study plan, a task distribution scheme and other requirements to succeed in producing a good solution when working cooperatively: flux diagrams, concept maps, schematics, tables, pictures, etc.

(This section is mandatory. It must be filled in order to get a mark.)

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1.14 Topics and activities checklist

Topics Activities

Group member in

charge Comments

1 2 3

1. The FSM architecture. Design of a 4-bit binary counter a)

2. State diagram and timing diagram a)

3. CLK and CD signals. a)

4. Specify FSM coding styles using ATTRIBUTE statements. a)

5. The very specific CSD style to write FSM in VHDL. a)

6. The state diagram netlist tool. a)

7. Gate-level simulations using VHO and DSO files. b)

8. Installation and use of the Active-HDL Lattice Edition or the ModelSim Altera Edition simulators.

b)

9. Frequency dividers for crystal oscillators. c), d), e), f)

10. Toggle flip-flop (T-FF). d)

11. Real-time 1 Hz square waveform. d), f)

12. Digital signals’ parameters measurements using laboratory instruments. f)

13. Design basic sequential blocks: parallel data register, a Johnson counter, a shift register, etc.

g), h), i)

14. Explain how a matrix keypad encoder works and design one of them for a 16 keys keypad.

j), k), l), m) n), o)

15. A push-button or a switch debouncing filter p), q)

16. LED sequencer, a traffic light controller, , etc.) r)

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1.15 Grading grid Here you are the way the exercise could be grades.

Part 1

The theory

Part 2

Frequency dividers

Part 3

Sequential standard blocks

Part4

Simple applications

Total

a) , b) c), d), e), f) g), h), i) j), k), l), m) n), o), p), q), r)

Scores 1p 2p 3p 4p

Self-assessment

Instructor’s grades

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1.16 Questions in solving EX22

Write here your questions, comments, doubts, opinions, etc. ...

2 Add more sheets if necessary to report your progress or comments though the exercise.

Aquests fulls de dubtes i d’explicació de com heu anat fent l’exercici són obligatoris. Si no és present, no es corregeix l’exercici i s’ha de tornar a lliurar. Abans de corregir i posar-vos qualificacions volem saber quin ha estat procés en què heu dissenyat els circuits i comparar-lo amb les nostres pròpies observacions de classe.

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EX1 - digsys.upc.esdigsys.upc.es/.../EX/EX3/CSD_Curs_10-11_Q1_EX3.docx · Web view... and synthesise in a FLEX10K a synchronous 4-bit counter ... let’s take 5 Hz; (2) the digital

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