Conception de systèmes numériques (CSN) Evolution PLD & méthodologies, This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License Evolution des PLDs et des méthodologies Etienne Messerli septembre 2019 E. Messerli (HES-SO / HEIG-VD / REDS), 2019 p 1 Evolution PLD & méthodologies, Hard drive capacity over time Evolution de la technologie: loi de MOORE Capacity (GB) E. Messerli (HES-SO / HEIG-VD / REDS), 2019 p 2 source: https://en.wikipedia.org/wiki/Transistor_count autor: Wgsimon source: https://en.wikipedia.org/wiki/File:Hard_drive_capacity_over_time.svg autor: Hankwang
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Conception de systèmes numériques (CSN)
Evolution PLD & méthodologies,
This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License
▪ LVTTL, LVCMOS, SSTL et différentiel SSTL, LVDS, LVECL, …
Nbr I/O jusqu'à 1‘600▪ boitier FBGA2597 pins => 1‘600 I/O
p 5E. Messerli (HES-SO / HEIG-VD / REDS), 2019
Evolution PLD & méthodologies,
Nouvelle technologie: Virtex-7 HT
Xilinx’s Stacked Silicon Interconnect (SSI) Combines enhanced Super Logic Region (SLR) FPGA die slices
and 25-28.05 Gb/s transceivers on a passive silicon interposer to create a three dimensional (3D) die stack
Up to 2000K logic cells offered in the largest Virtex-7 T device
Site Xilinx: mars 2013
E. Messerli (HES-SO / HEIG-VD / REDS), 2019 p 6
source: Xilinx
Evolution PLD & méthodologies,
Stacked Silicon Interconnect technology
E. Messerli (HES-SO / HEIG-VD / REDS), 2019 p 7
Interconnectingmultiple dies for Xilinx FPGAs 3D devices
one die
source: Xilinx
Evolution PLD & méthodologies,
Virtex UltraScale + HBM
Virtex UltraScale+ HBM FPGA: A Revolutionary Increase in Memory Performance
E. Messerli (HES-SO / HEIG-VD / REDS), 2019 p 8
Site Xilinx: juillet 2019
Evolution PLD & méthodologies,
Nouvelle technologie: Stratix-10
Stratix® 10 FPGAs and SoCs to support data rates up to 56 Gbps. Altera is demonstratingtoday the FPGA industry’s first dual-mode 56-Gbps pulse-amplitude modulation with 4-levels (PAM-4) and 30-Gbps non-return-to-zero (NRZ) transceivers.
p 9
Customers can use Stratix 10 FPGAs to build next-generationcommunications and networking infrastructure that support 50G,100G, 200G, 400G and terabit applications.
E. Messerli (HES-SO / HEIG-VD / REDS), 2019
Evolution PLD & méthodologies,
Nouvelle architecture: SoC 64bits + FPGA
E. Messerli (HES-SO / HEIG-VD / REDS), 2019 p 10
Intel-Altera Stratix-10 TX
Evolution PLD & méthodologies,
Embedded Multi-Die Interconnect Bridge
New technology EMIB from Intel
E. Messerli (HES-SO / HEIG-VD / REDS), 2019 p 11
(EMIB)
source: Intel
Evolution PLD & méthodologies,
Stratix-V: Structure des blocs IO
E. Messerli (HES-SO / HEIG-VD / REDS), 2019 p 12source: Altera - Intel