Aim: The aim of this project is to design a 3-bit even parity generator that can detect a one-bit error in a message and draw the CMOS layout in L-Edit, which can then be simulated using PSPICE. Abstract: An even parity bit generator generates an output of 0 if the number of 1’s in the input sequence is even and 1 if the number of 1’s in the input sequence is odd. The checker circuit gives an output of 0 if there is no error in the parity bit generated. Thus it basically checks to see if the parity bit generator is error free or not. Schematic: The design procedure is made simple by writing the truth table for the circuit. Truth table: Message Even parity bit Checker bit X Y Z P C 0 0 0 0 0 0 0 1 1 0 1
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Aim: The aim of this project is to design a 3-bit even parity generator that can detect a one-bit
error in a message and draw the CMOS layout in L-Edit, which can then be simulated
using PSPICE.
Abstract:An even parity bit generator generates an output of 0 if the number of 1’s in the input
sequence is even and 1 if the number of 1’s in the input sequence is odd. The checker
circuit gives an output of 0 if there is no error in the parity bit generated. Thus it basically
checks to see if the parity bit generator is error free or not.
Schematic:
The design procedure is made simple by writing the truth table for the circuit.
Truth table:
Message Even parity bit Checker bit
X Y Z P C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 0
The circuit can now be derived by drawing the K-map for the output.
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From this the minimal output equation is
This function can be implemented using exclusive-or gates. The schematic of the parity
generator circuit is shown in Figure 1.
Figure 1: Parity bit generator
Similarly the checker circuit can be designed using XOR gates, where
and the circuit is shown in Figure 2.
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Figure 2: Checker circuit
Now the parity bit generator and the checker circuit can be combined into one circuit for
simplicity. The final schematic of the circuit is shown in Figure 3.
Figure 3: Combined schematic of both parity bit generator and checker circuit
The final layout consists of four XOR gates, which can be designed, in L-EDIT using the
CMOS technology. The basic building blocks in CMOS technology are MOSFET’s. A
MOSFET is a metal oxide semiconductor field effect transistor. The advantages of
MOSFET over BJT’s are, they are smaller in size and the drain and source terminals are
interchangeable. This provides the designers with area minimization on the chip.
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Software used:
1. L-EDIT student version for drawing the layouts.
2. PSPICE for simulating the layouts.
Basic building blocks:
MOSFET’s are the basic building blocks. There are three main components to a CMOS
transistor. The Source and Drain can be interchanged at the silicon level and
occasionally at the device level. These are the main current carrying terminals. The Gate
is separated from the Composite (Silicon) by a thin layer of SiO2, which acts as an
insulator or dielectric. In the CMOS world you can create a Capacitor by shorting the
Source and Drain together calling that one terminal, and using the Gate for the other
terminal. The difference between an NMOS and a PMOS device depends on the type of
WELL (base) the transistor is sitting in.The layout of a p-channel MOSFET drawn in L-
Edit is shown in Figure 4. Layout of a MOSFET using L-Edit is very straightforward. An
n-channel device is constructed by creating an n+ region ndiff defined by
ndiff = (ACTIVE) AND (NSELECT)
A POLY over ndiff creates the transistor. The drawing steps for creating the nFET are as
follows.
1. Construct an ACTIVE box/polygon.
2. Surround ACTIVE with NSELECT. The intersection of the two is ndiff.
3. Create a POLY box that crosses completely over ndiff and extends beyond the
ACTIVE area. This creates the gate.
The actual drawing sequence is not important. However, all design rules should be
obeyed. Figure 4 shows the layout of an nMOSFET structure. Each layer is drawn
sequentially obeying all the design rules and a DRC is performed to check if there are any
errors in the layout design.
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Figure 4: nMOSFET
Figure 5 shows that nMOSFET is constructed without violating any design
rules.
Figure 5: DRC file for Figure 4
Figure 6 is the Extraction definition file for the layout in Figure 4.
Figure 6: Extract definition file for layout in Figure 4
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A p-channel MOSFET follows the same basic order, except that the n-well must be
defined. The steps are:
1. Create an NWELL region for the pMOSFET.
2. Construct an ACTIVE box/polygon for the transistor.
3. Surround ACTIVE with PSELECT. The intersection of the two is pdiff.
4. Draw a POLY box over pdiff for the gate.
5. Provide an ACTIVE and NSELECT box within NWELL for the n-well contact
(to VDD)
Note that the n+ contact formed in step 5 is needed to bias the n-well to the power supply
voltage.
Figure 7 shows the layout of a pMOSFET. Design is constructed sequentially by
performing DRC at each stage.
Figure 7: pMOSFET
Figure 8 shows the DRC file for a pMOSFET. All design rules are obeyed.
Figure 8: DRC file for Figure 7
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Figure 9 shows the extraction definition file for the layout in Figure 7.
Figure 9: Extract definition file for layout in Figure 7
The definition files are extracted using the morbn20.ext file, which gives the information
about the transistors and the corresponding nodes and parasitic capacitances. This is used
as a netlist in the PSPICE to generate the output waveform.
Procedure:
Any layout in L-Edit can be drawn using these two transistors. In this project, four XOR
gates are needed which can be built from the basic transistors. It is important to
understand the schematic of an XOR gate. A simple XOR gate can be built using two
inverters and two transmission gates.
CMOS Inverter:The schematic of a CMOS inverter circuit is shown in Figure 10. It consists of a p-FET
and an n-FET connected back in the form of a complimentary pair. The gates of the two
transistors are connected to the input pulse and the inverted output pulse is obtained at the
point where the source of the p-FET is connected to the drain of the n-FET. When the
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input pulse is at 0 level, the p-FET turns ON and the DC voltage VDD is observed at the
output. When the input is at HIGH level, the n-FET turns ON and the ground voltage 0 is
observed at the output.
Figure 10: CMOS Inverter
The layout of an inverter in L-Edit is shown in Figure 11.
Figure 11: Inverter layout
The .SPC file is extracted from this layout, which is shown in Figure 12. This file
indicates that there are two transistors in the layout i.e., M1 and M8. The line M1 11 3 10
PMOS indicates the nodes for the p-MOSFET in the order Drain Gate Source. By
observing the node numbers for both the transistors we can say that node 3 is the
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PMOS
NMOS
VDD
VSS
VOUTVIN
common gate where the input pulse is to be given and node 10 is the common point
where output is obtained. Voltage VDD is given at node 11 and VSS is given at node 9. By
using this information a .CIR file can be created wherein the values for these voltages are
specified at corresponding nodes.
Figure 12: .SPC file for inverter
The .cir file for an inverter is shown in Figure 13.
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Figure 13: .CIR file for an inverter
The lines VDD 11 0 DC 5 and VGND 9 0 DC 0 indicate the voltages between the starting
node and ending node and DC specifies the type of voltage given. The general format of
these lines can be written as
Node_ name starting_node ending_node voltage_type value
The next line in the .cir file indicates the pulse voltage given at the input. The general