Evaluating System-wide Monitoring Evaluating System-wide Monitoring Capsule Design Capsule Design Using Xilinx Virtex-II Pro FPGA Using Xilinx Virtex-II Pro FPGA Taeweon Suh Taeweon Suh § , Hsien-Hsin S. Lee Hsien-Hsin S. Lee § , Sally A. Mckee Sally A. Mckee † , and Martin Schulz Martin Schulz ♀ § Georgia Institute of Technology, Georgia Institute of Technology, † Cornell University, Cornell University, and and ♀ Lawrence Livermore National Laboratory Lawrence Livermore National Laboratory
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Evaluating System-wide Monitoring Capsule Design Using Xilinx Virtex-II Pro FPGA
Evaluating System-wide Monitoring Capsule Design Using Xilinx Virtex-II Pro FPGA. Taeweon Suh § , Hsien-Hsin S. Lee § , Sally A. Mckee † , and Martin Schulz ♀ § Georgia Institute of Technology , † Cornell University, and ♀ Lawrence Livermore National Laboratory. - PowerPoint PPT Presentation
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Using Xilinx Virtex-II Pro FPGAUsing Xilinx Virtex-II Pro FPGA
Taeweon SuhTaeweon Suh §, Hsien-Hsin S. Lee Hsien-Hsin S. Lee §, Sally A. Mckee Sally A. Mckee †,
and Martin Schulz Martin Schulz ♀
§ Georgia Institute of Technology, Georgia Institute of Technology, † Cornell University, Cornell University, and and ♀ Lawrence Livermore National LaboratoryLawrence Livermore National Laboratory
Georgia Tech, Cornell, LLNL - WARFP 2005
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Overcome traditional sampling, counter-based performance monitoring
Proposed general framework for system-wide monitoring called Owl
Monitoring capsule can be deployed anywhere in a system
Each monitoring capsule consists of FPGA cells to hold monitoring modules as well as standardized hardware interfaces
Pre-built monitoring modules are dynamically deployed in monitoring capsule’s FPGA fabric
Measure system perturbation adopting monitoring modules with different injection rates, by comparing execution times of SPEC2000 with/without monitoring
Georgia Tech, Cornell, LLNL - WARFP 2005
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Owl Evaluation Challenges on FPGA platformOwl Evaluation Challenges on FPGA platform
Memory on board is too fast, compared to processors in FPGAs
DDR SDRAM: 100MHz
Microblaze: 100MHz
=> This can be solved by inserting wait cycles for memory transactions in monitoring capsule
Available processors (Microblaze, PowerPC405) in FPGAs are too simple to mimic the state-of-the-art superscalar processors
=> However, Owl concept covers any complexity system,
which includes a rapid prototyped simple system like