Vivek Singh Intel Fellow Director, Computational Lithography Technology Manufacturing Group Intel Corporation EUV: The Computational Landscape EUVL Workshop, 2014
Vivek Singh Intel Fellow
Director, Computational Lithography
Technology Manufacturing Group
Intel Corporation
EUV: The Computational Landscape
EUVL Workshop, 2014
2 V. Singh EUVL Workshop, 2014
Outline
What the world wants (hint: 3D transistors)
Lithography: Choices for 14 nm and 10 nm – Inverse lithography and SMO
– “Double” patterning
– EUV lithography
Computational techniques for EUV – Flare
– Shadowing
– Out of band radiation
3 V. Singh EUVL Workshop, 2014
Outline
What the world wants (hint: 3D transistors)
Lithography: Choices for 14 nm and 10 nm – Inverse lithography and SMO
– “Double” patterning
– EUV lithography
Computational techniques for EUV – Flare
– Shadowing
– Out of band radiation
4 V. Singh EUVL Workshop, 2014
Connecting People to a World of Opportunity
Access Connectivity Healthcare Education
The World Ahead
Making
Technology
Available To
More People
Extending
Broadband
Connections
Transforming
Education To
Improve Teaching
And Learning
Delivering
Innovative
Healthcare
Solutions
5 V. Singh EUVL Workshop, 2014
Needs a Continuum of Personal Computing Experiences
Desktops Laptops Intelligent Systems
Smartphones Ultrabook™ Tablets
6 V. Singh EUVL Workshop, 2014
And that needs leading edge technology Every new node: more performance on more features at lower power
1x
0.1x
0.01x
0.001x Lo
wer
Tra
nsis
tor
Leakag
e
Higher Transistor Performance (Switching Speed)
Source: Intel
* projected
32nm 45nm 65nm 22nm
7 V. Singh EUVL Workshop, 2014
Intel 22nm technology introduces revolutionary 3-D Tri-Gate transistors
Such as… 3D transistors!
8 V. Singh EUVL Workshop, 2014
Real, high volume stuff
9 V. Singh EUVL Workshop, 2014
22nm Tri-Gate Transistor Benefits
Moore’s Law, at its heart, is about continuing
innovation to give the world what it wants
10 V. Singh EUVL Workshop, 2014
Source:
WSTS/Gartner/Intel
FAB $4 B
PILOT LINE $1-2 B
R&D PROCESS TEAM $0.5-1 B Source:
Intel
The
Benefit:
The
Cost:
103
104
105
106
107
108
109
1010
’70 ’80 ’90 ’00
As the number
of transistors
goes UP
Price per
transistor goes
DOWN
10
10-6
10-5
10-4
10-3
10-2
10-1
100
10-7
$
Yes. It makes our gadgets cheaper.
But can we afford Moore’s Law?
11 V. Singh EUVL Workshop, 2014
The End of Scaling is Near?
Various industry comments over the past 30 years
“Optical lithography will reach its limits in the range of 0.75-0.50 microns”
“Minimum geometries will saturate in the range of 0.3 to 0.5 microns”
“X-ray lithography will be needed below 1 micron”
“Minimum gate oxide thickness is limited to ~2 nm”
“Copper interconnects will never work”
“Scaling will end in ~10 years” Source: Mark
Bohr ISSCC
keynote, Feb.
2009 To paraphrase Mark Twain, rumors of
Scaling’s death are greatly exaggerated
In 2014, things look no different
12 V. Singh EUVL Workshop, 2014
Our limit to visibility goes out ~10 years
Innovation-Enabled Technology Pipeline is Full
13 V. Singh EUVL Workshop, 2014
Outline
What the world wants (hint: 3D transistors)
Lithography: Choices for 14 nm and 10 nm – Inverse lithography and SMO
– “Double” patterning
– EUV lithography
Computational techniques for EUV – Flare
– Shadowing
– Out of band radiation
14 V. Singh EUVL Workshop, 2014
Intel® Atom™ - dual-core
Rice – single grain
47 Million Transistors 45nm node
Hi-k Metal Gate 193 dry Litho
In 2012, on 22nm technology, the above chip would be ¼ the size - Smaller than the grain of rice!
Moore’s Law: circa 2008
15 V. Singh EUVL Workshop, 2014
Moore’s Law: circa 2010
263 mm2
240 mm2
Intel® Xeon® 5500 Processor (Gainstown), 45 nm Hi-k
731M Transistors, 4 Core, 8 MB Cache
Intel® “Westmere-EP” Processor (Gulftown), 32 nm 2nd Generation Hi-k
1.17B Transistors, 6 Core, 12 MB Cache
1.8x transistors/mm2
50% More Cores
50% More Cache 45 nm 32 nm
4 Core, 3.33 GHz
4 Core, 2.93 GHz
6 Core, 3.33 GHz
6 Core, 2.93 GHz
Perf.
Volume
130W
95W
16 V. Singh EUVL Workshop, 2014
22nm Intel Microprocessor codenamed Ivy Bridge (image released at Sept IDF)
Moore’s Law: circa 2012
17 V. Singh EUVL Workshop, 2014
Too small for the light we use… …have to find ways to bridge the gap
0.01
0.1
1
1980 1985 1990 1995 2000 2005 2010 2015 2020 2025
micron
10
100
1000
nm
32nm
22nm
14nmFeature Size
Wavelength248nm
193nm
EUV
13.5nm
Co-optimization
Computational Litho
Multi-patterning
18 V. Singh EUVL Workshop, 2014
Co-optimization: Living within your means
90nm
• All gates in one direction
except SRAM.
65nm
• All gates in one direction
everywhere.
• Different rules for minimum
pitch, larger gate pitch and
gate routing.
45nm/32nm
• All gates in one direction
and one pitch.
• Trench contact local
routing replaces orthogonal
to gate routing.
45nm 32nm
19 V. Singh EUVL Workshop, 2014
Layout has adapted to litho constraints, without affecting Moore’s march
65 nm Layout Style 32 nm Layout Style
• Bi-directional features
• Varied gate dimensions
• Varied pitches
• Uni-directional features
• Uniform gate dimension
• Gridded layout M. Bohr, ISCC, 2009
20 V. Singh EUVL Workshop, 2014
Outline
What the world wants (hint: 3D transistors)
Lithography: Choices for 14 nm and 10 nm – Inverse lithography and SMO
– “Double” patterning
– EUV lithography
Computational techniques for EUV – Flare
– Shadowing
– Out of band radiation
21 V. Singh EUVL Workshop, 2014
Lithography stepper, simplified
Light
Source
Mask
Lens
Wafer
Image
When feature is small,
image is blurred
22 V. Singh EUVL Workshop, 2014
Can we “bend” light by inverting the problem?
Light
Source
Mask
Lens
Wafer
Target
Image
Given an image,
what mask and source do I need?
23 V. Singh EUVL Workshop, 2014
Answer: Inverse Lithography (ILT) Input = design, Output = mask + source
Light
Source
Mask
Wafer
Target
Image
Computational Litho
Software
24 V. Singh EUVL Workshop, 2014
Increasing need for mask “correction”
From simple decorations to complex “distortions”
Intuition finally breaks down, optimal solution comes from math/computation
dog ears model-based
OPC
OPC + rule based
assist features
ILT
no correction
1990 2010 2000
25 V. Singh EUVL Workshop, 2014
ILT is non-intuitive
26 V. Singh EUVL Workshop, 2014
Changing shape of light source helps
Traditional light sources
lens must capture at least two diffracted orders
Normal Incidence light ray
0 +1 -1
Oblique Incidence light ray
ILT source
27 V. Singh EUVL Workshop, 2014
Solving the two problems simultaneously
+
ILT+SMO are used to sharpen the image of critical
masks for 14nm and 10nm nodes
28 V. Singh EUVL Workshop, 2014
Outline
What the world wants (hint: 3D transistors)
Lithography: Choices for 14 nm and 10 nm – Inverse lithography and SMO
– “Double” patterning
– EUV lithography
Computational techniques for EUV – Flare
– Shadowing
– Out of band radiation
29 V. Singh EUVL Workshop, 2014
Double Patterning: Capability…..with headaches!
A A A A A B A B AA B A C A B A
Conventional
All linewidthscorrelated
Pitch Halving
2 linewidth typesA & B anti-correlated
Pitch Quartering
3 linewidth typesA uncorrelated
B & C anti-correlated
Problems:
Cost, Complexity, Design Impact
30 V. Singh EUVL Workshop, 2014
Pitch halving and gate CD matching
Pitch halving eliminates the close correlation which currently exists between the CDs of adjacent gates
This has implications for memory cells and other circuits which depend upon this CD matching
A A
B
A
B B B 1266
1264 1262
860
Gate CD mismatch s
SR
AM
Vccm
in
C. Kenyon,
TOK conf.,
Dec. 2008
31 V. Singh EUVL Workshop, 2014
Misalignment in double-patterning
Misalignment between the 2 exposures is a crucial liability for this technique and can limit its usability
Transistor parameters can be affected by asymmetry between the source and drain regions
Print 1 Print 2
Misalignment
Registration (nm)
Normalized
IDSAT
K. Kuhn,
ICVC, 2009
32 V. Singh EUVL Workshop, 2014
EUV to the rescue! …can help contain rising cost of DP
Source: ITRS 2009
33 V. Singh EUVL Workshop, 2014
Single exposure EUV, simplified DRs
Advantages of EUV
High k1 relative to ArF
Single exposure
simplifies process flow
OPC is simpler
SE provides simpler DRs
Source: Obert Wood, EUV Workshop, July 2010
S. Sivakumar, SPIE 2011
34 V. Singh EUVL Workshop, 2014
The Challenges of EUV
Originally from S. Sivakumar, 2013 International Workshop on EUV Lithography
EUV HVM implementation depends on
satisfactory progress on all these fronts! M. Phillips, SPIE, 2014
Resists Patterning requirements...
Resolution – On track LWR/Dose – Need high power
Outgassing - Testing issues slow development
IDM TPT requirements Scanner outgassing requirements
Tool Source
Availability - Critical Power - Critical
Scanner Hardware - On track
Reticle Defectivity
Killer defect impact >> wafer process defect impact – Need pellicle Mitigation strategies
Reticle inspection - A-PI late, sources for A-PI, AIMS, A-BI are inadequate Patterned wafer inspection - not a substitute for A-PI or pellicle in HVM Alternative strategies
35 V. Singh EUVL Workshop, 2014
Short-term power outlook
• Need 40~80W stable MOPA+PP sources in the field linked to NXE:3300B scanners
• Not enough power for HVM, but enough to start TD and re-establish confidence in EUVL
• Seems achievable by Q1’14 given current status of program
• Need to look at remainder of EUV infrastructure and make sure it is on track for HVM introduction ~2017
M. Phillips, SPIE, 2014
36 V. Singh EUVL Workshop, 2014
The current lithography plan
Node Intel Approach
14nm ArF DP EUV Pilot Line
10nm ArF Extension EUV Pilot Line
37 V. Singh EUVL Workshop, 2014
Outline
What the world wants (hint: 3D transistors)
Lithography: Choices for 14 nm and 10 nm – Inverse lithography and SMO
– “Double” patterning
– EUV lithography
Computational techniques for EUV – Flare
– Shadowing
– Out of band radiation
38 V. Singh EUVL Workshop, 2014
Computational Lithography Infrastructure extends to EUV
Shadowing
Flare
Out-of-Band (OOB) Radiation
Computational
Litho Infrastructure
(Not to scale)
39 V. Singh EUVL Workshop, 2014
Lets start with Flare
-10
00
0
-80
00
-60
00
-40
00
-20
00 0
20
00
40
00
60
00
80
00
10
00
0
-10000
-5000
0
5000
10000
0.00E+00
5.00E-09
1.00E-08
1.50E-08
2.00E-08
2.50E-08
3.00E-08
3.50E-08
4.00E-08
PSFsc (1/nm2)
x (nm)
y (nm)
0.1
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
0.2
0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 80,000 90,000 100,000
Radial distance (nm)
Fla
re
otherwisezero600nm,fornm
1166.0PSF
239.2 r
r
After a sharp fall, PSF decays
very slowly
As a result, “far away” layout
geometry affects local flare
40 V. Singh EUVL Workshop, 2014
Components of flare contributions
Short range (mm) component Long range (mm) component
41 V. Singh EUVL Workshop, 2014
Final flare result for 3mm2 patch
Max = 16.9%
Min = 0.54%
Rng = 16.4%
Avg = 5.62%
42 V. Singh EUVL Workshop, 2014
Full Chip Flare Compensation
(work is in handling boundaries)
Domain with Flare Data Effect of flare on Image intensity
43 V. Singh EUVL Workshop, 2014
Modeling of Mask Shadowing
1. Create Mask Geometry 2. Calculate E-fields
3. Calculate
Wafer Image
44 V. Singh EUVL Workshop, 2014
H-V Delta for 0.25NA vs 0.35NA
45 V. Singh EUVL Workshop, 2014
OOB: Out-of-band radiation Problem: Resist is more sensitive to OOB
Source: J. Roberts, R.Bristol. T. Younkin, T. Fedynyshyn, D. Astolfi, A.Cabral
Proc. SPIE 7272 (2009)
46 V. Singh EUVL Workshop, 2014
EUV image comparison with OOB (rigorous simulation is too slow)
Resulting EUV+OOB images match within 0.003 (assuming 4% total flare from OOB).
EUV+OOB (fast)
EUV+OOB (rigorous)
47 V. Singh EUVL Workshop, 2014
Computational Litho for EUV is not a problem
48 V. Singh EUVL Workshop, 2014
“If you build it, they will come”
49 V. Singh EUVL Workshop, 2014
Summary
What the world wants (hint: 3D transistors)
–Demand and Economics drive Moore’s Law
Lithography: Choices for 14 nm and 10 nm
–Double Patterning is the workhorse, with caveats
Computational techniques for EUV
–Computational Litho for EUV is not a problem
50 V. Singh EUVL Workshop, 2014
How will this mask print?
51 V. Singh EUVL Workshop, 2014
The image from 193 pixelation
52 V. Singh EUVL Workshop, 2014
…if you used EUV, however…
53 V. Singh EUVL Workshop, 2014
Acknowledgments
Kenny Toh, Principal Engineer
Sam Sivakumar, Intel Fellow, Director of Lithography
Yan Borodovsky, Senior Intel Fellow, Director of Advanced Lithography
Michael C. Mayberry, Intel Vice President, Director of Components Research
Mark Phillips, Senior Principal Engineer
Richard Schenker, Senior Principal Engineer