DAC2003 Accellera SystemVerilog Workshop 127 Agenda Session 3: SystemVerilog Assertions Language Tutorial Bassam Tabbara, Novas Software Technology and User Experience Alon Flaisher, Intel Session 1: SystemVerilog for Design Language Tutorial Johny Srouji, Intel User Experience Matt Maidment, Intel Introduction: SystemVerilog Motivation Vassilios Gerousis, Infineon Technologies Accellera Technical Committee Chair Using SystemVerilog Assertions and Testbench Together Jon Michelson, Verification Central Session 4: SystemVerilog APIs Doug Warmke, Model Technology Lunch: 12:15 – 1:00pm Session 2: SystemVerilog for Verification Session 5: SystemVerilog Momentum Verilog2001 to SystemVerilog Stuart Sutherland, Sutherland HDL Language Tutorial Tom Fitzpatrick, Synopsys SystemVerilog Industry Support Vassilios Gerousis, Infineon User Experience Faisal Haque, Verification Central End: 5:00pm
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DAC2003 Accellera SystemVerilog Workshop 127
AgendaSession 3: SystemVerilog Assertions
Language TutorialBassam Tabbara, Novas Software
Technology and User ExperienceAlon Flaisher, IntelSession 1:
Using SystemVerilog Assertionsand Testbench Together
Jon Michelson, Verification Central
Session 4: SystemVerilog APIsDoug Warmke, Model Technology
Lunch: 12:15 – 1:00pm
Session 2:SystemVerilog for Verification Session 5: SystemVerilog Momentum
Verilog2001 to SystemVerilogStuart Sutherland, Sutherland HDLLanguage Tutorial
Tom Fitzpatrick, SynopsysSystemVerilog Industry Support
Vassilios Gerousis, InfineonUser Experience
Faisal Haque, Verification CentralEnd: 5:00pm
DAC2003 Accellera SystemVerilog Workshop 128
Goals of this presentation• Understand the testbench model for
SystemVerilog • Show how SystemVerilog constructs are
used to build testbenches• Walk through the construction of a
testbench for an Ethernet MAC
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My Background• Chair of SystemVerilog Assertions
committee• Co-author of “The Art of Verification with
Vera” • Co-author of upcoming SystemVerilog
book
www.verificationcentral.com
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packets
tran
sact
or
0101010
Gen
erat
or
Des
ign
Und
er T
est
0101010
tran
sact
or
Che
cker
packets
Dire
ctor
PredictResponse
Coverage Monitor
classes interfaces
A Typical TestbenchAdapted from “The Art of Verification with Vera”
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Recommended SV constructs for use in testbench• Program block• Classes• Interfaces• Clocking• Mailboxes, semaphores• Constraints and random variables• Assertions
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Program Block• Testbench implemented as multiple program blocks– For example: generator, checker in separate program blocks
• Testbench implemented as a single program block – Classes instantiated within program block
• Program block with classes instantiated within the interface
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Testbench implementation options
DUT
interface(s)Transactor(s)
ProgramGen
ProgramChecker
test_top.v
DUT
interface(s)Transactors
Program
GenChecker
test_top.v
DUT
interface(s)Transactors
GenChecker
test_top.v
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Classes• Provide a mechanism to encapsulate data • Recommended for almost all testbench
components• Layer classes to build powerful structures
Generator
Pkt Gen MII EventGen
Network Event Gen
Packet
DAC2003 Accellera SystemVerilog Workshop 135
Interfacing to the Design Under Test (DUT)• Use interface to logically group ports• interfaces can also instantiate tasks, program blocks or classes to act as transactors
• Classes instantiated inside program blocks will execute in the reactive region of SystemVerilog (Cycle based)
• Classes instantiated outside program blocks will display event based semantics
• Use clocking to define synchronization of the DUT ports with the Testbench
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Mailboxes and Semaphores• Use Mailboxes to pass messages between
two threads– Can be used to represent FIFO
implementations• Use semaphores to arbitrate between two