ETE 204 - Digital Electronics Latches and Flip-Flops [Lecture:12] Instructor: Sajib Roy Lecturer, ETE, ULAB.

ETE 204 - Digital Electronics

Latches and Flip-Flops

[Lecture:12]Instructor: Sajib RoyLecturer, ETE, ULAB

Brief introductionto

Sequential Logic Circuits

Summer 2012 ETE 204 - Digital Electronics 2


● The output of a sequential logic circuit is dependentnot only on the present inputs, but also on the pastsequence of the inputs.

● A sequential logic circuit must “remember” the pasthistory of the inputs.

● It does this using basic memory elements.

- Latches

- Flip-Flops

3Summer 2012 ETE 204 - Digital Electronics


inputsCombinational

LogicCircuit

outputs

Memory


Basic Memory Elements



● Latch- Clock input is level sensitive.

- Output can change multiple times during a clockcycle.

- Output changes while clock is

active.

● Flip-Flop- Clock input is edge sensitive.

- Output can change only once during a clock cycle.

- Output changes on clock transition.



Both latches and flip-flops use feedback toachieve “memory”.


Feedback Circuit with 2 Stable States

What is the problem with this circuit?


Latches


Set-Reset (SR) Latch● A Set-Reset Latch has two inputs

- Set (S) input

- Reset (R) input

● It can be constructed from two cross-coupled NORgates or two cross-coupled NAND gates.

● It has three modes of operation

- Set: Latch output set to 1 (Q+ = 1)

– Reset: Latch output reset to 0 (Q+ = 0)

- Store: Latch output does not change (Q+ = Q)


SR Latch: using NOR gates

A B NOR

0 X X'

1 X 0

Feedback NOR gates


SR Latch: Set (S = 1, R = 0)

A B NOR0 X X'

1 X 0

10

P = Q'

10


SR Latch: Reset (S = 0, R = 1)

A B NOR0 X X'

1 X 0

01

P = Q'

01


SR Latch: Store (S = 0, R = 0)

Initial Condition: P = 0, Q = 1 A B NOR0 X X'

1 X 0

00

P = Q'

10


SR Latch: Store (S = 0, R = 0)

Initial Condition: P = 1, Q = 0 A B NOR0 X X'

1 X 0

01

P = Q'

00


SR Latch: Behavior

Present Nextvalue value

S R Q Q+

0 0

0 0

0 1

0 0

1 1

0 0

• If S = 1 (Set), Q+ = 1

• If R = 1 (Reset), Q+ = 00 1 1 0

1 0 0 1 • If S = R = 0, Q+ = Q (no change)

1 0

1 1

1 1

0 not• S = R = 1 is not allowed.

1 1 1 allowed


SR Latch: Improper Operation

P ≠ Q′


SR Latch: Symbol

alwayscomplementary

Q'

Q

S Q

SRLatch

R Q'


SR Latch: Timing Diagram

store set store reset

Q'

Q

= propagation delay of the latch


SR Latch: Characteristic Equation

Q = present state

Q+ = next state

Characteristic Equation: Q+ = S + R'.Q (S.R = 0)20Summer 2012 ETE 204 - Digital Electronics

SR Latch: using NAND gates

A B NAND

0 X 1

1 X X'

S' R' Q Q+

1 1 0 0

1 1 1 1

1 0 0 0

1 0 1 0

0 1 0 1

0 1 1 1

0 0 0 not

0 0 1 allowed


Gated D Latch● A Gated D Latch has two inputs

- Gate (G) input

- Data (D) input

● It can be constructed from an SR Latch andadditional logic gates.

● It has the following behavior

- G = 1: D is passed to Q (Q+ = D)

- G = 0: Q remains unchanged (Q+

= Q)

● Also referred to as a transparent latch. 22Summer 2012 ETE 204 - Digital Electronics

Gated D Latch: Circuit and Timing

NOR gates

23

Summer 2012 ETE 204 - Digital Electronics

Gated D Latch: Symbol and Truth Table

No invalid inputs!


Gated D Latch: Characteristic Equation

0 2 6 4

1 3 7 5

Characteristic Equation: Q+ = G'.Q + G.D

Spring 2011 ECE 30 - Digital Electronics 25Summer 2012 ETE 204 - Digital Electronics

Gated D Latch: using NAND gates

S'

R'

NAND gates


Flip-Flops


D Flip-Flop● A D Flip-Flop has two inputs

- Clock (Ck) --- denoted by the small arrowhead

- Data (D)

● The output of the D Flip-Flop changes in response tothe clock input only.

- not in response to a change in the D input

● The D Flip-Flop is edge-triggered not level-sensitive

- Positive (or rising) edge-triggered: 0 → 1

– Negative (or falling) edge-triggered: 1 → 0


D Flip-Flop

Characteristic Equation:

Q+ = D


D Flip-Flop: Timing Diagram

Which clock edge is the D flip-flop triggered on?


D Flip-Flop (master-slave)

Gated D Latches

Enabled on opposite levels of the clock


D Flip-Flop: Timing Diagram

Which clock edge is the D flip-flop triggered on?


D Flip-Flop: Setup and Hold Times

Setup time Hold time

Propagation delay


D Flip-Flop: Minimum Clock Period


Questions?


ETE 204 - Digital Electronics Latches and Flip-Flops [Lecture:12] Instructor: Sajib Roy Lecturer, ETE, ULAB.

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