ESD8104 - ESD Protection Diode · ESD8104 ESD Protection Diode Low Capacitance Array for High Speed Data Lines The ESD8104 is designed to protect high speed data lines from ESD. Ultra−low
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The ESD8104 is designed to protect high speed data lines fromESD. Ultra−low capacitance and low ESD clamping voltage make thisdevice an ideal solution for protecting voltage sensitive high speeddata lines. The flow−through style package allows for easy PCB layoutand matched trace lengths necessary to maintain consistent impedancebetween high speed differential lines such as USB 3.0/3.1 and HDMI2.0.
Features• Low Capacitance (0.37 pF Max, I/O to GND)• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)• Low ESD Clamping Voltage• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified andPPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHSCompliant
Typical Applications• USB 3.0/3.1• eSATA• HDMI 1.3/1.4/2.0• DisplayPort
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Operating Junction Temperature Range TJ −55 to +125 °C
Storage Temperature Range Tstg −55 to +150 °C
Lead Solder Temperature −Maximum (10 Seconds)
TL 260 °C
IEC 61000−4−2 Contact (ESD)IEC 61000−4−2 Air (ESD)
ESDESD
±15±15
kVkV
Stresses exceeding those listed in the Maximum Ratings table may damage thedevice. If any of these limits are exceeded, device functionality should not beassumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of survivability specs.
MARKINGDIAGRAM
Device Package Shipping
ORDERING INFORMATION
UDFN10CASE 517BB
PIN CONFIGURATIONAND SCHEMATIC
www.onsemi.com
ESD8104MUTAG UDFN10(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationBrochure, BRD8011/D.
4C M�
�
4C = Specific Device Code (tbd)M = Date Code� = Pb−Free Package
I/O I/O I/OI/O GND
N/C N/C N/C N/CGND
1 4 52 3
10 7 69 8
(Note: Microdot may be in either location)
I/OPin 1
I/OPin 2
I/OPin 4
I/OPin 5
Pins 3, 8
Note: Common GND − Only Minimum of 1 GND connection required
Dynamic Resistance RDYN I/O Pin to GNDGND to I/O Pin
0.360.44
�
Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GNDVR = 0 V, f = 1 MHz between I/O PinsVR = 0 V, f = 1 MHz, TA = 65°C between I/O Pins and GND
0.300.150.37
0.370.200.47
pF
1. For test procedure see Figures 3 and 4 and application note AND8307/D.2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
Figure 4. Diagram of ESD Clamping Voltage Test Setup
50 �50 �Cable
TVS OscilloscopeESD Gun
The following is taken from Application NoteAND8307/D − Characterization of ESD ClampingPerformance.
ESD Voltage ClampingFor sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD eventto as low a voltage as possible. The ESD clamping voltageis the voltage drop across the ESD protection diode duringan ESD event per the IEC61000−4−2 waveform. Since theIEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is notclearly defined in the spec how to specify a clamping voltageat the device level. ON Semiconductor has developed a wayto examine the entire voltage waveform across the ESDprotection diode over the time domain of an ESD pulse in theform of an oscilloscope screenshot, which can be found onthe datasheets for all ESD protection diodes. For moreinformation on how ON Semiconductor creates thesescreenshots and how to interpret them please refer toAND8307/D.
NOTE: TLP parameter: Z0 = 50 �, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltagestress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP descriptionbelow for more information.
10 10
Transmission Line Pulse (TLP) MeasurementTransmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtainedfrom a 100 ns long rectangular pulse from a chargedtransmission line. A simplified schematic of a typical TLPsystem is shown in Figure 7. TLP I−V curves of ESDprotection devices accurately demonstrate the product’sESD capability because the 10s of amps current levels andunder 100 ns time scale match those of an ESD event. Thisis illustrated in Figure 8 where an 8 kV IEC 61000−4−2current waveform is compared with TLP current pulses at8 A and 16 A. A TLP I−V curve shows the voltage at whichthe device turns on as well as how well the device clampsvoltage over a range of current levels. For more informationon TLP measurements and how to interpret them pleaserefer to AND9007/D.
Figure 7. Simplified Schematic of a Typical TLPSystem
DUT
L S÷
Oscilloscope
Attenuator
10 M�
VC
VMIM
50 � CoaxCable
50 � CoaxCable
Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
PCB Layout GuidelinesSteps must be taken for proper placement and signal trace
routing of the ESD protection device in order to ensure themaximum ESD survivability and signal integrity for theapplication. Such steps are listed below.• Place the ESD protection device as close as possible to
the I/O connector to reduce the ESD path to ground andimprove the protection performance.♦ In USB 3.0/3.1 applications, the ESD protection
device should be placed between the AC couplingcapacitors and the I/O connector on the TXdifferential lanes as shown in Figure 16.
• Make sure to use differential design methodology andimpedance matching of all high speed signal traces.♦ Use curved traces when possible to avoid unwanted
reflections.♦ Keep the trace lengths equal between the positive
and negative lines of the differential data lanes toavoid common mode noise generation andimpedance mismatch.
♦ Place grounds between high speed pairs and keep asmuch distance between pairs as possible to reducecrosstalk.
ESD Protection Device TechnologyON Semiconductor’s portfolio contains three main
technologies for low capacitance ESD protection devicewhich are highlighted below and in Figure 17.• ESD7000 series: Zener diode based technology. This
technology has a higher breakdown voltage (VBR)limiting it to protecting chipsets with larger geometries.
• ESD8000 series: Silicon controlled rectifier (SCR) typetechnology. The key advatange for this technology is alow holding voltage (VH) which produces a deepersnapback that results in lower voltage over high
currents as shown in the TLP results in Figure 18. Thistechnology provides optimized protection for chipsetswith small geometries against thermal failures resultingin chipset damage (also known as “hard failures”).
• ESD8100 series: Low voltage punch through (LVPT)type technology. The key advatange for this technologyis a very low turn-on voltage as shown in Figure 19.This technology provides optimized protection forchipsets with small geometries against recoverablefailures due to voltage peaks (also known as “softfailures”).
Figure 17. ON Semiconductor’s Low-cap ESD Technology Portfolio
Figure 18. High Current, TLP, IV Characteristic of Each Technology
ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN0.15 AND 0.30mm FROM TERMINAL.
C SEATINGPLANE
D B
E0.10 C
A3 A
A1
2X
2X 0.10 C
DIMA
MINMILLIMETERS
0.45A1 0.00A3 0.13 REFb 0.15
D 2.50 BSCb2 0.35
E 1.00 BSCe 0.50 BSC
PIN ONEREFERENCE
0.08 C
0.10 C
10X
A0.10 C
NOTE 3
L
e
b2
bB
5
6
8X
1
10
10X
0.05 C
0.30L
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
0.450.50
DIMENSIONS: MILLIMETERS
1.30
PITCH
0.25
10X
0.550.05
0.250.45
0.40
MAX
ÇÇÇÇÇÇÉÉÉÉÉÉA1
A3
DETAIL B
MOLD CMPDEXPOSED Cu
OPTIONALCONSTRUCTION
L1DETAIL A
L
OPTIONALCONSTRUCTIONS
L
---L1 0.05
TOP VIEW
SIDE VIEW
BOTTOM VIEW
DETAIL B
DETAIL A
OUTLINEPACKAGE
A
2X
RECOMMENDED
2X
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ESD8104/D
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