EOS: A Monolithic CMOS Photonic Platform Vladimir Stojanović, Rajeev Ram, Milos Popović*, Jason Orcutt, Michael Georgas, Jonathan Leu, Benjamin Moss, Chen Sun, Jie Sun and Hanqing Li Massachusetts Institute of Technology * University of Colorado, Boulder
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EOS: A Monolithic CMOS Photonic
Platform
Vladimir Stojanović, Rajeev Ram, Milos Popović*,
Jason Orcutt, Michael Georgas, Jonathan Leu,
Benjamin Moss, Chen Sun, Jie Sun and Hanqing Li
Massachusetts Institute of Technology *University of Colorado, Boulder
Monolithic Si-Photonics for core-to-core and
core-to-DRAM networks
2 2
Supercomputers
Embedded apps
Si-photonics in advanced
CMOS and DRAM process
NO costly process changes
Bandwidth density – need dense WDM
Energy-efficiency – need monolithic integration
Many architectural studies show promise
3
[Shacham’07]
[Petracca’08]
[Vantrease’08]
[Psota’07]
[Kirman’06]
[Joshi’09]
[Pan’09]
[Batten’08] [Beamer’10] [Koka’08-10]
Significant integration activity,
but hybrid and older processes …
4
[Luxtera/Oracle/Kotura] [IBM]
[HP]
[Watts/Sandia/MIT]
[Intel]
130nm
thick BOX SOI
130nm
thick BOX SOI
Bulk CMOS
Backend
monolithic
[Lipson/Cornell]
[Kimerling/MIT]
[Many schools]
Big Challenge:
Efficient integration with circuits
5
Reg
iste
r
Mu
x
Pre-Driver Mod-DriverReceiver
Front-end
Φ Φ Φ
Φ Φ
+
Samplers &
Monitoring
Dem
ux
Reg
iste
r
PLL or
Opt. Clk
1 2 3 4 in PLL or
Opt. Clk
Phase
Adjust
Reg
iste
r
Mu
x
Pre-Driver Mod-DriverReceiver
Front-end
Φ Φ Φ
Φ Φ
+
Samplers &
Monitoring
Dem
ux
Reg
iste
r
PLL or
Opt. Clk
1 2 3 4 in PLL or
Opt. Clk
Phase
Adjust
Dense WDM – 128 wavelengths/waveguide - >1Tb/s per waveguide
Need 1000’s of transceivers on die with < 100fJ/bit cost at > 10Gb/s !
65 nm bulk CMOS Texas Instruments
90 nm bulk CMOS IBM cmos9sf
45 nm SOI CMOS IBM 12SOIs0
6
32 nm bulk CMOS Texas Instruments
~6-uA
EOS Platform for Monolithic CMOS
photonic integration
-200 0 200 400 600 800 1000
-14
-12
-10
-8
-6
-4
-2
0
Tra
nsm
issio
n, dB
Frequency, GHz
2007
2010
Zero-Change
Foundry Mask-Share Integration
7
Integrated link test cell
Detector Modulator
8
Bulk CMOS Cross Section
9
4
Front-end Photonic Integration
10
5
Optical Loss Determines Metal Spacing
• Vertical exclusion (Top Metal) doesn’t
interfere with global signal / power wires
• Lateral Exclusion (Low Metals) doesn’t
violate density rules
Localized Substrate Removal
11
14
Vapor-Phase Selective
Silicon Etch (Undercut)
Single Step
Self-Aligned
RIE Etch
Localized Substrate Removal - SEM
12
14
A 32nm bulk CMOS photonic platform
Monolithic CMOS photonic platform integrated with CMOS circuits
32nm process – fabrication support from Texas Instruments
Robust post-processing steps at MIT
Second-order resonator filterbank shows process precision
Great on-die matching (rings track within 40GHz)
Record thermal heating efficiency 25uW/K
Orcutt et al – CLEO 2008, Optics Express 2010 13
Polysilicon and Silicon Photonics on Thin BOX IBM SOI R