UPC CGO’03 San Francisco March 2003 Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache Enric Gibert 1 Jesús Sánchez 2 Antonio González 1,2 1 Dept. d’Arquitectura de Computadors Universitat Politècnica de Catalunya (UPC) Barcelona 2 Intel Barcelona Research Center Intel Labs Barcelona
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Enric Gibert 1 Jes ús Sánchez 2 Antonio González 1,2
Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache. Enric Gibert 1 Jes ús Sánchez 2 Antonio González 1,2. 1 Dept. d’Arquitectura de Computadors Universitat Politècnica de Catalunya (UPC) Barcelona. 2 Intel Barcelona Research Center - PowerPoint PPT Presentation
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UPC
CGO’03San Francisco
March 2003
Local Scheduling Techniques for Memory Coherence in a Clustered VLIW
Processor with a Distributed Data Cache
Local Scheduling Techniques for Memory Coherence in a Clustered VLIW
Processor with a Distributed Data Cache
Enric Gibert1
Jesús Sánchez2
Antonio González1,2
1Dept. d’Arquitectura de Computadors
Universitat Politècnica de Catalunya (UPC)
Barcelona
2Intel Barcelona Research CenterIntel LabsBarcelona
UPC
CGO’03San Francisco
March 2003
Motivation
Capacity vs. Communication-bound Clustered microarchitectures
– Simpler + faster– Power consumption– Communications not homogeneous
Clustering embedded/DSP domain
UPC
CGO’03San Francisco
March 2003
Clustered Microarchitectures
CLUSTER 1
Reg. FileReg. File
FUsFUs
CLUSTER 2
Reg. FileReg. File
FUsFUs
CLUSTER 3
Reg. FileReg. File
FUsFUs
CLUSTER 4
Reg. FileReg. File
FUsFUs
Register-to-register communication buses
L1 cacheL1 cache
L2 cacheL2 cache
Memory buses
CLUSTER 1
Reg. FileReg. File
FUsFUs
CLUSTER 2
Reg. FileReg. File
FUsFUs
CLUSTER 3
Reg. FileReg. File
FUsFUs
CLUSTER 4
Reg. FileReg. File
FUsFUs
Register-to-register communication buses
L1 cachemodule
L1 cachemodule
L2 cacheL2 cache
L1 cachemodule
L1 cachemodule
L1 cachemodule
L1 cachemodule
L1 cachemodule
L1 cachemodule
CLUSTER 1
Reg. FileReg. File
FUsFUs
CLUSTER 2
Reg. FileReg. File
FUsFUs
CLUSTER 3
Reg. FileReg. File
FUsFUs
CLUSTER 4
Reg. FileReg. File
FUsFUs
Register-to-register communication buses
L1 cachemodule
L1 cachemodule
L2 cacheL2 cache
L1 cachemodule
L1 cachemodule
L1 cachemodule
L1 cachemodule
L1 cachemodule
L1 cachemodule
Memory buses
UPC
CGO’03San Francisco
March 2003
Contributions
Distribution of data cache– Architecture design + data mapping
• Word-interleaved scheme [ICS’02]
– Appropriate scheduling techniques [MICRO’02]
– Memory coherence Scheduling techniques for mem. coherence
– Local software-based techniques– Applied to word-interleaved cache