ENKODER DAN DEKODER SANDI BLOK LINEAR (7,4) BERBASIS RANGKAIAN DIGITAL TUGAS AKHIR Diajukan untuk memenuhi salah satu syarat Memperoleh gelar Sarjana Teknik pada Program Studi Teknik Elektro Fakultas Teknik Universitas Sanata Dharma Disusun oleh: EKO HENDRI YETNO NIM : 005114098 PROGRAM STUDI TEKNIK ELEKTRO FAKULTAS TEKNIK UNIVERSITAS SANATA DHARMA YOGYAKARTA 2007 i
134
Embed
ENKODER DAN DEKODER SANDI BLOK LINEAR (7,4) BERBASIS ...repository.usd.ac.id/28201/2/005114098_Full.pdf · HALAMAN PERSEMBAHAN ....Ku Persembahkan Karya Ilmiah ini untuk penebusku
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
ENKODER DAN DEKODER SANDI BLOK LINEAR (7,4) BERBASIS RANGKAIAN
DIGITAL
TUGAS AKHIR Diajukan untuk memenuhi salah satu syarat
Memperoleh gelar Sarjana Teknik pada Program Studi Teknik Elektro
Fakultas Teknik Universitas Sanata Dharma
Disusun oleh: EKO HENDRI YETNO
NIM : 005114098
PROGRAM STUDI TEKNIK ELEKTRO
FAKULTAS TEKNIK
UNIVERSITAS SANATA DHARMA
YOGYAKARTA
2007 i
ENCODER AND DECODER OF LINEAR BLOCK (7,4) CODE BASED ON DIGITAL
CIRCUITS
FINAL PROJECT
Presented as Partial Fulfillment of the Requirements To Obtain the Sarjana Teknik Degree
in Electrical Engineering Study Program
By :
EKO HENDRI YETNO
NIM : 005114098
ELECTRICAL ENGINEERING STUDY PROGRAM
ELECTRICAL ENGINEERING DEPARTMENT
ENGINEERING FACULTY
SANATA DHARMA UNIVERSITY
YOGYAKARTA
2007
ii
iii
iv
v
Pernyataan Keaslian Karya
Saya menyatakan dengan sesungguhnya bahwa tugas akhir yang saya tulis
ini tidak memuat karya atau bagian karya orang lain, kecuali yang telah
disebutkan dalam kutipan dan daftar pustaka, sebagaimana layaknya karya ilmiah.
Yogyakarta, Juli 2007
Penulis
Eko Hendri Yetno
HALAMAN PERSEMBAHAN
....Ku Persembahkan Karya Ilmiah ini untuk penebusku dan
penyelamatku Tuhan Yesus Kristus yang memberi anugerah
yang tak ternilai dengan apapun di dunia ini.
....Untuk Kedua orang tua kandungku dan kedua orang tua angkatku
yang telah membesarkanku dengan kasih sayangnya dan
selalu mendoakan dan memberi semangat di dalam hidupku.
....Untuk kedua adikku terimakasih atas doa dan dukungannya
sehingga saya dapat menyelesaikan karya ilmiah ini.
....Untuk nenekku yang sungguh mengasihiku
....Untuk seseorang yang menjadi inspirasiku yang mewarnai
hidupku dengan sejuta tawa dan kebahagian..
vi
HALAMAN MOTTO
Takut akan Tuhan adalah permulaan pengetahuan, tetapi
orang bodoh menghina hikmat dan didikan.
(Amsal 1:7 )
Sesederhana apapun di kehidupan kita baik senang,
sedih, tertawa, menangis dan apapun itu juga, datangnya
dari Allah atas dasar kasih karuniaNya dan kerelaanNya
oleh karena itu kita harus senantiasa bersyukur di
dalam kehidupan kita dan bermazmur di dalam namaNya.
Takut gagal menghalangi kita untuk Mencoba Meraih
sukses, takut kalah menghalangi kita untuk mencoba
meraih kemenangan, takut apa kata orang menghalangi
kita untuk melangkah dengan berani, takut dicemooh
menghalangi kita untuk menyatakan iman kita kepada
Tuhan, diatas segalanya, ketakutan itu mencekik
pengharapan. ( Rich Devos)
All Beginning is difficult but Every Cloud has a silver
lining. Semua Permulaan adalah sulit tetapi di dalam
kesedihan/kesesakan selalu ada pengharapan akan
kebahagiaan.
vii
viii
INTI SARI
Sandi Blok linear (7,4) merupakan sandi pendeteksi dan koreksi kesalahan berbasis blok, yang menyadikan vektor pesan sepanjang 4 bit menjadi sebuah vektor sandi 7 bit dengan 3 bit adalah bit paritasnya. Sandi blok linear (7,4 ) mampu mendeteksi kesalahan lebih dari satu bit kesalahan tetapi hanya mampu mengoreksi 1 bit data kesalahan.
Sandi blok linear dibagi menjadi 4 bagian besar utama yaitu rangkaian penyandi ( Encoder ), Pembuat galat, rangkaian deteksi ( Sindrom ) dan rangkaian koreksi. Empat bit vektor pesan di masukkan ke dalam rangkaian penyandi secara seri melalui saklar dan selanjutnya diproses pada rangkaian penyandi sehingga menghasilkan 3 bit paritas. Hasil dari proses oleh rangkaian penyandi membentuk vektor sandi yang terdiri dari 7 bit data yang selanjutnya dikirimkan ke rangkaian sindrom melalui sebuah rangkaian pembuat galat. Bila kita menginginkan bahwa vektor sandi yang dikirimkan diberi galat, maka pemberian galat dilakukan pada rangkain pembuat galat. Rangkaian sindrom akan mendeteksi vektor sandi yang diterima, apakah ada galat atau tidak ada galat dan selanjutnya dikoreksi pada rangkaian pengkoreksi. Hasil dari rancangan ini di tampilkan dengan LED.
Kata Kunci : Sandi Blok Linear (7,4), Rangkian Digital.
ix
ABSTRACT
Linear block (7.4) code is a block-based error detecting and correcting code which encodes 4 (four) bit messages to be 7 (seven ) bit codes with 3 (three) bit parity. The linear block (7,4) code is able to detect more than one bit error but just one bit error datum.
The linear block (7,4) code consists of four main parts, that are : Encoder circuit, error generator circuit, error detector circuit or syndrome circuit and error corection. First the four bit message vector are put into the encoder circuit serially through an switch, then those codes processed by the encoder circuit produce three bit parity. The result of this procces forms a code vector consisting of seven bit data. The data will be sent to the syndrome circuit through the error generator circuit. If we want the code vector sent is given any error, it should be done in the error generator circuit. The syndrome circuit will detect the code vector received whether there is any error or not. At last the code will be corrected in the error corection circuit. The result of design is showed by LED.
Key Words : Linear Block (7,4) Code, Digital Circuit.
x
KATA PENGANTAR
Puji dan syukur penulis panjatkan ke hadirat Tuhan Yang Maha Esa, oleh
karena kasih dan penyertaan-Nya sehingga penulis dapat meyelesaikan Tugas
Akhir yang berjudul “Enkoder Dan Dekoder Sandi Blok Linear (7,4) Berbasis
Digital”. Tugas Akhir ini disusun sebagai salah satu syarat untuk memperoleh
gelar Sarjana pada jurusan Teknik Elektro, Fakultas Teknik Universitas Sanatha
Dharma Yogyakarta. Dalam penyusunannya, banyak pihak yang telah membantu
dan memberikan dukungan pada penulis, oleh karena itu, penulis ingin
mengucapkan terima kasih kepada:
1. Ibu Ir. Th. Prima Ari Setyani, M.T. sebagai pembimbing yang membagikan
semua ilmu-ilmu elektronika dan pengalaman yang dimilikinya dalam
membantu proses penyusunan tugas akhir ini.
2. Segenap karyawan / karyawati Universitas Sanata Dharma.
3. Bapak, Ibu, dan Eyang Puti yang tidak pernah berhenti memberikan doa,
semangat dan dukungannya.
4. Adik-adikku : Sugianto dan Annisa yang tidak pernah berhenti memberikan
doa, semangat dan dukungannya.
5. Keluarga besar pelayanan Para Navigator Regu B Yogyakarta, yang
memberikan dukungan dan doanya.
6. Kel. Abu Prawoto dan Mas Nug terimakasih sekali karena terus mendukungku
tidak hanya di dalam doa tetapi sering mentraktirku dan sebagai sahabat
terbaikku di dalam susah maupun senang dan juga mengajarkan tentang
makna hidup yang sesungguhnya.
7. Untuk Saudara-saudaraku di negeri sebrang : Mas Andre di banjarmasin, Mas
marcel dan Mas udut di Mataram Dan teman-teman AL Malang 2006 Uci Lisa
dan Bu Dovi di Ambon , Cak luhu dan Mb Santi di Surabaya, Bang Nara dan
Mb Ris di Yogyakarta, Mas Hananto, Mb Tyas dan Mb Nana Di Semarang,
Mas Yudha di purwokerto dan juga Mb Martina di bandung. Terimakasih atas
segala dukungannya baik di dalam doa maupun sms-sms yang menguatkan
xi
saya. Bahwa Ia yang memulai maka Ia akan meneruskan dan semua atas dasar
kasih karunia dan kerelaanNya..
8. Sobat-sobat seperjuangan di Prodi Teknik Elektro 2000. Ony, Nanto, Irwan,
Ignas, Kim, Zendy, Marsel Boli, Eny, Onsha, Pak leo, Aan, Agung Greg dan
untuk semuanya yang tidak dapat disebutkan satu per satu..
9. Untuk Felik makasih atas bantuan pemikirannya untuk menyelesaikan alat TA
ini.
Dalam penyusunan Tugas Akhir ini, penulis menyadari bahwa dalam
perancanggan Tugas Akhir ini masih banyak kekurangannya karena
keterbatasan kemampuan serta pengetahuan dari penulis. Oleh karena itu,
saran dan kritik yang membangun dari semua pembaca sangat penulis
harapkan.
Akhir kata, semoga Tugas Akhir ini dapat bermanfaat dan berguna bagi
yang membutuhkan.
Yogyakarta, 25 Juli 2007
Penulis
xii
D A F T A R I S I Hal
HALAMAN JUDUL .......................................................................................... i
HALAMAN PERSETUJUAN .......................................................................... iii
HALAMAN PENGESAHAN ........................................................................... iv
PERNYATAAN KEASLIAN KARYA ............................................................ v
HALAMAM PERSEMBAHAN........................................................................ vi
HALAMAN MOTTO........................................................................................ vii
INTISARI .......................................................................................................... viii
ABSTRACT ......................................................................................................... ix
KATA PENGANTAR ....................................................................................... x
DAFTAR ISI ..................................................................................................... xii
DAFTAR TABEL ............................................................................................. xv
DAFTAR GAMBAR ........................................................................................ xvi
DAFTAR LAMPIRAN ......................................................................................xviii
BAB I PENDAHULUAN 1.1. Judul ................................................................................................ 1
1.2. Latar belakang ................................................................................. 1
1.3. Tujuan Penelitian ............................................................................ 2
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
S b l P
Limits
U i T C di iSymbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage forAll Inputs
VIL Input LOW Voltage54 0.7
VGuaranteed Input LOW Voltage for
VIL Input LOW Voltage74 0.8
Vp g
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIHVOH Output HIGH Voltage74 2.7 3.5 V
CC , OH , IN IHor VIL per Truth Table
VOL Output LOW Voltage54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIL or VIHVOL Output LOW Voltage74 0.35 0.5 V IOL = 8.0 mA
VIN = VIL or VIHper Truth Table
IIH Input HIGH Current20 µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH Current0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC
Power Supply CurrentTotal, Output HIGH 6.2 mA VCC = MAXICCTotal, Output LOW 9.8
mA VCC MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
S b l P
Limits
U i T C di iSymbol Parameter Min Typ Max Unit Test Conditions
tPLH Turn-Off Delay, Input to Output 14 22 ns VCC = 5.0 V
tPHL Turn-On Delay, Input to Output 14 22 nsCC
CL = 15 pF
5-56
FAST AND LS TTL DATA
BCD TO 7-SEGMENTDECODER/DRIVER
The SN54/74LS47 are Low Power Schottky BCD to 7-Segment Decod-er /Drivers consisting of NAND gates, input buffers and seven AND-OR-IN-VERT gates. They offer active LOW, high sink current outputs for drivingindicators directly. Seven NAND gates and one driver are connected in pairsto make BCD data and its complement available to the seven decodingAND-OR-INVERT gates. The remaining NAND gate and three input buffersprovide lamp test, blanking input / ripple-blanking output and ripple-blankinginput.
The circuits accept 4-bit binary-coded-decimal (BCD) and, depending onthe state of the auxiliary inputs, decodes this data to drive a 7-segment displayindicator. The relative positive-logic output levels, as well as conditionsrequired at the auxiliary inputs, are shown in the truth tables. Outputconfigurations of the SN54/74LS47 are designed to withstand the relativelyhigh voltages required for 7-segment indicators.
These outputs will withstand 15 V with a maximum reverse current of250 µA. Indicator segments requiring up to 24 mA of current may be drivendirectly from the SN74LS47 high performance output transistors. Displaypatterns for BCD input counts above nine are unique symbols to authenticateinput conditions.
The SN54/74LS47 incorporates automatic leading and/or trailing-edgezero-blanking control (RBI and RBO). Lamp test (LT) may be performed at anytime which the BI /RBO node is a HIGH level. This device also contains anoverriding blanking input (BI) which can be used to control the lamp intensityby varying the frequency and duty cycle of the BI input signal or to inhibit theoutputs.
• Lamp Intensity Modulation Capability (BI/RBO)• Open Collector Outputs• Lamp Test Provision• Leading/Trailing Zero Suppression• Input Clamp Diodes Limit High-Speed Termination Effects
NOTES:a) 1 Unit Load (U.L.) = 40 µA HIGH, 1.6 mA LOW.b) Output current measured at VOUT = 0.5 V
The Output LOW drive factor is 7.5 U.L. for Military (54) and 15 U.L. for Commercial (74) Temperature Ranges.
SN54/74LS47
BCD TO 7-SEGMENTDECODER/DRIVER
LOW POWER SCHOTTKY
J SUFFIXCERAMIC
CASE 620-09
N SUFFIXPLASTIC
CASE 648-08
161
16
1
ORDERING INFORMATION
SN54LSXXJ CeramicSN74LSXXN PlasticSN74LSXXD SOIC
161
D SUFFIXSOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16GND = PIN 8
7 1 2 6 3 5
13 12 11 10 9 15 14 4
A B C D LT RBI
a b c d e f gBI/RBO
INPUTS OUTPUTS
TRUTH TABLE
5-57
FAST AND LS TTL DATA
SN54/74LS47
14 15
LOGIC DIAGRAM
NUMERICAL DESIGNATIONS — RESULTANT DISPLAYS
0 1 2 3 4 5 6 7 8 9 10 11 12 13
INPUT
BLANKING INPUT ORRIPPLE-BLANKINGOUTPUT
RIPPLE-BLANKINGINPUT
LAMP-TESTINPUT
A
B
C
D
a a
b b
c c
d d
e e
f f
g g
OUTPUT
DECIMALOR
FUNCTIONLT RBI D C B A BI/RBO a b c d e f g NOTE
0 H H L L L L H L L L L L L H A
1 H X L L L H H H L L H H H H A
2 H X L L H L H L L H L L H L
3 H X L L H H H L L L L H H L
4 H X L H L L H H L L H H L L
5 H X L H L H H L H L L H L L
6 H X L H H L H H H L L L L L
7 H X L H H H H L L L H H H H
8 H X H L L L H L L L L L L L
9 H X H L L H H L L L H H L L
10 H X H L H L H H H H L L H L
11 H X H L H H H H H L L H H L
12 H X H H L L H H L H H H L L
13 H X H H L H H L H H L H L L
14 H X H H H L H H H H L L L L
15 H X H H H H H H H H H H H H
BI X X X X X X L H H H H H H H B
RBI H L L L L L L H H H H H H H C
LT L X X X X X H L L L L L L L D
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
NOTES:(A) BI/RBO is wire-AND logic serving as blanking Input (BI) and/or ripple-blanking output (RBO). The blanking out (BI) must be open or held
at a HIGH level when output functions 0 through 15 are desired, and ripple-blanking input (RBI) must be open or at a HIGH level if blankingof a decimal 0 is not desired. X = input may be HIGH or LOW.
(B) When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a LOW level regardless of the state ofany other input condition.
(C) When ripple-blanking input (RBI) and inputs A, B, C, and D are at LOW level, with the lamp test input at HIGH level, all segment outputsgo to a HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition).
(D) When the blanking input/ripple-blanking output (BI/RBO) is open or held at a HIGH level, and a LOW level is applied to lamp test input,all segment outputs go to a LOW level.
5-58
FAST AND LS TTL DATA
SN54/74LS47
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 5474
4.54.75
5.05.0
5.55.25
V
TA Operating Ambient Temperature Range 5474
–550
2525
12570
°C
IOH Output Current — High BI /RBO 54, 74 –50 µA
IOL Output Current — Low BI /RBOBI /RBO
5474
1.63.2
mA
VO (off) Off-State Output Voltage a to g 54, 74 15 V
IO (on) On-State Output Current a to gOn-State Output Current a to g
5474
1224
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Theshold Voltagefor All Inputs
VIL Input LOW Voltage54 0.7
VGuaranteed Input LOW Threshold Voltagefor All InputsVIL Input LOW Voltage
74 0.8V
Guaranteed Input LOW Threshold Voltagefor All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage, BI /RBO 2.4 4.2 VVCC = MIN, IOH = –50 µA,VIN = VIN or VIL per Truth TableVOH Output HIGH Voltage, BI /RBO 2.4 4.2 VVCC = MIN, IOH = –50 µA,VIN = VIN or VIL per Truth Table
VOLOutput LOW VoltageBI /RBO
54, 74 0.25 0.4 V IOL = 1.6 mA VCC = MIN, VIN = VIN orVIL per Truth TableVOL
Output LOW VoltageBI /RBO 74 0.35 0.5 V IOL = 3.2 mA
VCC = MIN, VIN = VIN orVIL per Truth Table
IO (off)Off-State Output Currenta thru g 250 µA
VCC = MAX, VIN = VIN or VIL per TruthTable, VO (off) = 15 V
VO (on)On-State Output Voltagea thru g
54, 74 0.25 0.4 V IO (on) = 12 mA VCC = MAX, VIN = VIHor VIL per Truth TableVO (on)
On-State Output Voltagea thru g 74 0.35 0.5 V IO (on) = 24 mA
CC = MAX, VIN = VIHor VIL per Truth Table
IIH Input HIGH Current20 µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH Current0.1 mA VCC = MAX, VIN = 7.0 V
IILInput LOW Current BI/RBOAny Input except BI /RBO
–1.2–0.4 mA VCC = MAX, VIN = 0.4 V
IOS BI /RBO Output Short Circuit Current (Note 1) –0.3 –2.0 mA VCC = MAX, VOUT = 0 V
ICC Power Supply Current 7.0 13 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
The SN54/74LS74A dual edge-triggered flip-flop utilizes Schottky TTL cir-cuitry to produce high speed D-type flip-flops. Each flip-flop has individualclear and set inputs, and also complementary Q and Q outputs.
Information at input D is transferred to the Q output on the positive-goingedge of the clock pulse. Clock triggering occurs at a voltage level of the clockpulse and is not directly related to the transition time of the positive-goingpulse. When the clock input is at either the HIGH or the LOW level, the D inputsignal has no effect.
* Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictableif SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum thenwe cannot guarantee to meet the minimum level for VOH.
H, h = HIGH Voltage LevelL, I = LOW Voltage LevelX = Don’t Carei, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up timei, h (q) = prior to the HIGH to LOW clock transition.
SN54/74LS74A
DUAL D-TYPE POSITIVEEDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIXCERAMIC
CASE 632-08
N SUFFIXPLASTIC
CASE 646-06
141
14
1
ORDERING INFORMATION
SN54LSXXJ CeramicSN74LSXXN PlasticSN74LSXXD SOIC
141
D SUFFIXSOIC
CASE 751A-02
LOGIC SYMBOL
VCC = PIN 14GND = PIN 7
2
3
5D Q
CP
QCD
1
4
6
12
11
9D Q
CP
QCD
13
10
8
SD SD
5-73
FAST AND LS TTL DATA
SN54/74LS74A
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 5474
4.54.75
5.05.0
5.55.25
V
TA Operating Ambient Temperature Range 5474
–550
2525
12570
°C
IOH Output Current — High 54, 74 –0.4 mA
IOL Output Current — Low 5474
4.08.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage forAll Inputs
VIL Input LOW Voltage54 0.7
VGuaranteed Input LOW Voltage forAll InputsVIL Input LOW Voltage
74 0.8V
Guaranteed Input LOW Voltage forAll Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth TableVOH Output HIGH Voltage74 2.7 3.5 V
VCC = MIN, IOH = MAX, VIN = VIHor VIL per Truth Table
VOL Output LOW Voltage54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIL or VIHper Truth Table
VOL Output LOW Voltage74 0.35 0.5 V IOL = 8.0 mA
VIN = VIL or VIHper Truth Table
IIH
Input High CurrentData, ClockSet, Clear
2040
µA VCC = MAX, VIN = 2.7 V
IIHData, ClockSet, Clear
0.10.2 mA VCC = MAX, VIN = 7.0 V
IIL
Input LOW CurrentData, ClockSet, Clear
–0.4–0.8
mA VCC = MAX, VIN = 0.4 V
IOS Output Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 8.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
fMAX Maximum Clock Frequency 25 33 MHz Figure 1VCC = 5.0 VCL = 15 pFtPLH
tPHLClock, Clear, Set to Output
13 25 nsFigure 1
VCC = 5.0 VCL = 15 pFtPLH
tPHLClock, Clear, Set to Output
25 40 nsFigure 1 CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
tW(H) Clock 25 ns Figure 1
VCC = 5.0 V
tW(L) Clear, Set 25 ns Figure 2
VCC = 5.0 Vts
Data Setup Time — HIGHData Setup Time — LOW
20 nsFigure 1
VCC = 5.0 Vts
Data Setup Time — HIGHData Setup Time — LOW 20 ns
Figure 1CC = 5.0 V
th Hold Time 5.0 ns Figure 1
5-74
FAST AND LS TTL DATA
SN54/74LS74A
Figure 1. Clock to Output Delays, DataSet-Up and Hold Times, Clock Pulse Width
Figure 2. Set and Clear to Output Delays,Set and Clear Pulse Widths
AC WAVEFORMS
tW
1.3 V 1.3 V
tW
1.3 V 1.3 V
1.3 V
1.3 V1.3 V
1.3 V
tPLH tPHL
tPLHtPHL
SET
CLEAR
Q
Q
*The shaded areas indicate when the input is permitted to change for predictable output performance.
NOTES:tn = bit time before enablenegative-going transitiontn+1 = bit time after enablenegative-going transition
5-75
FAST AND LS TTL DATA
4-BIT D LATCHThe TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem-
porary storage for binary information between processing units and input /out-put or indicator units. Information present at a data (D) input is transferred tothe Q output when the Enable is HIGH and the Q output will follow the datainput as long as the Enable remains HIGH. When the Enable goes LOW, theinformation (that was present at the data input at the time the transition oc-curred) is retained at the Q output until the Enable is permitted to go HIGH.
The SN54 /74LS75 features complementary Q and Q output from a 4-bitlatch and is available in the 16-pin packages. For higher component densityapplications the SN54/74LS77 4-bit latch is available in the 14-pin packagewith Q outputs omitted.
14 13 12 11 10 9
1 2 3 4 5 6 7
16 15
8
CONNECTION DIAGRAMS DIP (TOP VIEW)
SN54/74LS75
14 13 12 11 10 9
1 2 3 4 5 6
8
7
SN54/74LS77
Q0
Q0
Q1 Q1 E0–1 GND Q2Q2 Q3
D0 D1 E2–3 VCC D2 D3 Q3
Q0 Q1 E0–1 GND NC Q2 Q3
D0 D1 E2–3 VCC D2 D3 NC
PIN NAMES LOADING (Note a)
HIGH LOW
D1–D4E0–1E2–3Q1–Q4Q1–Q4
Data InputsEnable Input Latches 0, 1Enable Input Latches 2, 3Latch Outputs (Note b)Complimentary Latch Outputs (Note b)
0.5 U.L.2.0 U.L.2.0 U.L.10 U.L.10 U.L.
0.25 U.L.1.0 U.L.1.0 U.L.
5 (2.5) U.L.5 (2.5) U.L.
NOTES:a) 1 Unit Load (U.L.) = 40 µA HIGH.b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
TRUTH TABLE(Each latch)
tn tn+1
DHL
QHL
SN54/74LS75SN54/74LS77
4-BIT D LATCH
LOW POWER SCHOTTKY
J SUFFIXCERAMIC
CASE 620-09
N SUFFIXPLASTIC
CASE 648-08
161
16
1
ORDERING INFORMATION
SN54LSXXJ CeramicSN74LSXXN PlasticSN74LSXXD SOIC
161
D SUFFIXSOIC
CASE 751B-03
J SUFFIXCERAMIC
CASE 632-08
N SUFFIXPLASTIC
CASE 646-06
141
14
1
141
D SUFFIXSOIC
CASE 751A-02
5-76
FAST AND LS TTL DATA
SN54/74LS75
LOGIC SYMBOLS
VCC = PIN 5GND = PIN 12
2 3 6 7
16 1 15 14 10 11 9 8
D0 D1 D2 D313
4
E0–1E2–3
Q0 Q1 Q2 Q3Q0 Q1 Q2 Q3
SN54/74LS75
VCC = PIN 4GND = PIN 11NC = PIN 7, 10
1 2 5 6
14 13 9 8
D0 D1 D2 D312
3
E0–1E2–3
Q0 Q3Q1 Q2
SN54/74LS77
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage forAll Inputs
VIL Input LOW Voltage54 0.7
VGuaranteed Input LOW Voltage forAll InputsVIL Input LOW Voltage
74 0.8V
Guaranteed Input LOW Voltage forAll Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth TableVOH Output HIGH Voltage74 2.7 3.5 V
VCC = MIN, IOH = MAX, VIN = VIHor VIL per Truth Table
VOL Output LOW Voltage54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIL or VIHper Truth Table
VOL Output LOW Voltage74 0.35 0.5 V IOL = 8.0 mA
VIN = VIL or VIHper Truth Table
IIH Input HIGH Current
D InputE Input
2080
µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH CurrentD InputE Input
0.10.4
mA VCC = MAX, VIN = 7.0 V
IIL Input LOW CurrentD InputE Input
–0.4–1.6 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 12 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
tPLHtPHL
Propagation Delay, Data to Q159.0
2717 ns
VCC = 5.0 VCL = 15 pF
tPLHtPHL
Propagation Delay, Data to Q127.0
2015 ns
VCC = 5.0 VCL = 15 pFtPLH
tPHLPropagation Delay, Enable to Q
1514
2725 ns
VCC = 5.0 VCL = 15 pF
tPLHtPHL
Propagation Delay, Enable to Q167.0
3015 ns
5-77
FAST AND LS TTL DATA
SN54/74LS77
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage forAll Inputs
VIL Input LOW Voltage54 0.7
VGuaranteed Input LOW Voltage forAll InputsVIL Input LOW Voltage
74 0.8V
Guaranteed Input LOW Voltage forAll Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth TableVOH Output HIGH Voltage74 2.7 3.5 V
VCC = MIN, IOH = MAX, VIN = VIHor VIL per Truth Table
VOL Output LOW Voltage54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIL or VIHper Truth Table
VOL Output LOW Voltage74 0.35 0.5 V IOL = 8.0 mA
VIN = VIL or VIHper Truth Table
IIH Input HIGH Current
D InputE Input
2080
µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH CurrentD InputE Input
0.10.4
mA VCC = MAX, VIN = 7.0 V
IIL Input LOW CurrentD InputE Input
–0.4–1.6 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 13 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
tPLHtPHL
Propagation Delay, Data to Q119.0
1917 ns
VCC = 5.0 VCL = 15 pFtPLH
tPHLPropagation Delay, Enable to Q
1010
1818 ns
VCC = 5.0 VCL = 15 pF
5-78
FAST AND LS TTL DATA
SN54/74LS75 � SN54/74LS77
LOGIC DIAGRAM
DATA
ENABLE
TO OTHER LATCH
Q (SN54/74LS75 ONLY)Q
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 5474
4.54.75
5.05.0
5.55.25
V
TA Operating Ambient Temperature Range 5474
–550
2525
12570
°C
IOH Output Current — High 54, 74 –0.4 mA
IOL Output Current — Low 5474
4.08.0
mA
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
tW Enable Pulse Width High 20 ns
VCC = 5.0 Vts Setup Time 20 ns VCC = 5.0 V
th Hold Time 0 ns
CC = 5.0 V
AC WAVEFORMS
D
E
Q
Q
1.3 V 1.3 V
1.3 V 1.3 V 1.3 V
1.3 V 1.3 V
1.3 V1.3 V
thts
tPLH
tPLH tPHL
tPHL
tPLHtPHL
tPHL tPLH
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to theclock transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH-to-LOW that the logic level must bemaintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level maybe released prior to the clock transition from HIGH-to-LOW and still be recognized.
The SN54/74LS76A offers individual J, K, Clock Pulse, Direct Set and Di-rect Clear inputs. These dual flip-flops are designed so that when the clockgoes HIGH, the inputs are enabled and data will be accepted. The Logic Levelof the J and K inputs will perform according to the Truth Table as long as mini-mum set-up times are observed. Input data is transferred to the outputs on theHIGH-to-LOW clock transitions.
*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictableif SD and CD go HIGH simultaneously.
H,h = HIGH Voltage LevelL,l = LOW Voltage LevelX = Immateriall, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time priorto the HIGH-to-LOW clock transition
LOGIC DIAGRAM
Q
CLEAR (CD)
J
CLOCK (CP)
K
SET (SD)
Q
SN54/74LS76A
DUAL JK FLIP-FLOPWITH SET AND CLEAR
LOW POWER SCHOTTKY
LOGIC SYMBOL
16
1
4
15
14
K Q
CP
J Q
SD
VCC = PIN 5GND = PIN 13
12
6
9
11
10
K Q
CP
J QCD
7
J SUFFIXCERAMIC
CASE 620-09
N SUFFIXPLASTIC
CASE 648-08
161
16
1
ORDERING INFORMATION
SN54LSXXJ CeramicSN74LSXXN PlasticSN74LSXXD SOIC
161
D SUFFIXSOIC
CASE 751B-03
2
3 8
CD
SD
5-80
FAST AND LS TTL DATA
SN54/74LS76A
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 5474
4.54.75
5.05.0
5.55.25
V
TA Operating Ambient Temperature Range 5474
–550
2525
12570
°C
IOH Output Current — High 54, 74 –0.4 mA
IOL Output Current — Low 5474
4.08.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage forAll Inputs
VIL Input LOW Voltage54 0.7
VGuaranteed Input LOW Voltage forAll InputsVIL Input LOW Voltage
74 0.8V
Guaranteed Input LOW Voltage forAll Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth TableVOH Output HIGH Voltage74 2.7 3.5 V
VCC = MIN, IOH = MAX, VIN = VIHor VIL per Truth Table
VOL Output LOW Voltage54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIL or VIHper Truth Table
VOL Output LOW Voltage74 0.35 0.5 V IOL = 8.0 mA
VIN = VIL or VIHper Truth Table
IIH Input HIGH Current
J, KClearClock
206080
µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH CurrentJ, KClearClock
0.10.30.4
mA VCC = MAX, VIN = 7.0 V
IIL Input LOW CurrentJ, KClear, Clock
–0.4–0.8 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 6.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
fMAX Maximum Clock Frequency 30 45 MHzVCC = 5.0 VCL = 15 pFtPLH
tPHLClock, Clear, Set to Output
15 20 nsVCC = 5.0 VCL = 15 pFtPLH
tPHLClock, Clear, Set to Output
15 20 nsCL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
The SN74LS76A offers individual J, K, Clock Pulse, Direct Set andDirect Clear inputs. These dual flip-flops are designed so that whenthe clock goes HIGH, the inputs are enabled and data will be accepted.The Logic Level of the J and K inputs will perform according to theTruth Table as long as minimum set-up times are observed. Input datais transferred to the outputs on the HIGH-to-LOW clock transitions.
MODE SELECT – TRUTH TABLE
OPERATING INPUTS OUTPUTSOPERATINGMODE SD CD J K Q Q
* Both outputs will be HIGH while both SD and CD are LOW, but the outputstates are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Immaterial
l, h (q) = Lower case letters indicate the state of the referenced input
i, h (q) = (or output) one setup time prior to the HIGH–to–LOW clock transition
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TA Operating AmbientTemperature Range
0 25 70 °C
IOH Output Current – High –0.4 mA
IOL Output Current – Low 8.0 mA
LOWPOWER
SCHOTTKY
SOICD SUFFIX
CASE 751B
PLASTICN SUFFIXCASE 648
16
1
16
1
Device Package Shipping
ORDERING INFORMATION
SN74LS76AN 16 Pin DIP 2000 Units/Box
SN74LS76AD SOIC–16 38 Units/Rail
SN74LS76ADR2 SOIC–16 2500/Tape & Reel
http://onsemi.com
SN74LS76A
http://onsemi.com2
LOGIC DIAGRAM
Q
CLEAR (CD)
J
CLOCK (CP)
K
SET (SD)
Q
LOGIC SYMBOL
16
1
4
15
14
K Q
CP
J Q
SD
VCC = PIN 5
GND = PIN 13
12
6
9
11
10
K Q
CP
J QCD
72
3 8
CD
SD
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage forAll Inputs
VIL Input LOW Voltage0.8
VGuaranteed Input LOW Voltage forAll Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL Output LOW Voltage0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN VIL or VIHVOL Output LOW Voltage0.35 0.5 V IOL = 8.0 mA
VIN = VIL or VIHper Truth Table
IIH Input HIGH Current
J, KClearClock
206080
µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH CurrentJ, KClearClock
0.10.30.4
mA VCC = MAX, VIN = 7.0 V
IIL Input LOW CurrentJ, KClear, Clock
–0.4–0.8 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 6.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
fMAX Maximum Clock Frequency 30 45 MHz
tPLH Clock Clear Set to Output15 20 ns VCC = 5.0 V
CL = 15 pFtPLHtPHL
Clock, Clear, Set to Output15 20 ns
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tW Clock Pulse Width High 20 ns
tW Clear Set Pulse Width 25 nsVCC 5 0 V
ts Setup Time 20 nsVCC = 5.0 V
th Hold Time 0 ns
SN74LS76A
http://onsemi.com3
PACKAGE DIMENSIONS
N SUFFIXPLASTIC PACKAGE
CASE 648–08ISSUE R
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.
–A–
B
F C
S
HG
D
J
L
M
16 PL
SEATING
1 8
916
K
PLANE–T–
MAM0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01����
D SUFFIXPLASTIC SOIC PACKAGE
CASE 751B–05ISSUE J
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
JM
R X 45�
G
8 PLP–B–
–A–
M0.25 (0.010) B S
–T–
D
K
C
16 PL
SBM0.25 (0.010) A ST
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
� � � �
SN74LS76A
http://onsemi.com4
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changeswithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATIONJAPAN : ON Semiconductor, Japan Customer Focus Center4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031Phone : 81–3–5740–2700Email : [email protected]
ON Semiconductor Website : http://onsemi.com
For additional information, please contact your localSales Representative.
SN74LS76A/D
Literature Fulfillment :Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone : 303–675–2175 or 800–344–3860 Toll Free USA/CanadaFax: 303–675–2176 or 800–344–3867 Toll Free USA/CanadaEmail : [email protected]
N. American Technical Support : 800–282–9855 Toll Free USA/Canada
The SN54 /74LS83A is a high-speed 4-Bit binary Full Adder with internalcarry lookahead. It accepts two 4-bit binary words (A1–A4, B1–B4) and aCarry Input (C0). It generates the binary Sum outputs ∑1–∑4) and the CarryOutput (C4) from the most significant bit. The LS83A operates with eitheractive HIGH or active LOW operands (positive or negative logic). TheSN54/74LS283 is recommended for new designs since it is identical infunction with this device and features standard corner power pins.
14 13 12 11 10 9
1 2 3 4 5 6
B4
7
16 15
8
Σ4 C4 C0 GND B1 A1 Σ1
A4 Σ3 A3 Σ2 B2 A2
CONNECTION DIAGRAM DIP (TOP VIEW)
B3 VCC
NOTE:The Flatpak version has thesame pinouts (ConnectionDiagram) as the Dual In-LinePackage.
PIN NAMES LOADING (Note a)
HIGH LOW
A1–A4B1–B4C0Σ1–Σ4C4
Operand A InputsOperand B InputsCarry InputSum Outputs (Note b)Carry Output (Note b)
1.0 U.L.1.0 U.L.0.5 U.L.10 U.L.10 U.L.
0.5 U.L.0.5 U.L.
0.25 U.L.5 (2.5) U.L.5 (2.5) U.L.
NOTES:a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
The LS83A adds two 4-bit binary words (A plus B) plus the incoming carry. The binary sum appears on the sum outputs (∑1–∑4)and outgoing carry (C4) outputs.
Due to the symmetry of the binary add function the LS83A can be used with either all inputs and outputs active HIGH (positivelogic) or with all inputs and outputs active LOW (negative logic). Note that with active HIGH Inputs, Carry Input can not be left open,but must be held LOW when no carry in is intended.
Example:
C0 A1 A2 A3 A4 B1 B2 B3 B4 ∑1 ∑2 ∑3 ∑4 C4
Logic Levels L L H L H H L L H H H L L H
Active HIGH 0 0 1 0 1 1 0 0 1 1 1 0 0 1 (10+9 = 19)
The SN54/74LS85 is a 4-Bit Magnitude Camparator which compares two4-bit words (A, B), each word having four Parallel Inputs (A0–A3, B0–B3); A3,B3 being the most significant inputs. Operation is not restricted to binarycodes, the device will work with any monotonic code. Three Outputs areprovided: “A greater than B” (OA>B), “A less than B” (OA<B), “A equal to B”(OA=B). Three Expander Inputs, IA>B, IA<B, IA=B, allow cascading withoutexternal gates. For proper compare operation, the Expander Inputs to theleast significant position must be connected as follows: IA<B= IA>B = L, IA=B= H. For serial (ripple) expansion, the OA>B, OA<B and OA=B Outputs areconnected respectively to the IA>B, IA<B, and IA=B Inputs of the next mostsignificant comparator, as shown in Figure 1. Refer to Applications section ofdata sheet for high speed method of comparing large words.
The Truth Table on the following page describes the operation of theSN54/74LS85 under all possible logic conditions. The upper 11 lines describethe normal operation under all conditions that will occur in a single device orin a series expansion scheme. The lower five lines describe the operationunder abnormal conditions on the cascading inputs. These conditions occurwhen the parallel expansion technique is used.
• Easily Expandable• Binary or BCD Comparison• OA>B, OA<B, and OA=B Outputs Available
CONNECTION DIAGRAM DIP (TOP VIEW)
NOTE:The Flatpak version has thesame pinouts (ConnectionDiagram) as the Dual In-LinePackage.
14 13 12 11 10 9
1 2 3 4 5 6 7
16 15
8
VCC
B3
A3 B2 A2 A1 A0B1 B0
IA<B IA=B IA>B OA>B OA=B OA<B GND
PIN NAMES LOADING (Note a)
HIGH LOW
A0–A3, B0–B3IA=BIA<B, IA>BOA>BOA<BOA=B
Parallel InputsA = B Expander InputsA < B, A > B, Expander InputsA Greater Than B Output (Note b)B Greater Than A Output (Note b)A Equal to B Output (Note b)
1.5 U.L.1.5 U.L.0.5 U.L.10 U.L.10 U.L.10 U.L.
0.75 U.L.0.75 U.L.0.25 U.L.
5 (2.5) U.L.5 (2.5) U.L.5 (2.5) U.L.
NOTES:a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
SN54/74LS85
4-BIT MAGNITUDECOMPARATOR
LOW POWER SCHOTTKY
J SUFFIXCERAMIC
CASE 620-09
N SUFFIXPLASTIC
CASE 648-08
161
16
1
ORDERING INFORMATION
SN54LSXXJ CeramicSN74LSXXN PlasticSN74LSXXD SOIC
161
D SUFFIXSOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16GND = PIN 8
10 12 13 15 9 11 14 1
423
576
A0 A1 A2 A3 B0 B1 B2 B3IA>BIA<BIA=B
OA>BOA<BOA=B
H = HIGH LevelL = LOW LevelX = IMMATERIAL
5-85
FAST AND LS TTL DATA
SN54/74LS85
LOGIC DIAGRAM
OA>B
OA<B
OA=B
(5)
(6)
(7)
A3B3
A2B2
A<BA=BA>B
A1B1
A0B0
(15)
(1)
(13)
(14)
(12)
(11)
(10)
(9)
(2)(3)(4)
TRUTH TABLE
COMPARING INPUTSCASCADING
INPUTS OUTPUTS
A3,B3 A2,B2 A1,B1 A0,B0 IA>B IA<B IA=B OA>B OA<B OA=BA3>B3 X X X X X X H L LA3<B3 X X X X X X L H LA3=B3 A2>B2 X X X X X H L LA3=B3 A2<B2 X X X X X L H LA3=B3 A2=B2 A1>B1 X X X X H L LA3=B3 A2=B2 A1<B1 X X X X L H LA3=B3 A2=B2 A1=B1 A0>B0 X X X H L LA3=B3 A2=B2 A1=B1 A0<B0 X X X L H LA3=B3 A2=B2 A1=B1 A0=B0 H L L H L LA3=B3 A2=B2 A1=B1 A0=B0 L H L L H LA3=B3 A2=B2 A1=B1 A0=B0 X X H L L HA3=B3 A2=B2 A1=B1 A0=B0 H H L L L LA3=B3 A2=B2 A1=B1 A0=B0 L L L H H L
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 5474
4.54.75
5.05.0
5.55.25
V
TA Operating Ambient Temperature Range 5474
–550
2525
12570
°C
IOH Output Current — High 54, 74 –0.4 mA
IOL Output Current — Low 5474
4.08.0
mA
NOTE:The SN54/74LS85 can be used as a 5-bit comparatoronly when the outputs are used to drive the A0–A3 andB0–B3 inputs of another SN54/74LS85 as shown inFigure 2 in positions #1, 2, 3, and 4.
5-86
FAST AND LS TTL DATA
SN54/74LS85
Figure 1. Comparing Two n-Bit Words
L = LOW LEVELH = HIGH LEVEL
A0 A1 A2 A3 B0 B1 B2 B3
A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3L
L
H
IA > BIA < BIA = B
OA > BOA < BOA = B
IA > BIA < BIA = B
OA > BOA < BOA = B
A > B
A < B
A = BSN54/74LS85 SN54/74LS85
An3
An2
An1
An
Bn3
Bn2
Bn1
Bn
APPLICATIONS
Figure 2 shows a high speed method of comparing two 24-bit words with only two levels of device delay. With the techniqueshown in Figure 1, six levels of device delay result when comparing two 24-bit words. The parallel technique can be expandedto any number of bits, see Table 1.
Table 1
WORD LENGTH NUMBER OF PKGS.
1–4 Bits 15–24 Bits 2–6
25–120 Bits 8–31
MSB = MOST SIGNIFICANT BITLSB = LEAST SIGNIFICANT BITL = LOW LEVELH = HIGH LEVELNC = NO CONNECTION
A0 A1 A2 A3 B0 B1 B2 B3
A0 A1 A2 A3 B0 B1 B2 B3L
L
H
IA > BIA < B
IA = B
OA > BOA < B
OA = B
#5
(LSB)
INPUTS
A0 A1 A2 A3 B0 B1 B2 B3IA > BIA < B
IA = B
OA > BOA < B
OA = B
#1
L NC
A20 A21 B23B22B21B20A23A22
A19B19
(MSB)
A5 A6 A7 A8 B5 B6 B7 B8
A0 A1 A2 A3 B0 B1 B2 B3IA > BIA < BIA = B
OA > BOA < BOA = B
#4
NCL
A4B4
A0 A1 A2 A3 B0 B1 B2 B3IA > BIA < BIA = B
OA > BOA < BOA = B
#3
NCL
A9B9
A10 A11 B13B12B11B10A13A12
A0 A1 A2 A3 B0 B1 B2 B3IA > BIA < BIA = B
OA > BOA < BOA = B
#2
NCL
A14B14
A15 A16 B18B17B16B15A18A17
OUTPUTS
A0 A1 A2 A3 B0 B1 B2 B3IA > BIA < BIA = B
OA > BOA < BOA = B
#6
INPUTS
Figure 2. Comparison of Two 24-Bit Words
5-87
FAST AND LS TTL DATA
SN54/74LS85
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage forAll Inputs
VIL Input LOW Voltage54 0.7
VGuaranteed Input LOW Voltage forAll InputsVIL Input LOW Voltage
74 0.8V
Guaranteed Input LOW Voltage forAll Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth TableVOH Output HIGH Voltage54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth TableVOH Output HIGH Voltage74 2.7 3.5 V
VCC = MIN, IOH = MAX, VIN = VIHor VIL per Truth Table
VOL Output LOW Voltage54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIL or VIHper Truth Table
VOL Output LOW Voltage74 0.35 0.5 V IOL = 8.0 mA
VIN = VIL or VIHper Truth Table
IIH
Input HIGH CurrentA < B, A > BOther Inputs
2060
µA VCC = MAX, VIN = 2.7 V
IIHA < B, A > BOther Inputs
0.10.3 mA VCC = MAX, VIN = 7.0 V
IIL
Input LOW CurrentA < B, A > BOther Inputs
–0.4–1.2
mA VCC = MAX, VIN = 0.4 V
IOS Output Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 20 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
1. For ordering information on the EIAJ version ofthe SOIC package, please contact your localON Semiconductor representative.
See Note 1
SN74LS86
http://onsemi.com2
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage forAll Inputs
VIL Input LOW Voltage0.8
VGuaranteed Input LOW Voltage forAll Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL Output LOW Voltage0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN VIL or VIHVOL Output LOW Voltage0.35 0.5 V IOL = 8.0 mA
VIN = VIL or VIHper Truth Table
IIH Input HIGH Current40 µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH Current0.2 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.8 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 2) –20 –100 mA VCC = MAX
ICC Power Supply Current 10 mA VCC = MAX
2. Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tPLHtPHL
Propagation Delay,Other Input LOW
1210
2317 ns
VCC = 5.0 V
tPLHtPHL
Propagation Delay,Other Input HIGH
2013
3022 ns
VCC = 5.0 VCL = 15 pF
SN74LS86
http://onsemi.com3
PACKAGE DIMENSIONS
1 7
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L
M --- 10 --- 10
N 0.015 0.039 0.38 1.01� �
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.
F
H G DK
C
SEATING
PLANE
N
–T–
14 PL
M0.13 (0.005)
L
MJ
0.290 0.310 7.37 7.87
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P 7 PL
14 8
71M0.25 (0.010) B M
SBM0.25 (0.010) A ST
–T–
FR X 45
SEATING
PLANED 14 PL K
C
JM
�DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
� � � �
D SUFFIXPLASTIC SOIC PACKAGE
CASE 751A–03ISSUE F
N SUFFIXPLASTIC PACKAGE
CASE 646–06ISSUE M
SN74LS86
http://onsemi.com4
PACKAGE DIMENSIONS
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 1.42 --- 0.056
A1
HE
Q1
LE
� 10 � 0 � 10
�
LEQ1
�
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASUREDAT THE PARTING LINE. MOLD FLASH ORPROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOTINCLUDE DAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTHDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWERRADIUS OR THE FOOT. MINIMUM SPACEBETWEEN PROTRUSIONS AND ADJACENT LEADTO BE 0.46 ( 0.018).
0.13 (0.005) M 0.10 (0.004)
DZ
E
1
14 8
7
e A
b
VIEW P
c
L
DETAIL P
M
A
b
c
D
E
e
0.50
M
Z
M SUFFIXSOEIAJ PACKAGE
CASE 965–01ISSUE O
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changeswithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATIONJAPAN : ON Semiconductor, Japan Customer Focus Center4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031Phone : 81–3–5740–2700Email : [email protected]
ON Semiconductor Website : http://onsemi.com
For additional information, please contact your localSales Representative.
SN74LS86/D
Literature Fulfillment :Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone : 303–675–2175 or 800–344–3860 Toll Free USA/CanadaFax: 303–675–2176 or 800–344–3867 Toll Free USA/CanadaEmail : [email protected]
N. American Technical Support : 800–282–9855 Toll Free USA/Canada
The SN54/74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift Regis-ter. Serial data is entered through a 2-Input AND gate synchronous with theLOW to HIGH transition of the clock. The device features an asynchronousMaster Reset which clears the register setting all outputs LOW independent ofthe clock. It utilizes the Schottky diode clamped process to achieve highspeeds and is fully compatible with all Motorola TTL products.
• Typical Shift Frequency of 35 MHz• Asynchronous Master Reset• Gated Serial Data Input• Fully Synchronous Data Transfers• Input Clamp Diodes Limit High Speed Termination Effects• ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
14 13 12 11 10 9
1 2 3 4 5 6
8
7
VCC Q7 Q6 Q5 Q4 MR CP
A B Q0 Q1 Q2 Q3 GND
NOTE:The Flatpak versionhas the same pinouts(Connection Diagram) asthe Dual In-Line Package.
PIN NAMES LOADING (Note a)
HIGH LOW
A, BCPMRQ0–Q7
Data InputsClock (Active HIGH Going Edge) InputMaster Reset (Active LOW) InputOutputs (Note b)
0.5 U.L.0.5 U.L.0.5 U.L.10 U.L.
0.25 U.L.0.25 U.L.0.25 U.L.
5 (2.5) U.L.
NOTES:a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
The LS164 is an edge-triggered 8-bit shift register with seri-al data entry and an output from each of the eight stages. Datais entered serially through one of two inputs (A or B); either ofthese inputs can be used as an active HIGH Enable for dataentry through the other input. An unused input must be tiedHIGH, or both inputs connected together.
Each LOW-to-HIGH transition on the Clock (CP) input shiftsdata one place to the right and enters into Q0 the logical ANDof the two data inputs (A•B) that existed before the rising clockedge. A LOW level on the Master Reset (MR) input overridesall other inputs and clears the register asynchronously, forcingall Q outputs LOW.
MODE SELECT — TRUTH TABLE
OPERATINGMODE
INPUTS OUTPUTSMODE
MR A B Q0 Q1–Q7
Reset (Clear) L X X L L – L
H I I L q0 – q6Shift H I h L q0 – q6
H h I L q0 – q6H h h H q0 – q6
L (l) = LOW Voltage LevelsH (h) = HIGH Voltage LevelsX = Don’t Careqn = Lower case letters indicate the state of the referenced input or output oneqn = set-up time prior to the LOW to HIGH clock transition.
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 5474
4.54.75
5.05.0
5.55.25
V
TA Operating Ambient Temperature Range 5474
–550
2525
12570
°C
IOH Output Current — High 54, 74 –0.4 mA
IOL Output Current — Low 5474
4.08.0
mA
5-3
FAST AND LS TTL DATA
SN54/74LS164
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage forAll Inputs
VIL Input LOW Voltage54 0.7
VGuaranteed Input LOW Voltage forAll InputsVIL Input LOW Voltage
74 0.8V
Guaranteed Input LOW Voltage forAll Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage54 2.5 3.5
VVCC = MIN, IOH = MAX, VIN = VIHor VIL per Truth TableVOH Output HIGH Voltage
74 2.7 3.5V
VCC = MIN, IOH = MAX, VIN = VIHor VIL per Truth Table
VOL Output LOW Voltage54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIH or VILper Truth Table
VOL Output LOW Voltage74 0.35 0.5 V IOL = 8.0 mA
VIN = VIH or VILper Truth Table
IIH Input HIGH Current20 µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH Current0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 27 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
fMAX Maximum Clock Frequency 25 36 MHz
VCC = 5.0 VCL = 15 pF
tPHLPropagation DelayMR to Output Q 24 36 ns VCC = 5.0 V
CL = 15 pFtPLHtPHL
Propagation DelayClock to Output Q
1721
2732 ns
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
tW CP, MR Pulse Width 20 ns
VCC = 5.0 Vts Data Setup Time 15 ns
VCC = 5.0 Vth Data Hold Time 5.0 ns
VCC = 5.0 V
trec MR to Clock Recovery Time 20 ns
5-4
FAST AND LS TTL DATA
SN54/74LS164
AC WAVEFORMS
*The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delaysand Clock Pulse Width
Figure 2. Master Reset Pulse Width,Master Reset to Output Delay and