Enhancing Beneficial Jitter Using Phase Shifted Clock Distribution Phase-Shifted Clock Distribution Dong Jiao, Jie Gu, Pulkit Jain , and Chris H. Kim University of Minnesota Department of Electrical and Computer Engineering [email protected]www.umn.edu/~chriskim/ 1
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Enhancing Beneficial Jitter Using Phase Shifted Clock DistributionPhase-Shifted Clock Distribution
Dong Jiao, Jie Gu, Pulkit Jain, and Chris H. Kim
University of MinnesotaDepartment of Electrical and Computer Engineeringp p g g
cpf/1• : Supply noise phase at clock launch• or : Clock path delaycpt
resθ
dataclk s,s• : Delay sensitivity to supply− Change in speed with respect to supply variation− E.g. If 10% Vdd change causes 15% speed change, s is 1.5g % g % p g ,
• : Resonant frequencyresf
10
Impact of Clock Path Delay65nm, 25°C,1.2V Vdd12% Vdd noise- 20
00
-20
fres=200MHz, fclk=2GHz, sclk: sdata = 0.7:1
No Supply N i
- 60
- 40
Noisy Clock Supply
-60
-40Noise
- 100
- 80
-100
-80Clean Clock
Supply
58ps
- 1200 0.4 0.8 1.2 1.60 0.4 0.8 1.2 1.6
cp cp,
-120
• Optimal clock path delay exists– Small : Approaches clean clock case
Large : Average supply voltages seen by clock edges closercpff
cp cp,
11
– Large : Average supply voltages seen by clock edges closer• Up to 58ps (11.6% Tclk) slack improvement with proper cpf
cpf
Impact of Delay Sensitivity65nm, 25°C,1.2V Vdd12% Vdd noise
• Typical clock path delay sensitivity is around 0.6 due to interconnect RC delay
• Much larger (or much smaller) sensitivity worsens
12
• Much larger (or much smaller) sensitivity worsens timing slack
Impact of Resonant Frequency65nm, 25°C,1.2V Vdd12% Vdd noise
• Beneficial jitter effect prominent in typical resonant frequency range
13
frequency range• Up to 87ps (11.6% Tclk) slack improvement
Presentation Agendag
• Resonant Noise and TimingResonant Noise and Timing
• Revised accurate model– No closed-form expression exists
Sol e non linear eq ation (i) itho t making appro imations
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– Solve non-linear equation (i) without making approximations– Follow derivation steps of simple model
Timing Model versus HSPICE100
g65nm, 25°C,1.2V Vdd12% Vdd noise
0
50
‐50
‐150
‐100
0 5 10 15 200 5 10 15 20
• Confirms intrinsic compensation effect
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Confirms intrinsic compensation effect• Reduces modeling error from 25ps to 8ps (5% to 1.6% Tclk)
Timing Model versus HSPICEg65nm, 25°C,1.2V Vdd12% Vdd noise
• Revised simple model good for first order approximation
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Revised simple model good for first order approximation• Reduces modeling error from 30ps to 4ps (6% to 0.8% Tclk)
Presentation Agendag
• Resonant Noise and TimingResonant Noise and Timing
• Overview of Beneficial Jitter Effect
• Timing Models and 65nm Simulations
• Phase-Shifted Clock Distribution
• Conclusions
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Intrinsic Beneficial Jitter Effect
• Beneficial jitter effect can be harnessed furtherBeneficial jitter effect can be harnessed further– Datapath delay depends on instantaneous Vdd value.– Clock period depends on Vdd value difference seen by two
consecutive clock edges
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consecutive clock edges.– Worst delay point does not coincide with max clock period point
Enhancing Beneficial Jitter Effect U i Ph Shift d Cl k Di t ib tiUsing Phase-Shifted Clock Distribution
• Phase-shift the clockpath supply noise• Clock period can be stretched out the most when the
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• Clock period can be stretched out the most when the worst case datapath delay occurs
Phase-Shifted Clock Buffer Designg
• New clock buffer with built-in RCfilterO ti l RC l l t d i• Optimal RC value selected using the revised timing models to enhance beneficial jitter effect