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1 Enhanced Reliability through Automated Design Analysis™ for the Electronics Industry Gregg Kittlesen [email protected] October 12, 2011
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Enhanced Reliability through Automated Design Analysis for the

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Page 1: Enhanced Reliability through Automated Design Analysis for the

1

Enhanced Reliability through Automated

Design Analysis™ for the Electronics Industry

Gregg Kittlesen [email protected]

October 12, 2011

Page 2: Enhanced Reliability through Automated Design Analysis for the

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Tech Insertion

Design

Supply Chain

Test

Warranty

Focus on Quality/Reliability/Durability of Electronics

All levels

of the supply chain

Page 3: Enhanced Reliability through Automated Design Analysis for the

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DfR Solutions – Senior Experts

o Dr. Craig Hillman, CEO and Managing Partner o Expertise: Design for Reliability (DfR), Pb-free Transition,

Supplier Benchmarking, Passive Components, Printed Circuit Board

o PhD, Material Science (UCSB)

o Dr. Nathan Blattau, Senior Vice President o Expertise: Power Devices, DfR, Nonlinear Finite Element

Analysis (FEA), Solder Joint Reliability, Fracture, Fatigue Mechanics.

o PhD, Mechanical Eng. (University of Maryland)

o Walt Tomczykowski, Vice President, CRE o Expertise: Systems Eng., Life Cycle Management (including

obsolescence), Spares Analysis, Counterfeit Mitigation, Failure Analysis

o M.S., Reliability Eng. (University of Maryland)

o Cheryl Tulkoff, CRE o Expertise: Pb-Free Transition, PCB and PCBA Fabrication, IC

Fabrication, RCA (8D and Red X) o B.S., Mechanical Engineering (Georgia Tech)

o Dr. Ron Wunderlich o Expertise: Design for EMI/EMC, Power Supply Design,

Analog Circuit Design, Spice Model Development, Monte Carlo Circuit Simulation

o PhD, Electrical Engineering (SUNY – Binghamton)

o Greg Caswell o Expertise: Nanotechnology CMOS, CMOS/SOS, Input

Protection Networks / ESD, SMT, Pb-free o B.S., Electrical Engineering (Rutgers)

o Dr. Randy Schueller o Expertise: IC Fabrication, IC Packaging, Pb-Free

Transition Activities, Supplier Benchmarking, Corrosion Mechanisms

o PhD, Material Science (University of Virginia)

o Dr. Gregg Kittlesen o Expertise: Semiconductor Lasers and Integrated Modules,

Photonic and RF Technologies, IC Process Development and Qualification, Supply Chain Management

o PhD, Inorganic Chemistry (MIT)

o James McLeish, CRE o Expertise: FMEA, Root-Cause Analysis, Warranty

Analysis, Automotive Electronics, Physics of Failure, Battery Technology

o M.S., Electrical Eng. (Wayne State University)

o Norm Anderson o Expertise: Avionics, Product Qualification, Safety

Criticality Assessment, FTA, FMEA, Component Uprating, Obsolescence

o B.S., Electrical Engineering (Iowa State University)

o Anne Marie Neufelder o Expertise: Software Reliability Prediction, Best Practices

in Software Risk Management o B.S., Systems Engineering (Georgia Tech)

Page 4: Enhanced Reliability through Automated Design Analysis for the

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o Early assessment of assembly level reliability

o Uniform design for reliability process

o Design trade-off analysis

o Include reliability assessment

Purpose

Page 5: Enhanced Reliability through Automated Design Analysis for the

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o Analyses

o Methodology

o Design Assessment

o Hardware Capability Assessment

Presentation Outline

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Analyses

Capabilities

o Virtual Shock Testing

o Virtual Vibration Testing

o Virtual Thermal Cycling

o Virtual CAF Testing

o Conductive Anodic Filament

Shock Strain Example

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Methodology - Inputs

Input Data Sources

o ODB++ archive

o ODB XML archive

o Files

o Layers

o Drill holes

o BOM

o Pick and place

o Thermal map

Environmental Stresses

o Mechanical Shock

o Random Vibration

o Harmonic Vibration

o Thermal Cycle

Page 8: Enhanced Reliability through Automated Design Analysis for the

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Methodology – Input Review

Parts List Stack-up

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Methodology – Input Review

Top Components Bottom Components

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Virtual Shock Testing - Maximum Stress

Parameters Shock Profile

Page 11: Enhanced Reliability through Automated Design Analysis for the

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Virtual Shock Testing - FEA Results

PCB Displacement

25G, 4.9ms, half sine pulse

PCB Strain

25G, 4.9ms, half sine pulse

Page 12: Enhanced Reliability through Automated Design Analysis for the

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Virtual Shock Testing - Component Assessments

Components with Highest Strain Shock Fatigue Scores

Page 13: Enhanced Reliability through Automated Design Analysis for the

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Virtual Vibration Testing - Stress

Parameters Random Vibration Profile

(Harmonic Vibration also available)

Page 14: Enhanced Reliability through Automated Design Analysis for the

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Virtual Vibration Testing - FEA Results

PCB Displacement PCB Strain

Page 15: Enhanced Reliability through Automated Design Analysis for the

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Virtual Vibration Testing - Component Assessments

Components with Highest Strain Shock Fatigue Scores

Page 16: Enhanced Reliability through Automated Design Analysis for the

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Virtual Thermal Cycle Testing - Stress

Parameters Temperature Cycle Profile

Page 17: Enhanced Reliability through Automated Design Analysis for the

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Virtual Thermal Cycle Testing - Component Assessments

Components with Shortest Lifetime Solder Fatigue Scores

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Virtual Thermal Cycle Testing - PTH Assessments

PTH with Shortest Lifetime PTH Fatigue Scores

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Virtual Conductive Anodic Filament (CAF) Assessments

Hole Pairs with Closest Spacing CAF Scores

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Scorecard

Tutorial Board Scores Score Classifications

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Life Prediction

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o Daily thermal cycle

o Modeled daily dT = 40˚C

o Ambient dT + solar load + internal dT

o Compared 3 temperature ramp durations: 1, 2, 3 hours

o Daily thermal cycle with mini-cycles

o Modeled daily dT = 20˚C, temperature ramp 1 hour

o Superimposed 25 daily cycles dT = 20˚C at low temp

o Superimposed 25 daily cycles dT = 20˚C at high temp

Outdoor Deployment Thermal Stresses

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Outdoor Deployment Thermal Stresses (cont.)

Daily dT = 40˚C Daily dT = 20˚C + mini-cycles

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Daily 40˚C dT Solder Fatigue by Solder and Component

63Sn37Pb SAC305

0

10000

20000

30000

40000

0.22 0.33 0.67

Cycl

es

Temperature Ramp Rate (˚C/min)

Cycles to 63% Failure

LCCC-20 TSOP-32 BGA-676

0

10000

20000

30000

40000

0.22 0.33 0.67

Cycl

es

Temperature Ramp Rate (˚C/min)

Cycles to 63% Failure

LCCC-20 TSOP-32 BGA-676

Page 25: Enhanced Reliability through Automated Design Analysis for the

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Daily 40˚C dT Assembly Solder Fatigue Life Prediction

63Sn37Pb SAC305

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Daily 20˚C dT + 20˚C Mini-cycles

Assembly Solder Fatigue Life Prediction

63Sn37Pb SAC305

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o Solder fatigue predictions at dT = 40˚C

o ~10% failures at 15 years for this SnPb assembly

o ~ 6% failures at 15 years for this SAC305 assembly

o Predictions at dT = 20˚C + 20˚C mini-cycles

o ~1% failures at 15 years for this SnPb assembly

o <1 % failures at 15 years for this SAC305 assembly

Observations

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o All components included in this analysis except BGA

components are predicted to have longer solder joint

lifetimes with SAC305 compared to SnPb eutectic.

o Solder fatigue is predicted to increase at slower

temperature ramp rates

Observations (cont.)

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o Recommend stress dependent lifetime modeling for

assemblies with sizable BGA and QFN components

o Model validation reports are available from DfR Solutions

Further Information