ENGR 303 Introduction to Logic Design Lecture 5...ENGR 303 –Introduction to Logic Design Lecture 5 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

ENGR 303 – Introduction to Logic Design Lecture 5

Dr. Chuck BrownEngineering and Computer Information Science

Folsom Lake College

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• Boolean expressions can be minimized by combining terms

• E.g. Y=A’B’C’ + A’B’C -> A’B’(C’+C) -> Y=A’B’

• K-maps minimize equations graphically

Recap Karnaugh Maps (K-Maps)

ENGR 303

A B C Y

0 0 0 1

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 0

1 1 0 0

1 0 0 0

A 00 01 11 10

0

1

BC

A’B’C’ A’B’C A’BC A’BC’

AB’C’ AB’C ABC ABC’

A B’C’ B’C BC BC’

A’

A

BC

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• Combinatorial Building Blocks

• Multiplexers, Decoders

• Time Delay & Glitches

Outline for Todays Lecture

ENGR 303

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• Multiplexers

• Decoders

• Timing

• Glitches

Combinational Building Blocks

ENGR 303

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• Selects between one of N inputs to connect to output

• log2N-bit select input – control input• Example: 2:1 Mux

Multiplexer (Mux)

Y

0 0

0 1

1 0

1 1

0

1

0

1

0

0

0

0

0 0

0 1

1 0

1 1

1

1

1

1

0

0

1

1

0

1

S

D0

YD

1

D1

D0

S Y

0

1 D1

D0

S

ENGR 303

Verilogmodule mux2 (input [1:0] d0, d1,

input s,output y);

assign y = s ? d1 : d0;endmodule

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• Logic gates– Sum-of-products form

Y

D0

S

D1

D1

Y

D0

S

S00 01

0

1

Y

11 10

D0

D1

0

0

0

1

1

1

1

0

Y = D0S + D

1S

• Tristates– For an N-input mux, use N

tristates

– Turn on exactly one to

select the appropriate input

Multiplexer Implementations

ENGR 303

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A B Y0 0 0

0 1 0

1 0 0

1 1 1

Y = AB

00

Y01

10

11

A B

• Using the mux as a lookup table

Logic using Multiplexers

ENGR 303

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A B Y0 0 0

0 1 0

1 0 0

1 1 1

Y = AB

A Y

0

1

0 0

1

A

BY

B

• Reducing the size of the mux

Logic using Multiplexers

ENGR 303

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• Select input selects Bus0 when low and

Bus1 when high

Bus Select using Multiplexers

ENGR 303

Select

0

1

Bus0

Bus1

Bus0ut

4

4

4

4bit 2:1 Mux

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2:4

Decoder

A1

A0

Y3

Y2

Y1

Y0

00011011

0 0

0 1

1 0

1 1

0

0

0

1

Y3

Y2

Y1

Y0

A0

A1

0

0

1

0

0

1

0

0

1

0

0

0

• N inputs, 2N outputs

• One-hot outputs: only one output HIGH at

once

Decoders

ENGR 303

Verilogmodule decoder2_4 (input [1:0] a,

output reg [3:0] y);always @ (*)

case (a)2’b00: y = 4’b0001;2’b01: y = 4’b0010;2’b10: y = 4’b0100;2’b11: y = 4’b1000;

endcaseendmodule

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Y3

Y2

Y1

Y0

A0A1

Decoder Implementation

ENGR 303

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2:4

Decoder

A

B00011011

Y = AB + AB

Y

ABABABAB

Minterm

= A B

• OR minterms

Logic Using Decoders

ENGR 303

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A

Y

Time

delay

A Y

• Delay between input change and output

changing

• How to build fast circuits?

Timing

ENGR 303

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A

Y

Time

A Y

tpd

tcd

• Propagation delay: tpd = max delay from input to output

• Contamination delay: tcd = min delay from input to

output

Propagation & Contamination Delay

ENGR 303

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• Delay is caused by

– Capacitance and resistance in a circuit

– Speed of light limitation

• Reasons why tpd and tcd may be different:

– Different rising and falling delays

– Multiple inputs and outputs, some of which are

faster than others

– Circuits slow down when hot and speed up when

cold

Propagation & Contamination Delay

ENGR 303

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AB

C

D Y

Critical Path

Short Path

n1

n2

Critical (Long) Path: tpd = 2tpd_AND + tpd_OR

Short Path: tcd = tcd_AND

Critical (Long) & Short Paths

ENGR 303

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• When a single input change causes an output

to change multiple times

Glitches

ENGR 303

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• What happens when A = 0, C = 1, B falls?

Glitch Example

ENGR 303

1 1 1 0

0 0 1 0

A 00 01 11 10

0

1

BC

Y = A’B’ + BC

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A = 0B = 1 0

C = 1

Y = 1 0 1

Short Path

Critical Path

B

Y

Time

1 0

0 1

glitch

n1

n2

n2

n1

Glitch Example (cont.)

ENGR 303

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B = 1 0Y = 1

A = 0

C = 1

Fixing the Glitch

ENGR 303

1 1 1 0

0 0 1 0

A 00 01 11 10

0

1

BC

Y = A’B’ + BC + A’C

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• Glitches don’t cause problems because of

synchronous design conventions (we will

study that latter)

• It’s important to recognize a glitch: in

simulations or on oscilloscope

• Add min-terms to remove glitches

• Can’t get rid of all glitches – simultaneous

transitions on multiple inputs can also cause

glitches …move to synchronous design

Why Understand Glitches?

ENGR 303