ENG3640 Microcomputer Interfacing Week #1 Review of Transistors.

ENG3640 Microcomputer Interfacing

Week #1 Review of Transistors

ENG3640 Fall 2012 2

Topics

Semiconductors PN Junction (Diodes) Bi-Polar Junction Transistors (BJTs) MOS Transistors (nMOS/pMOS) CMOS Technology Interfacing TTL with CMOS

ENG3640 Fall 2012 3

Semiconductor Materials

Electronic materials generally can be divided into three categories:

Insulators Semiconductors Conductors

The primary parameter used to distinguish among these materials is the resistivity (rho)

Insulator 105 < rho Semiconductors 10-3 < rho < 105

Conductors rho < 10-3

Silicon and germanium are the most important semiconductor materials

ENG3640 Fall 2012 4

P-type and N-type The real advantage of semiconductors emerge

when impurities are added to the material in minute amounts (Doping)

Impurity doping enables us to change the resistivity over a very wide range and determine whether the electron or hole population controls the resistivity of the material.

Donor Impurities: have five valence electrons in the outer shell (phosphorus and arsenic). Semiconductors doped with donor impurities are called n-type.

Acceptor Impurities: have one less electron than silicon in the outer shell (boron). Semiconductors doped with acceptor impurities are called p-type.

ENG3640 Fall 2012 5

Diffusion of majority carriers into the opposite sides causes a depletion region to appear at the junction.

Diodes: PN Junction

The diode is the simplest and most fundamental nonlinear circuit element.

The diode essentially allows an electric current to flow in one direction and locks it in the other direction

ENG3640 Fall 2012 6

Diodes

i = IS(e (v/nVT) - 1)

i = -IS

IS = Saturation Current

VT = Thermal Voltage

v = Terminal voltage

n = Constant (1)

ENG3640 Fall 2012 7

Half-wave Rectifier with resistive load.

Diodes: Applications

ENG3640 Fall 2012 8

Transistors: MOSFET vs. BJT

N-channel MOSFET NPN bipolar transistor

gate

source

body

drain collector

base

emitter

Uni-Polar Junction Transistor

Voltage Controlled Switch

Bi-Polar Junction Transistor

Current Controlled Switch

ENG3640 Fall 2012 9

History of Transistors

1940: Ohl develops the PN Junction 1945: Shockley's laboratory established 1947: Bardeen and Brattain create point

contact transistor (U.S. Patent 2,524,035)

ENG3640 Fall 2012 10

collector

base

emitter

BJT Symbols

collector

base

emitter

NPN Bipolar Transistor PNP Bipolar Transistor

ENG3640 Fall 2012 11

Bipolar Junction Transistor1. Acts like a current

controlled switch.

2. If we put a small current into the base then the switch is on (i.e. current may flow between collector and emitter)

3. If no current is put into the base, switch is off.

4. Regions of operations

• Cutoff

• Active

• Saturation

ENG3640 Fall 2012 12

BJT Modes of Operation

Mode EBJ CBJ

cutoff Reverse Reverse

Active Forward Reverse

Saturation Forward Forward

ENG3640 Fall 2012 13

BJT: Bipolar Junction Transistor

A current controlled deviceTwo types: NPN and PNP Handles more current than MOSFETs (Faster) More difficult to manufacture Dissipates more power Achieves less density on an IC Does not have full swing voltage

ENG3640 Fall 2012 14

The MOS TransistorMetal Oxide Semiconductor

Polysilicon

Aluminum

ENG3640 Fall 2012 15

MOS: Operation

n+n+

p-substrate

D

SG

B

VGS

xL

V(x) +–

VDS

ID

MOS transistor and its bias conditions

ENG3640 Fall 2012 16

nMOS vs. pMOS Devices

ENG3640 Fall 2012 17

MOSFET: Metal Oxide Semiconductor

Field Effect Transistor

A voltage controlled deviceTwo types: NMOS and PMOS Handles less current than a BJT (Slower) Easier to manufacture Dissipates less power Achieves higher density on an IC Has full swing voltage 0 5V

ENG3640 Fall 2012 18

VLSI Trends: Moore’s Law

In 1965, Gordon Moore predicted that transistors would continue to shrink, allowing: Doubled transistor density every 18-24 months Doubled performance every 18-24 months

History has proven Moore right But, is the end is in sight?

Physical limitations Economic limitations

Gordon MooreIntel Co-Founder and Chairmain Emeritus

Image source: Intel Corporation www.intel.com

ENG3640 Fall 2012 19

Technology Evolution

ENG3640 Fall 2012 20

NMOS Transistors in Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high

X Y

A B

Y = X if A and B

X Y

A

B Y = X if A OR B

NMOS Transistors pass a “strong” 0 but a “weak” 1NMOS Transistors pass a ``strong” 0 but a ``weak” 1

ENG3640 Fall 2012 21

PMOS Transistors in Series/Parallel Connection

X Y

A B

Y = X if A AND B = A + B

X Y

A

B Y = X if A OR B = AB

PMOS Transistors pass a “strong” 1 but a “weak” 0

PMOS switch closes when switch control input is low

PMOS Transistors pass a ``strong” 1 but a ``weak” 0

ENG3640 Fall 2012 22

Complementary MOS (CMOS)

NMOS Transistors pass a ``strong” 0 but a ``weak” 1

PMOS Transistors pass a ``strong” 1 but a ``weak” 0

Combining both would lead to circuits that can pass strong 0’s and strong 1’s

X Y

C

C

ENG3640 Fall 2012 23

Static Complementary CMOS

VDD

F(In1,In2,…InN)

In1In2

InN

In1In2

InN

PUN

PDN

PMOS only

NMOS only

PUN and PDN are dual logic networks

……

At every point in time (except during the switching transients) each gate output is connected to either VDD or VSS via a low resistive path

VSS

ENG3640 Fall 2012 24

CMOS Inverter

A Y

0

1

VDD

A Y

GNDA Y

Pull-up Network

Pull-down Network

ENG3640 Fall 2012 25

CMOS Inverter

A Y

0

1 0

VDD

A=1 Y=0

GND

ON

OFF

A Y

ENG3640 Fall 2012 26

CMOS Inverter

A Y

0 1

1 0

VDD

A=0 Y=1

GND

OFF

ON

A Y

ENG3640 Fall 2012 27

Types of Outputs

There are different types of outputs associated with digital circuits

1. Totem Pole (normal output)

2. Tri-state (High, Low, High Impedance)

3. Open Collector or Open Drain

ENG3640 Fall 2012 28

1. Totem Pole (normal output)

VDD

A Y

GNDA Y

Pull-up Network

Pull-down Network

Simply refers to the vertical alignment of components

Q1, Q2 act as switches controlled by Input A

When One transistor is on the other is off

Q1 is pull-up, Q2 is pull-down Not possible to join totem

pole outputs together.

ENG3640 Fall 2012 29

A Y

E A Y

0 X Z

1 0 1

1 1 0

E

EA Y

2. Tri-State Output Tri-state gates enable a device to electrically

disconnect its output when it is not driving the bus.

ENG3640 Fall 2012 30

As with tri-state output, open collector outputs allow multiple logic devices to drive the same line.

Since the pull-up transistor is missing, the circuit has the capability of pulling the signal down.

To pull a signal up we need an EXTERNAL RESISTOR (passive pull-up to high level)

*

3. Open Collector

Pull-down Network

Low to high transitions are much slower for open drain gate than for standard gate with active pull-up

ENG3640 Fall 2012 31

Open Collector: IRQ

Most common use of open collector is to connect several devices to a common interrupt line.

*

*

+5V

IRQ

MCU

I/O Device A

I/O Device B

ENG3640 Fall 2012 32

Logic Families RTL, DTL earliest TTL was used 70s, 80s

Still available and used occasionally 7400 series logic, refined over generations

CMOS Was low speed, low noise Now fast and is most common

BiCMOS and GaAs Speed

ENG3640 Fall 2012 33

Resistor-Transistor Logic (RTL)

Vin

Vout

Vcc

RB

RC

Q1

Vin

Vout

SaturationCutof f

Forward-active

VCE(sat)

VCC

VB E(on) V in(eos)

VTC of nonsaturating gate

ENG3640 Fall 2012 34

TTL (Transistor-Transistor)

Q1

Q2

In Q1 Q2 Out

0 ON OFF 1

In

1 Off ON 0

ENG3640 Fall 2012 35

CMOS/TTL Interfacing

Several factors to consider

1. Noise Margin

TTL (VIL = 0.4 V, VIH = 2.4V)

CMOS TTL

CMOS (VOL = 0, VOH = 5V)

No problem for CMOS to drive TTL since CMOS has full swing output

ENG3640 Fall 2012 36

CMOS/TTL Interfacing

TTL (VOL = 0.7 V, VOH = 3.3V)

CMOSTTL

CMOS (VIL = 2.3, VIH = 3.3V)

1. We do have a problem when TTL drives CMOS.

2. TTL driving HC (high speed CMOS) doesn’t work unless the TTL high output happens to be higher and the CMOS high input threshold happens to be lower by a total of 1V.

3. To drive CMOS inputs properly from TTL outputs, the CMOS device should be TTL compatible (i.e. use HCT, VHCT, FCT)

ENG3640 Fall 2012 37

CMOS/TTL Interfacing

Other factors to consider

(2) Fan-out: defined as Min( IOH/IIH, IOL/IIL)

CMOS TTL

We would encounter problems when CMOS drives TTL since CMOS has limited driving current.

ENG3640 Fall 2012 38

CMOS/TTL Interfacing

CMOS has very high input impedance so almost no current is required in either state!

So TTL can drive CMOS with no problems if we are considering fan-out (up to 15 gates)

CMOSTTL

ENG3640 Fall 2012 39

ENG3640 Fall 2012 40

History of MOS Transistors 1961: TI and Fairchild introduce the first logic ICs ($50 in

quantity) 1962: RCA develops the first MOS transistor

RCA 16-transistor MOSFET ICFairchild bipolar RTL Flip-Flop

ENG3640 Fall 2012 41

Bell Labs

1951: Shockley develops a junction transistor manufacturable in quantity (U.S.

Patent 2,623,105)

ENG3640 Fall 2012 42

BJT Operating Regions

For different values of VBE

ENG3640 Fall 2012 43

BJT in Cutoff Region

VBB is smaller than 0.5V

Under this condition iB= 0

As a result iC becomes negligibly small

Both base-emitter as well base- collector junctions may be reverse biased

Under this condition the BJT can be treated as an off switch

ENG3640 Fall 2012 44

BJT in Active Region

VBB is above 0.5V around 0.7VUnder this condition iB= (VBB – VBE)/RBB

As a result iC = IB

EBJ is forward CBJ is reverse

ENG3640 Fall 2012 45

BJT in Saturation Region

Both base emitter as well as base collector junctions are forward biased.

VCE 0.2 V

Under this condition the BJT can be treated as an on switch

ENG3640 Fall 2012 46

A BJT can enter saturation in the following ways:

1. For a particular value of iB, if we keep on increasing RCC

2. For a particular value of RCC, if we keep on increasing iB

3. For a particular value of iB, if we replace the transistor with one with higher

BJT in Saturation Region

ENG3640 Fall 2012 47

Current flow in an NPN transistor biased to operate in the active mode.

BJT: Active Region Bias

ENG3640 Fall 2012 48

NPN BJT Current flow

IE = IC +IB

?

ENG3640 Fall 2012 49

BJT ( and )

From the previous figure iE = iB + iC

Define = iC / iE = 0.99

Define = iC / iB = 100

Then = iC / (iE –iC) = /(1- )

Then iC = iE ; iB = (1-) iE

Typically 100 for small signal BJTs (BJTs that handle low power) operating in active region (region where BJTs work as amplifiers)

ENG3640 Fall 2012 50

(1) Totem Pole, BJT Simply refers to the vertical alignment of components Q1, Q2 act as switches controlled by In When One transistor is on the other is off Q1 is pull-up, Q2 is pull-down Not possible to join totem pole outputs together.

Q1

Q2

In Q1 Q2 Out

0 ON OFF 1

In

1 Off ON 0

ENG3640 Fall 2012 51

(2) Tri-State Output When interfacing to a bus we need to connect logic gates

together. Tri-state gates enable a device to electrically disconnect its

output when it is not driving the bus. By adding diodes to the previous totem-pole configuration we

can disable both Q1,Q2 and achieve high impedance

Q1

Q2

E In Q1 Q2 Out

1 0 ON OFF 1

In

1 1 OFF ON 0

0 X OFF OFF Z

E

ENG3640 Fall 2012 52

(3) Open Collector

As with tri-state output, open collector outputs allow multiple logic devices to drive the same line.

Since the pull-up transistor is missing, the circuit has the capability of pulling the signal down.

To pull a signal up we need an EXTERNAL RESISTOR (passive pull-up to high level)

Low to high transitions are much slower for open drain gate than for standard gate with active pull-up

*Symbols

ENG3640 Fall 2012 53

MOSFET Symbols

A circle is sometimesused on the gate terminalto show active low input

ENG3640 Fall 2012 54

MOSFET Operating Regions

Strong Inversion VGS > VT

Linear (Resistive) VDS < VDSAT

Saturated (Constant Current) VDS VDSAT

Weak Inversion (Sub-Threshold) VGS VT

Exponential in VGS with linear VDS dependence

ENG3640 Fall 2012 55

Threshold Voltage: Concept

n+n+

p-substrate

DSG

B

VGS

+

-

Depletion

Region

n-channel

ENG3640 Fall 2012 56

Transistor in Saturation

n+n+

S

G

VGS

D

VDS > VGS - VT

VGS - VT+-

Pinch-off

ENG3640 Fall 2012 57

Complementary CMOS Logic Style

ENG3640 Fall 2012 58

CMOS NAND Gate

A B Y

0 0

0 1

1 0

1 1A

B

Y

Y = A.B

ENG3640 Fall 2012 59

CMOS NAND Gate

A B Y

0 0 1

0 1

1 0

1 1

A=0

B=0

Y=1

OFF

ON ON

OFF

Y = A.B

ENG3640 Fall 2012 60

CMOS NAND Gate

A B Y

0 0 1

0 1 1

1 0

1 1

A=0

B=1

Y=1

OFF

OFF ON

ON

Y = A.B

ENG3640 Fall 2012 61

CMOS NAND Gate

A B Y

0 0 1

0 1 1

1 0 1

1 1

A=1

B=0

Y=1

ON

ON OFF

OFF

Y = A.B

ENG3640 Fall 2012 62

CMOS NAND Gate

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

A=1

B=1

Y=0

ON

OFF OFF

ON

ENG3640 Fall 2012 63

Example Gate: NOR

ENG3640 Fall 2012 64

Complex CMOS Gate

OUT = D + (A • (B + C))

D

A

B C

D

A

B

C

ENG3640 Fall 2012 65

Open Collector: Driving a Bus

Open-drain outputs can be tied together to allow several devices (one at a time) to put information on a common bus.

+5V

D1

D2 D4

D3

D6

D5

D8

D7

Data Out

E1

E2

E3

E4

E5

E6

E7

E8

At most one ``Enable Bit” is high at any time enabling the corresponding data bit to be passed through the bus